WO2017045346A1 - 移位寄存器单元及其驱动方法、栅极驱动装置以及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动装置以及显示装置 Download PDF

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WO2017045346A1
WO2017045346A1 PCT/CN2016/073625 CN2016073625W WO2017045346A1 WO 2017045346 A1 WO2017045346 A1 WO 2017045346A1 CN 2016073625 W CN2016073625 W CN 2016073625W WO 2017045346 A1 WO2017045346 A1 WO 2017045346A1
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Prior art keywords
unit
signal
output
shift register
control unit
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PCT/CN2016/073625
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English (en)
French (fr)
Inventor
何小祥
邓银
韦东梅
王杨
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/517,415 priority Critical patent/US9928797B2/en
Publication of WO2017045346A1 publication Critical patent/WO2017045346A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present disclosure relates to a shift register unit and a method of driving the same, a gate driving device, and a display device.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • the driving circuit of the TFT-LCD mainly includes a gate driving circuit and a data driving circuit.
  • the data driving circuit is configured to sequentially latch the input data according to the clock signal timing and convert the latched data into an analog signal and input the data to the data line of the display panel.
  • the gate driving circuit is usually implemented by a shift register that converts a clock signal into an on/off voltage, which are respectively output to respective gate lines of the display panel.
  • a gate line on the display panel is typically interfaced to a shift register unit (ie, the stage of the shift register).
  • the progressive scan of the pixels in the display panel is realized by causing the respective shift register units to sequentially output the turn-on voltages.
  • Such progressive scanning of pixels can be divided into one-way scanning and two-way scanning according to the scanning direction.
  • GOA Gate Driver on Array
  • the GOA technology directly integrates the gate driving circuit of the TFT-LCD on the array substrate, thereby replacing the driving chip made of the silicon chip bonded on the outer edge of the panel. Since the technology can directly drive the driving circuit on the array substrate, there is no need to bond the IC and the wiring around the panel, which reduces the manufacturing process of the panel, reduces the product cost, and improves the integration degree of the TFT-LCD panel, so that the panel can be realized. Narrow borders and high resolution.
  • GOA technology has inherent problems in terms of service life and the like. In the GOA design of the actual product, how to use less circuit components to realize the shift register function and reduce the electrical stress of the key TFT to keep the gate drive circuit stable for a long time is a key issue in the GOA design.
  • the present disclosure provides a shift register unit and a driving method thereof, a gate driving device, and a display device.
  • the electrical stress of some of the key TFTs in the shift register unit and the gate driving device is alleviated, thereby improving the operational stability and prolonging the service life; moreover, the shift register unit according to the embodiment of the present disclosure employs fewer transistors, and thus It can realize the narrow bezel design of the liquid crystal display.
  • the gate driving device according to an embodiment of the present invention can adopt GOA technology to improve the integration degree of the TFT-LCD panel.
  • a shift register unit comprising:
  • a scanning direction selecting unit connected to the first power input end, the second power input end, the signal input end and the reset signal end, configured to input the signal input end signal or the second under the control of the voltage input by the first power input end
  • the input signal of the reset signal terminal is supplied to the output end of the scan direction selection unit under the control of the voltage input from the power input terminal;
  • control unit wherein the input end is connected to the output end of the scan direction selection unit, and configured to provide a first output signal at the first output end of the control unit according to the signal of the output end of the scan direction selection unit, and provide the second output end of the control unit a second output signal and a third output signal at a third output of the control unit;
  • a bootstrap unit wherein the input end is connected to the first output end of the control unit, configured to output a signal at a signal output end of the shift register unit according to the first output signal of the first output end;
  • a first pull-down maintaining unit configured as a second output signal according to the second output end of the control unit a third output signal of the third output of the control unit outputs a signal to the signal output terminal;
  • a second pull-down maintaining unit configured as a second output signal and control according to the second output end of the control unit a third output signal of the third output of the unit outputs a signal to the signal output;
  • the first pull-down maintaining unit and the second pull-down maintaining unit are alternately used between two frames.
  • a gate driving apparatus including a plurality of the above-described shift register units connected in series is provided.
  • signals of each of the shift register units The output ends are connected to a signal input end of a next shift register unit adjacent thereto and a reset signal end of a previous shift register unit adjacent thereto, the signal input end of the first shift register is input from the frame
  • the start signal is connected to the signal input end of the second shift register, and the signal output end of the last shift register is connected to the reset signal end of the previous shift register adjacent thereto.
  • a display device including the above-described gate driving device is provided.
  • a driving method of a shift register unit including a scan direction selecting unit, a control unit, a bootstrap unit, a first pull-down maintaining unit, and a second pull-down maintaining unit
  • the method includes: selecting a scanning direction by a scanning direction selecting unit; causing the second pull-down maintaining unit to be inoperative during the first frame, and controlling the first pull-down maintaining unit to operate by the control unit; During the second frame, the first pull-down maintaining unit is rendered inoperative, and the second pull-down maintaining unit is controlled to operate by the control unit.
  • FIG. 1 shows a circuit block diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • FIG. 2 shows an internal circuit diagram of a control unit in the shift register unit of FIG. 1.
  • FIG. 3 shows a specific circuit configuration diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 illustrates a schematic diagram of a gate driving device formed by cascading a plurality of shift register cells in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a timing chart showing a case where a shift register unit performs forward scanning according to an embodiment of the present invention.
  • the transistors employed in all embodiments of the present invention may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection of the drain and the source of each transistor can be In other words, the drain and source of each transistor in the embodiment of the present invention are practically indistinguishable.
  • the drain and source of each transistor in the embodiment of the present invention are practically indistinguishable.
  • the gate one of which is called the drain and the other is called the source.
  • FIG. 1 shows a circuit block diagram of a shift register unit in accordance with an embodiment of the present invention.
  • the shift register unit 100 includes a scan direction selection unit 101, a control unit 102, a bootstrap unit 103, a first pull-down maintaining unit 104, and a second pull-down maintaining unit 105.
  • the scanning direction selecting unit 101 is connected to the first power input terminal UD, the second power input terminal DU, the signal input terminal INPUT and the reset signal terminal RESET, and is configured to input the signal input terminal INPUT under the control of the voltage input by the first power input terminal.
  • the input signal of the reset signal terminal RESET is supplied to the output terminal of the scan direction selecting unit 101 under the control of the input signal or the voltage input at the second power input terminal.
  • the input end of the control unit 102 is connected to the output end of the scan direction selecting unit 101, and is configured to provide a first output signal at the first output end 1 of the control unit 102 according to the signal of the output end of the scan direction selecting unit 101, respectively, at the control unit 102
  • the second output terminal 2 provides a second output signal and provides a third output signal at a third output of the control unit 102, output3.
  • the input end of the bootstrap unit 103 is connected to the first output terminal output1 of the control unit 102, and is configured to output a signal at the signal output terminal OUTPUT of the shift register unit 100 according to the first output signal of the first output terminal output1.
  • the first input end of the first pull-down maintaining unit 104 is connected to the second output end output2 of the control unit 102, and the second input end is connected to the third output end output3 of the control unit 102, and is configured to be output2 according to the second output end of the control unit 102.
  • the second output signal and the third output signal of the third output terminal output3 of the control unit 102 output a signal to the signal output terminal OUTPUT.
  • the first input end of the second pull-down maintaining unit 105 is connected to the second output end output2 of the control unit 102, and the second input end is connected to the third output end output3 of the control unit 102, and is configured according to the second output end of the control unit 102.
  • the second output signal and the third output signal of the third output terminal output3 of the control unit 102 output a signal to the signal output terminal OUTPUT.
  • the first pull-down maintaining unit 104 and the second pull-down maintaining unit 105 are alternately used between two frames.
  • an embodiment of the present invention further discloses a driving method of a shift register unit, where the shift register unit includes a scan direction selecting unit, a control unit, a bootstrap unit, a first pull-down maintaining unit, and a second pull-down maintaining unit, For two consecutive frames, the method includes:
  • the first pull-down maintaining unit is rendered inoperative, and the second pull-down maintaining unit is controlled by the control unit to operate.
  • the shift register unit shares the scan direction selection unit 101, the control unit 102, and the bootstrap unit 103 through two frames, and alternately uses the first pull-down maintaining unit 104 and the second pull-down maintaining unit between the two frames. 105, reducing the electrical stress of some of the components in the corresponding pull-down sustaining unit.
  • FIG. 2 shows an internal circuit diagram of the control unit 102 in the shift register unit of FIG. 1.
  • the control unit 102 includes a first switching unit 1021, a second switching unit 1022, and a pull-down unit 1023.
  • the input end of the first switching unit 1021 is connected to the output end of the scanning direction selecting unit 101, and configured to output the signal of the output end of the scanning direction selecting unit 101 to the first output terminal 1, the second switching unit 1022, and the pull-down unit 1023 of the control unit 102.
  • a first output signal is provided.
  • the input end of the second switching unit 1022 is connected to the output end of the first switching unit 1021, and is configured to provide a second output signal to the second output terminal 2 of the control unit 102 according to the first output signal of the output end of the first switching unit 1021.
  • the input end of the pull-down unit 1023 is connected to the output end of the first switching unit 1021, and is configured to provide a third output signal to the third output terminal output3 of the control unit 102 according to the first output signal of the output end of the first switching unit 1021.
  • FIG. 3 shows a specific circuit configuration diagram of a shift register unit according to an embodiment of the present invention.
  • the scanning direction selecting unit 101 includes a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is connected to the first power input terminal UD, the source is connected to the signal input terminal INPUT;
  • the gate of the second transistor T2 is connected to the second power input terminal DU, and the source is connected to the reset signal terminal RESET;
  • the drain of the first transistor T1 and the drain of the second transistor T2 are connected to each other to constitute an output end of the scanning direction selecting unit 101.
  • the first switching unit 1021 includes a third transistor T3 whose gate is connected to the first clock signal terminal CK, the source is connected to the output end of the scanning direction selecting unit 101, and the drain is used as the first switching unit.
  • the output of 1021 is coupled to the first output output1 of control unit 102.
  • the second switching unit 1022 includes a fourth transistor T4 whose gate is connected to the second clock signal terminal CKB, the source is connected to the first output terminal output1 of the control unit 102, and the drain is connected as the output terminal of the second switching unit 1022. To the second output of the control unit 102, output2.
  • the pull-down unit 1023 includes a fifth transistor T5 whose gate is connected to the first output terminal output1 of the control unit 102, the source is connected to the first clock signal terminal CK, and the drain is connected to the control unit 102 as an output terminal of the pull-down unit 1023.
  • the third output is output3.
  • the bootstrap unit 103 includes a sixth transistor T6 and a first capacitor C1.
  • the gate of the sixth transistor T6 is connected to the first output terminal output1 of the control unit 102, the source is connected to the second clock signal terminal CKB, and the drain is connected to the signal output terminal OUTPUT; one end of the first capacitor C1 is connected to the signal output terminal. The other end is connected to the first output output1 of the control unit 102.
  • the first pull-down maintaining unit 104 includes seventh to twelfth transistors T7-T12.
  • the gate of the seventh transistor T7 is connected to the first control signal terminal CL1, the source is connected to the third output terminal output3 of the control unit 102, the drain is connected to the first node PD1, and the gate of the eighth transistor T8 is connected to the first
  • the node PD1 has a source connected to the third low voltage source P1 and a drain connected to the second output terminal 2 of the control unit 102; the gate of the ninth transistor T9 is connected to the first control signal terminal CL1, and the source is connected to the tenth
  • the drain of the transistor T10 is connected to the first node PD1; the gate of the tenth transistor T10 is connected to the first clock signal terminal CK, the source is connected to the fourth low voltage source P2; the gate of the eleventh transistor T11 Connected to the first node PD1, the source is connected to the third low voltage source P1, the drain is connected to the signal output terminal OUTPUT
  • the first pull-down maintaining unit 104 is configured to mitigate the eighth transistor T8 and the tenth in the first pull-down maintaining unit 104 by keeping the first node PD1 at a low level during one frame under the control of each signal.
  • the second pull-down maintaining unit 105 includes thirteenth to eighteenth transistors T13-T18.
  • the gate of the thirteenth transistor T13 is connected to the second control signal terminal CL2, the source is connected to the third output terminal output3 of the control unit 102, the drain is connected to the second node PD2, and the gate of the fourteenth transistor T14 is connected to
  • the second node PD2 has a source connected to the third low voltage source P1 and a drain connected to the second output terminal 2 of the control unit 102.
  • the gate of the fifteenth transistor T15 is connected to the second control signal terminal CL2, and the source is connected.
  • the drain is connected to the second node PD2; the sixteenth crystal
  • the gate of the body tube T16 is connected to the first clock signal terminal CK, the source is connected to the fourth low voltage source P2; the gate of the seventeenth transistor T17 is connected to the second node PD2, and the source is connected to the third low voltage source.
  • P1 the drain is connected to the signal output terminal OUTPUT; the gate of the eighteenth transistor T18 is connected to the first control signal terminal CL1, the source is connected to the third low voltage source P1, and the drain is connected to the second node PD2.
  • the second pull-down maintaining unit 105 is configured to mitigate the fourteenth transistor T14 and the seventeenth in the second pull-down maintaining unit 105 by keeping the second node PD2 at a low level during one frame under the control of each signal.
  • the shift register unit shares the scan direction selection unit 101, the control unit 102, and the bootstrap unit 103 through two frames, and alternately uses the first pull-down maintaining unit 104 and the second pull-down maintaining unit between the two frames.
  • 105 to avoid the PD point (PD1 or PD2) is always in a certain working state, so the electrical stress of some key TFTs in the corresponding pull-down sustain circuit can be alleviated.
  • the clock signal of the second clock signal terminal CKB of the shift register unit and the clock signal of the first clock signal terminal CK are mutually inverted.
  • each The unit may also adopt other suitable circuit structures, as long as the respective functions can be implemented separately, and the present invention does not limit this.
  • FIG. 4 shows a schematic diagram of a gate driving device formed by cascading a plurality of the above-described shift register units 100, in accordance with an embodiment of the present invention.
  • a plurality of the above-described shift register units 100 are connected in series, and each of the shift register unit R1 and the last shift register unit Rm are removed.
  • the signal output terminal OUTPUT of the bit register unit Rn (1 ⁇ n ⁇ m) is equal to the signal input terminal INPUT of the next shift register unit Rn+1 adjacent thereto and the previous shift register unit Rn-1 adjacent thereto
  • the reset signal terminal RESET is connected; the signal input terminal INPUT of the first shift register unit R1 inputs a frame start signal STV, and the signal output terminal OUTPUT is connected to the signal input terminal INPUT of the second shift register unit R2;
  • the signal output terminal OUTPUT of the last shift register unit Rm is connected to the reset signal terminal RESET of the previous shift register unit Rm-1 adjacent thereto.
  • OUTPUT_n is the output signal of the nth stage shift register unit.
  • the adjacent two-stage shift register unit The clock signals input from the first clock signal terminal are inverted with each other, and the clock signals input from the second clock signal terminal of the adjacent two-stage shift register unit are mutually inverted.
  • the first clock signal terminal of the shift register unit Rn inputs the CLK signal
  • the second clock signal terminal inputs the CLKB signal
  • the first clock signal terminal of the shift register unit Rn+1 inputs the CLKB signal
  • the second clock signal terminal inputs the CLK signal.
  • the CLK signal and the CLKB signal are inverted from each other.
  • DCF1 and DCF2 are control signals outputted by the first control signal terminal CL1 and the second control signal terminal CL2, respectively, and DCF1 and DCF2 are both DC signals within one frame.
  • VGL and VGH are voltage signals output by the third low voltage source P1 and the fourth low voltage source P2, respectively.
  • FIG. 5 is a timing chart showing a case where a shift register unit performs forward scanning according to an embodiment of the present invention.
  • a specific operation of the above-described shift register unit 100 according to an embodiment of the present invention will be described below with reference to FIG.
  • an example in which the above transistors are N-type transistors will be described.
  • the above-described shift register unit 100 is capable of bidirectional scanning.
  • the structure of the shift register unit does not change, but the functions of the signal input terminal and the reset signal terminal are changed.
  • the high level signal VDD is input from the first power input terminal UD
  • the low level signal VSS is input from the second power input terminal DU
  • the first power input terminal UD is input when the reverse scan is performed.
  • the low level signal VSS inputs a high level signal VDD from the second power input terminal DU.
  • the signal input terminal INPUT at the time of forward scanning is used as the reset signal terminal RESET at the time of reverse scanning
  • the reset signal terminal RESET at the time of forward scanning is used as the signal input terminal INPUT at the time of reverse scanning.
  • the operation of the shift register unit according to the embodiment of the present invention at the time of forward scanning will be described with reference to the timing chart at the time of forward scanning shown in FIG.
  • the high level signal VDD is input from the first power input terminal UD, the first transistor T1 remains turned on; the low level signal VSS is input from the second power input terminal DU, and the second transistor T2 remains off.
  • the work process consists of the following steps.
  • the first pull-down maintaining unit 104 operates, the control signal DCF2 outputted by the second control signal terminal CL2 is at a low level, the twelfth transistor T12 is turned off, and does not affect the potential of the first node PD1;
  • the maintenance unit 105 does not work, the control signal DCF1 outputted by the first control signal terminal CL1 is at a high level, and the eighteenth transistor T18 is always turned on, so the second node PD2 is always at a low level, thereby alleviating the second pull-down maintaining unit
  • the electrical stress of the fourteenth transistor T14 and the seventeenth transistor T17 in 105 are alleviating the second pull-down maintaining unit The electrical stress of the fourteenth transistor T14 and the seventeenth transistor T17 in 105.
  • the working process can be subdivided into the following stages during the first frame.
  • the first stage a-1 the shift register outputs a low level signal through the control unit and the bootstrap unit.
  • the high level signal VDD is input from the first power input terminal UD, and the first transistor T1 is turned on in response to the input signal of the high level.
  • the signal input terminal INPUT of the shift register unit (Rn) inputs a high level signal, wherein the input signal of the signal input terminal INPUT is an output signal of the signal output terminal OUTPUT of the shift register unit (Rn-1) of the previous stage (
  • the signal input terminal INPUT of the first shift register unit R1 inputs a frame start signal STV).
  • the clock signal CLK of the first clock signal terminal CK is at a high level
  • the third transistor T3 is turned on, and a high-level input signal on the signal input terminal INPUT is input from the third transistor T3 to charge the first capacitor C1.
  • the first output terminal output1 of the control unit 102 is at a high level.
  • the fourth transistor T4 is turned on, and the voltage of the clock signal CLK of the first clock signal terminal CK is output to the third output terminal output3 of the control unit 102 via the fourth transistor T4. Since the control signal DCF1 output from the first control signal terminal CL1 is a high level, the seventh transistor T7 and the ninth transistor T9 are turned on.
  • the high level on the third output terminal output3 charges the first node PD1 to a high level through the seventh transistor T7.
  • the clock signal CLK of the first clock signal terminal CK is at a high level, so the tenth transistor T10 is also turned on, the voltage signal VGH outputted by the fourth low voltage source P2 is transmitted to the first node PD1, and the eleventh transistor T11 is turned on.
  • the potential of the signal output terminal OUTPUT is pulled to the low level of the third low voltage source P1. Since the first output terminal output1 of the control unit 102 is at a high level, the sixth transistor T6 is turned on, and the clock signal CLKB of the second clock signal terminal CKB is at a low level, so the signal output terminal OUTPUT outputs a low level signal.
  • the eighth transistor T8 Since the first node PD1 is at a high level, the eighth transistor T8 is turned on, and the potential of the second output terminal output2 of the control unit 102 is pulled to a low level output by the third low voltage source P1. Since the clock signal CLKB of the second clock signal terminal CKB is at a low level, the fourth transistor T4 is turned off, preventing the potential of the first output terminal output1 from being pulled low. Since the control signal DCF1 outputted by the first control signal terminal CL1 is at a high level, the eighteenth transistor T18 is turned on, and the potential of the second node PD2 is pulled to the low level output from the third low voltage source P1. Since the control signal DCF2 outputted by the second control signal terminal CL2 is low level, the twelfth transistor T12 is turned off.
  • Second stage b-1 The shift register is caused to output a high level signal by the control unit and the bootstrap unit.
  • the signal input terminal INPUT of the shift register unit (Rn) inputs a low level signal, wherein the input signal of the signal input terminal INPUT is a letter of the shift register unit (Rn-1) of the previous stage.
  • the output signal of the output terminal OUTPUT (the signal input terminal INPUT of the first shift register unit R1 inputs the frame start signal STV).
  • the clock signal CLK of the first clock signal terminal CK is at a low level
  • the third transistor T3 is turned off
  • the clock signal CLKB of the second clock signal terminal CKB is at a high level
  • the potential of the first output terminal output1 is latched to a high level. .
  • the sixth transistor T6 since the first output terminal output1 is at a high level, the sixth transistor T6 is turned on, and the clock signal of the second clock signal terminal CKBCLKB is at a high level. According to the charge retention principle of the first capacitor C1, the first output terminal is output1. The potential is further increased. Since the clock signal CLK of the first clock signal terminal CK is at a low level, the tenth transistor T10 is turned off, and the voltage signal VGH output from the fourth low voltage source P2 cannot be transmitted to the first node PD1.
  • the fifth transistor T5 Since the first output terminal output1 is at a high level, the fifth transistor T5 is turned on, and since the control signal DCF1 outputted by the first control signal terminal CL1 is at a high level, the seventh transistor T7 is turned on, so the first clock signal terminal CK
  • the low-level clock signal CLK pulls the potential of the first node PD1 to a low level through the fifth transistor T5 and the seventh transistor T7, and the eighth transistor T8 and the eleventh transistor T11 are thus turned off, without affecting the signal output terminal OUTPUT Output.
  • the sixth transistor T6 Since the potential of the first output terminal output1 is at a high level, the sixth transistor T6 is turned on, and the clock signal CLKB of the second clock signal terminal CKB is at a high level, so the signal output terminal OUTPUT outputs a high level signal.
  • the third stage c-1 the shift register outputs a low level signal through the control unit and the bootstrap unit.
  • the signal input terminal INPUT of the shift register unit (Rn) inputs a low level signal, wherein the input signal of the signal input terminal INPUT is an output signal of the signal output terminal OUTPUT of the shift register unit (Rn-1) of the previous stage (
  • the signal input terminal INPUT of the first shift register unit R1 inputs a frame start signal STV).
  • the clock signal CLK of the first clock signal terminal CK is at a high level, the third transistor T3 is turned on, and the low level signal on the signal input terminal INPUT is pulled down to the low level by the first output terminal output1 through the third transistor T3.
  • the fifth transistor T5 and the sixth transistor T6 are turned off. Since the control signal DCF1 outputted by the first control signal terminal CL1 is a high level, the clock signal CLK of the first clock signal terminal CK is a high level, so the ninth transistor T9 and the tenth transistor T10 are respectively turned on, and the fourth low voltage is respectively.
  • the high voltage signal VGH outputted from the source P2 is transmitted to the first node PD1, the eleventh transistor T11 is turned on, and the potential of the signal output terminal OUTPUT is pulled to the low level output by the third low voltage source P1.
  • the eighth transistor T8 is turned on, and the potential of the second output terminal 2 of the control unit 102 is pulled to the low level output by the third low voltage source P1.
  • the shift register continues to output a low level signal through the control unit and the bootstrap unit until the next frame arrives.
  • the clock signal of the second clock signal terminal CKB CLKB and the clock signal CLK of the first clock signal terminal CK continue to alternately input high and low level signals, and other input signals and output signals remain unchanged until the next frame arrives, and the shift register unit receives the signal input terminal INPUT After the high level signal, the above stages are re-executed.
  • the second pull-down maintaining unit 105 operates, the control signal DCF1 outputted by the first control signal terminal CL1 is at a low level, and the eighteenth transistor T18 is turned off, without affecting the potential of the second node PD2;
  • the maintenance unit 104 does not work, the control signal DCF2 outputted by the second control signal terminal CL2 is at a high level, and the twelfth transistor T12 is always turned on, so the first node PD1 is always at a low level, thereby reducing the first pull-down maintenance.
  • the electrical stress of the eighth transistor T8 and the eleventh transistor T11 in the cell 104 is not work, the eighth transistor T8 and the eleventh transistor T11 in the cell 104.
  • the timing principle of the first phase a-2, the second phase b-2, and the third phase c-2 during the second frame is similar to the corresponding phase during the first frame except that the first control signal terminal CL1 during the second frame
  • the output control signal is low level
  • the control signal outputted by the second control signal terminal CL2 is high level
  • the voltage curve of the first node PD1 is the same as the voltage curve of the second node PD2 during the first frame
  • the second node PD2 is The voltage curve is the same as the voltage curve of the first node PD1 during the first frame
  • the other input signals and the output signals are the same as the corresponding signals during the first frame, and are not described herein again.
  • the shift register unit according to the embodiment of the present invention shares the scan direction selection unit 101, the control unit 102, and the bootstrap unit 103 through two frames, and alternately uses the first pull-down between two frames.
  • the unit 104 and the second pull-down maintaining unit 105 prevent the PD point (PD1 or PD2) from being in a certain working state all the time, so that the electrical stress of some key TFTs (T8, T11, T14, T17) in the corresponding pull-down maintaining unit can be alleviated. Thereby, the work stability is improved and the service life is prolonged; at the same time, the number of transistors used in the shift register unit according to the embodiment of the present invention is small, so that the narrow bezel design of the liquid crystal display can be realized.
  • the gate driving device may employ GOA technology as a gate driving circuit of a display device to provide a progressive scanning function to transmit a scanning signal to a display area.
  • the present invention also provides a display device including the above-described gate driving device.
  • the display device here can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.

Abstract

一种移位寄存器单元（100）及其驱动方法、栅极驱动装置以及显示装置。该移位寄存器单元（100）包含扫描方向选择单元（101）、控制单元（102）、自举单元（103）、第一下拉维持单元（104）以及第二下拉维持单元（105），用以减轻移位寄存器单元（100）中部分元件的电应力，从而提高其工作稳定性，延长了使用寿命。此外，该移位寄存器单元（100）还能够实现液晶显示器的窄边框设计。该栅极驱动装置可以采用ＧＯＡ技术，提高ＴＦＴ－ＬＣＤ面板的集成度。

Description

移位寄存器单元及其驱动方法、栅极驱动装置以及显示装置 技术领域
本公开涉及一种移位寄存器单元及其驱动方法、栅极驱动装置以及显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于生产生活的各个领域，在进行显示时，TFT-LCD通过驱动电路来驱动显示面板中的各个像素进行显示。TFT-LCD的驱动电路主要包含栅极驱动电路和数据驱动电路。其中，数据驱动电路用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示面板的数据线。栅极驱动电路通常用移位寄存器来实现，所述移位寄存器将时钟信号转换成开启/断开电压，分别输出到显示面板的各条栅线上。显示面板上的一条栅线通常与一个移位寄存器单元(即移位寄存器的一级)对接。通过使得各个移位寄存器单元依序轮流输出开启电压，实现对显示面板中像素的逐行扫描。像素的这种逐行扫描按照扫描方向可分为单向扫描和双向扫描。目前，在移动产品中，考虑到移动产品产能和良率的提升，通常要求能够实现双向扫描。
另一方面，随着平板显示的发展，高分辨率、窄边框成为发展的趋势。针对这一趋势，出现了阵列基板栅极驱动(Gate Driver on Array，GOA)技术。GOA技术直接将TFT-LCD的栅极驱动电路集成制作在阵列基板上，由此来代替在面板外沿粘接的、由硅芯片制作的驱动芯片。由于该技术可以将驱动电路直接做在阵列基板上，面板周围无需再粘接IC和布线，减少了面板的制作程序，降低了产品成本，同时提高了TFT-LCD面板的集成度，使面板实现窄边框和高分辨率。但是GOA技术存在固有的使用寿命等方面的问题。在实际产品的GOA设计中，如何使用较少的电路元器件来实现移位寄存功能、并且减小关键TFT的电应力以保持栅极驱动电路长期稳定工作，是GOA设计的关键问题。
发明内容
本公开提供了一种移位寄存器单元及其驱动方法、栅极驱动装置以及显示装置。减轻了移位寄存器单元及栅极驱动装置中部分关键TFT的电应力，从而提高工作稳定性，延长了使用寿命；此外，根据本公开实施例的移位寄存器单元中采用的晶体管较少，因而能够实现液晶显示器的窄边框设计。根据本发明实施例的栅极驱动装置可以采用GOA技术，提高TFT-LCD面板的集成度。
根据本公开的一个方面，提供了一种移位寄存器单元，包含：
扫描方向选择单元，连接第一电源输入端、第二电源输入端、信号输入端和复位信号端，配置为在第一电源输入端输入的电压的控制下将信号输入端的输入信号或者在第二电源输入端输入的电压的控制下将复位信号端的输入信号提供至该扫描方向选择单元的输出端；
控制单元，输入端连接扫描方向选择单元的输出端，配置为根据扫描方向选择单元的输出端的信号分别在控制单元的第一输出端提供第一输出信号、在控制单元的第二输出端提供第二输出信号和在控制单元的第三输出端提供第三输出信号；
自举单元，输入端连接控制单元的第一输出端，配置为根据该第一输出端的所述第一输出信号在该移位寄存器单元的信号输出端输出信号；
第一下拉维持单元，其第一输入端连接控制单元的第二输出端，其第二输入端连接控制单元的第三输出端，配置为根据控制单元的第二输出端的第二输出信号和控制单元的第三输出端的第三输出信号向所述信号输出端输出信号；
第二下拉维持单元，其第一输入端连接控制单元的第二输出端，其第二输入端连接控制单元的第三输出端，配置为根据控制单元的第二输出端的第二输出信号和控制单元的第三输出端的第三输出信号向所述信号输出端输出信号；
其中，在两帧之间交替使用第一下拉维持单元以及第二下拉维持单元。
根据本公开的另一方面，提供了一种栅极驱动装置，包含多个串联的上述移位寄存器单元。其中，所述多个串联的移位寄存器单元中除第一个移位寄存器单元和最后一个移位寄存器单元外，其余每个移位寄存器单元的信号 输出端均和与其相邻的下一个移位寄存器单元的信号输入端以及与其相邻的上一个移位寄存器单元的复位信号端相连，所述第一个移位寄存器的信号输入端输入帧起始信号，信号输出端与第二个移位寄存器的信号输入端连接，所述最后一个移位寄存器的信号输出端和与其相邻的上一个移位寄存器的复位信号端相连接。
根据本公开的又一方面，提供了一种包含上述栅极驱动装置的显示装置。
根据本公开的又一方面，提供了一种移位寄存器单元的驱动方法，该移位寄存器单元包含扫描方向选择单元、控制单元、自举单元、第一下拉维持单元以及第二下拉维持单元，对于连续的两帧画面，该方法包含：通过扫描方向选择单元选择扫描方向；在第一帧期间，使得第二下拉维持单元不工作，并且通过控制单元控制第一下拉维持单元工作；在第二帧期间，使得第一下拉维持单元不工作，并且通过控制单元控制第二下拉维持单元工作。
附图说明
图1示出了根据本公开实施例的移位寄存器单元的电路框图。
图2示出了图1的移位寄存器单元中的控制单元的内部电路图。
图3示出了根据本公开实施例的移位寄存器单元的一种具体电路结构图。
图4示出了根据本公开实施例的、由多个移位寄存器单元级联形成的栅极驱动装置的示意图。
图5示出了根据本发明实施例的移位寄存器单元进行正向扫描时的时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可 以互换，因此，本发明实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。
图1示出了根据本发明实施例的移位寄存器单元的电路框图。如图1所示，该移位寄存器单元100包含扫描方向选择单元101、控制单元102、自举单元103、第一下拉维持单元104以及第二下拉维持单元105。
扫描方向选择单元101连接第一电源输入端UD、第二电源输入端DU、信号输入端INPUT和复位信号端RESET，配置为在第一电源输入端输入的电压的控制下将信号输入端INPUT的输入信号或者在第二电源输入端输入的电压的控制下将复位信号端RESET的输入信号提供至该扫描方向选择单元101的输出端。
控制单元102的输入端连接扫描方向选择单元101的输出端，配置为根据扫描方向选择单元101的输出端的信号分别在控制单元102的第一输出端output1提供第一输出信号、在控制单元102的第二输出端output2提供第二输出信号和在控制单元102的第三输出端output3提供第三输出信号。
自举单元103的输入端连接控制单元102的第一输出端output1，配置为根据该第一输出端output1的所述第一输出信号在该移位寄存器单元100的信号输出端OUTPUT输出信号。
第一下拉维持单元104的第一输入端连接控制单元102的第二输出端output2，第二输入端连接控制单元102的第三输出端output3，配置为根据控制单元102的第二输出端output2的第二输出信号和控制单元102的第三输出端output3的第三输出信号向所述信号输出端OUTPUT输出信号。
第二下拉维持单元105的第一输入端连接控制单元102的第二输出端output2，第二输入端连接控制单元102的第三输出端output3，配置为根据控制单元102的第二输出端output2的第二输出信号和控制单元102的第三输出端output3的第三输出信号向所述信号输出端OUTPUT输出信号。
在两帧之间交替使用第一下拉维持单元104以及第二下拉维持单元105。
相应地，本发明实施例还公开一种移位寄存器单元的驱动方法，该移位寄存器单元包含扫描方向选择单元、控制单元、自举单元、第一下拉维持单元以及第二下拉维持单元，对于连续的两帧画面，该方法包含：
通过扫描方向选择单元选择扫描方向；
在第一帧期间，使得第二下拉维持单元不工作，并且通过控制单元控制第一下拉维持单元工作；
在第二帧期间，使得第一下拉维持单元不工作，并且通过控制单元控制第二下拉维持单元工作。
根据本发明实施例的移位寄存器单元通过两帧画面共享扫描方向选择单元101、控制单元102、自举单元103，在两帧之间交替使用第一下拉维持单元104和第二下拉维持单元105，减轻了相应下拉维持单元中部分元件的电应力。
图2示出了图1的移位寄存器单元中的控制单元102的内部电路图。如图2所示，控制单元102包含第一开关单元1021、第二开关单元1022以及下拉单元1023。
第一开关单元1021的输入端连接扫描方向选择单元101的输出端，配置为根据扫描方向选择单元101的输出端的信号向控制单元102的第一输出端output1、第二开关单元1022以及下拉单元1023提供第一输出信号。
第二开关单元1022的输入端连接第一开关单元1021的输出端，配置为根据第一开关单元1021的输出端的第一输出信号向控制单元102的第二输出端output2提供第二输出信号。
下拉单元1023的输入端连接第一开关单元1021的输出端，配置为根据第一开关单元1021的输出端的第一输出信号向控制单元102的第三输出端output3提供第三输出信号。
图3示出了根据本发明实施例的移位寄存器单元的一种具体电路结构图。
如图3所示，扫描方向选择单元101包含第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极连接至第一电源输入端UD，源极连接至信号输入端INPUT；第二晶体管T2的栅极连接至第二电源输入端DU，源极连接至复位信号端RESET；第一晶体管T1的漏极和第二晶体管T2的漏极相互连接，构成扫描方向选择单元101的输出端。
第一开关单元1021包含第三晶体管T3，其栅极连接至第一时钟信号端CK，源极连接至扫描方向选择单元101的输出端，漏极作为第一开关单元 1021的输出端连接至控制单元102的第一输出端output1。
第二开关单元1022包含第四晶体管T4，其栅极连接至第二时钟信号端CKB，源极连接至控制单元102的第一输出端output1，漏极作为该第二开关单元1022的输出端连接至控制单元102的第二输出端output2。
下拉单元1023包含第五晶体管T5，其栅极连接至控制单元102的第一输出端output1，源极连接至第一时钟信号端CK，漏极作为该下拉单元1023的输出端连接至控制单元102的第三输出端output3。
自举单元103包含第六晶体管T6和第一电容C1。第六晶体管T6的栅极连接至控制单元102的第一输出端output1，源极连接至第二时钟信号端CKB，漏极连接至信号输出端OUTPUT；第一电容C1的一端连接至信号输出端OUTPUT，另一端连接至控制单元102的第一输出端output1。
第一下拉维持单元104包含第七至第十二晶体管T7-T12。第七晶体管T7的栅极连接至第一控制信号端CL1，源极连接至控制单元102的第三输出端output3，漏极连接至第一节点PD1；第八晶体管T8的栅极连接至第一节点PD1，源极连接至第三低电压源P1，漏极连接至控制单元102的第二输出端output2；第九晶体管T9的栅极连接至第一控制信号端CL1，源极连接至第十晶体管T10的漏极，漏极连接至第一节点PD1；第十晶体管T10的栅极连接至第一时钟信号端CK，源极连接至第四低电压源P2；第十一晶体管T11的栅极连接至第一节点PD1，源极连接至第三低电压源P1，漏极连接至信号输出端OUTPUT；第十二晶体管T12的栅极连接至第二控制信号端CL2，源极连接至第三低电压源P1，漏极连接至第一节点PD1。第一下拉维持单元104配置为在各信号的控制下，通过在一帧期间保持第一节点PD1处一直是低电平来减轻该第一下拉维持单元104中第八晶体管T8和第十一晶体管T11的电应力。
第二下拉维持单元105包含第十三至第十八晶体管T13-T18。第十三晶体管T13的栅极连接至第二控制信号端CL2，源极连接至控制单元102的第三输出端output3，漏极连接至第二节点PD2；第十四晶体管T14的栅极连接至第二节点PD2，源极连接至第三低电压源P1，漏极连接至控制单元102的第二输出端output2；第十五晶体管T15的栅极连接至第二控制信号端CL2，源极连接至第十六晶体管T16的漏极，漏极连接至第二节点PD2；第十六晶 体管T16的栅极连接至第一时钟信号端CK，源极连接至第四低电压源P2；第十七晶体管T17的栅极连接至第二节点PD2，源极连接至第三低电压源P1，漏极连接至信号输出端OUTPUT；第十八晶体管T18的栅极连接至第一控制信号端CL1，源极连接至第三低电压源P1，漏极连接至第二节点PD2。第二下拉维持单元105配置为在各信号的控制下，通过在一帧期间保持第二节点PD2处一直是低电平来减轻该第二下拉维持单元105中第十四晶体管T14和第十七晶体管T17的电应力。
根据本发明实施例的移位寄存器单元通过两帧画面共享扫描方向选择单元101、控制单元102、自举单元103，在两帧之间交替使用第一下拉维持单元104和第二下拉维持单元105，避免PD点(PD1或PD2)一直处在某个工作状态，因此可以减轻相应下拉维持电路中部分关键TFT的电应力。
该移位寄存器单元的第二时钟信号端CKB的时钟信号与第一时钟信号端CK的时钟信号互为反相。
能够理解，图3中所示出的扫描方向选择单元101、控制单元102、自举单元103、第一下拉维持单元104以及第二下拉维持单元105的示例电路结构仅仅是一种示例，各个单元也可以采用其他适当的电路结构，只要能分别实现各自的功能即可，本发明对此不做限制。
图4示出了根据本发明实施例的、由多个上述移位寄存器单元100级联形成的栅极驱动装置的示意图。
如图4所示，在栅极驱动该装置中，多个上述移位寄存器单元100串联连接，并且其中除第一个移位寄存器单元R1和最后一个移位寄存器单元Rm外，其余每个移位寄存器单元Rn(1＜n＜m)的信号输出端OUTPUT均和与其相邻的下一个移位寄存器单元Rn+1的信号输入端INPUT以及与其相邻的上一个移位寄存器单元Rn-1的复位信号端RESET相连；所述第一个移位寄存器单元R1的信号输入端INPUT输入帧起始信号STV，信号输出端OUTPUT与第二个移位寄存器单元R2的信号输入端INPUT连接；所述最后一个移位寄存器单元Rm的信号输出端OUTPUT和与其相邻的上一个移位寄存器单元Rm-1的复位信号端RESET相连接。OUTPUT_n为第n级移位寄存器单元的输出信号。
另外，如图4所示，在该栅极驱动装置中，相邻两级移位寄存器单元的 第一时钟信号端输入的时钟信号互为反相，相邻两级移位寄存器单元的第二时钟信号端输入的时钟信号互为反相。例如移位寄存器单元Rn的第一时钟信号端输入CLK信号，第二时钟信号端输入CLKB信号，移位寄存器单元Rn+1的第一时钟信号端输入CLKB信号，第二时钟信号端输入CLK信号，其中CLK信号和CLKB信号互为反相。
此外，DCF1和DCF2分别是第一控制信号端CL1和第二控制信号端CL2输出的控制信号，在一帧以内DCF1和DCF2都是直流信号。VGL和VGH分别是第三低电压源P1和第四低电压源P2输出的电压信号。
图5示出了根据本发明实施例的移位寄存器单元进行正向扫描时的时序图。以下将参考图5对根据本发明实施例的上述移位寄存器单元100的具体工作过程进行描述。下面以上述晶体管均为N型晶体管为例进行说明。
首先需要说明的是，根据本发明实施例的上述移位寄存器单元100能够进行双向扫描。其中，在进行正向扫描和反向扫描时，所述移位寄存器单元的结构不发生改变，只是信号输入端和复位信号端的功能发生转变。例如，当正向扫描时，从第一电源输入端UD输入高电平信号VDD，从第二电源输入端DU输入低电平信号VSS；当反向扫描时，从第一电源输入端UD输入低电平信号VSS，从第二电源输入端DU输入高电平信号VDD。正向扫描时的信号输入端INPUT用作反向扫描时的复位信号端RESET，而正向扫描时的复位信号端RESET则用作反向扫描时的信号输入端INPUT。
首先结合图5所示的正向扫描时的时序图，对根据本发明实施例的移位寄存器单元在正向扫描时的工作过程进行描述。在正向扫描过程中，从第一电源输入端UD输入高电平信号VDD，第一晶体管T1保持导通；从第二电源输入端DU输入低电平信号VSS，第二晶体管T2保持截止。对于连续的两帧画面，该工作过程包含以下几个步骤。
在第一帧期间，第一下拉维持单元104工作,第二控制信号端CL2输出的控制信号DCF2为低电平，第十二晶体管T12截止，不影响第一节点PD1的电位；第二下拉维持单元105不工作，第一控制信号端CL1输出的控制信号DCF1为高电平，第十八晶体管T18一直导通，所以第二节点PD2一直是低电平，由此减轻第二下拉维持单元105中第十四晶体管T14和第十七晶体管T17的电应力。
如图5所示，该工作过程在第一帧期间可以细分为以下几个阶段。
第一阶段a-1：通过控制单元和自举单元使得所述移位寄存器输出低电平信号。从第一电源输入端UD输入高电平信号VDD，响应于该高电平的输入信号，第一晶体管T1导通。移位寄存器单元(Rn)的信号输入端INPUT输入高电平信号，其中，该信号输入端INPUT的输入信号为上一级移位寄存器单元(Rn-1)的信号输出端OUTPUT的输出信号(第一个移位寄存器单元R1的信号输入端INPUT输入帧起始信号STV)。此时第一时钟信号端CK的时钟信号CLK为高电平，第三晶体管T3导通，信号输入端INPUT上的高电平输入信号从第三晶体管T3输入，对第一电容C1进行充电，此时控制单元102的第一输出端output1处为高电平。同时，第四晶体管T4导通，第一时钟信号端CK的时钟信号CLK的电压经过第四晶体管T4输出到控制单元102的第三输出端output3。由于第一控制信号端CL1输出的控制信号DCF1是高电平，因此第七晶体管T7和第九晶体管T9导通。第三输出端output3上的高电平通过第七晶体管T7将第一节点PD1充电到高电平。第一时钟信号端CK的时钟信号CLK为高电平，因此第十晶体管T10也导通，第四低电压源P2输出的电压信号VGH传输到第一节点PD1，第十一晶体管T11导通，信号输出端OUTPUT的电位被拉到第三低电压源P1输出的低电平。由于控制单元102的第一输出端output1处为高电平，因此第六晶体管T6导通，第二时钟信号端CKB的时钟信号CLKB为低电平，因此信号输出端OUTPUT输出低电平信号。由于第一节点PD1为高电平，因此第八晶体管T8导通，控制单元102的第二输出端output2的电位被拉到第三低电压源P1输出的低电平。由于第二时钟信号端CKB的时钟信号CLKB为低电平，因此第四晶体管T4截止，防止第一输出端output1的电位被拉低。由于第一控制信号端CL1输出的控制信号DCF1是高电平，因此第十八晶体管T18导通，第二节点PD2的电位被拉到第三低电压源P1输出的低电平。由于第二控制信号端CL2输出的控制信号DCF2是低电平，因此第十二晶体管T12截止。
第二阶段b-1：通过控制单元和自举单元使得所述移位寄存器输出高电平信号。移位寄存器单元(Rn)的信号输入端INPUT输入低电平信号，其中，该信号输入端INPUT的输入信号为上一级移位寄存器单元(Rn-1)的信 号输出端OUTPUT的输出信号(第一个移位寄存器单元R1的信号输入端INPUT输入帧起始信号STV)。第一时钟信号端CK的时钟信号CLK为低电平，第三晶体管T3截止，第二时钟信号端CKB的时钟信号CLKB为高电平，第一输出端output1的电位被锁存为高电平。此外，由于第一输出端output1为高电平，第六晶体管T6导通，第二时钟信号端CKBCLKB的时钟信号为高电平，根据第一电容C1的电荷保持原理，第一输出端output1的电位进一步升高。因为第一时钟信号端CK的时钟信号CLK为低电平，因此第十晶体管T10截止，第四低电压源P2输出的电压信号VGH不能传输到第一节点PD1。由于第一输出端output1为高电平，第五晶体管T5导通，还由于第一控制信号端CL1输出的控制信号DCF1是高电平，第七晶体管T7导通，因此第一时钟信号端CK的低电平时钟信号CLK经过第五晶体管T5和第七晶体管T7将第一节点PD1的电位拉低到低电平，第八晶体管T8和第十一晶体管T11因此截止，不影响信号输出端OUTPUT的输出。由于第一输出端output1的电位为高电平，因此第六晶体管T6导通，第二时钟信号端CKB的时钟信号CLKB为高电平，因此信号输出端OUTPUT输出高电平信号。
第三阶段c-1：通过控制单元和自举单元使得所述移位寄存器输出低电平信号。移位寄存器单元(Rn)的信号输入端INPUT输入低电平信号，其中，该信号输入端INPUT的输入信号为上一级移位寄存器单元(Rn-1)的信号输出端OUTPUT的输出信号(第一个移位寄存器单元R1的信号输入端INPUT输入帧起始信号STV)。第一时钟信号端CK的时钟信号CLK为高电平，第三晶体管T3导通，信号输入端INPUT上的低电平信号经过第三晶体管T3将第一输出端output1拉低到低电平，第五晶体管T5和第六晶体管T6截止。由于第一控制信号端CL1输出的控制信号DCF1是高电平，第一时钟信号端CK的时钟信号CLK是高电平，因此第九晶体管T9和第十晶体管T10分别导通，第四低电压源P2输出的高电压信号VGH传输到第一节点PD1，第十一晶体管T11导通，信号输出端OUTPUT的电位被拉到第三低电压源P1输出的低电平。同时第八晶体管T8导通，控制单元102的第二输出端output2的电位被拉到第三低电压源P1输出的低电平。
在第三阶段之后，通过控制单元和自举单元使得所述移位寄存器持续输出低电平信号，直至下一帧到来。其中，第二时钟信号端CKB的时钟信号 CLKB和第一时钟信号端CK的时钟信号CLK继续交替输入高、低电平信号，其它输入信号和输出信号保持不变，直至下一帧到来，所述移位寄存器单元接收到信号输入端INPUT的高电平信号后，重新执行上述各个阶段。
在第二帧期间，第二下拉维持单元105工作,第一控制信号端CL1输出的控制信号DCF1为低电平，第十八晶体管T18截止，不影响第二节点PD2的电位；第一下拉维持单元104不工作，第二控制信号端CL2输出的控制信号DCF2为高电平，第十二晶体管T12一直导通，所以第一节点PD1一直是低电平，由此减轻第一下拉维持单元104中第八晶体管T8和第十一晶体管T11的电应力。
第二帧期间的第一阶段a-2、第二阶段b-2和第三阶段c-2的时序原理与第一帧期间的对应阶段相似，除了在第二帧期间第一控制信号端CL1输出的控制信号为低电平、第二控制信号端CL2输出的控制信号为高电平、第一节点PD1的电压曲线与第一帧期间第二节点PD2的电压曲线相同、第二节点PD2的电压曲线与第一帧期间第一节点PD1的电压曲线相同之外，其它输入信号和输出信号均与第一帧期间的对应信号相同，在此不再赘述。
根据本发明实施例的移位寄存器单元在反向扫描时的具体工作过程与正向扫描时的工作过程相似，在此不再赘述。
从以上的描述可以看出，根据本发明实施例的移位寄存器单元通过两帧画面共享扫描方向选择单元101、控制单元102、自举单元103，在两帧之间交替使用第一下拉维持单元104和第二下拉维持单元105，避免PD点(PD1或PD2)一直处在某个工作状态，因此可以减轻相应下拉维持单元中部分关键TFT(T8、T11、T14、T17)的电应力，从而提高了工作稳定性，延长了使用寿命；同时，根据本发明实施例的移位寄存器单元中采用的晶体管较少，因而能够实现液晶显示器的窄边框设计。
根据本发明实施例的栅极驱动装置可以采用GOA技术，用作显示装置的栅极驱动电路，以提供逐行扫描功能，将扫描信号传送至显示区域。
本发明还提供了一种包含上述栅极驱动装置的显示装置。
这里的显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限 于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年9月16日递交的中国专利申请第201510590964.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (16)

  1. 一种移位寄存器单元，包含：
    扫描方向选择单元，连接第一电源输入端、第二电源输入端、信号输入端和复位信号端，配置为在第一电源输入端输入的电压的控制下将信号输入端的输入信号或者在第二电源输入端输入的电压的控制下将复位信号端的输入信号提供至该扫描方向选择单元的输出端；
    控制单元，输入端连接扫描方向选择单元的输出端，配置为根据扫描方向选择单元的输出端的信号分别在控制单元的第一输出端提供第一输出信号、在控制单元的第二输出端提供第二输出信号和在控制单元的第三输出端提供第三输出信号；
    自举单元，输入端连接控制单元的第一输出端，配置为根据该第一输出端的所述第一输出信号在该移位寄存器单元的信号输出端输出信号；
    第一下拉维持单元，其第一输入端连接控制单元的第二输出端，其第二输入端连接控制单元的第三输出端，配置为根据控制单元的第二输出端的第二输出信号和控制单元的第三输出端的第三输出信号向所述信号输出端输出信号；
    第二下拉维持单元，其第一输入端连接控制单元的第二输出端，其第二输入端连接控制单元的第三输出端，配置为根据控制单元的第二输出端的第二输出信号和控制单元的第三输出端的第三输出信号向所述信号输出端输出信号；
    其中，在两帧之间交替使用第一下拉维持单元以及第二下拉维持单元。
  2. 根据权利要求1所述的移位寄存器单元，其中，控制单元包含：
    第一开关单元，输入端连接扫描方向选择单元的输出端，配置为根据扫描方向选择单元的输出端的信号向控制单元的第一输出端、第二开关单元以及下拉单元提供所述第一输出信号；
    第二开关单元，输入端连接第一开关单元的输出端，配置为根据第一开关单元的输出端的所述第一输出信号向控制单元的第二输出端提供所述第二输出信号；
    下拉单元，输入端连接第一开关单元的输出端，配置为根据第一开关单 元的输出端的所述第一输出信号向控制单元的第三输出端提供所述第三输出信号。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，扫描方向选择单元包含：
    第一晶体管，其栅极连接至第一电源输入端，源极连接至信号输入端；
    第二晶体管，其栅极连接至第二电源输入端，源极连接至复位信号端；
    第一晶体管的漏极和第二晶体管的漏极相互连接，构成扫描方向选择单元的输出端。
  4. 根据权利要求2所述的移位寄存器单元，其中，
    第一开关单元包含第三晶体管，其栅极连接至第一时钟信号端，源极连接至扫描方向选择单元的输出端，漏极作为第一开关单元的输出端连接至控制单元的第一输出端；
    第二开关单元包含第四晶体管，其栅极连接至第二时钟信号端，源极连接至控制单元的第一输出端，漏极作为该第二开关单元的输出端连接至控制单元的第二输出端；
    下拉单元包含第五晶体管，其栅极连接至控制单元的第一输出端，源极连接至第一时钟信号端，漏极作为该下拉单元的输出端连接至控制单元的第三输出端。
  5. 根据权利要求1-4中任一项所述的移位寄存器单元，其中自举单元包含：
    第六晶体管，其栅极连接至控制单元的第一输出端，源极连接至第二时钟信号端，漏极连接至信号输出端；
    第一电容，其一端连接至信号输出端，另一端连接至控制单元的第一输出端。
  6. 根据权利要求1-5中任一项所述的移位寄存器单元，其中第一下拉维持单元包含：
    第七晶体管，其栅极连接至第一控制信号端，源极连接至控制单元的第三输出端，漏极连接至第一节点；
    第八晶体管，其栅极连接至第一节点，源极连接至第三低电压源，漏极连接至控制单元的第二输出端；
    第九晶体管，其栅极连接至第一控制信号端，源极连接至第十晶体管的漏极，漏极连接至第一节点；
    第十晶体管，其栅极连接至第一时钟信号端，源极连接至第四低电压源；
    第十一晶体管，其栅极连接至第一节点，源极连接至第三低电压源，漏极连接至信号输出端；
    第十二晶体管，其栅极连接至第二控制信号端，源极连接至第三低电压源，漏极连接至第一节点。
  7. 根据权利要求1-6中任一项所述的移位寄存器单元，第二下拉维持单元包含：
    第十三晶体管，其栅极连接至第二控制信号端，源极连接至控制单元的第三输出端，漏极连接至第二节点；
    第十四晶体管，其栅极连接至第二节点，源极连接至第三低电压源，漏极连接至控制单元的第二输出端；
    第十五晶体管，其栅极连接至第二控制信号端，源极连接至第十六晶体管的漏极，漏极连接至第二节点；
    第十六晶体管，其栅极连接至第一时钟信号端，源极连接至第四低电压源；
    第十七晶体管，其栅极连接至第二节点，源极连接至第三低电压源，漏极连接至信号输出端；
    第十八晶体管，其栅极连接至第一控制信号端，源极连接至第三低电压源，漏极连接至第二节点。
  8. 根据权利要求1-7中任一项所述的移位寄存器单元，其中
    在正向扫描时，从第一电源输入端输入高电平信号，从第二电源输入端输入低电平信号；
    在反向扫描时，从第一电源输入端输入低电平信号，从第二电源输入端输入高电平信号；
    其中，正向扫描时的信号输入端用作反向扫描时的复位信号端，正向扫描时的复位信号端用作反向扫描时的信号输入端。
  9. 根据权利要求1-8中任一项所述的移位寄存器单元，其中所述移位寄存器单元的第二时钟信号端的时钟信号与第一时钟信号端的时钟信号反相。
  10. 一种栅极驱动装置，包含多个串联的移位寄存器单元，每个所述移位寄存器单元是如权利要求1-9中任一项所述的移位寄存器单元，
    其中所述多个串联的移位寄存器单元中除第一个移位寄存器单元和最后一个移位寄存器单元外，其余每个移位寄存器单元的信号输出端均和与其相邻的下一个移位寄存器单元的信号输入端以及与其相邻的上一个移位寄存器单元的复位信号端相连，
    所述第一个移位寄存器单元的信号输入端输入帧起始信号，信号输出端与第二个移位寄存器单元的信号输入端连接，所述最后一个移位寄存器单元的信号输出端和与其相邻的上一个移位寄存器单元的复位信号端相连接。
  11. 根据权利要求10所述的栅极驱动装置，其中
    相邻两级移位寄存器单元的第一时钟信号端输入的时钟信号互为反相，第二时钟信号端输入的时钟信号互为反相。
  12. 根据权利要求10或11所述的栅极驱动装置，该栅极驱动装置是采用了GOA的栅极驱动装置。
  13. 一种包含根据权利要求10-12中任一项所述的栅极驱动装置的显示装置。
  14. 一种移位寄存器单元的驱动方法，该移位寄存器单元包含扫描方向选择单元、控制单元、自举单元、第一下拉维持单元以及第二下拉维持单元，对于连续的两帧画面，该方法包含：
    通过扫描方向选择单元选择扫描方向；
    在第一帧期间，使得第二下拉维持单元不工作，并且通过控制单元控制第一下拉维持单元工作；
    在第二帧期间，使得第一下拉维持单元不工作，并且通过控制单元控制第二下拉维持单元工作。
  15. 根据权利要求14所述的驱动方法，该方法在第一帧期间包含：
    在第一阶段，通过控制单元和自举单元使得所述移位寄存器输出低电平信号；
    在第二阶段，通过控制单元和自举单元使得所述移位寄存器输出高电平信号；
    在第三阶段，通过控制单元和自举单元使得所述移位寄存器输出低电平 信号；
    在第三阶段之后，通过控制单元和自举单元使得所述移位寄存器持续输出低电平信号，直至下一帧到来。
  16. 根据权利要求14或15所述的驱动方法，该方法在第二帧期间包含：
    在第一阶段，通过控制单元和自举单元使得所述移位寄存器输出低电平信号；
    在第二阶段，通过控制单元和自举单元使得所述移位寄存器输出高电平信号；
    在第三阶段，通过控制单元和自举单元使得所述移位寄存器输出低电平信号；
    在第三阶段之后，通过控制单元和自举单元使得所述移位寄存器持续输出低电平信号，直至下一帧到来。
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