WO2017118136A1 - 移位寄存器及其驱动方法、栅极驱动电路以及显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路以及显示装置 Download PDF

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Publication number
WO2017118136A1
WO2017118136A1 PCT/CN2016/101987 CN2016101987W WO2017118136A1 WO 2017118136 A1 WO2017118136 A1 WO 2017118136A1 CN 2016101987 W CN2016101987 W CN 2016101987W WO 2017118136 A1 WO2017118136 A1 WO 2017118136A1
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Prior art keywords
transistor
pole
signal
high level
level pulse
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PCT/CN2016/101987
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English (en)
French (fr)
Inventor
郑灿
宋松
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京东方科技集团股份有限公司
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Priority to US15/519,966 priority Critical patent/US9966957B2/en
Publication of WO2017118136A1 publication Critical patent/WO2017118136A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • FIG. 1 is a schematic diagram of a pulse signal for an OLED (Organic Light-Emitting Diode) pixel circuit.
  • OLED Organic Light-Emitting Diode
  • G1, G2 and one high-level pulse signal G3 are required when writing data to the OLED pixel unit.
  • These signals G1, G2, G3 need to be provided by the shift register circuit.
  • the number of pixels increases, the number of rows that the shift register needs to scan in one frame time increases.
  • Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device that can be applied to a narrow bezel display using fewer circuit elements.
  • a shift register including a control signal The number generation module, the first low level pulse generation module, the second low level pulse generation module, and the high level pulse generation module.
  • the control signal generating module is connected to the first clock terminal, the second clock terminal, the first voltage terminal, the second voltage terminal, and the first input terminal, and is configured to generate the first control signal and the second control signal.
  • the first low level pulse generating module is coupled to the second clock terminal and the first voltage terminal, and configured to receive the first control signal and the second control signal from the control signal generating module, and generate a first low level pulse signal .
  • the second low level pulse generating module is coupled to the third clock terminal and the first voltage terminal, and configured to receive the first control signal and the second control signal from the control signal generating module, and generate a second low level pulse signal .
  • the high level pulse generating module is coupled to the first clock terminal, the first voltage terminal, the second voltage terminal, and the second input terminal, and configured to receive the first control signal from the control signal generating module and generate a high level pulse signal.
  • the control signal generating module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor.
  • the control electrode of the first transistor is connected to the first clock terminal, the first pole is connected to the first input terminal, and the second pole is connected to the second pole of the second transistor.
  • the control electrode of the second transistor is connected to the second clock terminal, the first pole is connected to the second pole of the third transistor, and the second pole is connected to the second pole of the first transistor.
  • the control electrode of the third transistor is connected to the first pole of the fourth transistor, the first pole is connected to the first voltage terminal, and the second pole is connected to the first pole of the second transistor.
  • the control electrode of the fourth transistor is connected to the first clock terminal, the first pole is connected to the control electrode of the third transistor, and the second pole is connected to the second voltage terminal.
  • the control electrode of the fifth transistor is connected to the second electrode of the first transistor, the first electrode is connected to the control electrode of the third transistor, and the second electrode is connected to the first clock terminal.
  • the first capacitor is connected between the first voltage terminal and the control electrode of the third transistor.
  • a junction of the second pole of the first transistor and the second pole of the second transistor forms a first control signal output for outputting the first control signal.
  • a junction of the gate of the third transistor and the first pole of the fourth transistor forms a second control signal output for outputting a second control signal.
  • the first low level pulse generating module includes a sixth transistor, a seventh transistor, and a second capacitor.
  • the control electrode of the sixth transistor is configured to receive the first control signal, the first pole of the sixth transistor is connected to the second pole of the seventh transistor, and the second pole and the second clock End connection.
  • the gate of the seventh transistor is configured to receive the second control signal, the first pole of the seventh transistor is coupled to the first voltage terminal, and the second pole is coupled to the first pole of the sixth transistor.
  • the second capacitor is connected between the first pole of the sixth transistor and the gate of the sixth transistor.
  • a connection point of the first pole of the sixth transistor and the second pole of the seventh transistor forms a first low-level pulse output terminal for outputting the first low-level pulse signal.
  • the second low level pulse generating module includes an eighth transistor, a ninth transistor, and a third capacitor.
  • the gate of the eighth transistor is configured to receive the first control signal, the first pole of the eighth transistor is coupled to the second pole of the ninth transistor, and the second pole is coupled to the third clock terminal.
  • the control electrode of the ninth transistor is configured to receive the second control signal, the first pole of the ninth transistor is coupled to the first voltage terminal, and the second pole is coupled to the first pole of the eighth transistor.
  • the third capacitor is connected between the first pole of the eighth transistor and the gate of the eighth transistor. A junction of the first pole of the eighth transistor and the second pole of the ninth transistor forms a second low level pulse output for outputting a second low level pulse signal.
  • the high level pulse generating module includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a fourth capacitor, and a Five capacitors.
  • the control electrode of the tenth transistor is connected to the first clock terminal, the first pole is connected to the first voltage terminal, and the second pole is connected to the first pole of the eleventh transistor.
  • the control electrode of the eleventh transistor is connected to the second input terminal, the first pole is connected to the second pole of the tenth transistor, and the second pole is connected to the first pole of the twelfth transistor.
  • the control electrode of the twelfth transistor is configured to receive the first control signal, the first pole of the twelfth transistor is coupled to the second pole of the eleventh transistor, and the second pole is coupled to the second voltage terminal.
  • the control electrode of the thirteenth transistor is connected to the first clock terminal, the first pole is connected to the second input terminal, and the second pole is connected to the control electrode of the fifteenth transistor.
  • the control electrode of the fourteenth transistor is connected to the second electrode of the eleventh transistor, the first pole is connected to the first clock terminal, and the second pole is connected to the first pole of the fifteenth transistor.
  • the control electrode of the fifteenth transistor is connected to the second pole of the thirteenth tube, the first pole is connected to the second pole of the fourteenth transistor, and the second pole is connected to the second voltage terminal.
  • the fourth capacitor is connected between the first voltage terminal and the control electrode of the fourteenth transistor.
  • a fifth capacitor is connected between the first pole of the fifteenth transistor and the gate of the fifteenth transistor. a connection point between the second pole of the fourteenth transistor and the first pole of the fifteenth transistor is formed for outputting high power The high level pulse output of the flat pulse signal.
  • a method for driving the shift register described above comprising: providing a low level signal at a first clock terminal and a high level at a second clock terminal in a first phase
  • the signal provides a high level signal at the third clock terminal, a low level signal at the first input terminal, and a high level signal at the second input terminal to cause the shift register to output a first low level of a high level
  • the pulse signal, the second low level pulse signal of the high level and the high level pulse signal of the low level In the second phase, a high level signal is provided at the first clock terminal, a low level signal is provided at the second clock terminal, a high level signal is provided at the third clock terminal, and a high level signal is provided at the first input terminal.
  • the second input terminal provides a high level signal, so that the shift register outputs a low level first low level pulse signal, a high level second low level pulse signal and a high level high level pulse signal.
  • a high level signal is provided at the first clock terminal
  • a high level signal is provided at the second clock terminal
  • a low level signal is provided at the third clock terminal
  • a high level signal is provided at the first input terminal.
  • the second input terminal provides a low level signal, so that the shift register outputs a first low level pulse signal of a high level, a second low level pulse signal of a low level, and a high level pulse signal of a high level.
  • a low level signal is provided at the first clock terminal, a high level signal is provided at the second clock terminal, a high level signal is provided at the third clock terminal, and a high level signal is provided at the first input terminal.
  • the second input terminal provides a low level signal, so that the shift register outputs a first low level pulse signal of a high level, a second low level pulse signal of a high level, and a high level pulse signal of a low level.
  • a gate driving circuit comprising a plurality of the above-described shift registers cascaded, wherein each stage shift register provides a first low level pulse signal, and a second Low level pulse signal and high level pulse signal.
  • each stage shift register provides a first low level pulse signal, and a second Low level pulse signal and high level pulse signal.
  • the first stage shift register provides a first low level pulse signal to the first input end of the shift register
  • the upper stage shift register provides high power to the second input end of the shift register Flat pulse signal.
  • a display device comprising the above-described gate drive circuit.
  • three different pulse signals can be generated in one shift register, which greatly reduces components and control compared with the technique of providing three pulse signals by three circuits respectively.
  • FIG. 1 is a schematic diagram of a pulse signal for an OLED pixel circuit
  • FIG. 2 is a circuit diagram showing the first low level pulse signal of FIG. 1;
  • FIG. 3 is a circuit diagram showing the second low level pulse signal of FIG. 1;
  • FIG. 4 is a circuit diagram showing the high level pulse signal of FIG. 1;
  • FIG. 5 is a schematic block diagram of a shift register in accordance with an embodiment of the present disclosure.
  • Figure 6 is an exemplary circuit diagram for explaining the shift register shown in Figure 5;
  • Figure 7 is a diagram for explaining the operation timing of the shift register shown in Figure 6;
  • FIG. 8 is a schematic block diagram of a gate drive circuit of one embodiment of the present disclosure.
  • FIG. 9 is a schematic block diagram of a gate drive circuit of another embodiment of the present disclosure.
  • the signals G1, G2, G3 in Fig. 1 can be generated by three circuits, respectively.
  • 2 is a circuit diagram showing the first low level pulse signal of FIG. 3 is a circuit diagram showing the second low level pulse signal of FIG. 4 is a circuit diagram showing the high level pulse signal of FIG. 1.
  • a total of 28 transistors and 7 capacitors are used in the three circuits, and for each circuit, different clocks, input signals, and the like are required for driving.
  • the number of circuit components is large, and the structure is complicated, and the occupied area is large, which is difficult to apply to a display with a narrow bezel.
  • FIG. 5 is a schematic block diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the shift register includes a control signal generating module, a first low level pulse generating module, a second low level pulse generating module, and a high level pulse generating module.
  • the control signal generating module is connected to the first clock terminal CK1, the second clock terminal CK2, the first voltage terminal VGH, the second voltage terminal VGL, and the first input terminal STVG, and is configured to generate the first control signal and the second control signal.
  • the first control signal and the second control signal are output to the first low level pulse generating module, the second low level pulse generating module, and the high level pulse generating module.
  • the first low level pulse generating module is coupled to the second clock terminal CK2 and the first voltage terminal VGH, and configured to receive the first control signal and the second control signal from the control signal generating module, and generate a first low level Pulse signal.
  • the second low level pulse generating module is coupled to the third clock terminal CK3 and the first voltage terminal VGH, and configured to receive the first control signal and the second control signal from the control signal generating module, and generate a second low Level pulse signal.
  • the high level pulse generating module is coupled to the first clock terminal CK1, the first voltage terminal VGH, the second voltage terminal VGL, and the second input terminal STVE, and is configured to receive the first control signal from the control signal generating module, And generate a high level pulse signal.
  • multiplexing of control signals is realized for the three pulse generating modules, and the number of circuit elements used in the shift register can be reduced.
  • Fig. 6 is a schematic circuit diagram for explaining the shift register shown in Fig. 5.
  • the control signal generating module includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.
  • the control electrode of the first transistor T1 is connected to the first clock terminal CK1, the first electrode is connected to the first input terminal STVG, and the second electrode is connected to the second electrode of the second transistor T2.
  • the control electrode of the second transistor T2 is connected to the second clock terminal CK2, the first electrode is connected to the second electrode of the third transistor T3, and the second electrode is connected to the second electrode of the first transistor T1.
  • the control electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4, the first electrode is connected to the first voltage terminal VGH, and the second electrode is connected to the first electrode of the second transistor T2.
  • the control electrode of the fourth transistor T4 is connected to the first clock terminal CK1, the first electrode is connected to the control electrode of the third transistor T3, and the second electrode is connected to the second voltage terminal VGL.
  • the control electrode of the fifth transistor T5 is connected to the second electrode of the first transistor T1, and the first electrode is connected to the control electrode of the third transistor T3.
  • the second pole is connected to the first clock terminal CK1.
  • the first capacitor C1 is connected between the first voltage terminal VGH and the control electrode of the third transistor T3.
  • a connection point of the second pole of the first transistor T1 and the second pole of the second transistor T2 forms a first control signal output terminal Q.
  • a connection point of the control electrode of the third transistor T3 and the first electrode of the fourth transistor T4 forms a second control signal output terminal P.
  • the first low level pulse generating module includes a sixth transistor T6, a seventh transistor T7, and a second capacitor C2.
  • the control electrode of the sixth transistor T6 is connected to the first control signal output terminal Q, that is, configured to receive the first control signal, the first pole of the sixth transistor T6 is connected to the second pole of the seventh transistor T7, and the second pole and the second The two clock terminals are connected to CK2.
  • the control electrode of the seventh transistor T7 is connected to the second control signal output terminal P, that is, configured to receive the second control signal, and the first electrode of the seventh transistor T7 is connected to the first voltage terminal VGH, and the second and sixth transistors are connected.
  • the first pole of the T6 is connected.
  • the second capacitor C2 is connected between the first pole of the sixth transistor T6 and the gate of the sixth transistor T6.
  • a connection point of the first pole of the sixth transistor T6 and the second pole of the seventh transistor T7 forms a first low-level pulse output terminal Reset for outputting the first low-level pulse signal.
  • the second low level pulse generating module includes an eighth transistor T8, a ninth transistor T9, and a third capacitor C3.
  • the control electrode of the eighth transistor T8 is connected to the first control signal output terminal Q, that is, configured to receive the first control signal, the first pole of the eighth transistor T8 is connected to the second pole of the ninth transistor T9, and the second pole is connected to the third pole.
  • the control electrode of the ninth transistor T9 is connected to the second control signal output terminal P, that is, configured to receive the second control signal, the first pole of the ninth transistor T9 is connected to the first voltage terminal VGH, and the second pole is connected to the eighth transistor T8.
  • the third capacitor C3 is connected between the first pole of the eighth transistor T8 and the gate of the eighth transistor T8.
  • a connection point of the first pole of the eighth transistor T8 and the second pole of the ninth transistor T9 forms a second low-level pulse output terminal Gate for outputting a second low-level pulse signal.
  • the high-level pulse generating module includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a fourth capacitor C4, and a fifth capacitor.
  • C5 The control electrode of the tenth transistor T10 is connected to the first clock terminal CK1, the first electrode is connected to the first voltage terminal VGH, and the second electrode is connected to the first electrode of the eleventh transistor T11.
  • the control electrode of the eleventh transistor T11 is connected to the second input terminal STVE, the first pole is connected to the second pole of the tenth transistor T10, and the first pole is coupled to the first of the twelfth transistor T12. Extremely connected.
  • the control electrode of the twelfth transistor T12 is connected to the first control signal output terminal Q, that is, configured to receive the first control signal, and the first pole of the twelfth transistor T12 is connected to the second pole of the eleventh transistor T11, The two poles are connected to the second voltage terminal VGL.
  • the control electrode of the thirteenth transistor T13 is connected to the first clock terminal CK1, the first electrode is connected to the second input terminal STVE, and the second electrode is connected to the control electrode of the fifteenth transistor T15.
  • the control electrode of the fourteenth transistor T14 is connected to the second electrode of the eleventh transistor T11, the first electrode is connected to the first clock terminal CK1, and the second electrode is connected to the first electrode of the fifteenth transistor T15.
  • the control electrode of the fifteenth transistor T15 is connected to the second pole of the thirteenth transistor T13, the first pole is connected to the second pole of the fourteenth transistor T14, and the second pole is connected to the second voltage terminal VGL.
  • the fourth capacitor C4 is connected between the first voltage terminal VGH and the control electrode of the fourteenth transistor T14.
  • the fifth capacitor C5 is connected between the first pole of the fifteenth transistor T15 and the gate of the fifteenth transistor T15.
  • a connection point of the second pole of the fourteenth transistor T14 and the first pole of the fifteenth transistor T15 forms a high-level pulse output terminal EM for outputting a high-level pulse signal.
  • the N point represents the connection point of the first pole of the twelfth transistor T12, the gate electrode of the fourteenth transistor T14, and the second pole of the fourth capacitor C4.
  • Point M represents the connection point of the second pole of the thirteenth transistor T13, the gate electrode of the fifteenth transistor T15, and the second pole of the fifth capacitor C5.
  • three pulse generation modules are realized using fewer circuit elements, and the number of circuit elements used in the shift register can be reduced.
  • Fig. 7 is a schematic diagram for explaining an operation timing of the shift register shown in Fig. 6.
  • the operation timing of the shift register in this example includes a first phase, a second phase, a third phase, and a fourth phase.
  • the signal state and the transistor state of each stage will be described by taking a transistor in the shift register as a P-type thin film transistor TFT as an example, and in this example, the clock terminal, the input terminal, and the second voltage terminal VGL are represented by VL.
  • the low level voltage is supplied, and VH is used to indicate the high level voltage supplied from the clock terminal, the input terminal and the first voltage terminal VGH.
  • the signal of the first clock terminal CK1, the signal of the second clock terminal CK2, and the signal of the third clock terminal CK3 are clock signals that are periodically switched between high and low levels, and the duty ratio of the low level is 33. %.
  • a low level signal is provided at the first clock end, a high level signal is provided at the second clock end, a high level signal is provided at the third clock end, and a low level signal is provided at the first input end.
  • the voltage of the first input terminal STVG and the first clock terminal CK1 jumps to a low level, and the first transistor T1 is turned on, and the voltage of the first input terminal STVG is low. It is passed to the first control signal output terminal Q. Since the P-type TFT transmits a low level with a threshold loss, the first control signal output terminal Q voltage is the sum of VL and the absolute value of the first transistor T1 threshold voltage Vthp. The sixth transistor T6 is turned on, and since the voltage of the second clock terminal CK2 is at this time high level, the voltage of the first low-level pulse output terminal Reset is at a high level.
  • the fourth transistor T4 is turned on, and the voltage of the second control signal output terminal P is pulled low, and the eighth transistor T8 and the ninth transistor T9 are turned on, and will be first.
  • the low-level pulse output terminal Reset and the second low-level pulse output terminal Gate are pulled high.
  • the thirteenth transistor T13 is turned on, and since the voltage of the second input terminal STVE becomes a high level in the first phase t1, the M point voltage becomes a high level, and the fifteenth transistor T15 is turned off.
  • a high level signal is provided at the first clock terminal, a low level signal is provided at the second clock terminal, a high level signal is provided at the third clock terminal, and a high level signal is provided at the first input terminal.
  • the second input terminal provides a high level signal, so that the shift register outputs a first low level pulse signal of a low level, a second low level pulse signal of a high level, and a high level pulse of a high level. signal.
  • the voltage of the first input terminal STVG and the first clock terminal CK1 jumps to a high level
  • the voltage of the second clock terminal CK2 jumps to a low level. Since the sixth transistor T6 is turned on in the first phase t1, the low level voltage of the second clock terminal CK2 is transmitted to the first control signal output terminal Q through the sixth transistor T6, and the fifth transistor T5 is turned on, and the second The voltage of the control signal output terminal P is pulled up to a high level of the voltage of the first clock terminal CK1.
  • the third transistor T3, the eighth transistor T8, and the ninth transistor T9 are turned off, because the first transistor T1 is also In the off state, the gate of the sixth transistor T6 is in a floating state, and the voltage across the capacitor of the second capacitor C2 cannot be abruptly changed (the voltage can be expressed as: VL+
  • the third transistor T3 operates in the linear region, and the voltage of the low level of the second clock terminal CK2 is transferred to the first low-level pulse output terminal Reset without a threshold loss, and the first low-level pulse output terminal Reset voltage is low. Voltage.
  • the low level voltage of the first control signal output terminal Q also causes the twelfth transistor T12 to operate in the linear region, the voltage at the N point is a low level voltage, and the fourteenth transistor T14 is well turned on, and the first clock terminal
  • the high level voltage of CK1 is output to the high level pulse signal output terminal EM.
  • the low level voltage of the first control signal output terminal Q also turns on the seventh transistor T7, and outputs the high level voltage of the third clock terminal CK3 to the second low level pulse output terminal Gate.
  • a high level signal is provided at the first clock terminal, a high level signal is provided at the second clock terminal, a low level signal is provided at the third clock terminal, and a high level signal is provided at the first input terminal.
  • the second input terminal provides a low level signal, so that the shift register outputs a first low level pulse signal of a high level, a second low level pulse signal of a low level, and a high level pulse of a high level. signal.
  • the voltage of the second clock terminal CK2 jumps to a high level
  • the voltage of the third clock terminal CK3 jumps to a low level. Since the voltage across the capacitor C2 cannot be abruptly changed, the voltage of the second clock terminal CK2 and the third clock terminal CK3 is reversed, so the voltage of the first control signal output terminal Q is still 2VL+
  • the sixth transistor T6, the seventh transistor T7, and the twelfth transistor T12 all operate in the linear region, and the sixth transistor T6 transmits the high level voltage of the second clock terminal CK2 to the first low level pulse output terminal Reset, which is the first low
  • the level pulse output terminal Reset is pulled up, and the seventh transistor T7 transmits the low level voltage of the third clock terminal CK3 without threshold loss to the second low level pulse output terminal Gate, and the twelfth transistor T12 remains N.
  • the point voltage is kept at a low level, so that the fourteenth transistor T14 transmits the high-level
  • a low level signal is provided at the first clock terminal, a high level signal is provided at the second clock terminal, a high level signal is provided at the third clock terminal, and a high level signal is provided at the first input terminal.
  • the voltage of the third clock terminal CK3 jumps to a high level, and the voltages of the first clock terminal CK1 and the second input terminal STVE transition to a low level. Since the voltage of the first clock terminal CK1 is at a low level, the fourth transistor T4 is turned on, and the voltage of the second control signal output terminal P is pulled to a low level, and the eighth transistor T8 and the ninth transistor T9 are turned on. The voltage of the low-level pulse output terminal Gate is pulled to a high level, and the voltage of the first low-level pulse output terminal Reset is maintained at a low level.
  • the first clock terminal CK1 the second input terminal STVE jump to a low level
  • the thirteenth transistor T13 is turned on
  • the M point voltage is pulled to a low level
  • the fifteenth transistor T15 is turned on, a high level pulse
  • the voltage of the output terminal EM is pulled to a low level. Since the voltage across the capacitor C4 cannot be abruptly changed, the voltage of the high-level pulse output terminal EM becomes a low level, and the M point is pulled to a lower level, the second The voltage of the low level of the voltage terminal VGL can be transferred to the high-level pulse output terminal EM through the fifteenth transistor T15 without threshold loss.
  • the fifth stage t5 of the non-working state is entered, and the time length of the fifth stage t5 is greater than the above four stages.
  • a signal periodically changing between a high level and a low level is provided at the first clock terminal CK1, and a periodic high level between the high level and the low level is provided at the second clock terminal CK2.
  • the changed signal provides a signal that periodically changes between a high level and a low level at the third clock terminal CK3, a high level signal is provided at the first input terminal STVG, and a low power is provided at the second input terminal STVE.
  • the flat signal is such that the shift register outputs a high level first low level pulse signal, a high level second low level pulse signal, and a low level high level pulse signal.
  • the first transistor T1 and the second transistor T2 are periodically turned on so that the first control signal is output as the voltages of the first clock terminal CK1 and the second clock terminal CK2 periodically change.
  • the voltage of the terminal Q is stably maintained at a high level.
  • the fourth transistor T4 is periodically turned on by the change in the voltage of the first clock terminal CK1, and the first capacitor C1 has a function of holding the voltage, so that the voltage of the second control signal output terminal P is maintained at a low level.
  • the thirteenth transistor T13 is periodically turned on by the change of the voltage of the first clock terminal CK1, and the M point is electrically The voltage is maintained at a lower level; the tenth transistor T10 is periodically turned on by the change of the voltage of the first clock terminal CK1, and the N point voltage is maintained at the high level because the fourth capacitor C4 has the function of holding the voltage .
  • the high level voltage of the first control signal output terminal Q, the low level voltage of the second control signal output terminal P, the lower level voltage of the M point, and the high level voltage of the N point make the first low level
  • the voltage of the pulse output terminal Reset and the second low-level pulse output terminal Gate is maintained at a high level, and the voltage of the high-level pulse output terminal EM is maintained at a low level.
  • FIG. 8 is a schematic block diagram of a gate drive circuit of one embodiment of the present disclosure.
  • the plurality of shift registers GOA are cascaded to form a gate driving circuit, and the first low level pulse output terminal Reset and the second low level pulse output terminal Gate of each stage shift register are The high level pulse output terminal EM is coupled to the pixel unit circuit pixel to provide pulse signals G1, G2, G3 required for writing data to the pixel unit circuit.
  • the first low level pulse output Reset of the previous stage shift register is connected to the first input terminal STVG of the next stage shift register, and the high level of the previous stage shift register
  • the pulse output EM is connected to the second input STVE of the shift register of the next stage.
  • FIG. 9 is a circuit block diagram of a gate drive circuit of another embodiment of the present disclosure.
  • the gate drive circuit of this example includes two columns of cascaded shift registers, and the two columns of cascaded shift registers are used interchangeably.
  • the first low-level pulse output terminal Reset of the first-stage shift register is connected to the first input terminal STVG of the third-stage shift register
  • the high-level pulse of the first-stage shift register is The output EM is connected to the second input STVE of the shift register of the third stage.
  • the first low level pulse output Reset of the second stage shift register is connected to the first input terminal STVG of the fourth stage shift register, and the high level pulse output end EM of the second stage shift register is connected to the fourth stage shift.
  • Embodiments of the present disclosure also provide a display device including the above-described gate driving circuit.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., having any display Functional product or part.
  • three pulse signal generations are realized by one shift register circuit, which reduces the number of circuit components, and can reduce 28 transistors and 7 capacitors to 15 transistors and 5 capacitors, and reduce The number of control signals.
  • the shift register can be cascaded to obtain a gate drive circuit with a smaller number of circuit components, which can meet the requirements of a narrow bezel display.
  • the high level and the low level are only used to distinguish whether the voltage can make the transistor turn on, and the value of the voltage is not limited.
  • a low level may refer to a ground level or a negative level.
  • the selected P-type TFT transistor is a schematic illustration and is not a specific limitation on the type of transistor. Based on the principles of the present disclosure, those skilled in the art will be able to make appropriate selections and adjustments for the types of transistors without undue creative effort, and such selections and adjustments are also considered to be within the scope of the disclosure.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路以及显示装置。该移位寄存器包括控制信号生成模块、第一低电平脉冲生成模块、第二低电平脉冲生成模块以及高电平脉冲生成模块。控制信号生成模块与第一时钟端（CK1）、第二时钟端（CK2）、第一电压端（VGH）、第二电压端（VGL）以及第一输入端（STVG）连接，生成第一控制信号以及第二控制信号。第一低电平脉冲生成模块接收第一控制信号以及第二控制信号，生成第一低电平脉冲信号。第二低电平脉冲生成模块接收第一控制信号以及第二控制信号，生成第二低电平脉冲信号。高电平脉冲生成模块与第一时钟端（CK1）、第一电压端（VGH）、第二电压端（VGL）以及第二输入端（STVE）连接，接收第一控制信号，并生成高电平脉冲信号。该移位寄存器减少了电路元件数量。

Description

移位寄存器及其驱动方法、栅极驱动电路以及显示装置
本申请要求2016年1月5日递交的中国专利申请第201610003941.X号的优先权，在此全文引用上述中国专利申请所公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域，尤其涉及移位寄存器及其驱动方法、栅极驱动电路以及显示装置。
背景技术
在显示技术领域，为了不断改善显示画面，提高用户体验，高清、高PPI(Pixels Per Inch，每英寸像素)、窄边框显示成了研究的热门。在进行显示时，显示器需要逐行扫描将数据信号写入像素单元。图1是用于OLED(Organic Light-Emitting Diode，有机发光二极管)像素电路的脉冲信号的示意图。如图1所示，一般来说，在对OLED像素单元写入数据时需要2个低电平脉冲信号G1、G2与1个高电平脉冲信号G3。这些信号G1、G2、G3需要由移位寄存器电路提供。随着像素数目的增加，移位寄存器在一帧时间内所需扫描的行数增加。在显示屏幕大小不变的情况下，留给每一行移位寄存器的面积逐渐减小。此外窄边框的要求，更是使对于移位寄存器每一行面积的要求更加严苛，因此探寻结构简单、晶体管数目较少的移位寄存器电路十分必要。
公开文本内容
本公开文本的实施例提供了移位寄存器及其驱动方法、栅极驱动电路以及显示装置，使用更少的电路元件，能够应用于窄边框显示器。
根据本公开文本的第一个方面，提供了一种移位寄存器，包括控制信 号生成模块、第一低电平脉冲生成模块、第二低电平脉冲生成模块以及高电平脉冲生成模块。其中，控制信号生成模块与第一时钟端、第二时钟端、第一电压端、第二电压端以及第一输入端连接，并被配置为生成第一控制信号以及第二控制信号。第一低电平脉冲生成模块与第二时钟端以及第一电压端连接，并被配置为接收来自控制信号生成模块的第一控制信号以及第二控制信号，并生成第一低电平脉冲信号。第二低电平脉冲生成模块与第三时钟端以及第一电压端连接，并被配置为接收来自控制信号生成模块的第一控制信号以及第二控制信号，并生成第二低电平脉冲信号。高电平脉冲生成模块与第一时钟端、第一电压端、第二电压端以及第二输入端连接，并被配置为接收来自控制信号生成模块的第一控制信号，并生成高电平脉冲信号。
在本公开文本的实施例中，控制信号生成模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管以及第一电容。第一晶体管的控制极与第一时钟端连接，第一极与第一输入端连接，第二极与第二晶体管的第二极连接。第二晶体管的控制极与第二时钟端连接，第一极与第三晶体管的第二极连接，第二极与第一晶体管的第二极连接。第三晶体管的控制极与第四晶体管的第一极连接，第一极与第一电压端连接，第二极与第二晶体管的第一极连接。第四晶体管的控制极与第一时钟端连接，第一极与第三晶体管的控制极连接，第二极与第二电压端连接。第五晶体管的控制极与第一晶体管的第二极连接，第一极与第三晶体管的控制极连接，第二极与第一时钟端连接。第一电容被连接在第一电压端与第三晶体管的控制极之间。第一晶体管的第二极与第二晶体管的第二极的连接点形成用于输出第一控制信号的第一控制信号输出端。第三晶体管的控制极与第四晶体管的第一极的连接点形成用于输出第二控制信号的第二控制信号输出端。
在本公开文本的实施例中，第一低电平脉冲生成模块包括第六晶体管、第七晶体管以及第二电容。第六晶体管的控制极被配置为接收第一控制信号，第六晶体管的第一极与第七晶体管的第二极连接，第二极与第二时钟 端连接。第七晶体管的控制极被配置为接收第二控制信号，第七晶体管的第一极与第一电压端连接，第二极与第六晶体管的第一极连接。第二电容被连接在第六晶体管的第一极与第六晶体管的控制极之间。第六晶体管的第一极与第七晶体管的第二极的连接点形成用于输出第一低电平脉冲信号的第一低电平脉冲输出端。
在本公开文本的实施例中，第二低电平脉冲生成模块包括第八晶体管、第九晶体管以及第三电容。第八晶体管的控制极被配置为接收第一控制信号，第八晶体管的第一极与第九晶体管的第二极连接，第二极与第三时钟端连接。第九晶体管的控制极被配置为接收第二控制信号，第九晶体管的第一极与第一电压端连接，第二极与第八晶体管的第一极连接。第三电容被连接在第八晶体管的第一极与第八晶体管的控制极之间。第八晶体管的第一极与第九晶体管的第二极的连接点形成用于输出第二低电平脉冲信号的第二低电平脉冲输出端。
在本公开文本的实施例中，高电平脉冲生成模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第四电容以及第五电容。第十晶体管的控制极与第一时钟端连接，第一极与第一电压端连接，第二极与第十一晶体管的第一极连接。第十一晶体管的控制极与第二输入端连接，第一极与第十晶体管的第二极连接，第二极与第十二晶体管的第一极连接。第十二晶体管的控制极被配置为接收第一控制信号，第十二晶体管的第一极与第十一晶体管的第二极连接，第二极与第二电压端连接。第十三晶体管的控制极与第一时钟端连接，第一极与第二输入端连接，第二极与第十五晶体管的控制极连接。第十四晶体管的控制极与第十一晶体管的第二极连接，第一极与第一时钟端连接，第二极与第十五晶体管的第一极连接。第十五晶体管的控制极与第十三管的第二极连接，第一极与第十四晶体管的第二极连接，第二极与第二电压端连接。第四电容被连接在第一电压端与第十四晶体管的控制极之间。第五电容被连接在第十五晶体管的第一极与第十五晶体管的控制极之间。第十四晶体管的第二极与第十五晶体管的第一极的连接点形成用于输出高电 平脉冲信号的高电平脉冲输出端。
根据本公开文本的第二个方面，提供一种用于驱动上述移位寄存器的方法，包括：在第一阶段，在第一时钟端提供低电平信号，在第二时钟端提供高电平信号，在第三时钟端提供高电平信号，在第一输入端提供低电平信号，在第二输入端提供高电平信号，以使得移位寄存器输出高电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与低电平的高电平脉冲信号。在第二阶段，在第一时钟端提供高电平信号，在第二时钟端提供低电平信号，在第三时钟端提供高电平信号，在第一输入端提供高电平信号，在第二输入端提供高电平信号，以使得移位寄存器输出低电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与高电平的高电平脉冲信号。在第三阶段，在第一时钟端提供高电平信号，在第二时钟端提供高电平信号，在第三时钟端提供低电平信号，在第一输入端提供高电平信号，在第二输入端提供低电平信号，以使得移位寄存器输出高电平的第一低电平脉冲信号、低电平的第二低电平脉冲信号与高电平的高电平脉冲信号。在第四阶段，在第一时钟端提供低电平信号，在第二时钟端提供高电平信号，在第三时钟端提供高电平信号，在第一输入端提供高电平信号，在第二输入端提供低电平信号，以使得移位寄存器输出高电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与低电平的高电平脉冲信号。
根据本公开文本的第三个方面，提供了一种栅极驱动电路，包括级联的多个上述的移位寄存器，其中，每一级移位寄存器提供第一低电平脉冲信号、第二低电平脉冲信号与高电平脉冲信号。其中，上一级移位寄存器向下一级移位寄存器的第一输入端提供第一低电平脉冲信号，上一级移位寄存器向下一级移位寄存器的第二输入端提供高电平脉冲信号。
根据本公开文本的第四个方面，提供了一种显示装置，包括上述的栅极驱动电路。
采用本公开文本的实施例的移位寄存器，能够在一个移位寄存器中生成三个不同的脉冲信号，与采用三个电路分别提供三个脉冲信号的技术相比，大大减少了元器件与控制信号的数量，可应用于窄边框的显示器。
附图说明
为了更清楚地说明本公开文本的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开文本的一些实施例，而非对本公开文本的限制，其中：
图1是用于OLED像素电路的脉冲信号的示意图；
图2是提供图1中的第一低电平脉冲信号的电路示意图；
图3是提供图1中的第二低电平脉冲信号的电路示意图；
图4是提供图1中的高电平脉冲信号的电路示意图；
图5是根据本公开文本的实施例的移位寄存器的示意性框图；
图6是用于说明图5所示的移位寄存器的示例性电路图；
图7是用于说明图6所示的移位寄存器的工作时序的示意图；
图8是本公开文本的一个实施例的栅极驱动电路的示意性框图；
图9本公开文本的另一个实施例的栅极驱动电路的示意性框图。
具体实施方式
为了使本公开文本的实施例的技术方案和优点更加清楚，下面将结合附图，对本公开文本的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开文本保护的范围。
图1中的信号G1、G2、G3可以由3个电路分别生成。图2是提供图1中的第一低电平脉冲信号的电路示意图。图3是提供图1中的第二低电平脉冲信号的电路示意图。图4是提供图1中的高电平脉冲信号的电路示意图。
如图2-4所示，3个电路使用了共计28个晶体管与7个电容，并且对于每个电路，均需要使用不同的时钟、输入信号等来进行驱动。电路元件数量多，并且结构复杂，占用的面积较大，难以应用于窄边框的显示器。
图5是根据本公开文本的实施例的移位寄存器的示意性框图。如图5所示，移位寄存器包括控制信号生成模块、第一低电平脉冲生成模块、第二低电平脉冲生成模块以及高电平脉冲生成模块。控制信号生成模块与第一时钟端CK1、第二时钟端CK2、第一电压端VGH、第二电压端VGL以及第一输入端STVG连接，并被配置为生成第一控制信号以及第二控制信号。第一控制信号以及第二控制信号被输出到第一低电平脉冲生成模块、第二低电平脉冲生成模块以及高电平脉冲生成模块。
第一低电平脉冲生成模块与第二时钟端CK2以及第一电压端VGH连接，并被配置为接收来自控制信号生成模块的第一控制信号以及第二控制信号，并生成第一低电平脉冲信号。第二低电平脉冲生成模块与第三时钟端CK3以及第一电压端VGH连接，并被配置为接收来自所述控制信号生成模块的第一控制信号以及第二控制信号，并生成第二低电平脉冲信号。高电平脉冲生成模块与第一时钟端CK1、第一电压端VGH、第二电压端VGL以及第二输入端STVE连接，并被配置为接收来自所述控制信号生成模块的第一控制信号，并生成高电平脉冲信号。
在本实施例的移位寄存器中，对于三个脉冲生成模块，实现了控制信号的复用，能够减少移位寄存器中使用的电路元件的数量。
图6是用于说明图5所示的移位寄存器的示意性电路图。如图6所示，控制信号生成模块包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第一电容C1。第一晶体管T1的控制极与第一时钟端CK1连接，第一极与第一输入端STVG连接，第二极与第二晶体管T2的第二极连接。第二晶体管T2的控制极与第二时钟端CK2连接，第一极与第三晶体管T3的第二极连接，第二极与第一晶体管T1的第二极连接。第三晶体管T3的控制极与第四晶体管T4的第一极连接，第一极与第一电压端VGH连接，第二极与第二晶体管T2的第一极连接。第四晶体管T4的控制极与第一时钟端CK1连接，第一极与第三晶体管T3的控制极连接，第二极与第二电压端VGL连接。第五晶体管T5的控制极与第一晶体管T1的第二极连接，第一极与第三晶体管T3的控制极连接， 第二极与第一时钟端CK1连接。第一电容C1被连接在第一电压端VGH与第三晶体管T3的控制极之间。第一晶体管T1的第二极与第二晶体管T2的第二极的连接点形成第一控制信号输出端Q。第三晶体管T3的控制极与第四晶体管T4的第一极的连接点形成第二控制信号输出端P。
第一低电平脉冲生成模块包括第六晶体管T6、第七晶体管T7以及第二电容C2。第六晶体管T6的控制极连接第一控制信号输出端Q，即被配置为接收第一控制信号，第六晶体管T6的第一极与第七晶体管T7的第二极连接，第二极与第二时钟端CK2连接。第七晶体管T7的控制极与第二控制信号输出端P连接，即被配置为接收第二控制信号，第七晶体管T7的第一极与第一电压端VGH连接，第二极与第六晶体管T6的第一极连接。第二电容C2的被连接在第六晶体管T6的第一极与第六晶体管T6的控制极之间。第六晶体管T6的第一极与第七晶体管T7的第二极的连接点形成用于输出第一低电平脉冲信号的第一低电平脉冲输出端Reset。
第二低电平脉冲生成模块包括第八晶体管T8、第九晶体管T9以及第三电容C3。第八晶体管T8的控制极连接第一控制信号输出端Q，即被配置为接收第一控制信号，第八晶体管T8的第一极连接第九晶体管T9的第二极，第二极连接第三时钟端CK3。第九晶体管T9的控制极连接第二控制信号输出端P，即被配置为接收第二控制信号，第九晶体管T9的第一极连接第一电压端VGH，第二极连接第八晶体管T8的第一极。第三电容C3被连接在第八晶体管T8的第一极和第八晶体管T8的控制极之间。第八晶体管T8的第一极与第九晶体管T9的第二极的连接点形成用于输出第二低电平脉冲信号的第二低电平脉冲输出端Gate。
高电平脉冲生成模块包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第四电容C4以及第五电容C5。第十晶体管T10的控制极与第一时钟端CK1连接，第一极与第一电压端VGH连接，第二极与第十一晶体管T11的第一极连接。第十一晶体管T11的控制极与第二输入端STVE连接，第一极与第十晶体管T10的第二极连接，第二极与第十二晶体管T12的第一 极连接。第十二晶体管T12的控制极与第一控制信号输出端Q连接，即被配置为接收第一控制信号，第十二晶体管T12的第一极与第十一晶体管T11的第二极连接，第二极与第二电压端VGL连接。第十三晶体管T13的控制极与第一时钟端CK1连接，第一极与第二输入端STVE连接，第二极与第十五晶体管T15的控制极连接。第十四晶体管T14的控制极与第十一晶体管T11的第二极连接，第一极与第一时钟端CK1连接，第二极与第十五晶体管T15的第一极连接。第十五晶体管T15的控制极与第十三晶体管T13的第二极连接，第一极与第十四晶体管T14的第二极连接，第二极与第二电压端VGL连接。第四电容C4被连接在第一电压端VGH与第十四晶体管T14的控制极之间。第五电容C5被连接在第十五晶体管T15的第一极与第十五晶体管T15的控制极之间。第十四晶体管T14的第二极与第十五晶体管T15的第一极的连接点形成用于输出高电平脉冲信号的高电平脉冲输出端EM。
N点表示第十二晶体管T12的第一极、第十四晶体管T14的控制极与第四电容C4的第二极的连接点。M点表示第十三晶体管T13的第二极、第十五晶体管T15的控制极与第五电容C5的第二极的连接点。
在本实施例的移位寄存器中，使用较少的电路元件实现了三个脉冲生成模块，能够减少移位寄存器中使用的电路元件的数量。
图7是用于说明图6所示的移位寄存器的工作时序的示意图。如图7所示，本例中移位寄存器的工作时序包括第一阶段、第二阶段、第三阶段、第四阶段。以下，以移位寄存器中的晶体管是P型薄膜晶体管TFT为例来对各个阶段信号状态以及晶体管状态进行说明，并且，在本例中，用VL表示时钟端、输入端与第二电压端VGL提供的低电平电压，用VH表示时钟端、输入端与第一电压端VGH提供的高电平电压。在图7中，第一时钟端CK1的信号、第二时钟端CK2的信号与第三时钟端CK3的信号为高低电平周期性地切换的时钟信号，低电平的占空比均为33％。
在第一阶段，在第一时钟端提供低电平信号，在第二时钟端提供高电平信号，在第三时钟端提供高电平信号，在第一输入端提供低电平信号， 在第二输入端提供高电平信号，以使得所述移位寄存器输出高电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号和低电平的高电平脉冲信号。
具体而言，在第一阶段t1中，第一输入端STVG与第一时钟端CK1的电压跳变为低电平，第一晶体管T1导通，将第一输入端STVG的低电平的电压传递到第一控制信号输出端Q。由于P型TFT传递低电平有阈值损失，所以第一控制信号输出端Q电压为VL与第一晶体管T1阈值电压Vthp绝对值之和。第六晶体管T6导通，并且因为第二时钟端CK2的电压此时为高电平，所以第一低电平脉冲输出端Reset的电压为高电平。同时，由于第一时钟端CK1的电压为低电平，第四晶体管T4导通，将第二控制信号输出端P的电压拉低，第八晶体管T8、第九晶体管T9导通，将第一低电平脉冲输出端Reset、第二低电平脉冲输出端Gate拉高。第十三晶体管T13导通，由于在第一阶段t1第二输入端STVE的电压变为高电平，M点电压变为高电平，第十五晶体管T15截止。同时，由于第一控制信号输出端Q电压被拉低，第十二晶体管T12导通，将N点电压拉低，第十四晶体管T14导通，高电平脉冲输出端EM输出与第一时钟端CK1相同的低电平电压。
在第二阶段，在第一时钟端提供高电平信号，在第二时钟端提供低电平信号，在第三时钟端提供高电平信号，在第一输入端提供高电平信号，在第二输入端提供高电平信号，以使得所述移位寄存器输出低电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与高电平的高电平脉冲信号。
具体而言，在第二阶段t2中，第一输入端STVG与第一时钟端CK1的电压跳变为高电平，第二时钟端CK2的电压跳变为低电平。由于在第一阶段t1中，第六晶体管T6导通，所以第二时钟端CK2的低电平电压通过第六晶体管T6传递到第一控制信号输出端Q，第五晶体管T5导通，第二控制信号输出端P的电压被上拉至第一时钟端CK1电压的高电平。第三晶体管T3、第八晶体管T8、第九晶体管T9截止，由于第一晶体管T1也 处于截止状态，所以第六晶体管T6栅极处于悬空状态，第二电容C2电容两端电压不能突变(其电压可表示为：VL+|Vthp|-VH)，所以第一低电平脉冲输出端Reset电压的电平会随着第一控制信号输出端Q电压电平的降低而降低，最后稳定(其电压可表示为：2VL+|Vthp|-VH)。第三晶体管T3工作在线性区，第二时钟端CK2的低电平的电压无阈值损失地传递到第一低电平脉冲输出端Reset，第一低电平脉冲输出端Reset电压为低电平的电压。第一控制信号输出端Q的低电平电压也使第十二晶体管T12工作在线性区，N点电压为低电平的电压，第十四晶体管T14很好的导通，将第一时钟端CK1的高电平的电压输出到高电平脉冲信号输出端EM。第一控制信号输出端Q的低电平电压也使第七晶体管T7导通，将第三时钟端CK3的高电平的电压输出到第二低电平脉冲输出端Gate。
在第三阶段，在第一时钟端提供高电平信号，在第二时钟端提供高电平信号，在第三时钟端提供低电平信号，在第一输入端提供高电平信号，在第二输入端提供低电平信号，以使得所述移位寄存器输出高电平的第一低电平脉冲信号、低电平的第二低电平脉冲信号与高电平的高电平脉冲信号。
具体而言，在第三阶段t3中，第二时钟端CK2的电压跳变为高电平，第三时钟端CK3的电压跳变为低电平。由于电容C2两端的电压不能突变，第二时钟端CK2与第三时钟端CK3的电压跳变的电平相反，所以第一控制信号输出端Q电压仍为2VL+|Vthp|-VH，第六晶体管T6、第七晶体管T7、第十二晶体管T12都工作在线性区，第六晶体管T6将第二时钟端CK2的高电平的电压传到第一低电平脉冲输出端Reset，对第一低电平脉冲输出端Reset进行上拉，第七晶体管T7将第三时钟端CK3的低电平的电压无阈值损失的传到第二低电平脉冲输出端Gate、第十二晶体管T12仍将N点电压保持在低电平，使第十四晶体管T14很好的将第一时钟端CK1的高平的电压传到高电平脉冲信号输出端EM。
在第四阶段，在第一时钟端提供低电平信号，在第二时钟端提供高电平信号，在第三时钟端提供高电平信号，在第一输入端提供高电平信号， 在第二输入端提供低电平信号，以使得所述移位寄存器输出高电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与低电平的高电平脉冲信号。
具体而言，在第四阶段t4中，第三时钟端CK3的电压跳变为高电平，第一时钟端CK1、第二输入端STVE的电压跳变为低电平。由于第一时钟端CK1的电压为低电平，第四晶体管T4导通，将第二控制信号输出端P的电压拉至低电平，第八晶体管T8、第九晶体管T9导通，将第二低电平脉冲输出端Gate的电压拉至高电平，第一低电平脉冲输出端Reset的电压维持在低电平。同时，第一时钟端CK1、第二输入端STVE跳变为低电平，第十三晶体管T13导通，将M点电压拉至低电平，第十五晶体管T15导通，高电平脉冲输出端EM的电压被拉至低电平，由于电容C4两端电压不能突变，高电平脉冲输出端EM的电压变为低电平，M点会被拉到更低的电平，第二电压端VGL的低电平的电压可以无阈值损失地通过第十五晶体管T15传递到高电平脉冲输出端EM。
在工作时序完成后，进入非工作状态的第五阶段t5，第五阶段t5的时间长度大于上述4个阶段。
在第五阶段t5，在第一时钟端CK1提供周期性地在高电平与低电平之间变化的信号，在第二时钟端CK2提供周期性地在高电平与低电平之间变化的信号，在第三时钟端CK3提供周期性地在高电平与低电平之间变化的信号，在第一输入端STVG提供高电平的信号，在第二输入端STVE提供低电平的信号，以使得移位寄存器输出高电平的第一低电平脉冲信号，高电平的第二低电平脉冲信号，低电平的高电平脉冲信号。
具体而言，在第五阶段t5中，随着第一时钟端CK1、第二时钟端CK2电压的周期性变化，周期性将第一晶体管T1、第二晶体管T2导通使得第一控制信号输出端Q的电压稳定地保持在高电平。通过第一时钟端CK1的电压的变化，周期性地将第四晶体管T4导通，并且第一电容C1具有保持电压的作用，所以第二控制信号输出端P的电压维持在低电平。通过第一时钟端CK1的电压的变化，周期性将第十三晶体管T13导通，M点电 压维持在较低的电平；通过第一时钟端CK1的电压的变化，周期性将第十晶体管T10导通，并且由于第四电容C4具有保持电压的作用，N点电压维持在高电平。第一控制信号输出端Q的高电平电压、第二控制信号输出端P的低电平电压、M点的较低电平的电压、N点的高电平的电压使第一低电平脉冲输出端Reset、第二低电平脉冲输出端Gate的电压保持在高电平、高电平脉冲输出端EM的电压保持在低电平。
图8是本公开文本的一个实施例的栅极驱动电路的示意性框图。如图8所示，上述的多个移位寄存器GOA级联使用构成栅极驱动电路，每一级移位寄存器的第一低电平脉冲输出端Reset、第二低电平脉冲输出端Gate、高电平脉冲输出端EM连接至像素单元电路pixel，提供对像素单元电路写入数据时需要的脉冲信号G1、G2、G3。在级联的移位寄存器之间，上一级移位寄存器的第一低电平脉冲输出端Reset连接下一级移位寄存器的第一输入端STVG，上一级移位寄存器的高电平脉冲输出端EM连接下一级的移位寄存器的第二输入端STVE。
图9本公开文本的另一个实施例的栅极驱动电路的电路框图。与图8所示电路的区别在于，本例的栅极驱动电路包括两列级联的移位寄存器，并且这两列级联的移位寄存器交叉使用。具体而言，在本例中，第一级移位寄存器的第一低电平脉冲输出端Reset连接第三级移位寄存器的第一输入端STVG，第一级移位寄存器的高电平脉冲输出端EM连接第三级的移位寄存器的第二输入端STVE。第二级移位寄存器的第一低电平脉冲输出端Reset连接第四级移位寄存器的第一输入端STVG，第二级移位寄存器的高电平脉冲输出端EM连接第四级的移位寄存器的第二输入端STVE。以此类推。通过多列级联的移位寄存器的交叉使用，缩短相邻的两级移位寄存器之间工作时间的间隔，提高了像素驱动电路对于像素单元的扫描速度。
本公开文本的实施例还提供了一种显示装置，包括上述的栅极驱动电路。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示 功能的产品或部件。
在本公开文本的实施例中，用一个移位寄存器电路实现了3路脉冲信号生成，减少了电路元件的数量，能够将28个晶体管与7个电容减少为15个晶体管5个电容，并且减少了控制信号的数量。能够级联使用该移位寄存器得到电路元件数量更少的栅极驱动电路，能够符合窄边框显示器的要求。
需要说明的是，在上述描述中，高电平、低电平仅仅用于区分电压是否能够使得晶体管导通，并没有限制电压的值。例如，低电平可以是指接地的电平，也可以是负电平。此外，所选择的P型TFT晶体管为示意性的说明，并不是对于晶体管类型的具体限制。根据本公开文本的原理，本领域技术人员能够在不付出创造性劳动的情况下，对于晶体管的类型做出适当的选择和调整，这些选择和调整也视为本公开文本的保护范围。
可以理解的是，以上实施方式仅仅是为了说明本公开文本的原理而采用的示例性实施方式，然而本公开文本并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开文本的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开文本的保护范围。

Claims (8)

  1. 一种移位寄存器，包括控制信号生成模块、第一低电平脉冲生成模块、第二低电平脉冲生成模块以及高电平脉冲生成模块；
    其中，所述控制信号生成模块与第一时钟端、第二时钟端、第一电压端、第二电压端以及第一输入端连接，并被配置为生成第一控制信号以及第二控制信号；
    所述第一低电平脉冲生成模块与所述第二时钟端以及所述第一电压端连接，并被配置为接收来自所述控制信号生成模块的所述第一控制信号以及所述第二控制信号，并生成第一低电平脉冲信号；
    所述第二低电平脉冲生成模块与第三时钟端以及所述第一电压端连接，并被配置为接收来自所述控制信号生成模块的所述第一控制信号以及所述第二控制信号，并生成第二低电平脉冲信号；
    所述高电平脉冲生成模块与所述第一时钟端、所述第一电压端、所述第二电压端以及第二输入端连接，并被配置为接收来自所述控制信号生成模块的所述第一控制信号，并生成高电平脉冲信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述控制信号生成模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管以及第一电容；
    所述第一晶体管的控制极与所述第一时钟端连接，第一极与所述第一输入端连接，第二极与所述第二晶体管的第二极连接；
    所述第二晶体管的控制极与所述第二时钟端连接，第一极与所述第三晶体管的第二极连接，第二极与所述第一晶体管的第二极连接；
    所述第三晶体管的控制极与所述第四晶体管的第一极连接，第一极与所述第一电压端连接，第二极与所述第二晶体管的第一极连接；
    所述第四晶体管的控制极与所述第一时钟端连接，第一极与所述第三晶体管的控制极连接，第二极与所述第二电压端连接；
    所述第五晶体管的控制极与所述第一晶体管的第二极连接，第一极与所述第三晶体管的控制极连接，第二极与所述第一时钟端连接；
    所述第一电容被连接在所述第一电压端与所述第三晶体管的控制极之间；
    所述第一晶体管的第二极与所述第二晶体管的第二极的连接点形成用于输出所述第一控制信号的第一控制信号输出端；
    所述第三晶体管的控制极与所述第四晶体管的第一极的连接点形成用于输出所述第二控制信号的第二控制信号输出端。
  3. 根据权利要求1所述的移位寄存器，其中，所述第一低电平脉冲生成模块包括第六晶体管、第七晶体管以及第二电容；
    所述第六晶体管的控制极被配置为接收所述第一控制信号，所述第六晶体管的第一极与所述第七晶体管的第二极连接，第二极与所述第二时钟端连接；
    所述第七晶体管的控制极被配置为接收所述第二控制信号，所述第七晶体管的第一极与所述第一电压端连接，第二极与所述第六晶体管的第一极连接；
    所述第二电容被连接在所述第六晶体管的第一极与所述第六晶体管的控制极之间；
    所述第六晶体管的第一极与所述第七晶体管的第二极的连接点形成用于输出所述第一低电平脉冲信号的第一低电平脉冲输出端。
  4. 根据权利要求1所述的移位寄存器，其中，所述第二低电平脉冲生成模块包括第八晶体管、第九晶体管以及第三电容；
    所述第八晶体管的控制极被配置为接收所述第一控制信号，所述第八晶体管的第一极与所述第九晶体管的第二极连接，第二极与所述第三时钟端连接；
    所述第九晶体管的控制极被配置为接收所述第二控制信号，所述第九晶体管的第一极与所述第一电压端连接，第二极与所述第八晶体管的第一极连接；
    所述第三电容被连接在所述第八晶体管的第一极与所述第八晶体管的控制极之间；
    所述第八晶体管的第一极与所述第九晶体管的第二极的连接点形成用于输出所述第二低电平脉冲信号的第二低电平脉冲输出端。
  5. 根据权利要求1所述的移位寄存器，其中，所述高电平脉冲生成模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第四电容以及第五电容；
    所述第十晶体管的控制极与所述第一时钟端连接，第一极与所述第一电压端连接，第二极与所述第十一晶体管的第一极连接；
    所述第十一晶体管的控制极与所述第二输入端连接，第一极与所述第十晶体管的第二极连接，第二极与所述第十二晶体管的第一极连接；
    所述第十二晶体管的控制极被配置为接收所述第一控制信号，所述第十二晶体管的第一极与所述第十一晶体管的第二极连接，第二极与所述第二电压端连接；
    所述第十三晶体管的控制极与所述第一时钟端连接，第一极与所述第二输入端连接，第二极与所述第十五晶体管的控制极连接；
    所述第十四晶体管的控制极与所述第十一晶体管的第二极连接，第一极与所述第一时钟端连接，第二极与所述第十五晶体管的第一极连接；
    所述第十五晶体管的控制极与所述第十三管的第二极连接，第一极与所述第十四晶体管的第二极连接，第二极与所述第二电压端连接；
    所述第四电容被连接在所述第一电压端与所述第十四晶体管的控制极之间；
    所述第五电容被连接在所述第十五晶体管的第一极与所述第十五晶体管的控制极之间；
    所述第十四晶体管的第二极与所述第十五晶体管的第一极的连接点形成用于输出所述高电平脉冲信号的高电平脉冲输出端。
  6. 一种用于驱动如权利要求1至5中任一项所述的移位寄存器的方法，包括：
    在第一阶段，在第一时钟端提供低电平信号，在第二时钟端提供高电平信号，在第三时钟端提供高电平信号，在第一输入端提供低电平信号， 在第二输入端提供高电平信号，以使得所述移位寄存器输出高电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与低电平的高电平脉冲信号；
    在第二阶段，在第一时钟端提供高电平信号，在第二时钟端提供低电平信号，在第三时钟端提供高电平信号，在第一输入端提供高电平信号，在第二输入端提供高电平信号，以使得所述移位寄存器输出低电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与高电平的高电平脉冲信号；
    在第三阶段，在第一时钟端提供高电平信号，在第二时钟端提供高电平信号，在第三时钟端提供低电平信号，在第一输入端提供高电平信号，在第二输入端提供低电平信号，以使得所述移位寄存器输出高电平的第一低电平脉冲信号、低电平的第二低电平脉冲信号与高电平的高电平脉冲信号；
    在第四阶段，在第一时钟端提供低电平信号，在第二时钟端提供高电平信号，在第三时钟端提供高电平信号，在第一输入端提供高电平信号，在第二输入端提供低电平信号，以使得所述移位寄存器输出高电平的第一低电平脉冲信号、高电平的第二低电平脉冲信号与低电平的高电平脉冲信号。
  7. 一种栅极驱动电路，包括级联的多个如权利要求1至5中任一项所述的移位寄存器，其中，每一级所述移位寄存器提供第一低电平脉冲信号、第二低电平脉冲信号、高电平脉冲信号；
    其中，上一级所述移位寄存器向下一级所述移位寄存器的所述第一输入端提供第一低电平脉冲信号，上一级所述移位寄存器向下一级所述移位寄存器的所述第二输入端提供高电平脉冲信号。
  8. 一种显示装置，包括如权利要求7所述的栅极驱动电路。
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