WO2016101618A1 - 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置 - Google Patents

移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置 Download PDF

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Publication number
WO2016101618A1
WO2016101618A1 PCT/CN2015/085394 CN2015085394W WO2016101618A1 WO 2016101618 A1 WO2016101618 A1 WO 2016101618A1 CN 2015085394 W CN2015085394 W CN 2015085394W WO 2016101618 A1 WO2016101618 A1 WO 2016101618A1
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Prior art keywords
pull
shift register
register unit
node
transistor
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PCT/CN2015/085394
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English (en)
French (fr)
Inventor
杨通
马睿
王国磊
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US14/912,635 priority Critical patent/US10593284B2/en
Priority to EP15871692.8A priority patent/EP3133583B1/en
Publication of WO2016101618A1 publication Critical patent/WO2016101618A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technologies, and more particularly to a shift register unit and a driving method thereof, a shift register circuit, and a display device.
  • a shift register is used in most flat panel displays.
  • the shift register implemented by GOA (Gate Drive on Array) technology can eliminate the gate drive integrated circuit IC and reduce one manufacturing process, thus reducing the flat panel display.
  • the manufacturing cost also shortens the manufacturing cycle to some extent.
  • the power consumption of the GOA unit itself is larger than that of a common gate drive IC.
  • CLK clock
  • the number of clock signals is a multiple of 2
  • the clock signal is reduced.
  • the frequency thus achieving the purpose of reducing power consumption.
  • the high level time in each clock cycle is n times the scanning time (n is an integer greater than or equal to 2), and there is an overlap between the adjacent clock signals of the two timings.
  • the actual charging time for each gate row is the phase identified by 2H. Based on the overlap portion, each gate row can be turned on in advance.
  • the time difference between the gate signal (Vgate) and the data signal (Vdata) is mainly determined by the gate line's own resistance and the gate load falling edge time (Tf) caused by the capacitive load, that is, the larger the Tf, the pixel
  • the effective charging time (Teff) will be less, as shown in Figure 2, Teff ⁇ 1H.
  • FIG. 3 shows a specific circuit diagram of a shift register unit implemented by a common GOA design method
  • FIG. 4 shows a shift register circuit including a plurality of shift register units of FIG. 3 cascaded.
  • the block diagram in which the timing of each clock signal is as shown in FIG. In Figure 3, transistors M3 and M4 are responsible for charging and discharging the output (OUTPUT), respectively.
  • CLK clock signal
  • the output terminal outputs a high level signal
  • CLK reset signal
  • transistors M2 and M4 are turned on, and the gate and output of transistor M3 are discharged.
  • the transistors M3 and M4 are in the off state and the on state, respectively, so that only the transistor M4 discharges the output terminal.
  • the output of the nth register unit in addition to driving the nth row of gate lines, resets the n-2th register unit and serves as an input to the n+2th register unit.
  • the shift register circuit implemented by the conventional GOA technology can only reduce Tr, thereby reducing the influence of Tr on the effective charging time of the pixel.
  • the present invention provides a shift register unit and a driving method thereof, a shift register circuit, and a display device for solving the problem in the prior art that the falling edge time (Tf) of the gate driving signal is long.
  • One aspect of the present invention provides a shift register unit comprising:
  • a charging module the input end and the control end are connected to the input end of the shift register unit, and the output end is connected to the pull-up node for receiving an input signal, and pulling the potential of the pull-up node under the control of the input signal to Generating a pull-up signal;
  • a pull-up module the control end is connected to the pull-up node, the input end is connected to the first clock signal end of the shift register unit, and the output end is connected to the output end of the shift register unit for receiving the first clock signal And charging the output of the shift register unit in a pull-up phase under control of a pull-up signal;
  • a first pull-down control module the first control end and the first input end are connected to the second clock signal end of the shift register unit, the second control end is connected to the pull-up node, and the second input end is connected to the shift a low voltage end of the register unit is connected, and the output end is connected to the pull-down control node for receiving the second clock signal, and generating a pull-down control signal at the pull-down control node under the control of the second clock signal and the pull-up signal;
  • a second pull-down control module the first control end is connected to the pull-down control node, the second control end is connected to the pull-up node, the first input end is connected to the second clock signal end of the shift register unit, and the second input end is connected to The low voltage terminal of the shift register unit is connected, and the output terminal is connected to the pull-down node for receiving the second clock signal, and generating a pull-down signal at the pull-down node under the control of the pull-down control signal and the pull-up signal;
  • a first pull-down module the control end is connected to the first reset end of the shift register unit, the input end is connected to the output end of the shift register unit, and the output end is connected to the low voltage end of the shift register unit And discharging the output end of the shift register unit under the control of the first reset signal in the first pull-down phase;
  • a second pull-down module the first control end is connected to the pull-down node, the second control end is connected to the second clock signal end of the shift register unit, the first input end is connected to the output end of the shift register, and the second The input terminal is connected to the pull-up node, and the output terminal is connected to the low voltage terminal of the shift register unit for outputting the shift register unit in the second pull-down phase under the control of the pull-down signal and the second clock signal Discharge at the end;
  • a reset module the control end is connected to the second reset end of the shift register unit, the input end is connected to the pull-up node, and the output end is connected to the low voltage end of the shift register unit for use in the second reset
  • the pull-up node is reset under the control of the signal
  • the pull-up module discharges an output of the shift register unit in the first pull-down phase.
  • the charging module includes a first transistor, a gate and a first electrode of the first transistor are connected to an input end of the shift register unit, and a second electrode is connected to the pull-up node.
  • the reset module includes a second transistor, a gate of the second transistor is connected to the second reset end, a first electrode is connected to the pull-up node, and a second electrode is connected to the low voltage end.
  • the pull-up module includes a third transistor, a gate of the third transistor is connected to the pull-up node, a first electrode is connected to the first clock signal end, and a second electrode and the output end connection.
  • the first pull-down module includes a fourth transistor, a gate of the fourth transistor is connected to the first reset end, a first electrode is connected to the output end, and a second electrode is connected to the low The voltage terminals are connected.
  • the second pull-down control module includes a fifth transistor and a sixth transistor, a gate of the fifth transistor is connected to the pull-down control node, a first electrode is connected to the second clock signal end, and a second An electrode is connected to the pull-down node; a gate of the sixth transistor is connected to a gate of the third transistor, a first electrode is connected to the pull-down node, and a second electrode is connected to the low voltage terminal.
  • the first pull-down control module includes a seventh transistor and a eighth transistor, a gate of the seventh transistor is connected to a gate of the third transistor, and a first electrode is connected to the pull-down control node, The second electrode is connected to the low voltage terminal; the gate and the first electrode of the eighth transistor are connected to the second clock signal end, and the second electrode is connected to the pull-down control node.
  • the second pull-down module includes a ninth transistor, a tenth transistor and an eleventh transistor, a gate of the ninth transistor is connected to the pull-down node, and a first electrode is connected to the pull-up node, a second electrode is connected to the low voltage end; a gate of the tenth transistor is connected to the pull-down node, a first electrode is connected to the output end, and a second electrode is connected to the low voltage end; A gate of a transistor is coupled to the second clock signal terminal, a first electrode is coupled to the output terminal, and a second electrode is coupled to the low voltage terminal.
  • the pull-up module and the first pull-down module simultaneously discharge the output of the shift register unit in a first pull-down phase.
  • the third transistor and the fourth transistor are larger in size than the other transistors.
  • the second reset signal is delayed by 1/2 of an actual charging time of one gate line with respect to the first reset signal.
  • the phase of the first clock signal is opposite to the phase of the second clock signal.
  • Another aspect of the present invention provides a method of driving a shift register unit, comprising:
  • the level of the pull-up node is pulled up by the charging module to generate a pull-up signal
  • the output terminal of the shift register unit is charged by the pull-up module under the control of the pull-up signal
  • the pull-up module and the first pull-down module simultaneously discharge the output end of the shift register unit in the first pull-down phase.
  • a further aspect of the present invention provides a shift register circuit comprising m cascaded shift register units, m is greater than or equal to 6, and an output end of each shift register unit is connected to a corresponding gate line.
  • the output of the nth shift register unit is connected to the input of the n+2th shift register unit, except for the first two shift register units and the last two shift register units.
  • first reset end of the nth shift register unit is coupled to the output of the n+2th shift register unit, and the second reset end is coupled to the output of the n+3 shift register unit, and
  • n is greater than or equal to 3 and less than or equal to m-3.
  • Another aspect of the present invention provides a display device including the shift register circuit.
  • the shift register unit of the present invention increases the pixel effective charging time Teff by reducing the falling edge time Tf of the gate driving signal, and ensures display picture quality.
  • the output of the shift register unit is discharged in the first pull-down phase by the pull-up module together with the first pull-down module (ie, the level of the output of the shift register is pulled down), thereby further reducing the shift register.
  • the falling edge time of the unit output increases the discharge efficiency.
  • the pull-up module of the present invention can be used not only for charging the output of the shift register during the pull-up phase, but also for the pull-down phase.
  • the output of the shift register unit is discharged, that is, the same module plays different roles at different stages, thereby simplifying the circuit structure while ensuring an improved discharge efficiency.
  • 1 is a timing chart showing the operation of a shift register circuit using a conventional GOA design
  • FIG. 2 is a graph showing the relationship between the actual charging time of the gate row and the effective charging time of the pixel using a conventional GOA design
  • FIG. 3 is a specific circuit diagram showing a shift register unit using a conventional GOA design
  • FIG. 4 is a block diagram showing a shift register circuit including a plurality of shift register cells of FIG. 3 in cascade;
  • FIG. 5 is a block diagram showing a shift register unit according to an embodiment of the present invention.
  • FIG. 6 is a specific circuit diagram showing the shift register unit of FIG. 5 according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a driving method of a shift register unit according to an embodiment of the present invention.
  • FIG. 8 is a block diagram showing a shift register circuit including a plurality of shift register cells in FIG. 5 cascaded.
  • Embodiments of the present invention provide a shift register unit and a driving method thereof, a shift register circuit, and a display device, which realize that a falling edge time of a shift register unit output is short, and an effective charging time of a pixel is long.
  • a bit register unit, and a shift register circuit and display device having a simple structure and low power consumption.
  • FIG. 5 is a block diagram showing a shift register unit 500 in accordance with an embodiment of the present invention.
  • the shift register unit 500 includes a charging module 501, a pull-up module 502, a first pull-down control module 530, a second pull-down control module 504, a first pull-down module 505, a second pull-down module 506, and a reset module 507.
  • the input end and the control end of the charging module 501 are connected to the input terminal INPUT of the shift register unit 500, and the output end is connected to the pull-up node PU for receiving an input signal and charging the pull-up node PU under the control of the input signal ( The potential of the pull-up node PU is pulled high to generate a pull-up signal.
  • the control terminal of the pull-up module 502 is connected to the pull-up node PU, the input terminal is connected to the first clock signal terminal CLK of the shift register unit 500, and the output terminal is connected to the output terminal OUTPUT of the shift register unit 500 for receiving the first The clock signal, and under the control of the pull-up signal, charges the output terminal OUTPUT of the shift register unit 500 during the pull-up phase (ie, pulls the level of the output terminal OUTPUT high).
  • the first control terminal and the first input end of the first pull-down control module 503 are connected to the second clock signal terminal CLKB of the shift register unit 500, the second control terminal is connected to the pull-up node PU, and the second input terminal is shifted.
  • the low voltage terminal VSS of the register unit 500 is connected, and the output terminal is connected to the pull-down control node PD_CN for receiving the second clock signal and controlling the second clock signal and the pull-up signal.
  • a pull-down control signal is generated at the pull-down control node PD_CN.
  • the first control terminal of the second pull-down control module 504 is connected to the pull-down control node PD_CN, the second control terminal is connected to the pull-up node PU, the first input terminal is connected to the second clock signal terminal CLKB, and the second input terminal and the shift register are
  • the low voltage terminal VSS of the unit 500 is connected, and the output terminal is connected to the pull-down node PD for receiving the second clock signal, and generates a pull-down signal at the pull-down node PD under the control of the pull-down control signal and the pull-up signal.
  • the control terminal of the first pull-down module 505 is connected to the first reset terminal RESET of the shift register unit 500, the input terminal is connected to the output terminal OUTPUT of the shift register unit 500, and the output terminal is connected to the low voltage terminal VSS of the shift register unit 500. a connection for discharging the output terminal OUTPUT of the shift register unit 500 under the control of the first reset signal in the first pull-down phase (ie, pulling the potential of the output terminal OUTPUT of the shift register unit 500 to a shift Low voltage of register unit 500).
  • the first control terminal of the second pull-down module 506 is connected to the pull-down node PD, the second control terminal is connected to the second clock signal terminal CLKB, the first input terminal and the output terminal OUTPUT of the shift register unit 500, the second input terminal and the upper
  • the pull node PU is connected, and the output end is connected to the low voltage terminal VSS of the shift register unit 500 for discharging the output terminal OUTPUT of the shift register unit 500 in the second pull-down phase under the control of the pull-down signal and the second clock signal. (ie, the level of the output terminal OUPUT of the shift register unit 500 is pulled down to the low voltage of the shift register unit 500).
  • the control terminal of the reset module 507 is connected to the second reset terminal RESET' of the shift register unit 500.
  • the input terminal is connected to the pull-up node PU, and the output terminal is connected to the low voltage terminal VSS of the shift register unit 500 for receiving.
  • the pull-up node PU is reset under the control of the second reset signal.
  • the first pull-down module 505 is separately connected to the first reset terminal of the shift register unit 500, that is, the first pull-down module 505 is provided with an independent reset signal.
  • the first reset signal reset provided to the first pull-down module 505 is different from the second reset signal reset' supplied to the reset module 507 in that the second reset signal reset' is delayed by one gate from the first reset signal reset
  • the actual charging time of the line is 1/2 (ie, 1H).
  • the first pull-down module 505 and the reset module 507 are connected to the same reset terminal, and after the scanning of one row of gate lines is completed, the first clock signal is turned to a low level.
  • the reset signal is high level, and the reset module 507 suspends the pull-up node PU (pull up) The node PU goes low.
  • the pull-up module 502 does not work, and the first pull-down module 505 and the second pull-down module 506 operate to pull the level of the output of the shift register unit low.
  • the first clock signal is turned to a low level
  • the reset signal supplied to the first pull-down module 505 is at a high level
  • the first pull-down module 505 is shifted.
  • the level of the output of the bit register is pulled low.
  • the second reset signal reset' supplied to the reset module 507 is still at a low level
  • the level of the pull-up node PU connected to the pull-up module 502 is still at a high level, so the pull-up module 502 remains At work, and since the first clock signal provided to the pull-up module 502 is now low, the pull-up module 502 and the first pull-down module 505 simultaneously discharge the output of the shift register unit.
  • the output terminal OUPUT of the shift register unit 500 is simultaneously discharged by the pull-up module 502 and the first pull-down module 505 in the first pull-down phase, thereby improving the discharge efficiency of the output terminal of the shift register unit and further reducing the gate.
  • the falling edge of the drive signal is at time Tf, thereby increasing the effective pixel charging time Teff.
  • the second reset signal reset' connected to the reset module 507 becomes a high voltage, so that the pull-up node PU becomes a low level, and the pull-up module 502 does not work.
  • the pull-up node PU becomes low-powered
  • the second pull-down module 506 operates to continue discharging the output of the shift register unit 500.
  • the first reset signal connected to the first pull-down module 505 is turned to a low level, and the first pull-down module 505 does not work.
  • the pull-up module according to the present embodiment can be used not only to charge the output of the shift register in the pull-up phase, but also to discharge the output of the shift register unit in the pull-down phase, that is, the same module at different stages It plays a different role, thus simplifying the circuit structure while ensuring improved discharge efficiency.
  • FIG. 6 shows a specific circuit diagram of each module of the shift register unit 500 according to an embodiment of the present invention.
  • the charging module 501 includes a first transistor M1.
  • the gate and the first electrode of the first transistor M1 are connected to the input terminal INPUT of the shift register unit 500, and the second electrode is connected to the pull-up node PU.
  • the gate of M1 corresponds to the control end of the charging module 501
  • the first electrode corresponds to the input end of the charging module 501
  • the second electrode corresponds to the output end of the charging module 501.
  • the reset module 507 includes a second transistor M2.
  • the gate of the second transistor M2 and the second reset The terminal RESET' is connected, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the low voltage terminal VSS.
  • the gate of M2 corresponds to the control terminal of the reset module 507, the first electrode corresponds to the input of the reset module 507, and the second electrode corresponds to the output of the reset module 507.
  • the pull up module 502 includes a third transistor M3.
  • the gate of the third transistor M3 is connected to the pull-up node PU, the first electrode is connected to the first clock signal terminal CLK, and the second electrode is connected to the output terminal OUTPUT.
  • the gate of M3 corresponds to the control end of the pull-up module 502
  • the first electrode corresponds to the input end of the pull-up module 502
  • the second electrode corresponds to the output end of the pull-up module 502.
  • the first pull down module 505 includes a fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the first reset terminal RESET, the first electrode is connected to the output terminal OUTPUT, and the second electrode is connected to the low voltage terminal VSS.
  • the gate of M4 corresponds to the control end of the first pull-down module 505
  • the first electrode corresponds to the input end of the first pull-down module 505
  • the second electrode corresponds to the output of the first pull-down module 505. end.
  • the second pull-down control module 504 includes a fifth transistor M5 and a sixth transistor M6.
  • the gate of the fifth transistor M5 is connected to the pull-down control node PD_CN, the first electrode is connected to the second clock signal terminal CLKB, and the second electrode is connected to the pull-down node PD.
  • the gate of the sixth transistor M6 is connected to the gate of the third transistor M3 (ie, the pull-up node PU), the first electrode is connected to the pull-down node PD, and the second electrode is connected to the low voltage terminal VSS.
  • the phase of the first clock signal sent by the first clock signal terminal CLK is opposite to the phase of the second clock signal sent by the second clock signal terminal CLKB.
  • the gate of M5 corresponds to the first control end of the second pull-down control module 504, the first electrode of M5 corresponds to the first input end of the second pull-down control module 504, and the second electrode of M5 corresponds to The output of the second pull-down control module 504; the gate of M6 corresponds to the second control end of the second pull-down control module 504, the first electrode corresponds to the output end of the second pull-down control module 504, and the second electrode corresponds to the second The second input of the control module 504 is pulled down.
  • the first pull-down control module 503 includes a seventh transistor M7 and an eighth transistor M8.
  • the gate of the seventh transistor M7 is connected to the gate of the third transistor M3 (ie, the pull-up node PU), and the first electrode and the pull-down control node
  • the PD_CN is connected, and the second electrode is connected to the low voltage terminal VSS.
  • the gate and the first electrode of the eighth transistor M8 are connected to the second clock signal terminal CLKB, and the second electrode is connected to the pull-down control node PD_CN.
  • the gate of M7 corresponds to the second control end of the first pull-down control module 503
  • the first electrode corresponds to the output end of the first pull-down control module 503
  • the second The electrode corresponds to the second input end of the first pull-down control module 503
  • the gate of the M8 corresponds to the first control end of the first pull-down control module 503
  • the first electrode corresponds to the first of the first pull-down control module 503
  • the second electrode corresponds to the output of the first pull-down control module 503.
  • the second pull-down module 506 includes a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.
  • the gate of the ninth transistor M9 is connected to the pull-down node PD, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the low voltage terminal VSS.
  • the gate of the tenth transistor M10 is connected to the pull-down node PD, the first electrode is connected to the output terminal OUTPUT, and the second electrode is connected to the low voltage terminal VSS.
  • the gate of the eleventh transistor M11 is connected to the second clock signal terminal CLKB, the first electrode is connected to the output terminal OUTPUT, and the second electrode is connected to the low voltage terminal VSS.
  • the gate of M9 corresponds to the first control end of the second pull-down module 506, the first electrode corresponds to the second input end of the second pull-down module 506, and the second electrode corresponds to the second pull-down module 506.
  • the output terminal; the gate of M10 corresponds to the first control end of the second pull-down module 506, the first electrode corresponds to the first input end of the second pull-down module 506, and the second electrode corresponds to the output end of the second pull-down module 506;
  • the gate of M11 corresponds to the second control end of the second pull-down module 506, the first electrode corresponds to the first input end of the second pull-down module 506, and the second electrode corresponds to the output end of the second pull-down module 506.
  • a first reset signal reset is provided to the gate of the transistor M4, and a second reset signal reset' is provided to the gate of the transistor M2, wherein the second reset signal reset' is delayed by a gate from the first reset signal reset
  • the actual charging time of the polar line is 1/2 (ie, 1H).
  • the gate is connected to the pull-up node PU, and the transistor M3 whose first electrode is connected to the first clock signal of the low level is still on. , discharges the output of the shift register unit. Therefore, the transistor M3 and the transistor M4 simultaneously discharge the output terminal of the shift register unit.
  • the transistor M2 is also turned on, and since the pull-up node PU is turned to the low level, the transistor M3 is turned off. Since the first reset signal reset is turned to a low level, the transistor M4 is also turned off.
  • the second pull-down module 506 Since the second clock signal is at a high level at this time, the second pull-down module 506 operates to continue discharging the output of the shift register unit 500. In this way, the output terminal OUPUT of the shift register unit 500 is simultaneously discharged by the transistor M3 and the transistor M4 in the first pull-down phase, thereby improving the discharge efficiency at the output end of the shift register unit and further reducing The falling edge of the gate drive signal is at time Tf, thereby increasing the effective pixel charging time Teff.
  • the transistors M3 and M4 charge and discharge the output terminals of the shift register unit, the sizes of the transistors M3 and M4 are much larger than those of the other transistors.
  • the transistors M1-M11 may be N-type thin film transistors.
  • this specification does not limit the types of transistors described above.
  • the transistors M1-M11 may also be P-type thin film transistors.
  • One of the two poles of the transistor in this embodiment except the gate is the source and the other is the drain. Due to the structural symmetry of the transistor, the functions of the source and drain of the transistor are interchangeable. That is, the first electrode is the source, the second electrode is the drain, or the first electrode is the drain, and the second electrode is the source.
  • the driving method of the shift register unit provided by the present invention will be described in detail below with reference to FIG.
  • the driving method includes a charging phase, a pull-up phase, a first pull-down phase, and a second pull-down phase.
  • the charging module 501 shown in FIG. 5 charges the pull-up node PU under the control of the input signal of the input terminal INPUT, that is, the level of the pull-up node PU is pulled high to generate a pull-up signal.
  • the output terminal OUTPUT of the shift register is low.
  • the first clock signal terminal CLK outputs a high-level first clock signal, a high-level pull-up signal (ie, the pull-up node PU is at a high level), and a high-level first clock signal.
  • the pull-up module 502 charges the output terminal OUTPUT of the shift register unit. The output terminal OUTPUT is pulled high to a high level, and the pull-up node PU is still high.
  • the reset terminal RESET outputs a first reset signal reset of a high level
  • the first pull-down module 505 discharges the output terminal OUTPUT of the shift register unit under the control of the first reset signal reset, so that The level of the output terminal OUTPUT is pulled low from the high level of the pull-up phase to a low level. Since the first clock signal terminal CLK is turned to the low level and the pull-up node PU is still at the high level in the first pull-down phase, the pull-up module 502 also discharges the output terminal OUTPUT.
  • the second clock signal terminal CLKB outputs a second clock signal of a high level at this time, since the pull-up node PU is at a high level, by adjusting the sizes of the transistors M8 and M9 of the first pull-down control module 503, The pull-down control node output by the first pull-down control module 503 disables the transistors M5 and M6 of the second pull-down control module 504, and in turn causes the second pull-down module 506 to not operate under the control of the pull-down signal.
  • the reset terminal RESET' outputs a second reset signal reset' of the high level
  • the reset module 507 pulls the pull-up node PU from the high level of the pull-up phase to the low level. Therefore, the pull-up module 502 does not work, that is, stops discharging the output terminal OUTPUT.
  • the first reset signal reset is turned to a low level, and the first pull-down module 505 does not operate. Since the pull-up node PU goes low, the second pull-down module 506 operates under the control of the high-level second clock signal, and continues to discharge the output terminal OUTPUT.
  • the pull-up module 502 and the first pull-down module 505 discharge the output end of the shift register unit together, thereby achieving the purpose of quickly pulling down the output terminal level, thereby shortening the pull-down. time.
  • FIG. 8 is a block diagram showing a shift register circuit 800 including a plurality of shift register cells 500 of FIG. 5 in cascade.
  • the shift register circuit 800 can include m shift register units 500, m greater than or equal to 6, and the output of each shift register unit is coupled to a corresponding gate line, except for the first two shift register units and the last two In addition to the shift register unit, the output of the nth shift register unit is coupled to the input of the n+2th shift register unit.
  • each shift register unit includes two reset terminals, wherein the first reset terminal (Reset) of the nth shift register unit and the output of the n+2th shift register unit The terminal is connected, and the second reset terminal (Reset') is connected to the output terminal of the n+3th shift register unit.
  • the timing of the clock signal shown in Fig. 8 is as shown in Fig. 1.
  • n is greater than or equal to 3 and less than or equal to m-3.
  • four or more clock signals are usually used.
  • the number of clock signals is a multiple of two.
  • the frequency of the clock signal is reduced to achieve the purpose of reducing power consumption.
  • the input of the first shift register unit is connected to the frame start signal STV1, and the input of the second shift register unit is also connected to the frame start signal STV1.
  • the last three shift register units are dummy units, and the reset signal terminal can be connected to the frame start signal STV1 to reset the last three shift register units by the frame start signal STV1 when the next cycle comes. In order to achieve a loop of timing (not shown in Figure 8).
  • the shift register circuit of the present embodiment is capable of providing a shift register circuit having a long effective charging time of a pixel and having a simple structure and low power consumption.
  • Embodiments of the present invention also provide a display device including the above shift register circuit.
  • the display device may be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器单元（500）及其驱动方法、一种移位寄存器电路、以及一种显示装置。该移位寄存器单元（500）包括：充电模块（501），与输入端连接、上拉节点连接，用于产生上拉信号；上拉模块（502），与上拉节点、第一时钟信号端以及所述移位寄存器单元（500）的输出端连接，用于对移位寄存器单元（500）的输出端充电；第一下拉控制模块（503），与第二时钟信号端、上拉节点、低电压端以及下拉控制节点连接，用于产生下拉控制信号；第二下拉控制模块（504），与下拉控制节点、上拉节点、第二时钟信号端、低电压端以及下拉节点连接，用于产生下拉信号；第一下拉模块（505），与第一复位端、移位寄存器单元（500）的输出端以及低电压端连接，用于对移位寄存器单元（500）的输出端放电；第二下拉模块（506），与下拉节点、第二时钟信号端、移位寄存器单元（500）的输出端、上拉节点以及低电压端连接，用于对移位寄存器单元（500）的输出端放电；以及复位模块（507），与第二复位端、上拉节点以及低电压端连接，对上拉节点复位。

Description

移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置 技术领域
本发明涉及显示技术领域，更具体地，涉及移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置。
背景技术
平板显示器，因其超薄且节能而被大力推广使用。多数平板显示器中要用到移位寄存器，通过GOA(Gate Drive on Array)技术实现的移位寄存器，即可以省去栅极驱动集成电路IC，还能减少一道制作工序，因此不但降低了平板显示器的制造成本，还在一定程度上缩短了制造周期。
因此，近几年来GOA技术被广泛应用于平板显示器制造。GOA单元自身的功耗相对普通栅极驱动IC较大，为了降低GOA单元本身的功耗往往采用4个或更多的时钟(CLK)信号(时钟信号数为2的倍数)，同时降低时钟信号的频率，从而达到降低功耗的目的。采用该设计，每个时钟周期中高电平时间为扫描一行时间的n倍(n为大于等于2的整数)，两时序相邻的时钟信号间有交叠部分。如图1所示，每一栅极行的实际充电时间为2H所标识的阶段。基于该交叠部分，可以对每一栅极行进行提前开启，待每行真正写入像素电压的时候，该栅极行才完全开启，从而减小了栅极行本身电阻、电容负载所引起的栅极信号上升沿时间(Tr)对充电时间的影响。考虑到栅极行自身的寄生电容和电阻产生的信号延迟，为保证显示屏实际工作中每个像素写入的电压的正确性，对每一个像素而言，往往需要在栅极信号关闭后数据信号才关闭。如图2所示，栅极信号(Vgate)与数据信号(Vdata)关闭的时间差主要取决于栅极行本身电阻、电容负载引起的栅极信号下降沿时间(Tf)，即Tf越大，像素的有效充电时间(Teff)就会越少，如图2，所示Teff＜1H。
图3示出了一种常用GOA设计方法实现的移位寄存器单元的具体电路图，图4示出了包括级联的多个图3中的移位寄存器单元的移位寄存器电路 的框图，其中，各个时钟信号的时序如图1所示。在图3中，晶体管M3和M4分别负责对输出端(OUTPUT)进行充电和放电。当晶体管M3的栅极为高电平且时钟信号(CLK)也为高电平时，输出端输出高电平信号；在完成一行栅极扫描之后，CLK变为低电平，复位信号(RESET)变为高电平，此时晶体管M2和M4开启，对晶体管M3的栅极和输出端进行放电。这样晶体管M3和M4分别处于关闭和开启的状态下，因此只有晶体管M4对输出端进行放电。如图4所示，第n个寄存器单元的输出除了驱动第n行栅极线，还对第n-2个寄存器单元进行复位，并作为第n+2个寄存器单元的输入。这样，通过传统GOA技术实现的移位寄存器电路，只能减小Tr，从而减小Tr对像素有效充电时间的影响。
对于高分辨率或高刷新频率的产品而言，像素的充电时间本身就很少，因此Tf对像素的有效充电时间的影响变得更加明显。
发明内容
本发明提供了一种移位寄存器单元及其驱动方法，一种移位寄存器电路、以及一种显示装置，用以解决现有技术中由于栅极驱动信号的下降沿时间(Tf)长而导致像素有效充电时间(Teff)短的问题。
本发明的一个方面提供了一种移位寄存器单元，包括：
充电模块，输入端和控制端与所述移位寄存器单元的输入端连接，输出端与上拉节点连接，用于接收输入信号，并在输入信号的控制下将上拉节点的电位拉高以产生上拉信号；
上拉模块，控制端与上拉节点连接，输入端与所述移位寄存器单元的第一时钟信号端连接，输出端与所述移位寄存器单元的输出端连接，用于接收第一时钟信号，并且在上拉信号的控制下在上拉阶段对所述移位寄存器单元的输出端进行充电；
第一下拉控制模块，第一控制端和第一输入端与所述移位寄存器单元的第二时钟信号端连接，第二控制端与上拉节点连接，第二输入端与所述移位寄存器单元的低电压端连接，输出端与下拉控制节点连接，用于接收第二时钟信号，并在第二时钟信号和上拉信号的控制下在下拉控制节点处产生下拉控制信号；
第二下拉控制模块，第一控制端与下拉控制节点连接，第二控制端与上拉节点连接，第一输入端与所述移位寄存器单元的第二时钟信号端连接，第二输入端与所述移位寄存器单元的低电压端连接，输出端与下拉节点连接，用于接收第二时钟信号，并在下拉控制信号和上拉信号的控制下，在下拉节点处产生下拉信号；
第一下拉模块，控制端与所述移位寄存器单元的第一复位端连接，输入端与所述移位寄存器单元的输出端连接，输出端与所述移位寄存器单元的低电压端连接，用于在第一下拉阶段在第一复位信号的控制下对所述移位寄存器单元的输出端进行放电；
第二下拉模块，第一控制端与下拉节点连接，第二控制端与所述移位寄存器单元的第二时钟信号端连接，第一输入端与所述移位寄存器的输出端连接，第二输入端与上拉节点连接，输出端与所述移位寄存器单元的低电压端连接，用于在下拉信号和第二时钟信号的控制下在第二下拉阶段对所述移位寄存器单元的输出端进行放电；以及
复位模块，控制端与所述移位寄存器单元的第二复位端连接，输入端与所述上拉节点连接，输出端与所述移位寄存器单元的低电压端连接，用于在第二复位信号的控制下对所述上拉节点进行复位；
其中，所述上拉模块在所述第一下拉阶段对所述移位寄存器单元的输出端进行放电。
优选地，所述充电模块包括第一晶体管，所述第一晶体管的栅极和第一电极与所述移位寄存器单元的输入端连接，第二电极与所述上拉节点连接。
优选地，所述复位模块包括第二晶体管，所述第二晶体管的栅极与所述第二复位端连接，第一电极与所述上拉节点连接，第二电极与低电压端连接。
优选地，所述上拉模块包括第三晶体管，所述第三晶体管的栅极与所述上拉节点连接，第一电极与所述第一时钟信号端连接，第二电极与所述输出端连接。
优选地，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极与所述第一复位端连接，第一电极与所述输出端连接，第二电极与所述低 电压端连接。
优选地，所述第二下拉控制模块包括第五晶体管和第六晶体管，所述第五晶体管的栅极与所述下拉控制节点连接，第一电极与所述第二时钟信号端连接，第二电极与所述下拉节点连接；所述第六晶体管的栅极与所述第三晶体管的栅极连接，第一电极与所述下拉节点连接，第二电极与所述低电压端连接。
优选地，所述第一下拉控制模块包括第七晶体管和第八晶体管，所述第七晶体管的栅极与所述第三晶体管的栅极连接，第一电极与所述下拉控制节点连接，第二电极与所述低电压端连接；所述第八晶体管的栅极和第一电极与所述第二时钟信号端连接，第二电极与所述下拉控制节点连接。
优选地，所述第二下拉模块包括第九晶体管、第十晶体管和第十一晶体管，所述第九晶体管的栅极与所述下拉节点连接，第一电极与所述上拉节点连接，第二电极与所述低电压端连接；所述第十晶体管的栅极与所述下拉节点连接，第一电极与所述输出端连接，第二电极与所述低电压端连接；所述第十一晶体管的栅极与所述第二时钟信号端连接，第一电极与所述输出端连接，第二电极与所述低电压端连接。
优选地，所述上拉模块和所述第一下拉模块在第一下拉阶段同时对所述移位寄存器单元的输出端放电。
优选地，所述第三晶体管和所述第四晶体管的尺寸大于其他晶体管的尺寸。
优选地，所述第二复位信号相对于所述第一复位信号延迟一条栅极线的实际充电时间的1/2。
优选地，所述第一时钟信号的相位与第二时钟信号的相位相反。
本发明的另一方面提供了一种驱动移位寄存器单元的方法，包括：
充电阶段，由充电模块将上拉节点的电平拉高，以产生上拉信号；
上拉阶段，在上拉信号的控制下，由上拉模块对所述移位寄存器单元的输出端进行充电；
第一下拉阶段，由第一下拉模块对所述移位寄存器单元的输出端进行放电；以及
第二下拉阶段，由第二下拉模块对所述移位寄存器单元的输出端进行 放电，
其中，在第一下拉阶段所述上拉模块和所述第一下拉模块同时对所述移位寄存器单元的输出端进行放电。
本发明的再一方面提供了一种移位寄存器电路，包括m个级联的上述移位寄存器单元，m大于或等于6，每个移位寄存器单元的输出端与对应的栅极线连接，除了前两个移位寄存器单元和最后两个移位寄存器单元以外，第n个移位寄存器单元的输出端与第n+2个移位寄存器单元的输入端连接，
其中第n个移位寄存器单元的第一复位端与第n+2个移位寄存器单元的输出端连接，第二复位端与n+3个移位寄存器单元的输出端连接，并且
n大于或等于3并小于或等于m-3。
本发明的另一方面提供了一种显示装置，包括所述移位寄存器电路。
本发明的移位寄存器单元通过减小栅极驱动信号的下降沿时间Tf，从而增加了像素有效充电时间Teff，并保证显示画面质量。具体地，通过上拉模块与第一下拉模块一同在第一下拉阶段对移位寄存器单元的输出进行放电(即，拉低移位寄存器输出端的电平)，进一步减小了移位寄存器单元输出的下降沿时间，从而提高了放电效率。另外，与传统GOA设计方法中上拉模块仅在上拉阶段中工作不同，本发明中的上拉模块不仅能够用于在上拉阶段对移位寄存器的输出进行充电，而且能够用于下拉阶段对移位寄存器单元的输出进行放电，即同一模块在不同阶段起到不同的作用，从而在保证提高放电效率的同时简化了电路结构。
附图说明
根据结合附图的以下详细描述，本公开的多个实施例的上述和其他方面、特征以及优点将更清楚，在附图中：
图1是示出了采用传统GOA设计的移位寄存器电路的工作时序图；
图2是采用传统GOA设计的栅极行的实际充电时间与像素的有效充电时间的关系图；
图3是示出了采用传统GOA设计的移位寄存器单元的具体电路图；
图4是示出了包括级联的多个图3中的移位寄存器单元的移位寄存器电路的框图；
图5是示出了根据本发明实施例的移位寄存器单元的框图；
图6是示出了根据本发明实施例的图5的移位寄存器单元的具体电路图；
图7是根据本发明实施例的移位寄存器单元的驱动方法流程图；以及
图8是示出了包括级联的多个图5中的移位寄存器单元的移位寄存器电路的框图。
具体实施方式
本发明实施例提供了一种移位寄存器单元及其驱动方法、一种移位寄存器电路以及一种显示装置，实现了移位寄存器单元输出的下降沿时间短，像素的有效充电时间长的移位寄存器单元，以及结构简单且功耗较低的移位寄存器电路和显示装置。
下面结合附图和具体实施例，对本发明的具体实现方式进行详细描述。
参照图5，图5是示出了根据本发明实施例的移位寄存器单元500的框图。移位寄存器单元500包括充电模块501、上拉模块502、第一下拉控制模块530、第二下拉控制模块504、第一下拉模块505、第二下拉模块506以及复位模块507。
充电模块501的输入端和控制端与移位寄存器单元500的输入端INPUT连接，输出端与上拉节点PU连接，用于接收输入信号，并在输入信号的控制下为上拉节点PU充电(即将上拉节点PU的电位拉高)以产生上拉信号。
上拉模块502的控制端与上拉节点PU连接，输入端与移位寄存器单元500的第一时钟信号端CLK连接，输出端与移位寄存器单元500的输出端OUTPUT连接，用于接收第一时钟信号，并且在上拉信号的控制下在上拉阶段对移位寄存器单元500的输出端OUTPUT进行充电(即，将输出端OUTPUT的电平拉高)。
第一下拉控制模块503的第一控制端和第一输入端与移位寄存器单元500的第二时钟信号端CLKB连接，第二控制端与上拉节点PU连接，第二输入端与移位寄存器单元500的低电压端VSS连接，输出端与下拉控制节点PD_CN连接，用于接收第二时钟信号，并在第二时钟信号和上拉信号的控 制下在下拉控制节点PD_CN处产生下拉控制信号。
第二下拉控制模块504的第一控制端与下拉控制节点PD_CN连接，第二控制端与上拉节点PU连接，第一输入端与第二时钟信号端CLKB连接，第二输入端与移位寄存器单元500的低电压端VSS连接，输出端与下拉节点PD连接，用于接收第二时钟信号，并在下拉控制信号和上拉信号的控制下，在下拉节点PD处产生下拉信号。
第一下拉模块505的控制端与移位寄存器单元500的第一复位端RESET连接，输入端与移位寄存器单元500的输出端OUTPUT连接，输出端与移位寄存器单元500的低电压端VSS连接，用于在第一下拉阶段在第一复位信号的控制下对移位寄存器单元500的输出端OUTPUT进行放电(即，将移位寄存器单元500的输出端OUTPUT的电位拉低至移位寄存器单元500的低电压)。
第二下拉模块506的第一控制端与下拉节点PD连接，第二控制端与第二时钟信号端CLKB连接，第一输入端与移位寄存器单元500的输出端OUTPUT，第二输入端与上拉节点PU连接，输出端与移位寄存器单元500的低电压端VSS连接，用于在下拉信号和第二时钟信号的控制下在第二下拉阶段对移位寄存器单元500的输出端OUTPUT进行放电(即，将移位寄存器单元500的输出端OUPUT的电平拉低至移位寄存器单元500的低电压)。
复位模块507的控制端与移位寄存器单元500的第二复位端RESET’连接，输入端与所述上拉节点PU连接，输出端与移位寄存器单元500的低电压端VSS连接，用于接收在第二复位信号的控制下对所述上拉节点PU进行复位。
在本实施例中，第一下拉模块505单独连接至移位寄存器单元500的第一复位端，即，为第一下拉模块505提供独立的复位信号。提供给第一下拉模块505的第一复位信号reset与提供给复位模块507的第二复位信号reset’的不同之处在于，第二复位信号reset’比第一复位信号reset延迟了一条栅极线的实际充电时间的1/2(即，1H)。
在如图3所示的传统的移位寄存器单元中，第一下拉模块505与复位模块507连接至同一复位端，在完成一行栅极线的扫描之后，第一时钟信号转为低电平，复位信号为高电平，复位模块507将上拉节点PU悬空(上拉 节点PU变为低电平)，此时上拉模块502不工作，第一下拉模块505和第二下拉模块506工作，将移位寄存器单元的输出端的电平拉低。
然而，根据本实施例，在完成一行栅极的扫描之后，第一时钟信号转为低电平，提供给第一下拉模块505的复位信号为高电平，第一下拉模块505将移位寄存器的输出端的电平拉低。与此同时，由于提供给复位模块507的第二复位信号reset’仍为低电平，因此与上拉模块502连接的上拉节点PU的电平仍为高电平，因此上拉模块502仍在工作，并且由于提供给上拉模块502的第一时钟信号此时转为低电平，因此上拉模块502与第一下拉模块505同时对移位寄存器单元的输出端进行放电。这样，通过上拉模块502与第一下拉模块505在第一下拉阶段同时对移位寄存器单元500的输出端OUPUT进行放电，提高了移位寄存器单元输出端的放电效率，进一步减小栅极驱动信号的下降沿时间Tf，从而增加了像素有效充电时间Teff。1H过后，与复位模块507连接的第二复位信号reset’变为高电压，使得上拉节点PU变为低电平，进而上拉模块502不工作，此时由于上拉节点PU变为低电平，第二下拉模块506工作，继续对移位寄存器单元500的输出端放电。同时与第一下拉模块505连接的第一复位信号转为低电平，第一下拉模块505不工作。
另外，根据本实施例的上拉模块不仅能够用于在上拉阶段对移位寄存器的输出进行充电，而且能够用于在下拉阶段对移位寄存器单元的输出进行放电，即同一模块在不同阶段起到不同的作用，从而在保证提高放电效率的同时简化了电路结构。
以下将参照图6，具体描述本发明实施例提供的移位寄存器单元的各个模块的具体电路图。
图6示出了根据本发明实施例的移位寄存器单元500的各个模块具体电路图。
参见图6，充电模块501包括第一晶体管M1。第一晶体管M1的栅极和第一电极与移位寄存器单元500的输入端INPUT连接，第二电极与上拉节点PU连接。在该实施例中，M1的栅极对应于充电模块501的控制端，第一电极对应于充电模块501的输入端，第二电极对应于充电模块501的输出端。
复位模块507包括第二晶体管M2。第二晶体管M2的栅极与第二复位 端RESET’连接，第一电极与上拉节点PU连接，第二电极与低电压端VSS连接。在该实施例中，M2的栅极对应于复位模块507的控制端，第一电极对应于复位模块507的输入端，第二电极对应于复位模块507的输出端。
上拉模块502包括第三晶体管M3。第三晶体管M3的栅极与上拉节点PU连接，第一电极与第一时钟信号端CLK连接，第二电极与输出端OUTPUT连接。在该实施例中，M3的栅极对应于上拉模块502的控制端，第一电极对应于上拉模块502的输入端，第二电极对应于上拉模块502的输出端。
第一下拉模块505包括第四晶体管M4。第四晶体管M4的栅极与第一复位端RESET连接，第一电极与输出端OUTPUT连接，第二电极与低电压端VSS连接。在该实施例中，M4的栅极对应于第一下拉模块505的控制端，第一电极对应于第一下拉模块505的输入端，第二电极对应于第一下拉模块505的输出端。
第二下拉控制模块504包括第五晶体管M5和第六晶体管M6。第五晶体管M5的栅极与下拉控制节点PD_CN连接，第一电极与第二时钟信号端CLKB连接，第二电极与下拉节点PD连接。第六晶体管M6的栅极与第三晶体管M3的栅极(即，上拉节点PU)连接，第一电极与下拉节点PD连接，第二电极与低电压端VSS连接。这里第一时钟信号端CLK发出的第一时钟信号的相位与第二时钟信号端CLKB发出的第二时钟信号的相位相反。在该实施例中，M5的栅极对应于第二下拉控制模块504的第一控制端，M5的第一电极对应于第二下拉控制模块504的第一输入端，M5的第二电极对应于第二下拉控制模块504的输出端；M6的栅极对应于第二下拉控制模块504的第二控制端，第一电极对应于第二下拉控制模块504的输出端，第二电极对应于第二下拉控制模块504的第二输入端。
第一下拉控制模块503包括第七晶体管M7和第八晶体管M8，第七晶体管M7的栅极与第三晶体管M3的栅极(即，上拉节点PU)连接，第一电极与下拉控制节点PD_CN连接，第二电极与低电压端VSS连接。第八晶体管M8的栅极和第一电极与第二时钟信号端CLKB连接，第二电极与下拉控制节点PD_CN连接。在该实施例中，M7的栅极对应于第一下拉控制模块503的第二控制端，第一电极对应于第一下拉控制模块503的输出端，第二 电极对应于第一下拉控制模块503的第二输入端；M8的栅极对应于第一下拉控制模块503的第一控制端，第一电极对应于第一下拉控制模块503的第一输入端，第二电极对应于第一下拉控制模块503的输出端。
第二下拉模块506包括第九晶体管M9、第十晶体管M10和第十一晶体管M11。第九晶体管M9的栅极与下拉节点PD连接，第一电极与上拉节点PU连接，第二电极与低电压端VSS连接。第十晶体管M10的栅极与下拉节点PD连接，第一电极与输出端OUTPUT连接，第二电极与低电压端连接VSS。第十一晶体管M11的栅极与第二时钟信号端CLKB连接，第一电极与输出端OUTPUT连接，第二电极与低电压端VSS连接。在该实施例中，M9的栅极对应于第二下拉模块506的第一控制端，第一电极对应于第二下拉模块506的第二输入端，第二电极对应于第二下拉模块506的输出端；M10的栅极对应于第二下拉模块506的第一控制端，第一电极对应于第二下拉模块506的第一输入端，第二电极对应于第二下拉模块506的输出端；M11的栅极对应于第二下拉模块506的第二控制端，第一电极对应于第二下拉模块506的第一输入端，第二电极对应于第二下拉模块506的输出端。
在本实施例中，向晶体管M4的栅极提供第一复位信号reset，向晶体管M2的栅极提供第二复位信号reset’，其中第二复位信号reset’比第一复位信号reset延迟了一条栅极线的实际充电时间的1/2(即，1H)。在完成一行栅极线的扫描之后(即，在上拉阶段之后)，第一时钟信号转为低电平，提供给晶体管M4的第一复位信号reset为高电平，晶体管M4开启，对移位寄存器单元的输出端进行放电。与此同时，由于上拉节点PU的电平仍为高电平，因此栅极与上拉节点PU连接、而第一电极与低电平的第一时钟信号连接的晶体管M3仍处在开启状态，对移位寄存器单元的输出端进行放电。因此晶体管M3和晶体管M4同时对移位寄存器单元的输出端进行放电。1H过后，由于第二复位信号reset’开启，晶体管M2也开启，同时由于上拉节点PU转为低电平，晶体管M3关闭。而由于第一复位信号reset转为低电平，因此晶体管M4也关闭。由于此时第二时钟信号为高电平，第二下拉模块506工作，继续对移位寄存器单元500的输出端放电。这样，通过晶体管M3与晶体管M4在第一下拉阶段同时对移位寄存器单元500的输出端OUPUT进行放电，提高了移位寄存器单元输出端的放电效率，进一步减小 栅极驱动信号的下降沿时间Tf，从而增加了像素有效充电时间Teff。
另外，根据本实施例，由于晶体管M3和晶体管M4对移位寄存器单元的输出端进行充放电，因此晶体管M3和晶体管M4的尺寸要远大于其他晶体管的尺寸。
需要说明的是，在上述示例中，具体如图6所示，晶体管M1-M11可以为N型薄膜晶体管。然而本说明书不对上述晶体管的类型加以限制。例如，晶体管M1-M11也可以为P型薄膜晶体管。
本实施例中的晶体管除栅极之外的两个极之一为源极，另一个为漏极。由于晶体管在结构上的对称性，因此晶体管的源极和漏极的功能可以互换。即，第一电极为源极，第二电极为漏极，或者第一电极为漏极，第二电极为源极。
以下参照图7详细描述本发明提供的移位寄存器单元的驱动方法。该驱动方法包括充电阶段、上拉阶段、第一下拉阶段和第二下拉阶段。
在充电阶段，图5所示的充电模块501在输入端INPUT的输入信号的控制下，对上拉节点PU进行充电，即将上拉节点PU的电平拉高，以产生上拉信号。此时移位寄存器的输出端OUTPUT为低电平。
在上拉阶段，第一时钟信号端CLK输出高电平的第一时钟信号，在高电平的上拉信号(即，上拉节点PU处于高电平)和高电平的第一时钟信号的控制下，上拉模块502对移位寄存器单元的输出端OUTPUT进行充电。输出端OUTPUT由低电平被拉高至高电平，上拉节点PU仍为高电平。
在第一下拉阶段，复位端RESET输出高电平的第一复位信号reset，因此第一下拉模块505在第一复位信号reset的控制下对移位寄存器单元的输出端OUTPUT进行放电，使得将输出端OUTPUT的电平由上拉阶段的高电平拉低至低电平。由于在该第一下拉阶段，第一时钟信号端CLK转为低电平，而上拉节点PU仍为高电平，因此上拉模块502也对输出端OUTPUT进行放电。另外，尽管此时第二时钟信号端CLKB输出高电平的第二时钟信号，但是由于上拉节点PU为高电平，通过调整第一下拉控制模块503的晶体管M8和M9的大小，使第一下拉控制模块503输出的下拉控制节点使第二下拉控制模块504的晶体管M5和M6不开启，并进而使得第二下拉模块506在下拉信号的控制下不工作。
最后，在经过1H之后的第二下拉阶段，复位端RESET’输出高电平的第二复位信号reset’，复位模块507将上拉节点PU由上拉阶段的高电平拉低至低电平，因此上拉模块502不工作，即停止对输出端OUTPUT的放电。同时，在该第二下拉阶段，第一复位信号reset转为低电平，第一下拉模块505不工作。而由于上拉节点PU变为低电平，第二下拉模块506在高电平的第二时钟信号的控制下工作，继续对输出端OUTPUT进行放电。
这样实现了在第一下拉阶段上拉模块502与第一下拉模块505一同对移位寄存器单元的输出端进行放电的目的，进而实现了快速下拉输出端电平的目的，从而缩短了下拉时间。
图8是示出了包括级联的多个图5中的移位寄存器单元500的移位寄存器电路800的框图。
移位寄存器电路800可以包括m个移位寄存器单元500，m大于或等于6，每个移位寄存器单元的输出端与对应的栅极线连接，除了前两个移位寄存器单元和最后两个移位寄存器单元以外，第n个移位寄存器单元的输出端与第n+2个移位寄存器单元的输入端连接。另外，与图4不同之处在于，每个移位寄存器单元包含两个复位端，其中第n个移位寄存器单元的第一复位端(Reset)与第n+2个移位寄存器单元的输出端连接，第二复位端(Reset’)与第n+3个移位寄存器单元的输出端连接。
图8中所示的时钟信号的时序如图1所示。
这里，n大于或等于3并小于或等于m-3。另外为了降低移位寄存器电路的功耗，通常采用4个或更多的时钟信号。优选地，时钟信号的数目为2的倍数。同时降低时钟信号的频率，以达到降低功耗的目的。
通常第一个移位寄存器单元的输入端连接帧起始信号STV1，第二个移动寄存器单元的输入端也连接帧起始信号STV1。通常最后三个移位寄存器单元是伪(dummy)单元，其复位信号端可连接帧起始信号STV1，以便在下一周期到来时，将最后三个移位寄存器单元通过帧起始信号STV1复位，以便实现时序的循环(图8中未示出)。
本实施例的移位寄存器电路能够提供像素的有效充电时间长的、结构简单且功耗较低的移位寄存器电路。
本发明的实施例还提供了一种显示装置，包括上述移位寄存器电路。 所述显示装置可以为：液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
显然，本领域的技术人员可以在不脱离本发明的精神和范围的前提下对本发明的实施例进行各种改变和修改。本发明的范围由所附权利要求及其等同物来限定。

Claims (15)

  1. 一种移位寄存器单元，包括：
    充电模块，输入端和控制端与所述移位寄存器单元的输入端连接，输出端与上拉节点连接，用于接收输入信号，并在输入信号的控制下将上拉节点的电位拉高以产生上拉信号；
    上拉模块，控制端与上拉节点连接，输入端与所述移位寄存器单元的第一时钟信号端连接，输出端与所述移位寄存器单元的输出端连接，用于接收第一时钟信号，并且在上拉信号的控制下在上拉阶段对所述移位寄存器单元的输出端进行充电；
    第一下拉控制模块，第一控制端和第一输入端与所述移位寄存器单元的第二时钟信号端连接，第二控制端与上拉节点连接，第二输入端与所述移位寄存器单元的低电压端连接，输出端与下拉控制节点连接，用于接收第二时钟信号，并在第二时钟信号和上拉信号的控制下在下拉控制节点处产生下拉控制信号；
    第二下拉控制模块，第一控制端与下拉控制节点连接，第二控制端与上拉节点连接，第一输入端与所述移位寄存器单元的第二时钟信号端连接，第二输入端与所述移位寄存器单元的低电压端连接，输出端与下拉节点连接，用于接收第二时钟信号，并在下拉控制信号和上拉信号的控制下，在下拉节点处产生下拉信号；
    第一下拉模块，控制端与所述移位寄存器单元的第一复位端连接，输入端与所述移位寄存器单元的输出端连接，输出端与所述移位寄存器单元的低电压端连接，用于在第一下拉阶段在第一复位信号的控制下对所述移位寄存器单元的输出端进行放电；
    第二下拉模块，第一控制端与下拉节点连接，第二控制端与所述移位寄存器单元的第二时钟信号端连接，第一输入端与所述移位寄存器单元的输出端连接，第二输入端与上拉节点连接，输出端与所述移位寄存器单元的低电压端连接，用于在下拉信号和第二时钟信号的控制下在第二下拉阶段对所述移位寄存器单元的输出端进行放电；以及
    复位模块，控制端与所述移位寄存器单元的第二复位端连接，输入端 与所述上拉节点连接，输出端与所述移位寄存器单元的低电压端连接，用于在第二复位信号的控制下对所述上拉节点进行复位；
    其中，所述上拉模块在所述第一下拉阶段对所述移位寄存器单元的输出端进行放电。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述充电模块包括第一晶体管，所述第一晶体管的栅极和第一电极与所述移位寄存器单元的输入端连接，第二电极与所述上拉节点连接。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述复位模块包括第二晶体管，所述第二晶体管的栅极与所述第二复位端连接，第一电极与所述上拉节点连接，第二电极与低电压端连接。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述上拉模块包括第三晶体管，所述第三晶体管的栅极与所述上拉节点连接，第一电极与所述第一时钟信号端连接，第二电极与所述输出端连接。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极与所述第一复位端连接，第一电极与所述输出端连接，第二电极与所述低电压端连接。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述第二下拉控制模块包括第五晶体管和第六晶体管，所述第五晶体管的栅极与所述下拉控制节点连接，第一电极与所述第二时钟信号端连接，第二电极与所述下拉节点连接；所述第六晶体管的栅极与所述第三晶体管的栅极连接，第一电极与所述下拉节点连接，第二电极与所述低电压端连接。
  7. 根据权利要求1所述的移位寄存器单元，其中，所述第一下拉控制模块包括第七晶体管和第八晶体管，所述第七晶体管的栅极与所述第三晶体管的栅极连接，第一电极与所述下拉控制节点连接，第二电极与所述低电压端连接；所述第八晶体管的栅极和第一电极与所述第二时钟信号端连接，第二电极与所述下拉控制节点连接。
  8. 根据权利要求1所述的移位寄存器单元，其中，所述第二下拉模块包括第九晶体管、第十晶体管和第十一晶体管，所述第九晶体管的栅极与所述下拉节点连接，第一电极与所述上拉节点连接，第二电极与所述低电压端连接；所述第十晶体管的栅极与所述下拉节点连接，第一电极与所述 输出端连接，第二电极与所述低电压端连接；所述第十一晶体管的栅极与所述第二时钟信号端连接，第一电极与所述输出端连接，第二电极与所述低电压端连接。
  9. 根据权利要求1所述的移位寄存器单元，其中，所述上拉模块和所述第一下拉模块在第一下拉阶段同时对所述移位寄存器单元的输出端放电。
  10. 根据权利要求2至8中任一项所述的移位寄存器单元，其中，所述第三晶体管和所述第四晶体管的尺寸大于其他晶体管的尺寸。
  11. 根据权利要求1所述的移位寄存器单元，其中，所述第二复位信号相对于所述第一复位信号延迟一条栅极线的实际充电时间的1/2。
  12. 根据权利要求1所述的移位寄存器单元，其中所述第一时钟信号的相位与第二时钟信号的相位相反。
  13. 一种驱动根据权利要求1-12中任一项所述的移位寄存器单元的方法，包括：
    充电阶段，由充电模块将上拉节点的电平拉高，以产生上拉信号；
    上拉阶段，在上拉信号的控制下，由上拉模块对所述移位寄存器单元的输出端进行充电；
    第一下拉阶段，由第一下拉模块对所述移位寄存器单元的输出端进行放电；以及
    第二下拉阶段，由第二下拉模块对所述移位寄存器单元的输出端进行放电，
    其中，在所述第一下拉阶段所述上拉模块与所述第一下拉模块同时对所述移位寄存器单元的输出端进行放电。
  14. 一种移位寄存器电路，包括m个级联的如权利要求1-12中任一项所述的移位寄存器单元，m大于或等于6，每个移位寄存器单元的输出端与对应的栅极线连接，除了前两个移位寄存器单元和最后两个移位寄存器单元以外，第n个移位寄存器单元的输出端与第n+2个移位寄存器单元的输入端连接，
    其中第n个移位寄存器单元的第一复位端与第n+2个移位寄存器单元的输出端连接，第二复位端与第n+3个移位寄存器单元的输出端连接，并 且
    n大于或等于3并小于或等于m-3。
  15. 一种显示装置，包括权利要求14所述的移位寄存器电路。
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