WO2013135061A1 - 栅极驱动电路及显示器 - Google Patents

栅极驱动电路及显示器 Download PDF

Info

Publication number
WO2013135061A1
WO2013135061A1 PCT/CN2012/084022 CN2012084022W WO2013135061A1 WO 2013135061 A1 WO2013135061 A1 WO 2013135061A1 CN 2012084022 W CN2012084022 W CN 2012084022W WO 2013135061 A1 WO2013135061 A1 WO 2013135061A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
circuit
signal
clock
gate
Prior art date
Application number
PCT/CN2012/084022
Other languages
English (en)
French (fr)
Inventor
李天马
祁小敬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/995,142 priority Critical patent/US9201445B2/en
Publication of WO2013135061A1 publication Critical patent/WO2013135061A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present invention relates to the field of displays, and in particular to a gate driving circuit and a display for a Thin Film Transistor Liquid Crystal Display (TFT-LCD). Background technique
  • TFT-LCD the basic principle of displaying each frame of picture is to sequentially output the data signals required for each row of pixels in a row by row through a source driver.
  • the gate driver passes each of the gate drivers in turn.
  • a row of pixel gates inputs a square wave of a certain width and gates each row of pixels line by line.
  • the conventional method is to bind a gate driver IC and a source driver IC to a glass panel by a COG (Chip on Glass) process.
  • COG Chip on Glass
  • the gate drive has more output lines and increases the length of the gate drive integrated circuit, which not only increases the COG (Chip on Glass) process. The difficulty, and the product yield is reduced.
  • the related art has proposed a gate driver on Array (GOA) technology, which is to fabricate a gate drive integrated circuit on a glass panel by an array process, which can not only reduce production cost, but also increase The reliability of the panel, and for small-sized TFT-LCDs, can also reduce the difficulty of IC bounding.
  • GOA gate driver on Array
  • the shift register is used in GOA technology to form a gate drive circuit that generates the desired waveform for the gate.
  • Figure 1 shows the circuit schematic of the existing shift register.
  • the shift register includes four transistors and two capacitors, each of which includes a gate, a source, and a drain.
  • the drain of the first transistor T1, the source of the second transistor T2, the gate of the third transistor T3, the first end of the first capacitor C1 and the first end of the second capacitor C2 meet to form a node P.
  • the gate and the source of the first transistor T1 are connected, and serve as a signal input terminal STV of the shift register, the drain of the first transistor T1 is connected to the source of the second transistor T2; the gate and the fourth of the second transistor T2
  • the gate of the transistor T4 is connected, and receives a reset signal Reset from the outside, the drain of the second transistor T2 receives the low level signal Voff from the external circuit; the source of the third transistor T3 receives the second clock from the external circuit Signal CLK2, the gate of the third transistor T3 is connected to the node P, and the third transistor T3
  • the drain is connected to the source of the fourth transistor T4 and the second terminal of the second capacitor C2, and serves as an output terminal Row of the shift register; the gate of the fourth transistor T4 is connected to the gate of the second transistor T2, The drain of the fourth transistor T4 is connected to the drain of the second transistor T2 and receives the low level signal Voff from the external circuit; the second end of the first capacitor C1 is connected to the first clock signal
  • the above-mentioned shift register uses a higher clock frequency, which results in a gate drive circuit for generating a desired waveform of the gate, which not only has higher power consumption, but also has weak anti-interference ability, and has smaller output power and more burrs. Large, sometimes floating, causing the output waveform to be unstable. Summary of the invention
  • the technical problem to be solved by the present invention is to provide a gate driving circuit which has low power consumption, strong anti-interference ability, and stable waveform, in view of the above-mentioned drawbacks existing in the prior art.
  • the present invention also provides a display having low power consumption and strong anti-interference ability.
  • a gate driving circuit comprising a plurality of cascaded shift registers, the shift register comprising:
  • the signal output circuit receiving a forward clock signal from an external circuit, the signal output circuit comprising a clock transistor and a level transistor, the signal output circuit outputting the forward direction when the clock transistor is turned on a clock signal, the signal output circuit outputs a constant low level signal when the level transistor is turned on;
  • the signal input circuit is connected to a gate of the clock transistor, receives an output signal of a previous shift register, and causes the clock transistor when an output signal of the received previous shift register is valid Conduction
  • a reverse circuit the reverse circuit being coupled to a gate of the clock transistor and a gate of a level transistor, receiving a reverse clock signal from an external circuit, and causing the reverse clock signal to be active when the reverse clock signal is active Turning off the clock transistor while turning on the level transistor;
  • the signal input circuit, the signal output circuit, the reverse circuit, and the logic circuit meet to form a first node; the signal output circuit and the reverse circuit meet to form a second node.
  • the signal output circuit, the signal input circuit, and the reverse circuit are each composed of a MOS type transistor.
  • the signal input circuit includes a first transistor, a drain and a gate of the first transistor are connected to an output signal of a previous shift register; a source of the first transistor is connected to the first node.
  • the clock transistor includes a second transistor
  • the level transistor includes a third transistor
  • a drain of the second transistor receives a forward clock signal from an external circuit
  • a gate of the second transistor Connecting to the first node
  • a source of the second transistor is connected to a drain of the third transistor, and is also used as an output end of the signal output circuit
  • a gate of the third transistor is connected to The second node
  • the source of the third transistor receives a low level signal from an external circuit.
  • the inverting circuit includes a fourth transistor and a fifth transistor, a drain of the fourth transistor receiving a high level signal from an external circuit; a gate of the fourth transistor and the fifth a gate of the transistor is connected, and each receives a reverse clock signal from an external circuit; a source of the fourth transistor is coupled to the second node; a drain of the fifth transistor is coupled to the first node; The source of the fifth transistor receives a low level signal from an external circuit.
  • the logic circuit includes a capacitor, a first end of the capacitor coupled to the first node, and a second end of the capacitor coupled to a low level signal of an external circuit.
  • the shift register further includes: a hold circuit that ensures that the level transistor remains off when the clock transistor is turned on.
  • the holding circuit includes a sixth transistor and a seventh transistor, a drain of the sixth transistor is connected to a drain of the seventh transistor, and is connected to the second node; a gate of the transistor is connected to the first node; a source of the sixth transistor is connected to a source of the seventh transistor, and together receives a low level signal from an external circuit; The gate receives a forward clock signal from an external circuit.
  • the present invention also provides a display including a gate driving circuit using the gate driving circuit as described above.
  • the signal input circuit of the gate drive circuit turns on the valid output signal of the previous shift register to turn on the clock transistor; and, after the reverse circuit receives the effective reverse clock signal from the external circuit, Deactivating the clock transistor and turning on the level transistor; Thereby reducing the clock frequency, thereby reducing the power consumption of the gate driving circuit and improving the anti-interference ability of the gate driving circuit.
  • the logic circuit keeps the clock transistor turned on before the level transistor is turned on, reducing the glitch of the output waveform, thereby improving the stability of the output waveform of the gate driving circuit.
  • the gate driving circuit provided by the present invention uses fewer transistors, that is, less transistors are used to obtain the required waveform of the gate, thereby reducing the cost of the gate driving circuit.
  • the display provided by the invention uses a lower clock frequency when performing line scanning, thereby reducing the power consumption of the display, improving the anti-interference ability of the display, and thereby improving the picture quality of the display.
  • the gate drive circuit uses fewer transistors, which can reduce the cost of the display.
  • 1 is a circuit schematic diagram of a conventional shift register
  • FIG. 2 is a structural block diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a circuit schematic diagram of a shift register in a gate driving circuit according to an embodiment of the present invention
  • FIG. 4 is a timing chart of operation of a shift register in a gate driving circuit according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a display according to an embodiment of the present invention. detailed description
  • the gate driving circuit provided in this embodiment includes a plurality of shift registers OUT1, OUT2, and OUT3 having the same circuit structure.
  • the plurality of shift registers are cascaded to sequentially receive the forward clock signal CLK provided by the external circuit.
  • the reverse clock signal CLKB is 180 degrees out of phase with the forward clock signal CLK, and the input terminal STV of the latter shift register is connected to the output terminal OUTPUT of the previous shift register.
  • each shift register includes:
  • a signal output circuit 32 receives a forward clock signal CLK from an external circuit.
  • the signal output circuit 32 includes a clock transistor and a level transistor. When the clock transistor is turned on, the signal output circuit 32 outputs a clock signal.
  • the signal output circuit 32 outputs a constant low level signal;
  • the signal input circuit 31 is connected to the gate of the clock transistor, receives the output signal of the previous shift register, and turns on the clock transistor when the received output signal of the previous shift register is valid. ;
  • An inverting circuit 33 which is connected to the gate of the clock transistor and the gate of the level transistor, receives the inverted clock signal CLKB from the external circuit, and turns off the clock transistor when the inverted clock signal CLKB is active Turning on the level transistor;
  • the logic circuit 34 is coupled to the gate of the clock transistor to keep the clock transistor turned on before the level transistor is turned on;
  • the signal input circuit 31, the signal output circuit 32, the reverse circuit 33, the logic circuit 34 and the hold circuit 35 meet to form a first node P; the signal output circuit 32 and the reverse circuit 33 meet to form a second node Q. Further, the signal input circuit 31, the signal output circuit 32, and the reverse circuit 33 are each composed of an NMOS type transistor.
  • the signal input circuit 31 includes a first transistor M1, and the drain of the first transistor M1 is connected to its gate, and serves as an input terminal STV of the register and an output terminal of the previous shift register (output terminal of the signal output circuit 32). Connected to receive the output signal of the previous shift register; the source of the first transistor M1 is connected to the first node P.
  • the clock transistor in the signal output circuit 32 includes a second transistor M2, the level transistor includes a third transistor M3; the drain of the second transistor M2 receives a forward clock signal CLK from an external circuit; the gate of the second transistor M2 is connected to The first node P; the source of the second transistor M2 is connected to the drain of the third transistor M3, and together serves as the output terminal OUTPUT of the register; the gate of the third transistor M3 is connected to the second node Q; the third transistor M3 The source receives a low level signal Vss from an external circuit.
  • the reverse circuit 33 includes a fourth transistor M4 and a fifth transistor M5, the drain of the fourth transistor M4 receiving the high level signal Vdd from the external circuit; the gate of the fourth transistor M4 is connected to the gate of the fifth transistor M5, And receiving the reverse clock signal CLKB from the external circuit; the source of the fourth transistor M4 is connected to the second node Q; the drain of the fifth transistor M5 is connected to the first node Point P; The source of the fifth transistor M5 receives the low level signal Vss from the external circuit.
  • the logic circuit 34 includes a capacitor CO. The first end of the capacitor CO is connected to the first node P, and the capacitor
  • the second end of the CO is connected to the low level signal Vss of the external circuit.
  • the logic circuit 34 can maintain the first node P at a high level, thereby keeping the second transistor M2 turned on, causing the signal output circuit 32 to output a stable clock signal, thereby stabilizing the shift register output. Waveform.
  • the shift register further includes:
  • a hold circuit 35 ensures that the level transistor remains off when the clock transistor is turned on.
  • the hold circuit 35 is connected to the signal output circuit 32 and the reverse circuit 33 at the second node Q, and the hold circuit 35 is composed of an NMOS type transistor.
  • the holding circuit 35 includes a sixth transistor M6 and a seventh transistor M7.
  • the drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7 and is connected to the second node Q.
  • the gate of the sixth transistor M6 is connected.
  • To the first node P; the source of the sixth transistor M6 is connected to the source of the seventh transistor M7, and simultaneously receives the low level signal Vss from the external circuit; the gate of the seventh transistor M7 receives the positive from the external circuit To the clock signal CLK.
  • the third transistor M3 when the second transistor M2 is turned on by the holding circuit 35, the third transistor M3 is kept off, so that the clock signal outputted by the signal output circuit due to the conduction of the third transistor M3 can be avoided, thereby causing the shift register to be output.
  • a stable waveform when the second transistor M2 is turned on by the holding circuit 35, the third transistor M3 is kept off, so that the clock signal outputted by the signal output circuit due to the conduction of the third transistor M3 can be avoided, thereby causing the shift register to be output.
  • FIG. 4 is a timing chart showing the operation of a shift register in a gate driving circuit according to an embodiment of the present invention.
  • a high level is first applied to the reverse clock signal CLKB, so that the fifth transistor M5 is turned on, and the capacitor CO is discharged, so that the first node P is in low power.
  • the second transistor M2 is turned off.
  • the fourth transistor M4 is turned on, so that the second node Q is at a high level, so that the third transistor M3 is turned on, and the shift register outputs a low level.
  • the reverse clock signal CLKB inputs a low level signal
  • the fourth transistor M4 and the fifth transistor M5 are turned off.
  • the input terminal STV of the shift register receives a start signal, or an input signal, and the start signal is a high level signal
  • the first transistor M1 is turned on
  • the capacitor CO is charged
  • the first node P is at a high level, thereby making the sixth
  • the transistor M6 is turned on to ensure that the second node Q is at a low level, and the third transistor M3 is turned off; at the same time, the second transistor M2 is turned on, the forward clock signal CLK outputs a low-level clock signal, and the output terminal of the shift register is outputted by Vout. Low level.
  • the reverse clock signal CLKB inputs a low level signal, and the fourth transistor M4 and the fifth transistor M5 are turned off.
  • the first node P is still at a high level because the capacitor C0 is charged,
  • the two transistors M2 and the sixth transistor M6 are turned on, the second node Q is at a low level, and the third transistor M3 is turned off.
  • the forward clock signal CLK outputs a high-level clock signal, and the output terminal Vout of the shift register outputs a high level; meanwhile, the seventh transistor M7 is turned on, and the sixth transistor M6 and the seventh transistor M7 are turned on to ensure the second node Q.
  • the third transistor M3 is turned off, so that the output signal of the output terminal Vout of the shift register is synchronized with the output of the forward clock signal CLK, that is, the output of the output terminal Vout of the shift register is at a high level.
  • the reverse clock signal CLKB inputs a low level signal, and the fourth transistor M4 and the fifth transistor M5 are turned off.
  • the first node P is still at a high level due to the capacitance CO, the second transistor M2 and the sixth transistor M6 are turned on, the second node Q is at a low level, and the third transistor M3 is turned off.
  • the forward clock signal CLK outputs a low-level clock signal, and the output terminal Vout of the shift register outputs a low level; meanwhile, the seventh transistor M7 is turned off, and the sixth transistor M6 is turned on, which ensures that the second node Q is at a low level,
  • the three transistors M3 are turned off.
  • the forward clock signal CLK outputs a low level clock signal
  • the seventh transistor M7 is turned off.
  • the reverse clock signal CLKB inputs a high level signal
  • the fourth transistor M4 and the fifth transistor M5 are turned on.
  • the fifth transistor M5 is turned on to discharge the capacitor CO
  • the first node P is at a low level
  • the second transistor M2 and the sixth transistor M6 are turned off.
  • the fourth transistor M4 is turned on, the second node Q is at a high level, the third transistor M3 is turned on, and the output terminal Vout of the shift register outputs a low level.
  • the shift register uses a lower clock frequency, which can effectively reduce the power consumption of the gate drive circuit and improve the anti-interference ability of the gate drive circuit.
  • the output waveform of the shift register is stabilized, so that the output of the gate driving circuit is stabilized.
  • Fig. 5 is an output waveform diagram of the gate driving circuit according to the embodiment of the present invention.
  • the gate driving circuit of the present embodiment uses a smaller number of transistors to obtain a waveform required for a waveform-stabilized gate, and uses fewer transistors, thereby reducing the production cost of the gate driving circuit.
  • the gate driving circuit of the present embodiment is composed of an NMOS type transistor
  • the present invention is not limited thereto, and the gate driving circuit can also be composed of a PMOS type transistor, and can be obtained the same as the NMOS type transistor.
  • Technical effect is not limited thereto, and the gate driving circuit can also be composed of a PMOS type transistor, and can be obtained the same as the NMOS type transistor.
  • the signal input circuit of the gate drive circuit turns on the valid output signal of the previous shift register to turn on the clock transistor; and, after the reverse circuit receives the effective reverse clock signal from the external circuit, Turning off the clock transistor and turning on the level transistor; thereby reducing the clock frequency, thereby reducing the power consumption of the gate driving circuit and improving the gate driving power The anti-interference ability of the road.
  • the logic circuit keeps the clock transistor turned on before the level transistor is turned on, reducing the glitch of the output waveform, thereby improving the stability of the output waveform of the gate driving circuit.
  • the gate drive circuit uses the fewer transistors to obtain the desired waveform of the gate, thereby reducing the cost of the gate drive circuit.
  • FIG. 6 is a schematic structural diagram of a display according to an embodiment of the present invention.
  • the display includes a liquid crystal display panel, a gate driving circuit 200, and a data driving circuit 300.
  • the liquid crystal panel includes an array substrate 100, a color filter substrate (not shown), and the array substrate 100 and the color filter substrate.
  • the liquid crystal molecules (not shown) are provided with a thin film transistor array for controlling the twist angle of the liquid crystal molecules on the array substrate 100, and the gate driving circuit 200 outputs a row driving signal to control the on or off of the thin film transistor.
  • the gate driving circuit 200 uses the gate driving circuit provided in this embodiment.
  • the present invention has been described above by taking a liquid crystal display as an example, it should be understood that the present invention can be applied not only to a liquid crystal display but also to other display devices including a pixel array and driven in a row or column manner, such as an OLED display device.
  • the display of the present embodiment uses the gate driving circuit provided by the above embodiment, which uses a lower clock frequency when performing line scanning, thereby reducing the power consumption of the display, improving the anti-interference ability of the display, and thereby improving The picture quality of the display.
  • the gate drive circuit uses fewer transistors, which can reduce the cost of the display.
  • the source s and the drain g of the above various transistors are manufactured in the same process, and are nominally interchangeable, and can be changed in name according to the direction of the voltage.
  • the types of the transistors in the same pixel circuit may be the same or different, and it is only necessary to adjust the timing high and low levels of the corresponding gate-on signal source according to the characteristics of its own threshold voltage.
  • the preferred way is that the transistors that require the same gate-on signal source are of the same type. More preferably, all of the thin film transistors are of the same type in the same pixel circuit, and are either n-type transistors or p-type transistors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种栅极驱动电路及显示器，该栅极驱动电路包括多个级联的移位寄存器。移位寄存器包括：信号输出电路（32）、信号输入电路（31）、反向电路（33）和逻辑电路（33）。信号输出电路（32）接收来自外部电路的正向时钟信号，信号输出电路（32）包括时钟晶体管和电平晶体管。时钟晶体管导通时信号输出电路输出正向时钟信号，电平晶体管导通时信号输出电路输出恒低电平信号。信号输入电路（31）接收前一移位寄存器的输出信号，并在接收的前一移位寄存器输出信号有效时使时钟晶体管导通。反向电路（33）接收来自外部电路的反向时钟信号，在反向时钟信号有效时使时钟晶体管截止，同时使电平晶体管导通。逻辑电路（33）在电平晶体管导通前，使时钟晶体管保持导通。该栅极驱动电路功耗低，抗干扰能力强，输出波形稳定。

Description

槺极驱动电路及显示器 技术领域
本发明涉及显示器领域，具体涉及一种用于薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, 简称 TFT-LCD ) 的栅极驱动电路及显 示器。 背景技术
在 TFT-LCD中， 显示每一帧画面的基本原理是通过源极驱动器（source driver )将每一行像素所需的数据信号依次逐行输出， 同时，栅极驱动器（ gate driver )通过依次对每一行像素栅极输入一定宽度的方波而逐行选通每一行像 素。
传统的方法是将栅极驱动集成电路 ( gate driver IC )和源极驱动集成电路 ( source driver IC )通过 COG ( Chip on Glass )工艺绑定（ bounding )在玻璃 面板上。 然而， 在实际生产过程中， 当 TFT-LCD的分辨率较高时， 栅极驱动 的输出线较多， 而且会增加栅极驱动集成电路的长度， 这不仅增加了 COG ( Chip on Glass )工艺的难度， 而且降低了产品的良率。
为此， 相关技术人员提出了阵列基板栅极驱动 ( Gate Driver on Array, 以 下简称 GOA )技术， 其是将栅极驱动集成电路通过阵列工艺制作在玻璃面板 上， 这不仅可以降低生产成本， 增加面板的可靠性， 而且对于小尺寸的 TFT-LCD而言， 还可以减小集成电路绑定（ IC bounding ) 的难度。
移位寄存器在 GOA技术中被用于构成产生栅极所需波形的栅极驱动电 路。 图 1 为现有的移位寄存器的电路原理图。 请参阅图 1 , 移位寄存器包括 四个晶体管和两个电容， 每个晶体管均包括栅极、 源极和漏极。 其中， 第一 晶体管 T1的漏极、 第二晶体管 T2的源极、 第三晶体管 T3的栅极、 第一电 容 C1的第一端和第二电容 C2的第一端交汇形成节点 P。 第一晶体管 T1的 栅极和源极连接， 并作为移位寄存器的信号输入端 STV, 第一晶体管 T1 的 漏极与第二晶体管 T2的源极连接； 第二晶体管 T2的栅极与第四晶体管 T4 的栅极连接， 并接收来自外部的重设信号 Reset, 第二晶体管 T2的漏极接收 来自外部电路的低电平信号 Voff;第三晶体管 T3的源极接收来自外部电路的 第二时钟信号 CLK2, 第三晶体管 T3的栅极与节点 P连接， 第三晶体管 T3 的漏极与第四晶体管 T4的源极、 第二电容 C2的第二端连接， 并作为移位寄 存器的输出端 Row; 第四晶体管 T4的栅极与第二晶体管 T2的栅极连接， 第 四晶体管 T4的漏极与第二晶体管 T2的漏极连接， 并接收来自外部电路的低 电平信号 Voff; 第一电容 C1的第二端与第一时钟信号 CLK1连接，第一端与 节点 P连接； 第二电容 C2的第一端与节点 P连接， 第二端与第三晶体管 T3 的漏极、 第四晶体管 T4的源极连接。
然而， 上述移位寄存器使用的时钟频率较高， 导致用于产生栅极所需波 形的栅极驱动电路不仅功耗较高， 抗干扰能力较弱， 而且输出功率较小， 毛 刺较多、 较大， 有时还会出现悬空， 导致输出波形不稳定。 发明内容
本发明要解决的技术问题就是针对现有技术中存在的上述缺陷， 提供一 种栅极驱动电路， 其不仅功耗低， 抗干扰能力强， 而且波形稳定。
为此， 本发明还提供一种显示器， 其功耗低， 抗干扰能力强。
根据本发明实施例， 提供了一种栅极驱动电路， 包括多个级联的移位寄 存器， 所述移位寄存器包括：
信号输出电路， 所述信号输出电路接收来自外部电路的正向时钟信号， 所述信号输出电路包括时钟晶体管和电平晶体管， 在所述时钟晶体管导通时 所述信号输出电路输出所述正向时钟信号， 在所述电平晶体管导通时所述信 号输出电路输出恒低电平信号；
信号输入电路， 所述信号输入电路与所述时钟晶体管的栅极连接， 其接 收前一移位寄存器的输出信号， 并在所接收的前一移位寄存器的输出信号有 效时使所述时钟晶体管导通；
反向电路， 所述反向电路与所述时钟晶体管的栅极和电平晶体管的栅极 连接， 其接收来自外部电路的反向时钟信号， 并在所述反向时钟信号有效时 使所述时钟晶体管截止， 同时使所述电平晶体管导通；
逻辑电路， 所述逻辑电路与所述时钟晶体管连接， 其在所述电平晶体管 导通前， 使所述时钟晶体管保持导通。
在一个示例中， 所述信号输入电路、 所述信号输出电路、 所述反向电路 和所述逻辑电路交汇形成第一节点； 所述信号输出电路和所述反向电路交汇 形成第二节点。 在一个示例中， 所述信号输出电路、 所述信号输入电路和所述反向电路 均是由 MOS型晶体管组成。
在一个示例中， 所述信号输入电路包括第一晶体管， 所述第一晶体管的 漏极和栅极连接前一移位寄存器的输出信号； 所述第一晶体管的源极连接至 所述第一节点。
在一个示例中， 所述时钟晶体管包括第二晶体管， 所述电平晶体管包括 第三晶体管； 所述第二晶体管的漏极接收来自外部电路的正向时钟信号； 所 述第二晶体管的栅极连接至所述第一节点； 所述第二晶体管的源极与所述第 三晶体管的漏极连接， 而且一并作为所述信号输出电路的输出端； 所述第三 晶体管的栅极连接至所述第二节点； 所述第三晶体管的源极接收来自外部电 路的低电平信号。
在一个示例中， 所述反向电路包括第四晶体管和第五晶体管， 所述第四 晶体管的漏极接收来自外部电路的高电平信号； 所述第四晶体管的栅极与所 述第五晶体管的栅极连接， 并均接收来自外部电路的反向时钟信号； 所述第 四晶体管的源极连接至所述第二节点； 所述第五晶体管的漏极连接至所述第 一节点； 所述第五晶体管的源极接收来自外部电路的低电平信号。
在一个示例中， 所述逻辑电路包括电容， 所述电容的第一端连接至所述 第一节点， 所述电容的第二端连接到外部电路的低电平信号。
在一个示例中， 所述移位寄存器还包括： 保持电路， 所述保持电路是在 所述时钟晶体管导通时， 确保所述电平晶体管保持截止。
在一个示例中， 所述保持电路包括第六晶体管和第七晶体管， 所述第六 晶体管的漏极和所述第七晶体管的漏极连接， 并连接至所述第二节点； 所述 第六晶体管的栅极连接至所述第一节点； 所述第六晶体管的源极与所述第七 晶体管的源极连接， 并一并接收来自外部电路的低电平信号； 所述第七晶体 管的栅极接收来自外部电路的正向时钟信号。
本发明还提供一种显示器， 包括栅极驱动电路， 所述栅极驱动电路釆用 如上所述的栅极驱动电路。
本发明具有以下有益效果：
其一， 栅极驱动电路的信号输入电路接收到前一移位寄存器的有效的输 出信号后使所述时钟晶体管导通； 而且， 反向电路接收到来自外部电路的有 效的反向时钟信号后， 使所述时钟晶体管截止， 并使所述电平晶体管导通； 从而降低了时钟频率， 进而降低了栅极驱动电路的功耗， 提高了栅极驱动电 路的抗干扰能力。
其二， 逻辑电路是在所述电平晶体管导通前， 使所述时钟晶体管保持导 通， 减少了输出波形的毛刺， 从而提高了栅极驱动电路输出波形的稳定性。
其三， 本发明提供的栅极驱动电路使用的晶体管较少， 即， 釆用较少的 晶体管获了得栅极所需波形， 从而降低了栅极驱动电路的成本。
因此， 本发明提供的显示器在进行行扫描时， 使用的时钟频率较低， 从 而降低了显示器的功耗， 提高了显示器的抗干扰能力， 进而提高了显示器的 画面质量。 另外， 栅极驱动电路使用的晶体管较少， 从而可以降低显示器的 成本。 附图说明
图 1为现有的移位寄存器的电路原理图；
图 2为本发明实施例栅极驱动电路的结构框图；
图 3为本发明实施例栅极驱动电路中的移位寄存器的电路原理图； 图 4为本发明实施例栅极驱动电路中的移位寄存器的工作时序图； 图 5为本发明实施例栅极驱动电路的输出波形图；
图 6为本发明实施例显示器的结构示意图。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结合附图对 本发明提供的栅极驱动电路及显示器进行详细描述。 显然， 所描述的实施例 仅仅是本发明一部分实施例， 而不是全部的实施例。基于本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施 例， 都属于本发明保护的范围。
图 2为本发明实施例的栅极驱动电路的结构框图。 请参阅图 2, 本实施 例提供的栅极驱动电路包括多个具有相同电路结构的移位寄存器 0UT1、 OUT2和 OUT3 , 多个移位寄存器级联，依次接收外部电路提供的正向时钟信 号 CLK和与该正向时钟信号 CLK相位相差 180°的反向时钟信号 CLKB, 后 一移位寄存器的输入端 STV连接前一移位寄存器的输出端 OUTPUT。
图 3为本发明实施例栅极驱动电路中的移位寄存器的电路原理图。 请一 并参阅图 2和图 3 , 每一移位寄存器均包括：
一信号输出电路 32,其接收来自外部电路的正向时钟信号 CLK,信号输 出电路 32包括时钟晶体管和电平晶体管，在时钟晶体管导通时该信号输出电 路 32输出时钟信号， 在电平晶体管导通时该信号输出电路 32输出恒低电平 信号；
一信号输入电路 31 , 信号输入电路 31与时钟晶体管的栅极连接， 其接 收前一移位寄存器的输出信号， 并在所接收到的前一移位寄存器的输出信号 有效时使时钟晶体管导通；
一反向电路 33 , 反向电路 33与时钟晶体管的栅极和电平晶体管的栅极 连接， 其接收来自外部电路的反向时钟信号 CLKB, 在反向时钟信号 CLKB 有效时使时钟晶体管截止并使电平晶体管导通；
一逻辑电路 34, 逻辑电路 34与时钟晶体管的栅极连接， 其在电平晶体 管导通前， 使时钟晶体管保持导通； 以及
其中， 信号输入电路 31、 信号输出电路 32、 反向电路 33、 逻辑电路 34 和保持电路 35交汇形成第一节点 P; 信号输出电路 32、 反向电路 33交汇形 成第二节点 Q。 而且， 信号输入电路 31、 信号输出电路 32、 反向电路 33均 是由 NMOS型晶体管组成。
信号输入电路 31包括第一晶体管 Ml , 第一晶体管 Ml的漏极与其栅极 连接， 并一并作为寄存器的输入端 STV与前一移位寄存器的输出端（信号输 出电路 32的输出端） OUTPUT连接， 以接收前一移位寄存器的输出信号； 第 一晶体管 Ml的源极连接至第一节点 P。
信号输出电路 32中的时钟晶体管包括第二晶体管 M2, 电平晶体管包括 第三晶体管 M3; 第二晶体管 M2 的漏极接收来自外部电路的正向时钟信号 CLK; 第二晶体管 M2的栅极连接至第一节点 P; 第二晶体管 M2的源极与第 三晶体管 M3的漏极连接， 而且一并作为寄存器的输出端 OUTPUT; 第三晶 体管 M3的栅极连接至第二节点 Q; 第三晶体管 M3的源极接收来自外部电 路的低电平信号 Vss。
反向电路 33包括第四晶体管 M4和第五晶体管 M5 , 第四晶体管 M4的 漏极接收来自外部电路的高电平信号 Vdd; 第四晶体管 M4的栅极与第五晶 体管 M5的栅极连接， 并均接收来自外部电路的反向时钟信号 CLKB; 第四 晶体管 M4的源极连接至第二节点 Q; 第五晶体管 M5的漏极连接至第一节 点 P; 第五晶体管 M5的源极接收来自外部电路的低电平信号 Vss。 逻辑电路 34包括电容 CO , 电容 CO的第一端连接至第一节点 P, 电容
CO的第二端连接到外部电路的低电平信号 Vss。
在第三晶体管 M3截止时， 逻辑电路 34可以使第一节点 P保持高电平， 从而使第二晶体管 M2保持导通， 使信号输出电路 32输出稳定的时钟信号， 进而使移位寄存器输出稳定的波形。
在一个示例中， 移位寄存器还包括：
一保持电路 35 , 其是在时钟晶体管导通时， 确保电平晶体管保持截止。 保持电路 35在第二节点 Q与信号输出电路 32和反向电路 33连接， 并 且保持电路 35由 NMOS型晶体管组成。
保持电路 35包括第六晶体管 M6和第七晶体管 M7 , 第六晶体 M6管的 漏极和第七晶体管 M7的漏极连接， 并一并连接至第二节点 Q; 第六晶体管 M6的栅极连接至第一节点 P; 第六晶体管 M6的源极与第七晶体管 M7的源 极连接， 并一并接收来自外部电路的低电平信号 Vss; 第七晶体管 M7的栅极 接收来自外部电路的正向时钟信号 CLK。
本实施例借助保持电路 35在第二晶体管 M2导通时， 使第三晶体管 M3 保持截止， 从而可以避免因第三晶体管 M3导通而影响信号输出电路输出的 时钟信号， 进而使移位寄存器输出稳定的波形。
图 4为本发明实施例栅极驱动电路中的移位寄存器的工作时序图。 请一 并参阅图 3和图 4 , 在 tl时间段之前， 首先对反向时钟信号 CLKB施加一高 电平，使第五晶体管 M5导通，电容 CO放电，从而使第一节点 P处于低电平， 进而使第二晶体管 M2断开。 同时， 第四晶体管 M4导通， 使第二节点 Q处 于高电平， 从而使第三晶体管 M3导通， 移位寄存器输出低电平。
在 tl时间段内， 反向时钟信号 CLKB输入低电平信号， 第四晶体管 M4 和第五晶体管 M5截止。移位寄存器的输入端 STV接收起始信号，或称 Input 信号， 起始信号为高电平信号， 第一晶体管 Ml导通， 电容 CO充电， 第一节 点 P处于高电平，从而使第六晶体管 M6导通，确保第二节点 Q处于低电平， 第三晶体管 M3截止； 同时使第二晶体管 M2导通， 正向时钟信号 CLK输出 低电平时钟信号， 移位寄存器的输出端 Vout输出低电平。
在 t2时间段内， 反向时钟信号 CLKB输入低电平信号， 第四晶体管 M4 和第五晶体管 M5截止。 第一节点 P由于电容 C0被充电而仍处于高电平， 第 二晶体管 M2和第六晶体管 M6导通， 第二节点 Q处于低电平， 第三晶体管 M3截止。正向时钟信号 CLK输出高电平时钟信号，移位寄存器的输出端 Vout 输出高电平； 同时第七晶体管 M7导通， 第六晶体管 M6和第七晶体管 M7 导通， 可以确保第二节点 Q处于低电平，从而可以确保第三晶体管 M3截止， 从而使移位寄存器的输出端 Vout的输出信号与正向时钟信号 CLK的输出同 步， 即移位寄存器的输出端 Vout的输出为高电平。
在 t3时间段内， 反向时钟信号 CLKB输入低电平信号， 第四晶体管 M4 和第五晶体管 M5截止。 第一节点 P由于电容 CO的原因而仍处于高电平， 第 二晶体管 M2和第六晶体管 M6导通， 第二节点 Q处于低电平， 第三晶体管 M3截止。正向时钟信号 CLK输出低电平时钟信号，移位寄存器的输出端 Vout 输出低电平； 同时第七晶体管 M7截止， 第六晶体管 M6导通， 可以确保第 二节点 Q处于低电平， 第三晶体管 M3截止。
在 t4时间段内， 正向时钟信号 CLK输出低电平时钟信号， 第七晶体管 M7截止。反向时钟信号 CLKB输入高电平信号，第四晶体管 M4和第五晶体 管 M5导通。第五晶体管 M5导通使得电容 CO放电，第一节点 P处于低电平， 第二晶体管 M2和第六晶体管 M6截止。 第四晶体管 M4导通， 第二节点 Q 处于高电平， 第三晶体管 M3导通， 移位寄存器的输出端 Vout输出低电平。
从工作时序来看， 移位寄存器使用的时钟频率较低， 从而可以有效地降 低栅极驱动电路的功耗， 而且可以提高栅极驱动电路的抗干扰能力。 另外， 移位寄存器的输出波形稳定， 从而使得栅极驱动电路的输出稳定， 如图 5所 示， 图 5为本发明实施例栅极驱动电路的输出波形图。 此外， 本实施例栅极 驱动电路釆用了较少的晶体管即可获得波形稳定的栅极所需的波形， 使用了 较少的晶体管， 从而可以降低栅极驱动电路的生产成本。
需要说明的是， 虽然本实施例栅极驱动电路是由 NMOS型晶体管组成， 但本发明并不局限于此， 栅极驱动电路也可以釆用 PMOS型晶体管组成， 而 且可以获得与 NMOS型晶体管相同的技术效果。
本实施例提供的栅极驱动电路具有以下优点：
其一， 栅极驱动电路的信号输入电路接收到前一移位寄存器的有效的输 出信号后使所述时钟晶体管导通； 而且， 反向电路接收到来自外部电路的有 效的反向时钟信号后， 使所述时钟晶体管截止， 并使所述电平晶体管导通； 从而降低了时钟频率， 进而降低了栅极驱动电路的功耗， 提高了栅极驱动电 路的抗干扰能力。
其二，逻辑电路在所述电平晶体管导通前，使所述时钟晶体管保持导通， 减少了输出波形的毛刺， 从而提高了栅极驱动电路输出波形的稳定性。
其三， 栅极驱动电路釆用较少的晶体管获得了栅极所需波形， 从而降低 了栅极驱动电路的成本。
图 6为本发明实施例显示器的结构示意图。 请参阅图 6, 显示器包括液 晶显示面板、 栅极驱动电路 200和数据驱动电路 300 , 液晶面板包括阵列基 板 100、 彩膜基板（图中未示出） 以及设置在阵列基板 100和彩膜基板之间 的液晶分子（图中未示出）， 在阵列基板 100上设有控制液晶分子扭转角度的 薄膜晶体管阵列， 栅极驱动电路 200输出行驱动信号以控制薄膜晶体管的导 通或截止。 而且， 栅极驱动电路 200釆用本实施例提供的栅极驱动电路。
尽管上面以液晶显示为例描述了本发明， 然而应了解本发明不仅可以应 用于液晶显示器， 而且还可以应用于包括像素阵列且按照行或列方式驱动的 其它显示装置， 诸如 OLED显示装置。
本实施例显示器由于釆用上述本实施例提供的栅极驱动电路， 其在进行 行扫描时， 使用的时钟频率较低， 从而降低了显示器的功耗， 提高了显示器 的抗干扰能力， 进而提高显示器的画面质量。 另外， 栅极驱动电路使用的晶 体管较少， 从而可以降低显示器的成本。
需要说明的是， 上述各种晶体管的源极 s和漏极 g的制作工艺相同， 名 称上是可以互换的， 其可根据电压的方向在名称上改变。 而且， 同一像素电 路中各个晶体管的类型可以相同， 也可以不同， 只需根据其自身阔值电压的 特点， 调整相应的栅极开启信号源的时序高低电平即可。 当然， 优选的方式 为， 需要相同栅极开启信号源的晶体管的类型相同。 更为优选的， 同一像素 电路中， 所有薄膜晶体管的类型相同， 均为 n型晶体管或 p型晶体管。
可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而釆用的示 例性实施方式， 然而本发明并不局限于此。 对于本领域内的普通技术人员而 言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变型和改进， 这 些变型和改进也视为本发明的保护范围。

Claims

权 利 要 求 书
1、 一种栅极驱动电路， 包括多个级联的移位寄存器， 所述移位寄存器包 括：
信号输出电路， 所述信号输出电路接收来自外部电路的正向时钟信号， 所述信号输出电路包括时钟晶体管和电平晶体管， 在所述时钟晶体管导通时 所述信号输出电路输出所述正向时钟信号， 在所述电平晶体管导通时所述信 号输出电路输出恒低电平信号；
信号输入电路， 所述信号输入电路与所述时钟晶体管的栅极连接， 其接 收前一移位寄存器的输出信号， 并在所接收的前一移位寄存器的输出信号有 效时使所述时钟晶体管导通；
反向电路， 所述反向电路与所述时钟晶体管的栅极和电平晶体管的栅极 连接， 其接收来自外部电路的反向时钟信号， 并在所述反向时钟信号有效时 使所述时钟晶体管截止， 同时使所述电平晶体管导通；
逻辑电路， 所述逻辑电路与所述时钟晶体管连接， 其在所述电平晶体管 导通前， 使所述时钟晶体管保持导通。
2、 根据权利要求 1所述的栅极驱动电路， 其中， 所述信号输入电路、 所 述信号输出电路、 所述反向电路和所述逻辑电路交汇形成第一节点； 所述信 号输出电路和所述反向电路交汇形成第二节点。
3、 根据权利要求 2所述的栅极驱动电路， 其中， 所述信号输出电路、 所 述信号输入电路和所述反向电路均是由 MOS型晶体管组成。
4、根据权利要求 3所述的栅极驱动电路， 其中， 所述信号输入电路包括 第一晶体管，所述第一晶体管的漏极和栅极连接前一移位寄存器的输出信号； 所述第一晶体管的源极连接至所述第一节点。
5、根据权利要求 3所述的栅极驱动电路， 其中， 所述时钟晶体管包括第 二晶体管， 所述电平晶体管包括第三晶体管； 所述第二晶体管的漏极接收来 自外部电路的正向时钟信号； 所述第二晶体管的栅极连接至所述第一节点； 所述第二晶体管的源极与所述第三晶体管的漏极连接， 而且一并作为所述信 号输出电路的输出端； 所述第三晶体管的栅极连接至所述第二节点； 所述第 三晶体管的源极接收来自外部电路的低电平信号。
6、根据权利要求 3所述的栅极驱动电路， 其中， 所述反向电路包括第四 晶体管和第五晶体管， 所述第四晶体管的漏极接收来自外部电路的高电平信 号； 所述第四晶体管的栅极与所述第五晶体管的栅极连接， 并均接收来自外 部电路的反向时钟信号； 所述第四晶体管的源极连接至所述第二节点； 所述 第五晶体管的漏极连接至所述第一节点； 所述第五晶体管的源极接收来自外 部电路的低电平信号。
7、根据权利要求 3所述的栅极驱动电路，其中，所述逻辑电路包括电容， 所述电容的第一端连接至所述第一节点， 所述电容的第二端连接到外部电路 的低电平信号。
8、根据权利要求 1所述的栅极驱动电路，其中，所述移位寄存器还包括： 保持电路， 所述保持电路是在所述时钟晶体管导通时， 确保所述电平晶 体管保持截止。
9、根据权利要求 8所述的栅极驱动电路， 其中， 所述保持电路包括第六 晶体管和第七晶体管，所述第六晶体管的漏极和所述第七晶体管的漏极连接， 并连接至所述第二节点； 所述第六晶体管的栅极连接至所述第一节点； 所述 第六晶体管的源极与所述第七晶体管的源极连接， 并一并接收来自外部电路 的低电平信号； 所述第七晶体管的栅极接收来自外部电路的正向时钟信号。
10、 一种显示器， 包括栅极驱动电路， 其特征在于， 所述栅极驱动电路 釆用权利要求 1-9任意一项所述的栅极驱动电路。
PCT/CN2012/084022 2012-03-14 2012-11-02 栅极驱动电路及显示器 WO2013135061A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/995,142 US9201445B2 (en) 2012-03-14 2012-11-02 Gate driving circuit for thin film transistor liquid crystal display and thin film transistor liquid crystal display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210067475.3A CN102651208B (zh) 2012-03-14 2012-03-14 一种栅极驱动电路及显示器
CN201210067475.3 2012-03-14

Publications (1)

Publication Number Publication Date
WO2013135061A1 true WO2013135061A1 (zh) 2013-09-19

Family

ID=46693205

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/084022 WO2013135061A1 (zh) 2012-03-14 2012-11-02 栅极驱动电路及显示器

Country Status (3)

Country Link
US (1) US9201445B2 (zh)
CN (1) CN102651208B (zh)
WO (1) WO2013135061A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105047130A (zh) * 2015-06-23 2015-11-11 上海天马有机发光显示技术有限公司 一种移位寄存单元及其驱动方法、栅极驱动电路

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101340197B1 (ko) * 2011-09-23 2013-12-10 하이디스 테크놀로지 주식회사 쉬프트 레지스터 및 이를 이용한 게이트 구동회로
CN102651208B (zh) * 2012-03-14 2014-12-03 京东方科技集团股份有限公司 一种栅极驱动电路及显示器
JP2014112166A (ja) * 2012-12-05 2014-06-19 Japan Display Inc 表示装置
CN104078017B (zh) 2014-06-23 2016-05-11 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104091574B (zh) * 2014-06-25 2016-03-02 京东方科技集团股份有限公司 移位寄存器、阵列基板、显示装置及其驱动方法
CN104064159B (zh) * 2014-07-17 2016-06-15 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104518767B (zh) * 2014-07-18 2017-10-24 上海华虹宏力半导体制造有限公司 时钟幅度加倍电路
CN104157252B (zh) * 2014-07-29 2017-01-18 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
US9766517B2 (en) * 2014-09-05 2017-09-19 Semiconductor Energy Laboratory Co., Ltd. Display device and display module
CN105895011B (zh) * 2015-01-26 2019-02-15 上海和辉光电有限公司 移位寄存器单元、栅极驱动电路及显示面板
CN104658498B (zh) * 2015-02-06 2017-04-19 昆山龙腾光电有限公司 移位寄存器与栅极驱动电路
CN105185411B (zh) * 2015-06-30 2019-03-26 上海天马有机发光显示技术有限公司 一种移位寄存器及其驱动方法
CN105047127B (zh) * 2015-09-21 2017-12-22 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、行扫描驱动电路、显示装置
CN105206225B (zh) * 2015-10-12 2017-09-01 深圳市华星光电技术有限公司 Oled栅极驱动电路架构
CN106652867B (zh) * 2015-11-04 2020-02-21 上海和辉光电有限公司 移位寄存器单元、栅极驱动电路及显示面板
CN105489190B (zh) * 2016-02-15 2019-03-15 京东方科技集团股份有限公司 移位寄存单元及其驱动方法、栅极驱动电路、阵列基板
CN105869588B (zh) * 2016-05-27 2018-06-22 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN106952614B (zh) * 2017-03-20 2019-02-22 昆山国显光电有限公司 驱动电路、阵列基板、显示屏及其初始化方法
KR20210045171A (ko) * 2019-10-16 2021-04-26 엘지디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시장치
CN114299884B (zh) * 2022-01-10 2023-10-03 合肥京东方卓印科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553456A (zh) * 2003-06-04 2004-12-08 友达光电股份有限公司 移位寄存电路
CN101295546A (zh) * 2007-04-27 2008-10-29 群康科技(深圳)有限公司 移位寄存器及液晶显示器
CN101303838A (zh) * 2007-01-05 2008-11-12 统宝光电股份有限公司 用纵向移位寄存器产生非重叠输出信号以显示影像的系统
CN102132356A (zh) * 2008-10-30 2011-07-20 夏普株式会社 移位寄存器电路和显示装置以及移位寄存器电路的驱动方法
WO2011148655A1 (ja) * 2010-05-24 2011-12-01 シャープ株式会社 シフトレジスタ
CN102651208A (zh) * 2012-03-14 2012-08-29 京东方科技集团股份有限公司 一种栅极驱动电路及显示器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040097503A (ko) * 2003-05-12 2004-11-18 엘지.필립스 엘시디 주식회사 쉬프트 레지스터
KR101030528B1 (ko) * 2004-05-27 2011-04-26 엘지디스플레이 주식회사 쉬프트 레지스터 및 이를 사용한 액정표시장치
US8055695B2 (en) * 2006-07-12 2011-11-08 Wintek Corporation Shift register with each stage controlled by a specific voltage of the next stage and the stage after thereof
TWI385624B (zh) * 2007-04-11 2013-02-11 Wintek Corp 移位暫存器及其位準控制器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553456A (zh) * 2003-06-04 2004-12-08 友达光电股份有限公司 移位寄存电路
CN101303838A (zh) * 2007-01-05 2008-11-12 统宝光电股份有限公司 用纵向移位寄存器产生非重叠输出信号以显示影像的系统
CN101295546A (zh) * 2007-04-27 2008-10-29 群康科技(深圳)有限公司 移位寄存器及液晶显示器
CN102132356A (zh) * 2008-10-30 2011-07-20 夏普株式会社 移位寄存器电路和显示装置以及移位寄存器电路的驱动方法
WO2011148655A1 (ja) * 2010-05-24 2011-12-01 シャープ株式会社 シフトレジスタ
CN102651208A (zh) * 2012-03-14 2012-08-29 京东方科技集团股份有限公司 一种栅极驱动电路及显示器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105047130A (zh) * 2015-06-23 2015-11-11 上海天马有机发光显示技术有限公司 一种移位寄存单元及其驱动方法、栅极驱动电路

Also Published As

Publication number Publication date
CN102651208B (zh) 2014-12-03
US20140085283A1 (en) 2014-03-27
CN102651208A (zh) 2012-08-29
US9201445B2 (en) 2015-12-01

Similar Documents

Publication Publication Date Title
WO2013135061A1 (zh) 栅极驱动电路及显示器
JP6328153B2 (ja) シフトレジスタ、表示装置、ゲート駆動回路及び駆動方法
US10095058B2 (en) Shift register and driving method thereof, gate driving device
US10593284B2 (en) Shift register unit and method for driving same, shift register circuit and display apparatus
US9305509B2 (en) Shift register unit, gate driving circuit and display apparatus
US9558843B2 (en) Shift register unit, gate driving circuit, and display device comprising the same
EP2725581B1 (en) Shift register and method for driving the same, gate driving device, display device and electronic product
US10204694B2 (en) Shift register, gate driving circuit and display apparatus
WO2016155205A1 (zh) 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法
TWI552130B (zh) 顯示裝置及其閘極移位暫存器的初始化方法
WO2018059075A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US9928797B2 (en) Shift register unit and driving method thereof, gate driving apparatus and display apparatus
WO2016070543A1 (zh) 移位寄存器单元、栅极驱动电路及显示装置
WO2018076665A1 (zh) 移位寄存器、栅极驱动电路、显示面板及驱动方法
WO2012161042A1 (ja) 走査信号線駆動回路、それを備えた表示装置、および走査信号線の駆動方法
US20210183326A1 (en) Shift register element, method for driving the same, gate driver circuit, and display device
CN102800289A (zh) 移位寄存器及其驱动方法、栅极驱动装置与显示装置
KR20190035855A (ko) Goa 회로
WO2014172965A1 (zh) 移位寄存器单元、栅极驱动电路及阵列基板
WO2013026387A1 (zh) 栅极集成驱动电路、移位寄存器及显示屏
WO2013078955A1 (zh) 移位寄存器及其驱动方法、栅极驱动装置与显示装置
US10559242B2 (en) Shift register, driving method thereof, gate line integrated driving circuit and display device
WO2016161727A1 (zh) 移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板
US20180336857A1 (en) Goa circuit and liquid crystal display device
US20070075959A1 (en) Display device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13995142

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12871248

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSZUANT TO RULE 112(1) EPC

122 Ep: pct application non-entry in european phase

Ref document number: 12871248

Country of ref document: EP

Kind code of ref document: A1