WO2013078955A1 - 移位寄存器及其驱动方法、栅极驱动装置与显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动装置与显示装置 Download PDF

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Publication number
WO2013078955A1
WO2013078955A1 PCT/CN2012/084920 CN2012084920W WO2013078955A1 WO 2013078955 A1 WO2013078955 A1 WO 2013078955A1 CN 2012084920 W CN2012084920 W CN 2012084920W WO 2013078955 A1 WO2013078955 A1 WO 2013078955A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
gate
pull
source
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PCT/CN2012/084920
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English (en)
French (fr)
Inventor
祁小敬
吴博
谭文
高永益
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/805,710 priority Critical patent/US9058893B2/en
Publication of WO2013078955A1 publication Critical patent/WO2013078955A1/zh
Priority to US14/708,727 priority patent/US9589537B2/en
Priority to US15/420,876 priority patent/US9734918B2/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of circuit drive technologies, and in particular, to a shift register using GOA (Gate Driver On Array) technology, a driving method thereof, a gate driving device and a display device.
  • GOA Gate Driver On Array
  • TFT-LCD the basic principle of realizing one-frame picture display is to output the signals required for each line of pixels from top to bottom sequentially by source (gate) drive, and sequentially from top to bottom through gate (gate) drive.
  • a pixel line enters a square wave of a certain width for strobing.
  • the conventional shift register applied to the liquid crystal display gate driving device includes a precharge unit T1, a pull-up unit ⁇ 3, a reset unit ⁇ 2, and a pull-down unit ⁇ 4.
  • the ⁇ node (the node connected to the source of T1) is connected to the clock signal CLK1 through the capacitor C1
  • the drain of ⁇ 3 is connected to the clock signal CLK2
  • the ⁇ node is connected to the source of ⁇ 3 through the capacitor C2
  • Voff is zero or low potential Can be (such as GND or VSS power).
  • T1 precharges the P node (the node connected to the source of T1); T3 matches the timing of CLK2 to make the output signal of the shift register of this stage Row. (n) is high level; when the output signal Reset(n+1) of the rear stage shift register is high level, T2 resets the control terminal of T3, and T4 outputs the output signal Row(n) to the shift register of the current stage. Reset.
  • the control terminal and the output terminal of T3 are left floating, which causes the output signal Row(X) of the shift register of this stage to be unstable.
  • the main object of the present invention is to provide a shift register and a driving method thereof, a gate driving device and a display device, which improve the problem that the threshold voltage of the pull-down thin film transistor drifts under a DC bias, and at the same time improve the shift register circuit.
  • the problem of floating out of the output improves the reliability of the circuit.
  • the present invention provides a shift register including a pull-up unit, a reset unit, and an output signal terminal, where
  • the pull-up unit is connected to the output signal end for pulling up an output signal, so that the output signal is at a high level;
  • the resetting unit is respectively connected to the control end of the pull-up unit and the output signal end, and is configured to reset a potential of the control end of the pull-up unit after the output signal is at a high level, so that the The output signal is low;
  • the shift register further includes a pull-down unit
  • the pull-down unit is respectively connected to the control end of the pull-up unit and the output signal end, and is configured to pull down the pull-up unit after resetting the potential of the control terminal of the pull-up unit by the reset unit
  • the potential of the control terminal and the output signal cause the pull up unit to turn off to control the output signal to remain low.
  • the shift register of the present invention further includes a pre-charging unit, the pull-up unit includes a first thin film transistor and a pull-up capacitor, and the pull-up capacitor is connected in parallel to a gate and a source of the first thin film transistor Between the poles;
  • the first thin film transistor has a drain connected to the first clock signal input end, a source connected to the output signal end, and a gate connected to the start signal input end through the precharge unit;
  • the pre-charging unit is configured to pre-charge the pull-up capacitor under the control of the first clock signal and the start signal before the pull-up unit pulls up the output signal, so that the first thin film transistor Turn on.
  • the pre-charging unit includes a second thin film transistor
  • the second thin film transistor has a gate and a drain connected to the start signal input terminal, and a source connected to a gate of the first thin film transistor;
  • the reset unit includes a third thin film transistor and a fourth thin film transistor
  • the third thin film transistor has a gate connected to the reset signal input end, a drain connected to the output signal end, and a source connected to the low level output end;
  • the fourth thin film transistor has a gate connected to the reset signal input end and a gate of the third thin film transistor, a drain connected to a gate of the first thin film transistor, and a source respectively The source of the three thin film transistors is connected to the low level output.
  • the pull-down unit includes a dual pull-down module and a dual pull-down control module, where the dual pull-down module is respectively associated with the dual pull-down control module, the output signal end, and the The control terminal of the pull-up unit is connected to alternately pull down the output signal and the potential of the control terminal of the pull-up unit under the control of the dual pull-down control module.
  • the dual pull-down module includes a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor;
  • the dual pull-down control module is respectively connected to the first clock signal input end and the second signal input end;
  • the dual pull-down control module includes an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor;
  • the fifth thin film transistor has a gate connected to a gate of the sixth thin film transistor, a drain of the ninth thin film transistor, and a source of the eleventh thin film transistor, and a source connected to the low level output end. a drain connected to a gate of the first thin film transistor, a source of the second thin film transistor, and a gate of the eighth thin film transistor, respectively;
  • the sixth thin film transistor has a source connected to the low level output terminal and a drain connected to the output signal end;
  • the seventh thin film transistor has a gate connected to the second clock signal input end, a source connected to the low level output end, and a drain connected to the output signal end;
  • the eighth thin film transistor has a gate connected to a gate of the first thin film transistor, a source connected to a low level output terminal, and a drain and a source of the tenth thin film transistor and a gate of the eleventh thin film transistor, respectively Pole connection
  • the ninth thin film transistor has a gate connected to a gate of the first thin film transistor, a source connected to a low level output terminal, and a drain connected to a source of the eleventh thin film transistor;
  • the tenth thin film transistor has a gate and a drain connected to the first clock signal input terminal, and a source connected to a gate of the eleventh thin film transistor;
  • the eleventh thin film transistor has a drain connected to the first clock signal input end.
  • the dual pull-down module includes a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor;
  • the dual pull-down control module is respectively connected to the first clock signal input end and the second signal input end;
  • the dual pull-down control module includes an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor;
  • the fifth thin film transistor has a gate and a gate of the sixth thin film transistor and a ninth thin film a drain of the film transistor is connected to a source of the eleventh thin film transistor, a source is connected to a low level output terminal, and a drain is respectively connected to a gate of the first thin film transistor and a source of the second thin film transistor a pole connected to a gate of the eighth thin film transistor;
  • the sixth thin film transistor has a source connected to the low level output terminal and a drain connected to the output signal end;
  • the seventh thin film transistor has a gate connected to the second clock signal input end, a source connected to the low level output end, and a drain connected to the output signal end;
  • the eighth thin film transistor has a gate connected to a gate of the first thin film transistor, a source connected to a low level output terminal, and a drain and a source of the tenth thin film transistor and a gate of the eleventh thin film transistor, respectively Pole connection
  • the ninth thin film transistor has a gate connected to the output signal terminal, a source connected to the low level output terminal, and a drain connected to the source of the eleventh thin film transistor;
  • the tenth thin film transistor has a gate and a drain connected to the first clock signal input terminal, and a source connected to a gate of the eleventh thin film transistor;
  • the eleventh thin film transistor has a drain connected to the first clock signal input end.
  • the dual pull-down module includes a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor;
  • the dual pull-down control module includes an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor;
  • the fifth thin film transistor has a gate connected to a gate of the sixth thin film transistor, a drain of the ninth thin film transistor, and a source of the eleventh thin film transistor, and a source connected to the low level output end. a drain connected to a gate of the first thin film transistor and a source of the second thin film transistor, respectively;
  • the sixth thin film transistor has a source connected to the low level output terminal and a drain connected to the output signal end;
  • the seventh thin film transistor has a gate connected to the second clock signal input end, a source connected to the low level output end, and a drain connected to the output signal end;
  • the eighth thin film transistor has a gate connected to the output signal terminal, a source connected to the low level output terminal, and a drain connected to the source of the tenth thin film transistor and the gate of the eleventh thin film transistor, respectively; a ninth thin film transistor having a gate connected to a gate of the first thin film transistor, a source connected to the low level output terminal, and a drain connected to a source of the eleventh thin film transistor;
  • the tenth thin film transistor has a gate and a drain connected to the first clock signal input end, and a source connected to the gate of the eleventh thin film transistor;
  • the eleventh thin film transistor has a drain connected to the first clock signal input terminal.
  • the dual pull-down module includes a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor;
  • the dual pull-down control module includes an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor;
  • the fifth thin film transistor has a gate connected to a gate of the sixth thin film transistor, a drain of the ninth thin film transistor, and a source of the eleventh thin film transistor, and a source connected to the low level output end. a drain connected to a gate of the first thin film transistor and a source of the second thin film transistor, respectively;
  • the sixth thin film transistor has a source connected to the low level output terminal and a drain connected to the output signal end;
  • the seventh thin film transistor has a gate connected to the second clock signal input end, a source connected to the low level output end, and a drain connected to the output signal end;
  • the eighth thin film transistor has a gate connected to the output signal terminal, a source connected to the low level output terminal, and a drain connected to the source of the tenth thin film transistor and the gate of the eleventh thin film transistor, respectively;
  • the ninth thin film transistor has a gate connected to the output signal terminal, a source connected to the low level output terminal, and a drain connected to the source of the eleventh thin film transistor;
  • the tenth thin film transistor has a gate and a drain connected to the first clock signal input end, and a source connected to the gate of the eleventh thin film transistor;
  • the eleventh thin film transistor has a drain connected to the first clock signal input terminal.
  • the present invention also provides a method of driving a shift register applied to the shift register described above, the method of driving the shift register comprising the steps of:
  • Pull-up step The pull-up unit pulls up the output signal of each stage of the shift register, so that the output signal of the stage shift register is high;
  • Reset step after the output signal is high, resetting the potential of the control terminal of the pull-up unit, so that the output signal is low;
  • Pull-down step The pull-down unit pulls down the potential of the control terminal of the pull-up unit and the output signal, so that the pull-up unit is turned off and the output signal is maintained at a low level.
  • the method of driving the shift register further includes a pre-charging step before the pull-up step: the first clock signal is low and the start signal is high Normally, the pull-up capacitor is precharged to turn on the pull-up thin film transistor.
  • the present invention also provides a gate driving device comprising a plurality of stages of the above shift register fabricated on a liquid crystal display array substrate by an array film forming process;
  • the output signal terminals of each of the other shift registers are connected to the reset signal input end of the previous stage shift register adjacent to the shift register;
  • the present invention also provides a display device comprising the above-described liquid crystal display gate driving device.
  • the shift register, the liquid crystal display gate driving device and the method and the display device of the invention improve the pull-down while solving the spurious effect caused by the clock modulation through the double pull-down design.
  • the problem that the threshold voltage of the thin film transistor drifts under the DC bias improves the problem of the output floating in the shift register circuit and improves the reliability of the circuit; at the same time, the use of the power supply is reduced, and the power consumption is reduced.
  • FIG. 1 is a circuit diagram of a conventional shift register applied to a liquid crystal display gate driving device
  • FIG. 2 is a circuit diagram of a shift register according to the first embodiment of the present invention
  • FIG. 3 is a circuit diagram of a shift register according to a second embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a shift register according to a third embodiment of the present invention.
  • FIG. 5 is a timing diagram of the first clock signal CLK, the second clock signal CLKB, the start signal STV, the PU node potential, the PD node potential, the gate drive signal OUT, and the reset signal RESET of the shift register of the embodiment. ;
  • FIG. 6 is a circuit diagram of a liquid crystal display gate driving device according to the present invention.
  • FIG. 7 is a timing chart of an output signal of a liquid crystal display gate driving device according to the present invention
  • FIG. 8 is a circuit diagram of a shift register according to a fourth embodiment of the present invention.
  • FIG. 9 is a circuit diagram of a shift register according to a fifth embodiment of the present invention.
  • Figure 10 is a circuit diagram of a shift register according to a sixth embodiment of the present invention. detailed description As shown in FIG. 2, the shift register according to the first embodiment of the present invention includes a pull-up unit 21, a reset unit 22, a pull-down unit 23, and an output signal terminal OUTPUT, where
  • the pull-up unit 21 is connected to the output signal terminal OUTPUT for pulling up the output signal, so that the output signal is at a high level;
  • the reset unit 22 is respectively connected to the control end of the pull-up unit 21 and the output signal end
  • An OUTPUT connection configured to reset a potential of the control terminal of the pull-up unit 21 after the output signal is at a high level, so that the output signal is at a low level;
  • the pull-down unit 23 is respectively connected to the control end of the pull-up unit 21 and the output signal terminal OUTPUT, and is configured to pull down after the reset unit 22 resets the potential of the control terminal of the pull-up unit 21
  • the potential of the control terminal of the pull-up unit 21 and the output signal cause the pull-up unit 21 to be turned off to control the output signal to remain at a low level.
  • FIG. 3 a circuit diagram of a shift register according to a second embodiment of the present invention.
  • the shift register according to the second embodiment of the present invention is a shift register according to the first embodiment of the present invention.
  • the shift register according to the second embodiment of the present invention further includes a pre-charging unit 31, the pull-up unit 21 includes a first thin film transistor T1 and a pull-up capacitor C1, and the pull-up capacitor C1 is connected in parallel to the first film. Between the gate and the source of the transistor T1;
  • the first thin film transistor T1 has a drain connected to the first clock signal input terminal CLKIN, a source connected to the output signal terminal OUTPUT, and a gate connected to the start signal input terminal STVIN through the precharge unit 31;
  • the pre-charging unit 31 is configured to pre-charge the pull-up capacitor C1 under the control of the first clock signal CLK and the start signal STV before the pull-up unit 21 pulls up the output signal, so that the The first thin film transistor T1 is turned on.
  • the shift register according to the third embodiment of the present invention includes a precharge unit, a pull-up unit, a reset unit, a pull-down unit, a first clock signal input terminal CLKIN, a second clock signal input terminal CLKBIN, The start signal input terminal STVIN, the reset signal input terminal RESETIN, and the output signal terminal OUTPUT, the shift register described in the third embodiment operates under the CLK and CLKB dual clocks of the differential input, wherein
  • the output signal of the shift register is a gate drive signal OUT of the liquid crystal display
  • the first clock signal CLK is input by the first clock signal input terminal CLKIN;
  • the second clock signal CLKB is input by the second clock signal input terminal CLKBIN;
  • the start signal STV is input by the start signal input terminal STVIN;
  • the reset signal RESET is input by the reset signal input terminal RESETIN;
  • the pull-up unit includes a first thin film transistor T1 and a pull-up capacitor C1;
  • a pull-up capacitor C1 is connected in parallel between the gate and the source of the first thin film transistor T1;
  • the first thin film transistor T1 has a drain connected to the first clock signal input terminal CLKIN, a source connected to the output signal terminal OUTPUT, and a gate connected to the start signal input terminal through the precharge unit
  • the pre-charging unit includes a second thin film transistor T2 for half a clock cycle when the first clock signal is low level, the second clock signal is high level, and the start signal is high level.
  • the pull-up capacitor C1 is pre-charged, so that the gate-source voltage of the first thin film transistor T1 rises to a predetermined voltage, which is greater than the threshold voltage of the first thin film transistor T1, so that the first film Transistor T1 is turned on;
  • the first thin film transistor T1 is configured to pull up an output signal and a PU node within a half clock cycle after the first clock signal is at a low level and the start signal is at a high level. That is, the potential of the node connected to the gate of the pull-up thin film transistor T1 is such that the output signal is at a high level;
  • the second thin film transistor T2 has a gate and a drain connected to the start signal input terminal STVIN, and a source connected to the gate of the first thin film transistor T1;
  • the reset unit includes a third thin film transistor T3 and a fourth thin film transistor T4 for resetting the output signal in a half clock cycle in which the reset signal after the output signal is at a high level, so that the output signal is The output signal is low;
  • the third thin film transistor T3 has a gate connected to the reset signal input terminal RESETIN, a drain connected to the output signal terminal OUTPUT, and a source connected to the power source VSS;
  • the fourth thin film transistor T4 has a gate connected to the reset signal input terminal RESETIN and the gate of the third thin film transistor T3, and a drain connected to the gate of the first thin film transistor T1, and the source and the gate respectively
  • the source of the third thin film transistor T3 is connected to the power source VSS;
  • the pull-down unit is configured to pull down an output signal after the half clock cycle, so that the output signal is low level
  • the pull-down unit includes a dual pull-down module 41 and a dual pull-down control module 42, wherein the dual pull-down module 41 is respectively connected to the dual pull-down control module 42, the output signal terminal OUTPUT, and the control terminal of the pull-up unit Connected (in FIG. 4, ie, PU point) for powering the output signal and the control terminal of the pull-up unit under the control of the dual pull-down control module 42 Bits are alternately pulled down;
  • the dual pull-down module 41 includes a fifth thin film transistor T5, a sixth thin film transistor ⁇ 6, and a seventh thin film transistor ⁇ 7;
  • the dual pull-down control module 42 includes an eighth thin film transistor ⁇ 8, a ninth thin film transistor ⁇ 9, a tenth thin film transistor T10, and an eleventh thin film transistor T11;
  • the fifth thin film transistor T5 has gates connected to the gate of the sixth thin film transistor T6, the drain of the ninth thin film transistor T9, and the source of the eleventh thin film transistor T11, respectively, the source and the power supply VSS. Connecting, a drain is respectively connected to a gate of the first thin film transistor T1, a source of the second thin film transistor T2, and a gate of the eighth thin film transistor T8;
  • the sixth thin film transistor ⁇ 6 the source is connected to the power source VSS, and the drain and the output signal end
  • the seventh thin film transistor T7 has a gate connected to the second clock signal input terminal CLKBIN, a source connected to the power source VSS, and a drain connected to the output signal terminal OUTPUT;
  • the eighth thin film transistor T8 has a gate connected to the gate of the first thin film transistor T1, a source connected to the power source VSS, and a drain connected to the source of the tenth thin film transistor T10 and the eleventh thin film transistor T11, respectively.
  • the ninth thin film transistor T9 has a gate connected to the gate of the first thin film transistor T1, a source connected to the power source VSS, and a drain connected to the source of the eleventh thin film transistor T11;
  • the tenth thin film transistor T10 has a gate and a drain connected to the first clock signal input terminal CLKIN, and a source connected to the gate of the eleventh thin film transistor T11;
  • the eleventh thin film transistor T11 has a drain connected to the first clock signal input terminal CLKIN;
  • T6 and ⁇ 7 alternately pull down the output signal to prevent the output of the shift register from floating;
  • An inverter composed of T8, T9, T10, and Til can quickly convert the voltage of the PD node (the node connected to the gate of T6) and the PU node (the node connected to the gate of T1).
  • the inverters composed of T8, T9, T10 and Til have lower pull-up voltage loss than single-stage inverters.
  • the carrier mobility becomes smaller.
  • the required driving voltage becomes variable. Large, so the inverter composed of T8, T9, T10, Til has good effect at low temperature.
  • the simulation results also show that the inverter composed of T8, ⁇ 9, T10 and Til has good effect at low temperature.
  • the second thin film transistor T2 is configured to precharge the pull-up capacitor C1 in a half clock cycle in which the start signal STV is at a high level; a first thin film transistor T1 for outputting a high level signal for gate driving in a half clock cycle after CLK is at a high level after the pull-up capacitor CI is precharged;
  • the fourth thin film transistor T4 is configured to reset the potential of the PU point after the gate drive square wave of the shift register of the current stage is output;
  • the third thin film transistor T3 is configured to: after the first thin film transistor T1 outputs a high level signal for gate driving, CLK becomes a low level, and CLKB becomes a high level within a half clock period, at a next stage Under the control of the shift register output, the output signal of the shift register of the stage is pulled down and reset; the dual pull-down control module 42 is configured to control the dual pull-down module under the control of the dual clock CLK and CLKB and the potential of the PU node. 41 work;
  • the dual pull-down module 41 is configured to alternately pull down the output signal of the shift register of the stage and the potential of the PU node under the control of the output signal of the dual pull-down control module 42.
  • power supply VSS is a low level output.
  • Precharge phase CLK is low, CLKB is high, STV is high, RESET is low; T3, T4, T10, Til are off, T2, ⁇ 7 are on; gate drive signal OUT Set to low level; STV pre-charges the pull-up capacitor C1, so that the voltage of the PU node rises, but T8 and ⁇ 9 cannot be turned on; the PD point potential is low, ⁇ 5, ⁇ 6 are all turned off, so that the gate of T1 That is, the PU node maintains the precharge state, and the gate drive signal OUT remains at a low level;
  • Reset phase STV is low level, CLK is low level, CLKB is high level, RESET is high level; Tl, T2, T10, T11, ⁇ 8, ⁇ 9 are off, ⁇ 3, ⁇ 4, ⁇ 7 are on, The PD node potential is low, the PU node is set low, and the gate drive signal OUT is set low; (4) The first pull-down phase: CLK is high and CLKB is low. STV is low,
  • RESET is ⁇ level; Tl, ⁇ 3, ⁇ 2, ⁇ 4, ⁇ 7, ⁇ 8, ⁇ 9 are off, ⁇ 10, T11 are on, The PD node potential is high, T5, ⁇ 6 are on, and the PU node potential and the gate drive signal OUT are pulled down to a low level;
  • the shift from the start signal STV to the gate drive signal OUT is realized, that is, the top-down gate drive scan output is realized under the dual clock control, and the duty cycle of the pull-down thin film transistor is reduced, thereby improving the Vth drift problem.
  • the present invention reduces the dangling of the output signal and the PU node in the shift register, reducing the stray effect.
  • FIG. 6 A circuit diagram of an embodiment of a liquid crystal display gate driving device according to the present invention is shown in FIG. 6.
  • STV is a start signal
  • an output signal of each stage of the shift register is used as a start signal STV, and an output signal of the following stage As a reset signal RESET, it operates under dual clocks to realize a top-down gate drive scan output.
  • Fig. 7 is a waveform diagram showing the shift output of the liquid crystal display gate driving device of the embodiment.
  • SR1 is the first stage shift register
  • SR2 is the second stage shift register
  • SR3 is the third stage shift register
  • SRn is the nth stage shift register
  • n is a positive integer greater than 3
  • GL1 For the first gate
  • GL2 is the second gate
  • GL3 is the third gate
  • GLn is the nth gate.
  • OUT1 is the output signal of the first stage shift register
  • OUT2 is the output signal of the second stage shift register
  • OUT3 is the output signal of the third stage shift register.
  • FIG. 8 a circuit diagram of a shift register according to a fourth embodiment of the present invention.
  • the shift register according to the fourth embodiment of the present invention is different from the shift register described in the third embodiment above in that the gate of T9 is connected to the output signal terminal OUTPUT instead of the gate of the thin film transistor T1.
  • FIG. 9 a circuit diagram of a shift register according to a fifth embodiment of the present invention.
  • the shift register according to the fifth embodiment of the present invention is different from the shift register described in the third embodiment above in that the gate of T8 is connected to the output signal terminal OUTPUT instead of the gate of the pull-up thin film transistor T1. .
  • FIG. 10 a circuit diagram of a shift register according to a sixth embodiment of the present invention.
  • the shift register according to the sixth embodiment of the present invention is different from the shift register described in the third embodiment above in that the gate of T8 is connected to the output signal terminal OUTPUT instead of the gate of the pull-up thin film transistor T1.
  • the gate of T9 is connected to the output signal terminal OUTPUT instead of the gate of the thin film transistor T1. Extremely connected.
  • the invention avoids the use of large capacitance and avoids direct connection of the clock signal to the capacitor, and only uses the power source
  • VSS helps to reduce the power consumption and space of the circuit.
  • the double pull-down design of the invention improves the stray effect of the pull-down thin film transistor under the DC bias while improving the stray effect brought by the clock modulation, and improves the reliability of the circuit; meanwhile, the power supply is reduced. Use, reduce power consumption.

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Abstract

本发明提供一种移位寄存器及其驱动方法、栅极驱动装置与显示装置。所述移位寄存器包括上拉单元、复位单元、下拉单元和输出信号端；上拉单元与所述输出信号端连接，用于上拉输出信号；复位单元分别与上拉单元的控制端和输出信号端连接，用于在该输出信号为高电平后，对上拉单元的控制端的电位进行复位；下拉单元分别与上拉单元的控制端和所述输出信号端连接，用于在复位单元对所述上拉单元的控制端的电位进行复位后，下拉上拉单元的控制端的电位和该输出信号，使得该上拉单元关闭以控制该输出信号维持为低电平。本发明改善了下拉薄膜晶体管阈值电压在直流偏压下漂移的问题，同时改善了移位寄存器电路中输出悬空的问题，提高了电路的可靠性。

Description

移位寄存器及其驱动方法、 栅极驱动装置与显示装置 技术领域
本发明涉及电路驱动技术领域， 尤其涉及一种釆用了 GOA ( Gate Driver On Array, 阵列基板行驱动）技术的移位寄存器及其驱动方法、 栅极驱动装 置与显示装置。 背景技术
在 TFT-LCD中， 实现一帧画面显示的基本原理是通过 source (源）驱动 将每一行像素所需的信号依次从上往下输出， 通过 gate (栅极）驱动依次从 上到下对每一像素行输入一定宽度的方波进行选通。
如图 1所示， 现有的应用于液晶显示器栅极驱动装置的移位寄存器包括 预充电单元 Tl、 上拉单元 Τ3、 复位单元 Τ2和下拉单元 Τ4。 Ρ节点 （与 T1 的源极连接的节点）通过电容 C1与时钟信号 CLK1连接， Τ3的漏极与时钟 信号 CLK2连接， Ρ节点通过电容 C2与 Τ3的源极连接， Voff是零或低电位 均可（如 GND或 VSS电源）。 当前级移位寄存器的输出信号 Input(n-l)为高 电平时， T1对 P节点（与 T1的源极连接的节点 )进行预充电； T3配合 CLK2 的时序使本级移位寄存器的输出信号 Row(n)为高电平； 当后级移位寄存器的 输出信号 Reset(n+1)为高电平时， T2对 T3的控制端进行复位， T4对本级移 位寄存器的输出信号 Row(n)进行复位。 当后级移位寄存器的输出信号 Reset(n+1)为低电平时， T3 的控制端和输出端悬空， 导致本级移位寄存器的 输出信号 Row(X)不稳定。
并且现今的制造方法是将 gate驱动 IC和 source驱动 IC通过 COG( Chip On Glass, 将芯片固定于玻璃上）工艺黏结在玻璃面板上。 小尺寸 TFT-LCD, 当分辨率较高时， gate驱动和 source驱动输出较多， 驱动 IC的长度将增大， 这将不利于模组驱动 IC的 bonding (绑定 )工艺。 发明内容
本发明的主要目的在于提供一种移位寄存器及其驱动方法、 栅极驱动装 置与显示装置， 改善了下拉薄膜晶体管阔值电压在直流偏压下漂移的问题， 同时改善了移位寄存器电路中输出悬空的问题， 提高了电路的可靠性。 为了达到上述目的， 本发明提供了一种移位寄存器， 包括上拉单元、 复 位单元和输出信号端， 其中，
所述上拉单元， 与所述输出信号端连接， 用于上拉输出信号， 使得该输 出信号为高电平；
所述复位单元， 分别与所述上拉单元的控制端和所述输出信号端连接， 用于在该输出信号为高电平后， 对所述上拉单元的控制端的电位进行复位， 使得该输出信号为低电平；
其特征在于， 所述移位寄存器还包括下拉单元；
所述下拉单元， 分别与所述上拉单元的控制端和所述输出信号端连接， 用于在所述复位单元对所述上拉单元的控制端的电位进行复位后， 下拉所述 上拉单元的控制端的电位和该输出信号， 使得该上拉单元关闭以控制该输出 信号维持为低电平。
实施时， 本发明所述的移位寄存器还包括预充电单元， 所述上拉单元包 括第一薄膜晶体管和上拉电容， 所述上拉电容并联于所述第一薄膜晶体管的 栅极和源极之间；
所述第一薄膜晶体管， 漏极连接第一时钟信号输入端， 源极连接输出信 号端， 栅极通过所述预充电单元连接起始信号输入端；
所述预充电单元， 用于在所述上拉单元上拉输出信号之前， 在第一时钟 信号和起始信号的控制下对所述上拉电容进行预充电， 以使得所述第一薄膜 晶体管导通。
实施时， 所述预充电单元包括第二薄膜晶体管；
所述第二薄膜晶体管， 栅极和漏极与所述起始信号输入端连接， 源极与 所述第一薄膜晶体管的栅极连接；
所述复位单元， 包括第三薄膜晶体管和第四薄膜晶体管；
所述第三薄膜晶体管， 栅极与复位信号输入端连接， 漏极与所述输出信 号端连接， 源极与低电平输出端连接；
所述第四薄膜晶体管 , 栅极分别与所述复位信号输入端和所述第三薄膜 晶体管的栅极连接， 漏极与所述第一薄膜晶体管的栅极连接， 源极分别与所 述第三薄膜晶体管的源极和低电平输出端连接。
实施时， 所述下拉单元包括双下拉模块和双下拉控制模块， 其中， 所述双下拉模块， 分别与所述双下拉控制模块、 所述输出信号端和所述 上拉单元的控制端连接， 用于在所述双下拉控制模块的控制下对所述输出信 号和所述上拉单元的控制端的电位进行交替下拉。
实施时， 所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七 薄膜晶体管；
所述双下拉控制模块分别与第一时钟信号输入端和第二信号输入端连 接；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极、 所述第二薄膜晶体管的源极 和所述第八薄膜晶体管的栅极连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接；
所述第七薄膜晶体管， 栅极与所述第二时钟信号输入端连接， 源极与低 电平输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述第一薄膜晶体管的栅极连接， 源极与 低电平输出端连接， 漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管 的栅极连接；
所述第九薄膜晶体管， 栅极与所述第一薄膜晶体管的栅极连接， 源极与 低电平输出端连接， 漏极与所述第十一薄膜晶体管的源极连接；
所述第十薄膜晶体管， 栅极和漏极与所述第一时钟信号输入端连接， 源 极与第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与所述第一时钟信号输入端连接。
实施时， 所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七 薄膜晶体管；
所述双下拉控制模块分别与第一时钟信号输入端和第二信号输入端连 接；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极、 所述第二薄膜晶体管的源极 和所述第八薄膜晶体管的栅极连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接；
所述第七薄膜晶体管， 栅极与所述第二时钟信号输入端连接， 源极与低 电平输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述第一薄膜晶体管的栅极连接， 源极与 低电平输出端连接， 漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管 的栅极连接；
所述第九薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接， 漏极与所述第十一薄膜晶体管的源极连接；
所述第十薄膜晶体管， 栅极和漏极与所述第一时钟信号输入端连接， 源 极与第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与所述第一时钟信号输入端连接。
实施时， 所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七 薄膜晶体管；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的源极 连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接；
所述第七薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与低电平 输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接，漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管的栅极连接； 所述第九薄膜晶体管， 栅极与第一薄膜晶体管的栅极连接， 源极与低电 平输出端连接， 漏极与所述第十一薄膜晶体管的源极连接； 所述第十薄膜晶体管， 栅极和漏极与第一时钟信号输入端连接， 源极与 第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与第一时钟信号输入端连接。
实施时， 所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七 薄膜晶体管；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的源极 连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接；
所述第七薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与低电平 输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接，漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管的栅极连接； 所述第九薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接， 漏极与所述第十一薄膜晶体管的源极连接；
所述第十薄膜晶体管， 栅极和漏极与第一时钟信号输入端连接， 源极与 第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与第一时钟信号输入端连接。
本发明还提供了一种驱动移位寄存器的方法，应用于上述的移位寄存器， 所述驱动移位寄存器的方法包括以下步骤：
上拉步骤： 上拉单元上拉每一级移位寄存器的输出信号， 使得该级移位 寄存器的输出信号为高电平；
复位步骤： 在该输出信号为高电平后， 对所述上拉单元的控制端的电位 进行复位， 使得该输出信号为低电平；
下拉步骤： 下拉单元下拉所述上拉单元的控制端的电位和该输出信号， 使得该上拉单元关闭并该输出信号维持为低电平。
实施时， 当所述上拉单元为上拉薄膜晶体管， 并所述上拉薄膜晶体管的 栅极和源极间并联有上拉电容时， 所述驱动移位寄存器的方法在所述上拉步 骤之前还包括预充电步骤：在第一时钟信号为低电平而起始信号为高电平时， 对所述上拉电容进行预充电， 以使得所述上拉薄膜晶体管导通。
本发明还提供了一种栅极驱动装置， 包括通过阵列成膜工艺制作在液晶 显示器阵列基板上的多级上述的移位寄存器；
除第一级移位寄存器之外， 其余每个移位寄存器的输出信号端均和与该 移位寄存器相邻的上一级移位寄存器的复位信号输入端连接；
除最后一级移位寄存器之外， 其余每个移位寄存器的输出信号端均和与 该移位寄存器相邻的下一级移位寄存器的起始信号输入端连接。
本发明还提供了一种显示装置， 包括上述的液晶显示器栅极驱动装置。 与现有技术相比， 本发明所述的移位寄存器、 液晶显示器栅极驱动装置 和方法与显示装置， 通过双下拉设计， 在解决时钟调变带来的杂散效应的同 时， 改善了下拉薄膜晶体管阔值电压在直流偏压下漂移的问题， 同时改善了 移位寄存器电路中输出悬空的问题， 提高了电路的可靠性； 同时， 减少了电 源的使用， 降低功耗。 附图说明
图 1是现有的应用于液晶显示器栅极驱动装置的移位寄存器的电路图； 图 2是本发明第一实施例所述的移位寄存器的电路图；
图 3是本发明第二实施例所述的移位寄存器的电路图；
图 4是本发明第三实施例所述的移位寄存器的电路图；
图 5是该实施例所述的移位寄存器的第一时钟信号 CLK、 第二时钟信号 CLKB、 起始信号 STV、 PU节点电位、 PD节点电位、 栅极驱动信号 OUT和 复位信号 RESET的时序图；
图 6是本发明所述的液晶显示器栅极驱动装置的电路图；
图 7是本发明所述的液晶显示器栅极驱动装置的输出信号的时序图； 图 8是本发明第四实施例所述的移位寄存器的电路图；
图 9是本发明第五实施例所述的移位寄存器的电路图；
图 10是本发明第六实施例所述的移位寄存器的电路图。 具体实施方式 如图 2所示， 本发明第一实施例所述的移位寄存器， 包括上拉单元 21、 复位单元 22、 下拉单元 23和输出信号端 OUTPUT, 其中，
所述上拉单元 21 ,与所述输出信号端 OUTPUT连接，用于上拉输出信号， 使得该输出信号为高电平；
所述复位单元 22, 分别与所述上拉单元 21的控制端和所述输出信号端
OUTPUT连接，用于在该输出信号为高电平后，对所述上拉单元 21的控制端 的电位进行复位， 使得该输出信号为低电平；
所述下拉单元 23 , 分别与所述上拉单元 21的控制端和所述输出信号端 OUTPUT连接， 用于在所述复位单元 22对所述上拉单元 21的控制端的电位 进行复位后， 下拉所述上拉单元 21的控制端的电位和该输出信号， 使得该上 拉单元 21关闭以控制该输出信号维持为低电平。
如图 3所示， 本发明第二实施例所述的移位寄存器的电路图。
本发明第二实施例所述的移位寄存器是基于本发明第一实施例所述的移 位寄存器。 本发明第二实施例所述的移位寄存器还包括预充电单元 31 , 所述 上拉单元 21包括第一薄膜晶体管 T1和上拉电容 C1 , 所述上拉电容 C1并联 于所述第一薄膜晶体管 T1的栅极和源极之间；
所述第一薄膜晶体管 T1 , 漏极连接第一时钟信号输入端 CLKIN, 源极连 接输出信号端 OUTPUT, 栅极通过所述预充电单元 31连接起始信号输入端 STVIN;
所述预充电单元 31 , 用于在所述上拉单元 21上拉输出信号之前， 在第 一时钟信号 CLK和起始信号 STV的控制下对所述上拉电容 C1进行预充电， 以使得所述第一薄膜晶体管 T1导通。
如图 4所示， 本发明的第三实施例所述的移位寄存器包括预充电单元、 上拉单元、 复位单元、 下拉单元、 第一时钟信号输入端 CLKIN、 第二时钟信 号输入端 CLKBIN、 起始信号输入端 STVIN、 复位信号输入端 RESETIN、 输 出信号端 OUTPUT,该第三实施例所述的移位寄存器工作于差分输入的 CLK 和 CLKB双时钟下， 其中，
所述移位寄存器的输出信号为液晶显示器的栅极驱动信号 OUT;
第一时钟信号 CLK由所述第一时钟信号输入端 CLKIN输入；
第二时钟信号 CLKB由所述第二时钟信号输入端 CLKBIN输入； 起始信号 STV由起始信号输入端 STVIN输入； 复位信号 RESET由复位信号输入端 RESETIN输入；
所述上拉单元包括第一薄膜晶体管 T1和上拉电容 C1 ;
所述第一薄膜晶体管 T1的栅极和源极间并联有上拉电容 C1 ;
所述第一薄膜晶体管 T1 , 漏极连接第一时钟信号输入端 CLKIN, 源极连 接输出信号端 OUTPUT, 栅极通过所述预充电单元连接起始信号输入端
STVIN;
所述预充电单元， 包括第二薄膜晶体管 T2, 用于在第一时钟信号为低电 平、 第二时钟信号为高电平而起始信号为高电平的半个时钟周期内， 对所述 上拉电容 C1进行预充电， 使得所述第一薄膜晶体管 T1的栅源电压上升至一 预定电压，该预定电压大于所述第一薄膜晶体管 T1的阔值电压， 以使得所述 第一薄膜晶体管 T1开启；
所述第一薄膜晶体管 T1 , 用于在该第一时钟信号为低电平而起始信号为 高电平后的半个时钟周期后的半个时钟周期内，上拉输出信号和 PU节点 (即 与所述上拉薄膜晶体管 T1的栅极连接的节点）的电位，使得该输出信号为高 电平；
所述第二薄膜晶体管 T2, 栅极和漏极与起始信号输入端 STVIN连接， 源极与所述第一薄膜晶体管 T1的栅极连接；
所述复位单元， 包括第三薄膜晶体管 T3和第四薄膜晶体管 T4, 用于在 该输出信号为高电平后的复位信号为高电平的半个时钟周期内， 复位所述输 出信号， 使得该输出信号为低电平；
所述第三薄膜晶体管 T3 , 栅极与复位信号输入端 RESETIN连接， 漏极 与输出信号端 OUTPUT连接， 源极与电源 VSS连接；
所述第四薄膜晶体管 T4, 栅极分别与复位信号输入端 RESETIN和所述 第三薄膜晶体管 T3的栅极连接，漏极与所述第一薄膜晶体管 T1的栅极连接， 源极分别与所述第三薄膜晶体管 T3的源极和电源 VSS连接；
所述下拉单元， 用于在该半个时钟周期后， 拉低输出信号， 使得该输出 信号为低电平；
所述下拉单元包括双下拉模块 41和双下拉控制模块 42, 其中， 所述双下拉模块 41， 分别与所述双下拉控制模块 42、 所述输出信号端 OUTPUT和所述上拉单元的控制端 （在图 4中即 PU点）连接， 用于在所述 双下拉控制模块 42的控制下对所述输出信号和所述上拉单元的控制端的电 位进行交替下拉；
所述双下拉模块 41包括第五薄膜晶体管 T5、第六薄膜晶体管 Τ6和第七 薄膜晶体管 Τ7;
所述双下拉控制模块 42包括第八薄膜晶体管 Τ8、 第九薄膜晶体管 Τ9、 第十薄膜晶体管 T10和第十一薄膜晶体管 T11 ;
所述第五薄膜晶体管 Τ5 , 栅极分别与所述第六薄膜晶体管 Τ6的栅极、 第九薄膜晶体管 Τ9的漏极和所述第十一薄膜晶体管 T11的源极连接，源极与 电源 VSS连接， 漏极分别与所述第一薄膜晶体管 T1的栅极、 所述第二薄膜 晶体管 Τ2的源极和所述第八薄膜晶体管 Τ8的栅极连接；
所述第六薄膜晶体管 Τ6, 源极与电源 VSS连接， 漏极与输出信号端
OUTPUT连接；
所述第七薄膜晶体管 T7 ,栅极与第二时钟信号输入端 CLKBIN连接， 源 极与电源 VSS连接， 漏极与输出信号端 OUTPUT连接；
所述第八薄膜晶体管 T8, 栅极与所述第一薄膜晶体管 T1的栅极连接， 源极与电源 VSS连接，漏极分别与第十薄膜晶体管 T10的源极和第十一薄膜 晶体管 T11的栅极连接；
所述第九薄膜晶体管 T9, 栅极与所述第一薄膜晶体管 T1的栅极连接， 源极与电源 VSS连接， 漏极与所述第十一薄膜晶体管 T11的源极连接；
所述第十薄膜晶体管 T10,栅极和漏极与第一时钟信号输入端 CLKIN连 接， 源极与第十一薄膜晶体管 T11的栅极连接；
所述第十一薄膜晶体管 T11 , 漏极与第一时钟信号输入端 CLKIN连接；
T6、 Τ7交替下拉输出信号， 防止了所述移位寄存器的输出悬空；
T8、 T9、 T10、 Til构成的反相器， 可以使得 PD节点 （与 T6的栅极连 接的节点 )和 PU节点 （与 T1的栅极连接的节点 ) 的电压快速转换。 同时 T8、 T9、 T10、 Til构成的反相器， 上拉电压损耗比单级反相器小， 低温情况 下， 载流子迁移率变小，要达到相同的驱动效果， 所需驱动电压变大， 故 T8、 T9、 T10、 Til构成的反相器在低温下的效果好， 模拟结果也表明 T8、 Τ9、 T10、 Til构成的反相器在低温下的效果好。
在该实施例所述的移位寄存器中：
第二薄膜晶体管 T2, 用于在起始信号 STV为高电平的半个时钟周期内， 对所述上拉电容 C1进行预充电； 第一薄膜晶体管 Tl , 用于在所述上拉电容 CI被预充电后， CLK为高电 平的半个时钟周期内， 输出用于栅极驱动的高电平信号；
第四薄膜晶体管 T4,用于在本级移位寄存器输出栅极驱动方波后，对 PU 点电位进行复位；
第三薄膜晶体管 T3 , 用于在第一薄膜晶体管 T1输出用于栅极驱动的高 电平信号后， CLK变为低电平， CLKB变为高电平的半个时钟周期内， 在下 一级移位寄存器输出控制下， 对本级移位寄存器的输出信号进行下拉、 复位； 所述双下拉控制模块 42,用于在双时钟 CLK和 CLKB以及 PU节点电位 的控制下， 控制所述双下拉模块 41工作；
所述双下拉模块 41 , 用于在所述双下拉控制模块 42的输出信号的控制 下， 对本级移位寄存器的的输出信号和 PU节点电位进行交替下拉。
在本发明的实施例中， 电源 VSS是低电平输出端。
下面根据图 4所示的该第三实施例所述的移位寄存器的电路图和图 5所 示的该移位寄存器的各信号的时序图， 分析该实施例所述的移位寄存器的工 作原理：
( 1 )预充电阶段： CLK为低电平， CLKB为高电平， STV为高电平， RESET为低电平； T3、 T4、 T10、 Til关闭， T2、 Τ7开启； 栅极驱动信号 OUT置位到低电平； STV对上拉电容 C1进行预充电， 使得 PU节点电压上 升， 但不能使 T8、 Τ9开启； PD点电位为低电平， Τ5、 Τ6均关闭， 使 T1的 栅极即 PU节点保持预充电状态， 栅极驱动信号 OUT保持低电平；
( 2 )上拉阶段： 在预充电阶段后， CLK为高电平， CLKB为低电平， STV为低电平， RESET为低电平； T3、 Τ2、 Τ4、 Τ7关闭， PU节点电位升高， Tl开启， 栅极驱动信号 OUT被上拉为高电平信号； T10、 Tll、 Τ8、 Τ9开启， 设计 Τ10、 Tll、 Τ8、 Τ9的宽长比使 PD节点电位为低电平， T5、 Τ6关闭； PU节点电位保持高电平，栅极驱动信号 OUT保持为高电平，对起始信号 STV 进行了移位；
( 3 )复位阶段： STV为低电平， CLK为低电平， CLKB为高电平， RESET 为高电平； Tl、 T2、 T10、 Tll、 Τ8、 Τ9关闭， Τ3、 Τ4、 Τ7开启， PD节点 电位为低电平， PU节点置位到低电平， 栅极驱动信号 OUT置位到低电平； ( 4 )第一下拉阶段： CLK为高电平， CLKB为低电平， STV为低电平，
RESET为氐电平； Tl、 Τ3、 Τ2、 Τ4、 Τ7、 Τ8、 Τ9关闭， Τ10、 T11开启， PD节点电位为高电平， T5、 Τ6开启， PU节点电位和栅极驱动信号 OUT下 拉至低电平；
( 5 )第二下拉阶段： CLK为低电平， CLKB为高电平， STV为低电平， RESET为低电平； Tl、 Τ2、 Τ3、 Τ4关闭， PU节点电位、 PD节点电位为低 电平， T8、 Τ9、 Τ5、 Τ6关闭， Τ7开启， 栅极驱动信号 OUT下拉至低电平。
如此实现了从起始信号 STV到栅极驱动信号 OUT的移位， 即在双时钟 控制下实现自上而下的栅极驱动扫描输出，减小下拉薄膜晶体管的工作周期， 从而改善 Vth漂移问题。 另外， 本发明减少移位寄存器中输出信号和 PU节 点的悬空， 减小 stray (杂散）效应。
本发明所述的液晶显示器栅极驱动装置的一实施例的电路图如图 6所 示， STV为起始信号，每级移位寄存器以上级的输出信号作为起始信号 STV, 以下级的输出信号作为复位信号 RESET, 在双时钟下工作， 实现自上而下的 栅驱动扫描输出。 图 7为该实施例所述的液晶显示器栅极驱动装置的移位输 出波形图。
在图 6中， SR1为第一级移位寄存器， SR2为第二级移位寄存器， SR3 为第三级移位寄存器， SRn为第 n级移位寄存器， n为大于 3的正整数； GL1 为第一栅极， GL2为第二栅极， GL3为第三栅极， GL n为第 n栅极。
在图 7中， OUT1是第一级移位寄存器的输出信号， OUT2为第二级移位 寄存器的输出信号， OUT3为第三级移位寄存器的输出信号。
如图 8所示， 本发明第四实施例所述的移位寄存器的电路图。 本发明第 四实施例所述的移位寄存器与以上第三实施例所述的移位寄存器的区别在 于， T9的栅极与输出信号端 OUTPUT连接而不是与薄膜晶体管 T1的栅极连 接。
如图 9所示， 本发明第五实施例所述的移位寄存器的电路图。 本发明第 五实施例所述的移位寄存器与以上第三实施例所述的移位寄存器的区别在 于， T8的栅极与输出信号端 OUTPUT连接而不是与上拉薄膜晶体管 T1的栅 极连接。
如图 10所示， 本发明第六实施例所述的移位寄存器的电路图。 本发明第 六实施例所述的移位寄存器与以上第三实施例所述的移位寄存器的区别在 于， T8的栅极与输出信号端 OUTPUT连接而不是与上拉薄膜晶体管 T1的栅 极连接， T9的栅极与输出信号端 OUTPUT连接而不是与薄膜晶体管 T1的栅 极连接。
本发明避免了使用大电容及避免电容直接连接时钟信号， 只使用电源
VSS, 有利于减小电路的功耗和空间。
本发明通过双下拉设计， 在解决时钟调变带来的 stray效应的同时， 改善 了下拉薄膜晶体管阔值电压在直流偏压下漂移的问题，提高了电路的可靠性； 同时， 减少了电源的使用， 降低功耗。
以上说明对本发明而言只是说明性的， 而非限制性的， 本领域普通技术 人员理解， 在不脱离所附权利要求所限定的精神和范围的情况下， 可做出许 多修改、 变化或等效， 但都将落入本发明的保护范围内。

Claims

权 利 要 求 书
1、 一种移位寄存器， 包括上拉单元、 复位单元和输出信号端， 其中， 所述上拉单元， 与所述输出信号端连接， 用于上拉输出信号， 使得该输 出信号为高电平；
所述复位单元， 分别与所述上拉单元的控制端和所述输出信号端连接， 用于在该输出信号为高电平后， 对所述上拉单元的控制端的电位进行复位， 使得该输出信号为低电平；
其特征在于， 所述移位寄存器还包括下拉单元；
所述下拉单元， 分别与所述上拉单元的控制端和所述输出信号端连接， 用于在所述复位单元对所述上拉单元的控制端的电位进行复位后， 下拉所述 上拉单元的控制端的电位和该输出信号， 使得该上拉单元关闭以控制该输出 信号维持为低电平。
2、 如权利要求 1所述的移位寄存器， 其特征在于， 还包括预充电单元， 所述上拉单元包括第一薄膜晶体管和上拉电容， 所述上拉电容并联于所述第 一薄膜晶体管的栅极和源极之间；
所述第一薄膜晶体管， 漏极连接第一时钟信号输入端， 源极连接输出信 号端， 栅极通过所述预充电单元连接起始信号输入端；
所述预充电单元， 用于在所述上拉单元上拉输出信号之前， 在第一时钟 信号和起始信号的控制下对所述上拉电容进行预充电， 以使得所述第一薄膜 晶体管导通。
3、 如权利要求 2所述的移位寄存器， 其特征在于，
所述预充电单元包括第二薄膜晶体管；
所述第二薄膜晶体管， 栅极和漏极与所述起始信号输入端连接， 源极与 所述第一薄膜晶体管的栅极连接；
所述复位单元， 包括第三薄膜晶体管和第四薄膜晶体管；
所述第三薄膜晶体管， 栅极与复位信号输入端连接， 漏极与所述输出信 号端连接， 源极与低电平输出端连接；
所述第四薄膜晶体管， 栅极分别与所述复位信号输入端和所述第三薄膜 晶体管的栅极连接， 漏极与所述第一薄膜晶体管的栅极连接， 源极分别与所 述第三薄膜晶体管的源极和低电平输出端连接。
4、 如权利要求 3所述的移位寄存器， 其特征在于， 所述下拉单元包括双 下拉模块和双下拉控制模块， 其中，
所述双下拉模块， 分别与所述双下拉控制模块、 所述输出信号端和所述 上拉单元的控制端连接， 用于在所述双下拉控制模块的控制下对所述输出信 号和所述上拉单元的控制端的电位进行交替下拉。
5、 如权利要求 4所述的移位寄存器， 其特征在于，
所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七薄膜晶体 管；
所述双下拉控制模块分别与第一时钟信号输入端和第二信号输入端连 接；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极、 所述第二薄膜晶体管的源极 和所述第八薄膜晶体管的栅极连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接；
所述第七薄膜晶体管， 栅极与所述第二时钟信号输入端连接， 源极与低 电平输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述第一薄膜晶体管的栅极连接， 源极与 低电平输出端连接， 漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管 的栅极连接；
所述第九薄膜晶体管， 栅极与所述第一薄膜晶体管的栅极连接， 源极与 低电平输出端连接， 漏极与所述第十一薄膜晶体管的源极连接；
所述第十薄膜晶体管， 栅极和漏极与所述第一时钟信号输入端连接， 源 极与第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与所述第一时钟信号输入端连接。
6、 如权利要求 4所述的移位寄存器， 其特征在于，
所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七薄膜晶体 管； 所述双下拉控制模块分别与第一时钟信号输入端和第二信号输入端连 接；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极、 所述第二薄膜晶体管的源极 和所述第八薄膜晶体管的栅极连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接；
所述第七薄膜晶体管， 栅极与所述第二时钟信号输入端连接， 源极与低 电平输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述第一薄膜晶体管的栅极连接， 源极与 低电平输出端连接， 漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管 的栅极连接；
所述第九薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接， 漏极与所述第十一薄膜晶体管的源极连接；
所述第十薄膜晶体管， 栅极和漏极与所述第一时钟信号输入端连接， 源 极与第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与所述第一时钟信号输入端连接。
7、 如权利要求 4所述的移位寄存器， 其特征在于，
所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七薄膜晶体 管；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的源极 连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接； 所述第七薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与低电平 输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接，漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管的栅极连接； 所述第九薄膜晶体管， 栅极与第一薄膜晶体管的栅极连接， 源极与低电 平输出端连接， 漏极与所述第十一薄膜晶体管的源极连接；
所述第十薄膜晶体管， 栅极和漏极与第一时钟信号输入端连接， 源极与 第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与第一时钟信号输入端连接。
8、 如权利要求 4所述的移位寄存器， 其特征在于，
所述双下拉模块包括第五薄膜晶体管、 第六薄膜晶体管和第七薄膜晶体 管；
所述双下拉控制模块包括第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜 晶体管和第十一薄膜晶体管；
所述第五薄膜晶体管， 栅极分别与所述第六薄膜晶体管的栅极、 第九薄 膜晶体管的漏极和所述第十一薄膜晶体管的源极连接， 源极与低电平输出端 连接， 漏极分别与所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的源极 连接；
所述第六薄膜晶体管， 源极与低电平输出端连接， 漏极与所述输出信号 端连接；
所述第七薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与低电平 输出端连接， 漏极与所述输出信号端连接；
所述第八薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接，漏极分别与第十薄膜晶体管的源极和第十一薄膜晶体管的栅极连接； 所述第九薄膜晶体管， 栅极与所述输出信号端连接， 源极与低电平输出 端连接， 漏极与所述第十一薄膜晶体管的源极连接；
所述第十薄膜晶体管， 栅极和漏极与第一时钟信号输入端连接， 源极与 第十一薄膜晶体管的栅极连接；
所述第十一薄膜晶体管， 漏极与第一时钟信号输入端连接。
9、一种驱动移位寄存器的方法，应用于如权利要求 1所述的移位寄存器， 其特征在于， 所述驱动移位寄存器的方法包括以下步骤： 上拉单元上拉每一级移位寄存器的输出信号， 使得该级移位寄存器的输 出信号为高电平；
在该输出信号为高电平后， 对所述上拉单元的控制端的电位进行复位， 使得该输出信号为低电平；
下拉单元下拉所述上拉单元的控制端的电位和该输出信号， 使得该上拉 单元关闭并该输出信号维持为低电平。
10、 如权利要求 9所述的驱动移位寄存器的方法， 其特征在于， 当所述 上拉单元包括第一薄膜晶体管和上拉电容， 所述上拉薄膜晶体管的栅极和源 极间并联有上拉电容时， 所述驱动移位寄存器的方法在所述上拉步骤之前还 包括预充电步骤： 在第一时钟信号为低电平而起始信号为高电平时， 对所述 上拉电容进行预充电， 以使得所述第一薄膜晶体管导通。
11、 一种栅极驱动装置， 其特征在于， 包括多级如权利要求 1至 8中任 一权利要求所述的移位寄存器；
除第一级移位寄存器之外， 其余每个移位寄存器的输出信号端均和与该 移位寄存器相邻的上一级移位寄存器的复位信号输入端连接；
除最后一级移位寄存器之外， 其余每个移位寄存器的输出信号端均和与 该移位寄存器相邻的下一级移位寄存器的起始信号输入端连接。
12、 一种显示装置， 其特征在于， 包括如权利要求 11所述的液晶显示器 栅极驱动装置。
PCT/CN2012/084920 2011-11-28 2012-11-20 移位寄存器及其驱动方法、栅极驱动装置与显示装置 WO2013078955A1 (zh)

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