WO2020168798A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置 Download PDF

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Publication number
WO2020168798A1
WO2020168798A1 PCT/CN2019/125666 CN2019125666W WO2020168798A1 WO 2020168798 A1 WO2020168798 A1 WO 2020168798A1 CN 2019125666 W CN2019125666 W CN 2019125666W WO 2020168798 A1 WO2020168798 A1 WO 2020168798A1
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WIPO (PCT)
Prior art keywords
signal terminal
electrically connected
nth
pull
transistor
Prior art date
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PCT/CN2019/125666
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
张星
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020558472A priority Critical patent/JP7433242B2/ja
Priority to EP19915877.5A priority patent/EP3929908A4/en
Priority to US16/767,230 priority patent/US11200825B2/en
Publication of WO2020168798A1 publication Critical patent/WO2020168798A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present disclosure relates to the field of display technology, in particular to a shift register unit and a driving method thereof, a gate driving circuit and a display device.
  • the gate drive circuit that drives the gate can be It is formed on the display panel and constitutes the gate drive circuit (Gate drive On Array, GOA) of the array substrate.
  • the gate driving circuit includes a plurality of cascaded shift register units, and each shift register unit includes a plurality of TFTs for implementing input, pull-down and pull-down control, output, reset, and noise reduction functions.
  • a larger number of transistors hinders the improvement of the panel.
  • the present disclosure proposes a shift register unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device.
  • a shift register unit includes a first input subcircuit to an Nth input subcircuit and a first output subcircuit to an Nth output subcircuit, the first output subcircuit to the Nth output subcircuit and the first input subcircuit to The N-th input sub-circuit has a one-to-one correspondence, where N is an integer greater than or equal to 2.
  • the n-th input sub-circuit is electrically connected to the n-th input signal terminal, the first level signal terminal and the pull-up node, and is configured to transfer the signal from the first input signal terminal under the control of the n-th input signal from the n-th input signal terminal.
  • the first level signal of the level signal terminal is transmitted to the pull-up node.
  • the n-th output sub-circuit is electrically connected to the n-th clock signal terminal, the pull-up node, and the n-th output signal terminal, and is configured to transfer the signal from the n-th clock signal terminal under the control of the voltage of the pull-up node
  • the shift register unit further includes a first pull-down sub-circuit to an N-th pull-down sub-circuit corresponding to the first output sub-circuit to the N-th output sub-circuit.
  • the nth pull-down sub-circuit is electrically connected to the pull-down node, the second-level signal terminal, and the n-th output signal terminal, and is configured to transfer the first signal from the second-level signal terminal under the control of the voltage of the pull-down node The two-level signal is transmitted to the nth output signal terminal.
  • the shift register unit further includes a control sub-circuit.
  • the control sub-circuit is electrically connected to the pull-up node, the second-level signal terminal, the third-level signal terminal, and the pull-down node, and is configured to control the voltage of the pull-up node
  • the second level signal or the third level signal from the third level signal terminal is transmitted to the pull-down node
  • the shift register unit further includes a first reset sub-circuit to an N-th reset sub-circuit corresponding to the first output sub-circuit to the N-th output sub-circuit.
  • the nth reset sub-circuit is electrically connected to the nth reset signal terminal, the second level signal terminal, and the pull-up node, and is configured to switch all devices under the control of the nth reset signal from the nth reset signal terminal.
  • the second level signal is transmitted to the pull-up node.
  • the shift register unit further includes an overall reset sub-circuit.
  • the general reset sub-circuit is electrically connected to the general reset signal terminal, the second level signal terminal and the pull-up node, and is configured to switch the first reset signal under the control of the general reset signal from the general reset signal terminal.
  • the two-level signal is transmitted to the pull-up node.
  • the shift register unit further includes an external compensation driving sub-circuit.
  • the external compensation driving sub-circuit is electrically connected to the compensation input signal terminal, the random output enable signal terminal, the compensation clock signal terminal, the second level signal terminal and the pull-up node, and is configured to Under the control of the random output enable signal from the output enable signal terminal and the compensation clock signal from the compensation clock signal terminal, the compensation clock signal is transmitted to the pull-up node.
  • the n-th input sub-circuit includes an n-th input transistor.
  • the control electrode of the nth input transistor is electrically connected to the nth input signal terminal
  • the first electrode of the nth input transistor is electrically connected to the first level signal terminal
  • the first electrode of the nth input transistor is electrically connected to the first level signal terminal.
  • the two poles are electrically connected to the pull-up node.
  • the nth output sub-circuit includes an nth output transistor and an nth storage capacitor.
  • the control electrode of the nth output transistor is electrically connected to the pull-up node
  • the first electrode of the nth output transistor is electrically connected to the nth clock signal terminal
  • the second electrode of the nth output transistor is electrically connected to the The nth output signal terminal is electrically connected.
  • the first pole of the nth storage capacitor is electrically connected to the pull-up node
  • the second pole of the nth storage capacitor is electrically connected to the nth output signal terminal.
  • the nth pull-down sub-circuit includes an nth pull-down transistor.
  • the control electrode of the nth pull-down transistor is electrically connected to the pull-down node
  • the first electrode of the nth pull-down transistor is electrically connected to the second-level signal terminal
  • the second electrode of the nth pull-down transistor is electrically connected to the The nth output signal terminal is electrically connected.
  • the control sub-circuit includes a first control transistor and a second control transistor.
  • the control electrode and the first electrode of the first control transistor are electrically connected to the third-level signal terminal, and the second electrode of the first control transistor is electrically connected to the pull-down node.
  • the control electrode of the second control transistor is electrically connected to the pull-up node, the first electrode of the second control transistor is electrically connected to the second level signal terminal, and the second electrode of the second control transistor Electrically connected to the pull-down node.
  • control sub-circuit further includes a third control transistor.
  • the control electrode of the third control transistor is electrically connected to the pull-down node
  • the first electrode of the third control transistor is electrically connected to the second level signal terminal
  • the second electrode of the third control transistor is electrically connected to The pull-up node is electrically connected.
  • the nth reset sub-circuit includes an nth reset transistor.
  • the control electrode of the nth reset transistor is electrically connected to the nth reset signal terminal
  • the first electrode of the nth reset transistor is electrically connected to the second level signal terminal
  • the first electrode of the nth reset transistor is electrically connected to the second level signal terminal.
  • the two poles are electrically connected to the pull-up node.
  • the total reset sub-circuit includes a total reset transistor.
  • the control electrode of the overall reset transistor is electrically connected to the overall reset signal terminal, the first electrode of the overall reset transistor is electrically connected to the second level signal terminal, and the second electrode of the overall reset transistor is electrically connected to the The pull-up node is electrically connected.
  • the external compensation driving sub-circuit includes a first compensation driving transistor, a second compensation driving transistor, a third compensation driving transistor, and a compensation driving capacitor.
  • the control electrode of the first compensation drive transistor is electrically connected to the random output enable signal terminal, the first electrode of the first compensation drive transistor is electrically connected to the compensation input signal terminal, and the first compensation drive transistor
  • the second pole of the compensation drive capacitor is electrically connected to the first pole of the compensation drive capacitor.
  • the control electrode of the second compensation drive transistor is electrically connected to the first electrode of the compensation drive capacitor, the first electrode of the second compensation drive transistor is electrically connected to the compensation clock signal terminal, and the second compensation drive
  • the second pole of the transistor is electrically connected to the first pole of the third compensation driving transistor.
  • the control electrode of the third compensation driving transistor is electrically connected to the compensation clock signal terminal, and the second electrode of the third compensation driving transistor is electrically connected to the pull-up node.
  • the second pole of the compensation driving capacitor is electrically connected to the second level signal terminal.
  • each frame includes a first driving period to an Nth driving period.
  • the method includes: during the n-th driving period, driving through the n-th input sub-circuit, the n-th output sub-circuit and the n-th reset sub-circuit, wherein the n-th driving period includes the n-th input period and the n-th output Period and the nth reset period.
  • the pull-up node is charged to the first effective level through the n-th input sub-circuit; during the n-th output period, under the control of the voltage of the pull-up node , Transmitting the n-th clock signal to the n-th output signal terminal; and during the n-th reset period, under the control of the n-th reset signal, reset the pull-up node to an inactive level through a second level signal.
  • each frame further includes a blank phase after the first driving period to the Nth driving period.
  • the method further includes: under the control of the random output enable signal, during a random period from the first output period to the Nth output period, causing the compensation input signal from the compensation input signal terminal to be The second compensation drive transistor is turned on; during the blank phase, the pull-up node is raised to an effective level by the compensation clock signal, so that the first clock signal to the Nth clock signal can be transmitted to the first clock signal respectively An output signal terminal to the Nth output signal terminal; and according to the random output enable signal, one of the first clock signal to the Nth clock signal has a high level during at least a part of the blank period, so as So that one of the first output signal terminal to the Nth output signal terminal can output a high level signal in the blank phase.
  • a gate driving circuit includes a plurality of cascaded shift register unit groups, and each shift register unit group includes K cascaded shift register units, wherein each shift register unit is based on any one of the above
  • K is an integer greater than or equal to 3.
  • the K cascaded shift register cells in the shift register cell group of each stage are used to drive adjacent N ⁇ K gate lines, wherein the N ⁇ K gate lines include first gate lines arranged in sequence Group to the Nth gate line group, each gate line group includes K gate lines arranged in sequence, wherein the nth output signal in the K cascaded shift register units in each shift register unit group
  • the terminals are respectively electrically connected to the K gate lines in the nth gate line group in one-to-one correspondence. Except for the first input signal terminal of the first stage shift register unit in the first stage shift register unit group, each input signal terminal is electrically connected to the previous gate line of the gate line corresponding to the input signal terminal The output signal terminal is electrically connected.
  • the first input signal terminal of the first stage shift register unit in the first stage shift register unit group is electrically connected to the frame start signal terminal.
  • each stage of the shift register unit group in the gate driving circuit is electrically connected to the first clock signal line to the N ⁇ Kth clock signal line to receive the first clock signal to the N ⁇ Kth clock signal line, respectively signal.
  • each reset signal terminal is electrically connected to the output corresponding to the reset signal terminal.
  • the output signal terminal of the succeeding gate line of the gate line driven by the sub-circuit is electrically connected.
  • the Nth reset signal terminal of the last stage shift register unit in the last stage shift register unit group is electrically connected to the frame start signal terminal.
  • the driving method includes: providing a frame start signal to a first input signal terminal in a first-pole shift register unit in the first-stage shift register unit group; and through the N ⁇ K clock signal lines The clock signal is provided to the clock signal terminal in the shift register unit group at each level, wherein the clock signal provided through the first clock signal line in the N ⁇ K clock signal lines is greater than the first edge of the first cycle The first edge of the frame start signal lags 1/N ⁇ K clock cycles.
  • the duty cycle of the first clock signal to the N ⁇ Kth clock signal is 1/N ⁇ K, and is sequentially delayed by 1/N ⁇ K clock cycles.
  • a display device includes the gate driving circuit according to any one of the above embodiments.
  • Fig. 1 shows a schematic circuit diagram of a related art shift register unit.
  • Fig. 2 shows a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • Fig. 3 shows a structural block diagram of a further embodiment of the shift register unit shown in Fig. 2.
  • FIG. 4 shows an example circuit diagram of the shift register unit shown in FIG. 3.
  • FIG. 5 shows a timing diagram of the shift register unit shown in FIG. 4.
  • FIG. 6 shows a structural block diagram of a further embodiment of the shift register unit shown in FIG. 3.
  • FIG. 7 shows an example circuit diagram of the shift register unit in FIG. 6.
  • FIG. 8 shows a timing diagram of the shift register unit shown in FIG. 7.
  • FIG. 9 shows a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 10 shows a cascade structure diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 11 shows a flowchart of a driving method of a gate driving circuit according to an embodiment of the present disclosure.
  • Fig. 12 shows a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • connection can refer to two components directly connected or electrically connected, or can refer to two components being connected or connected via one or more other components. Electric connection. In addition, these two components can be electrically connected or electrically connected in a wired or wireless manner.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors.
  • the transistor used in the present disclosure includes a "control electrode", a "first electrode” and a "second electrode".
  • the control electrode refers to the gate of the thin film transistor
  • the first electrode refers to one of the source and drain of the thin film transistor
  • the second electrode refers to the source and drain of the thin film transistor. The other one. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged.
  • N-type thin film transistor is used as an example for description.
  • P-type thin film transistors can also be used to implement the technical solutions of the present disclosure.
  • Those skilled in the art can understand that, in this case, by inverting the input signal, clock signal, constant voltage signal, etc. (and/or making other adaptive modifications), the technical solution of the present disclosure can also be implemented.
  • the clock signal is a periodic signal. In one cycle, the clock signal is divided into a high-level period and a low-level period that occur successively through two signal edges (the first edge and the second edge that lags the first edge).
  • the terms “active level” and “inactive level” are the levels that turn on and off the relevant transistors, respectively.
  • the "first effective level” and the “second effective level” are only used to distinguish the two effective levels from having different amplitudes. In the following, since an N-type thin film transistor is used as an example, the "effective level” is a high level and the "invalid level” is a low level.
  • FIG. 1 shows a schematic circuit diagram of a related art shift register unit 100.
  • the clock signal from the clock signal terminal CLK1 can provide a high level to the output signal terminal OUT through the thin film transistor T8.
  • the clock signal from the constant voltage signal The signal at the terminal VSS can provide a low level to the output signal terminal OUT through the thin film transistor T9. Therefore, by controlling the potential timing of the pull-up node PU and the pull-down node PD, it is possible to control the signal output by the output signal terminal OUT.
  • the input signal is used to charge the pull-up node PU to a high level through the input transistor T1; in the reset phase, the low level from VSS is used by resetting the transistor T2 The level signal resets the pull-up node PU to a low level; and also realizes the noise reduction function on the pull-up node PU through the thin film transistor T3.
  • the high level from VDD and the low level from VSS are respectively transmitted to the pull-down node PD through the sub-circuit structure formed by the thin film transistors T4, T5, T6, and T7. .
  • the final voltage of the pull-down node PD is determined by the channel width-to-length ratio of T6 and T7. By setting the width-to-length ratio appropriately, the PD point voltage can be properly set.
  • FIG. 2 shows a schematic structural diagram of a shift register unit 200 according to an embodiment of the present disclosure.
  • the shift register unit 200 includes first input sub-circuit 210-1 to N-th input sub-circuit 210-N, and first output sub-circuit 220-1 to N-th output sub-circuit 220-N.
  • the first output sub-circuit 210-1 to the N-th output sub-circuit 210-N correspond to the first input sub-circuit 220-1 to the N-th input sub-circuit 220-N one-to-one.
  • N is an integer greater than or equal to 2.
  • the shift register unit 200 also has a first input signal terminal IN1 to an Nth input signal terminal INN, a first output signal terminal OUT1 to an Nth output signal terminal OUTN, a first clock signal terminal CLK1 to an Nth clock signal terminal CLKN, and a One level signal terminal VDDA.
  • the n-th input sub-circuit 210-n and the n-th input signal terminal INn, the first level signal terminal VDDA and the pull-up The node PU is electrically connected.
  • the n-th input sub-circuit 210-n is configured to transmit the first-level signal from the first-level signal terminal VDDA to the pull-up node PU under the control of the n-th input signal from the n-th input signal terminal INn.
  • the nth output sub-circuit 220-n is electrically connected to the nth clock signal terminal CLKn, the pull-up node PU, and the nth output signal terminal OUTn.
  • the nth output sub-circuit 220-n is configured to transmit the nth clock signal from the nth clock signal terminal CLKn to the nth output signal terminal OUTn under the control of the voltage of the pull-up node PU.
  • the n-th input sub-circuit 210-n may not be electrically connected to the first level signal terminal VDDA , And only electrically connected to the n-th input signal terminal INn and the pull-up node PU.
  • the n-th input sub-circuit 210-n is configured to transmit the n-th input signal to the pull-up node PU under the control of the n-th input signal from the n-th input signal terminal INn.
  • FIG. 3 shows a structural block diagram of a further embodiment of the shift register unit 200 of FIG. 2.
  • the shift register unit 200 further includes first pull-down sub-circuits 230-1 to N-th pull-down sub-circuit 230-N, and first pull-down sub-circuits 230-1 to N-th pull-down sub-circuit 230-N There is a one-to-one correspondence with the first output sub-circuit 220-1 to the Nth output sub-circuit 220-N.
  • the nth pull-down sub-circuit 230-n is electrically connected to the pull-down node PD, the second level signal terminal VSS, and the nth output signal terminal 220-n.
  • the nth pull-down sub-circuit 230-n is configured to transmit the second level signal from the second level signal terminal VSS to the nth output signal terminal 220-n under the control of the voltage of the pull-down node PD.
  • the shift register unit 200 further includes a control sub-circuit 240.
  • the control sub-circuit 240 is electrically connected to the pull-up node PU, the second-level signal terminal VSS, the third-level signal terminal VDDB, and the pull-down node PD.
  • the control sub-circuit 240 is configured to transmit the second level signal or the third level signal from the third level signal terminal VDDB to the pull-down node PD under the control of the voltage of the pull-up node PU.
  • the shift register unit 200 further includes a first reset sub-circuit 250-1 to an N-th reset sub-circuit 250-N, and the first reset sub-circuit 250-1 to an N-th reset sub-circuit 250 -N corresponds to the first output sub-circuit 220-1 to the Nth output sub-circuit 220-N one-to-one.
  • the nth reset sub-circuit 250-n is electrically connected to the nth reset signal terminal RSTn, the second level signal terminal VSS, and the pull-up node PU.
  • the nth reset sub-circuit 250-n is configured to transmit the second level signal to the pull-up node PU under the control of the nth reset signal from the nth reset signal terminal RSTn.
  • FIG. 4 shows an example circuit diagram of the shift register unit 200 in FIG. 3.
  • FIG. 4 only shows the circuit diagram when N is equal to 2. It should be understood that the present disclosure is not limited to this. In other embodiments, N may be any integer greater than 2. Those skilled in the art can know the circuit structure and work flow when N is other values on the basis of the following description and description.
  • the first input sub-circuit 210-1 includes a first input transistor T11.
  • the control electrode of the first input transistor T11 is electrically connected to the first input signal terminal IN1
  • the first electrode of the first input transistor T11 is electrically connected to the first level signal terminal VDDA
  • the second electrode of the first input transistor T11 is electrically connected to the pull-up
  • the node PU is electrically connected.
  • the second input sub-circuit 210-2 includes a second input transistor T12.
  • the control electrode of the second input transistor T12 is electrically connected to the second input signal terminal IN2
  • the first electrode of the second input transistor T12 is electrically connected to the first level signal terminal VDDA
  • the second electrode of the second input transistor T12 is electrically connected to the pull-up
  • the node PU is electrically connected.
  • the first input transistor T11 and the second input transistor T12 may have a diode connection form. Specifically, the control electrode and the first electrode of the first input transistor T11 are electrically connected to the first input signal terminal IN1, and the second electrode of the first input transistor T11 is electrically connected to the pull-up node PU. Similarly, the control electrode and the first electrode of the second input transistor T12 are electrically connected to the second input signal terminal IN2, and the second electrode of the second input transistor T12 is electrically connected to the pull-up node PU.
  • the first output sub-circuit 220-1 includes a first output transistor T21 and a first storage capacitor C1.
  • the control electrode of the first output transistor T21 is electrically connected to the pull-up node PU, the first electrode of the first output transistor T21 is electrically connected to the first clock signal terminal CLK1, and the second electrode of the first output transistor T21 is electrically connected to the first output signal terminal.
  • OUT1 is electrically connected.
  • the first pole of the first storage capacitor C1 is electrically connected to the pull-up node PU, and the second pole of the first storage capacitor C1 is electrically connected to the first output signal terminal OUT1.
  • the second output sub-circuit 220-2 includes a second output transistor T22 and a second storage capacitor C2.
  • the control electrode of the second output transistor T22 is electrically connected to the pull-up node PU
  • the first electrode of the second output transistor T22 is electrically connected to the second clock signal terminal CLK2
  • the second electrode of the second output transistor T22 is electrically connected to the second output signal terminal.
  • OUT2 is electrically connected.
  • the first pole of the second storage capacitor C2 is electrically connected to the pull-up node PU
  • the second pole of the second storage capacitor C2 is electrically connected to the second output signal terminal OUT2.
  • the first pull-down sub-circuit 230-1 includes a first pull-down transistor T31.
  • the control electrode of the first pull-down transistor T31 is electrically connected to the pull-down node PD, the first electrode of the first pull-down transistor T31 is electrically connected to the second level signal terminal VSS, and the second electrode of the first pull-down transistor T31 is electrically connected to the first The output signal terminal OUT1 is electrically connected.
  • the second pull-down sub-circuit 230-2 includes a second pull-down transistor T32.
  • the control electrode of the second pull-down transistor T32 is electrically connected to the pull-down node PD
  • the first electrode of the second pull-down transistor T32 is electrically connected to the second level signal terminal VSS
  • the second electrode of the second pull-down transistor T32 is electrically connected to the second output signal terminal.
  • OUT2 is electrically connected.
  • the control sub-circuit 240 includes a first control transistor Tc1 and a second control transistor Tc2.
  • the control electrode and the first electrode of the first control transistor Tc1 are electrically connected to the third level signal terminal VDDB, and the second electrode of the first control transistor Tc1 is electrically connected to the pull-down node PD.
  • the control electrode of the second control transistor Tc2 is electrically connected to the pull-up node PU, the first electrode of the second control transistor Tc2 is electrically connected to the second level signal terminal VSS, and the second electrode of the second control transistor Tc2 is electrically connected to the pull-down node PD. connection.
  • control sub-circuit 240 further includes a third control transistor Tc3.
  • the control electrode of the third control transistor Tc3 is electrically connected to the pull-down node PD
  • the first electrode of the third control transistor Tc3 is electrically connected to the second level signal terminal VSS
  • the second electrode of the third control transistor Tc3 is electrically connected to the pull-up node PU. connection.
  • the first reset sub-circuit 250-1 includes a first reset transistor T51.
  • the control electrode of the first reset transistor T51 is electrically connected to the first reset signal terminal RST1
  • the first electrode of the first reset transistor T51 is electrically connected to the second level signal terminal VSS
  • the second electrode of the first reset transistor T51 is connected to the pull-up
  • the node PU is electrically connected.
  • the second reset sub-circuit 250-2 includes a second reset transistor T52.
  • the control electrode of the second reset transistor T52 is electrically connected to the second reset signal terminal RST2
  • the first electrode of the second reset transistor T52 is electrically connected to the second level signal terminal VSS
  • the second electrode of the second reset transistor T52 is connected to the pull-up The node PU is electrically connected.
  • FIG. 5 shows a timing diagram of the shift register unit 200 shown in FIG. 4. The operation flow of the shift register unit 200 in FIG. 4 will be described below in conjunction with FIG. 5.
  • one clock cycle is equally divided into 8 periods.
  • the clock signal of the second clock signal terminal CLK2 lags behind the clock signal of the first clock signal terminal CLK1 by 4 periods, that is, half a clock cycle.
  • the signal of the second input signal terminal IN2 lags behind the clock signal of the first input signal terminal IN1 by 4 periods, and the signal of the second reset signal terminal RST2 lags behind the signal of the first reset signal terminal RST1 by 4 periods.
  • the signals of the first level signal terminal VDDA and the third level signal terminal VDDB are both shown as constant high level signals in the timing chart of FIG. 5.
  • VDDB only VDDB may be set, and the first input transistor T11 and the second input transistor T12 are implemented as diode connections. At this time, VDDA is achieved through the first input signal terminal IN1 and the second input signal terminal IN2. The role of.
  • the signal of the input signal terminal IN1 changes from a low level (for example, vgl) to a high level (for example, vgh), and the first input transistor T11 is turned on.
  • the high level of the first level signal terminal VDDA is transmitted to the pull-up node PU, and the voltage of the pull-up node PU is pulled up to the first effective level, that is, the high level vgh.
  • the first output transistor T21 and the second output transistor T22 are both turned on, but at this time the first clock signal terminal CLK1 and the second clock signal terminal CLK2 still provide a low level vgl Therefore, the first output signal terminal OUT1 and the second output signal terminal OUT2 receive low-level signals from the first clock signal terminal CLK1 and the second clock signal terminal CLK2.
  • the third control transistor Tc3 (used to keep the PU noise reduction after reset) is provided, before the beginning of the t1 period, since the third constant voltage signal terminal VDDB has been directed to the first control The control electrode and the first electrode of the transistor Tc1 provide a high level. Therefore, the high-level signal from VDDB maintains the level of the PD point at a high level, which makes the third transistor Tc3 turn on and thus the low level from VSS Keep PU at low level before t1. If the high-level signal from VDDA can pull the PU point high, the channel width-to-length ratio of the first input transistor T11 and the channel width-to-length ratio of the third transistor Tc3 need to be set.
  • the second control transistor Tc2 is turned on, and the low level signal from the second level signal terminal VSS can be transmitted to the pull-down node PD.
  • the third level signal terminal VDDB provides a high level signal to the pull-down node PD.
  • setting the channel width-to-length ratio according to Tc1 and Tc2 can make the pull-down node PD finally set to a low level.
  • the low level at the pull-down node PD turns off the first pull-down transistor T31 and the second pull-down transistor T32.
  • the output signals of the first output signal terminal OUT1 and the second output signal terminal OUT2 are both low-level signals.
  • the signal of the first clock signal terminal CLK1 changes to a high level
  • the second clock signal terminal CLK2 maintains a low level
  • the signal of the first input signal terminal IN1 changes to a low level.
  • the high level of the signal of the first clock signal terminal CLK1 makes the first output signal terminal OUT1 receive a high level signal. Since the low level of the first input signal terminal IN1 causes the first input transistor T11 to be turned off, the pull-up node PU is floated. Through the bootstrap action of the first capacitor C1, the voltage of the PU point will be further increased to the second effective level, for example, 2vgh. In addition, since the second clock signal terminal CLK2 still outputs a low-level signal, the second output signal terminal OUT2 keeps receiving a low-level signal.
  • the first pull-down transistor T31 and the second pull-down transistor T32 are turned off. Therefore, the first output signal terminal OUT1 outputs a high-level signal and the second output signal terminal OUT2 outputs a low-level signal.
  • the signal of the first clock signal terminal CLK1 becomes low level
  • the signal of the second clock signal terminal CLK2 remains low level
  • the signal of the first reset signal terminal RST1 becomes high level.
  • the first reset transistor T51 is turned on to pull the pull-up node PU to a low level, so as to reset the PU point.
  • This turns off the first output transistor T21 and the second transistor T22.
  • the reset of the PU point turns off the second control transistor Tc2, which causes the pull-down node PD to become a high level under the action of the signal from VDDB.
  • the first pull-down transistor T31 and the second pull-down transistor T32 are both turned on, and the low level signal of VSS is further transmitted to the first output signal terminal OUT1 and the second output signal terminal OUT2, so that both output low level.
  • the signal of the first clock signal terminal CLK1 and the signal of the second clock signal terminal CLK2 remain low, and the signal of the first reset signal terminal RST1 becomes low.
  • the PD point has changed to a high level in the t3 period. Therefore, in the embodiment where the third control transistor Tc3 is provided, the low level signal from the VSS reduces the noise of the PU point through the third control transistor Tc3.
  • the signal of the input signal terminal IN2 changes from a low level (for example, vgl) to a high level (for example, vgh), turning on the second input transistor T12.
  • a low level for example, vgl
  • a high level for example, vgh
  • the high level of the first level signal terminal VDDA is transmitted to the pull-up node PU, and the voltage of the pull-up node PU is pulled up to the first effective level, that is, the high level vgh.
  • the first output transistor T21 and the second output transistor T22 are both turned on, but at this time the first clock signal terminal CLK1 and the second clock signal terminal CLK2 still provide a low level vgl Therefore, the first output signal terminal OUT1 and the second output signal terminal OUT2 receive low-level signals from the first clock signal terminal CLK1 and the second clock signal terminal CLK2.
  • the low level from VSS maintains the noise reduction of the PU and makes it low. If the high-level signal from VDDA can pull the PU point high, the channel width-to-length ratio of the second input transistor T12 and the channel width-to-length ratio of the third transistor Tc3 need to be set.
  • the second control transistor Tc2 is turned on, and the low level signal from the second level signal terminal VSS can be transmitted to the pull-down node PD.
  • the third level signal terminal VDDB provides a high level signal to the pull-down node PD.
  • setting the channel width-to-length ratio according to Tc1 and Tc2 can make the pull-down node PD finally set to a low level.
  • the low level at the pull-down node PD turns off the first pull-down transistor T31 and the second pull-down transistor T32.
  • the output signals of the first output signal terminal OUT1 and the second output signal terminal OUT2 are both low-level signals.
  • the signal of the second clock signal terminal CLK2 changes to a high level
  • the signal of the first clock signal terminal CLK1 remains low
  • the signal of the second input signal terminal IN2 changes to a low level.
  • the high level of the signal of the second clock signal terminal CLK2 makes the second output signal terminal OUT2 receive a high level signal. Since the low level of the second input signal terminal IN2 turns off the second input transistor T12, the pull-up node PU is floated. Through the bootstrap action of the second capacitor C2, the voltage of the PU point will be further increased to the second effective level, for example, 2vgh. In addition, since the first clock signal terminal CLK1 still outputs a low-level signal, the first output signal terminal OUT1 keeps receiving a low-level signal.
  • the first pull-down transistor T31 and the second pull-down transistor T32 are turned off. Therefore, the first output signal terminal OUT1 outputs a low level signal and the second output signal terminal OUT2 outputs a high level signal.
  • the signal of the second clock signal terminal CLK2 becomes low level
  • the signal of the first clock signal terminal CLK1 remains low level
  • the signal of the second reset signal terminal RST2 becomes high level.
  • the second reset transistor T52 is turned on and pulls the pull-up node PU to a low level to reset the PU point. This turns off the first output transistor T21 and the second transistor T22.
  • the reset of the PU point turns off the second control transistor Tc2, which causes the pull-down node PD to become a high level under the action of the signal from VDDB.
  • the first pull-down transistor T31 and the second pull-down transistor T32 are both turned on, and the low level signal of VSS is further transmitted to the first output signal terminal OUT1 and the second output signal terminal OUT2, so that both output low level.
  • the signal of the first clock signal terminal CLK1 and the signal of the second clock signal terminal CLK2 remain low, and the signal of the second reset signal terminal RST2 becomes low.
  • the PD point has changed to a high level in the t7 period. Therefore, in the embodiment where the third control transistor Tc3 is provided, the low level signal from VSS reduces the noise of the PU point through the third control transistor Tc3.
  • the shift register unit 200 may also operate according to other timing sequences.
  • one clock cycle can be divided into 6 periods, and the clock signal of the second clock signal terminal CLK2 lags the clock signal of the first clock signal terminal CLK1 by 3 periods, that is, half a clock cycle.
  • the signal of the second input signal terminal IN2 lags the clock signal of the first input signal terminal IN1 by 3 periods, and the signal of the second reset signal terminal RST2 lags the signal of the first reset signal terminal RST1 by 3 periods.
  • a clock cycle can be generally divided into 2k periods (k is an integer greater than 4), and the clock signal of the second clock signal terminal CLK2 is greater than the clock signal of the first clock signal terminal CLK1.
  • k is an integer greater than 4
  • the signal of the second input signal terminal IN2 lags the clock signal of the first input signal terminal IN1 by k periods
  • the signal of the second reset signal terminal RST2 is longer than the signal of the first reset signal terminal RST1
  • the signal lags by k periods.
  • the t4 and t8 phases will cover k-3 consecutive periods respectively.
  • FIG. 6 shows a structural block diagram of a further embodiment of the shift register unit 200 shown in FIG. 3.
  • the shift register unit in FIG. 6 further includes a total reset sub-circuit 260 and an external compensation driving sub-circuit 270.
  • the total reset sub-circuit 260 is electrically connected to the total reset signal terminal TRST, the second level signal terminal VSS and the pull-up node PU.
  • the total reset sub-circuit 260 is configured to transmit the second level signal to the pull-up node PU under the control of the total reset signal from the total reset signal terminal TRST.
  • the external compensation driving sub-circuit 270 is electrically connected to the compensation input signal terminal INA, the random output enable signal terminal OE, the compensation clock signal terminal CLKA, the second level signal terminal VSS and the pull-up node PU.
  • the external compensation driving sub-circuit 270 is configured to transmit the compensation clock signal CLKA to the pull-up node PU under the control of the random output enable signal from the random output enable signal terminal OE and the compensation clock signal from the compensation clock signal terminal CLKA .
  • FIG. 7 shows an example circuit diagram of the shift register unit in FIG. 6.
  • N may be any integer greater than 2.
  • Those skilled in the art can know the circuit structure and work flow when N is other values on the basis of the following description and description.
  • the total reset sub-circuit 260 includes a total reset transistor T61.
  • the control electrode of the overall reset transistor T61 is electrically connected to the overall reset signal terminal TRST, the first electrode of the overall reset transistor T61 is electrically connected to the second level signal terminal VSS, and the second electrode of the overall reset transistor T61 is electrically connected to the pull-up node PU .
  • the external compensation driving sub-circuit 270 includes a first compensation driving transistor T71, a second compensation driving transistor T72, a third compensation driving transistor T73, and a compensation driving capacitor CA.
  • the control electrode of the first compensation drive transistor T71 is electrically connected to the random output enable signal terminal OE
  • the first electrode of the first compensation drive transistor T71 is electrically connected to the compensation input signal terminal INA
  • the second electrode of the first compensation drive transistor T71 is electrically connected to the
  • the first pole of the compensation driving capacitor CA is electrically connected to the node H.
  • the control electrode of the second compensation driving transistor T72 is electrically connected to node H, the first electrode of the second compensation driving transistor T72 is electrically connected to the compensation clock signal terminal CLKA, and the second electrode of the second compensation driving transistor T72 is electrically connected to the third compensation driving transistor.
  • the first pole of T73 is electrically connected.
  • the control electrode of the third compensation driving transistor T73 is electrically connected to the compensation clock signal terminal CLKA, and the second electrode of the third compensation driving transistor T73 is electrically connected to the pull-up node PU.
  • the second pole of the compensation driving capacitor CA is electrically connected to the second level signal terminal VSS.
  • FIG. 8 shows a timing diagram of the shift register unit shown in FIG. 7.
  • the operation flow of the shift register unit in FIG. 7 will be described below in conjunction with FIG. 8.
  • a frame is divided into two stages, namely, the display stage and the blank (Blank) stage.
  • the display stage includes t1-t8, and the blank stage includes t9-t11.
  • the timings of the input sub-circuits, output sub-circuits, pull-down sub-circuits, control sub-circuits, and reset sub-circuits in the display phase are the same as in FIG. 5, and only the operations of the overall reset sub-circuit 260 and the external compensation driver sub-circuit 270 will be described below.
  • the operation of the total reset sub-circuit 260 only exists in t12.
  • the total reset transistor T61 is turned on, so that the signal of VSS resets the PU. It should be pointed out that all the shift register units in the gate drive circuit where the shift register unit shown in FIG. 7 is located share the same TRST. Therefore, in t12, all shift register units in the gate drive circuit Perform an overall reset.
  • the operation of the external compensation driving sub-circuit 270 starts in the period t2.
  • the compensation input signal terminal INA starts to receive a high level
  • the random output enable signal terminal OE inputs a high level.
  • the first compensation driving transistor T71 is turned on to raise the node H to a high level. Therefore, the second compensation driving transistor T72 is turned on to transmit the CLKA signal to the first pole of the third compensation driving transistor T73.
  • the signal of CLKA is low, the third compensation driving transistor T73 is turned off, and the signal of CLKA is not transmitted to the pull-up node PU.
  • the compensation input signal terminal INA receives a low level, and the random output enable signal terminal OE inputs a low level, so that T71 is turned off, node H remains high, and T72 is continuously turned on.
  • the CLKA signal changes to a high level, turning on the third compensation driving transistor T73.
  • the high-level CLKA signal pulls the PU point up to the first effective level, such as the high level vgh, This makes both the first output transistor T21 and the second output transistor T22 conductive.
  • the signals of the first clock signal terminal CLK1 and the second clock signal terminal CLK2 are both low level, therefore, the outputs of the first output signal terminal OUT1 and the second output signal terminal OUT2 are both low level.
  • the signal of CLKA is low, the signal of CLK2 changes to high, and the signal of CLK1 remains low.
  • the PU point is in a floating state. Due to the bootstrap effect, the level of the PU point is raised to the second effective level, for example, a high level of 2vgh. At this time, due to the high-level signal of CLK2, the second output signal terminal OUT2 outputs a high-level output signal.
  • the signal of CLK2 changes from high level to low level, and the output of the high level output signal of the second output signal terminal OUT2 ends.
  • the signal from OE is also changed to a high level, so that the low-level INA signal resets the node H. At this point, the operation of one frame is over.
  • the high-level signal output by OUT2 during t10 is used to turn on the switching transistor in the pixel circuit that controls external compensation, so that external compensation can be performed on each pixel in the pixel row corresponding to OUT2. Since the phase of the OE signal is randomly determined by the timing controller, in each frame, the OE signal randomly matches the compensation input signal terminal INA of one of the shift register units in the gate drive circuit. This enables the PU point in the shift register unit to be pulled up in the blank phase, so as to realize the high-level output of OUT2 in the blank phase and realize external compensation.
  • the high-level output of OUT2 also requires its corresponding clock signal terminal (ie CLK2) to have a high level during part of the blank phase (ie t10 period). This can be done by the timing controller after the OE signal is randomly generated. To set up.
  • the external compensation in the shift register unit shown in FIG. 7 is not performed line by line, but is performed randomly through the randomly generated OE signal, which can eliminate the influence of the scanning line moving line by line on the display effect. .
  • FIG. 9 shows a flowchart of a driving method 900 of a shift register unit according to an embodiment of the present disclosure.
  • the method 900 can be used to drive the shift register unit shown in FIGS. 2-4 and 6-7.
  • a frame includes a display phase and a blank phase.
  • the display phase the corresponding gate lines are sequentially driven through each output signal terminal in the shift register unit through different driving periods. Therefore, the display phase may include the first driving period to the Nth driving period.
  • t5-t8 may correspond to the second driving period.
  • the n-th driving period the corresponding gate line is driven by the n-th input sub-circuit, the n-th output sub-circuit, and the n-th reset sub-circuit.
  • the n-th driving period can also be divided into the n-th input period and the n-th reset sub-circuit.
  • step S910 during the n-th input period, the pull-up node is charged to a first effective level (for example, vgh) through the n-th input sub-circuit.
  • a first effective level for example, vgh
  • step S920 during the nth output period, under the control of the voltage of the pull-up node, the nth clock signal is transmitted to the nth output signal terminal.
  • step S930 during the nth reset period, under the control of the nth reset signal, the pull-up node is reset to an inactive level (for example, vgl) through a second level signal.
  • an inactive level for example, vgl
  • the method further includes:
  • the compensation input signal from the compensation input signal terminal turns on the second compensation drive transistor
  • the pull-up node is raised to an effective level by the compensation clock signal, so that the first clock signal to the Nth clock signal can be respectively transmitted to the first output signal terminal to the Nth output signal End;
  • one of the first clock signal to the Nth clock signal is made to have a high level during at least part of the period of the blank phase, so that the first output signal terminal is One of the Nth output signal terminals can output a high level signal in the blank phase.
  • the driving method 900 can be used to drive the shift register unit as described in the above embodiments. Therefore, the above explanations and descriptions are equally applicable here, and will not be repeated here.
  • the gate driving circuit includes a plurality of cascaded shift register unit groups, and each shift register unit group includes K cascaded shift register units, wherein each shift register unit is The shift register unit according to any one of the above embodiments, wherein K is an integer greater than or equal to 3.
  • FIG. 10 shows a cascade structure diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the shift register unit group includes four cascaded shift register units SR1, SR2, SR3, and SR4. Each of these shift register units can be implemented by the shift register unit according to any of the above embodiments.
  • each grid line group includes 4 gate lines arranged in sequence.
  • FIG. 10 includes two gate line groups, the first gate line group includes GATE1-GATE4, and the second gate line group includes GATE5-GATE8.
  • each of SR1-SR4 includes a first output signal terminal OUT1, and the four OUT1 are respectively electrically connected to the four gate lines GATE1-GATE4 in the first gate line group.
  • each input signal terminal is electrically connected with the exception of the first input signal terminal IN1 in SR1
  • the output signal terminal of the previous gate line to the gate line corresponding to the input signal terminal is electrically connected.
  • the first input signal terminal IN1 of SR2 is electrically connected to the output signal terminal of the previous gate line GATE1 (that is, OUT1 of SR1) that is electrically connected to its corresponding gate line GATE2.
  • the second input signal terminal IN2 of SR1 is electrically connected to the output signal terminal of the previous gate line GATE4 (that is, OUT1 of SR4) electrically connected to the corresponding gate line GATE5.
  • the gate line corresponding to the input signal terminal refers to the gate line electrically connected to the output signal terminal corresponding to the input signal terminal.
  • the output signal terminal corresponding to the first input signal terminal IN1 of SR2 is OUT1
  • the output signal terminal OUT1 is electrically connected to the gate line GATE2
  • the gate line corresponding to the first input terminal IN1 of SR2 is the gate line GATE2.
  • the first input signal terminal IN1 of SR1 is electrically connected to the frame start signal terminal STV.
  • both the first clock signal line CK1 and the first gate line GATE1 are electrically connected to the first output sub-circuit in SR1, that is, the first clock signal line CK1 is electrically connected to the CLK1 of SR1, and the first gate line GATE1 is electrically connected to OUT1 is electrically connected.
  • each reset signal terminal is electrically connected to the output signal terminal of the succeeding gate line of the gate line driven by the output sub-circuit corresponding to the reset signal terminal.
  • the first reset signal terminal RST1 of SR1 is electrically connected to the output signal terminal of the succeeding gate line GATE2 of the gate line GATE1 driven by the first output sub-circuit in the corresponding SR1 (ie, OUT1 of SR2).
  • the first reset signal terminal RST1 of SR4 is electrically connected to the output signal terminal (ie OUT2 of SR1) of the next gate line GATE5 of the gate line GATE4 driven by the first output sub-circuit in SR4. connection.
  • the second reset signal terminal of the last stage shift register unit in the last stage shift register unit group of the gate driving circuit is electrically connected to the frame start signal terminal.
  • FIG. 11 shows a flowchart of a driving method 1100 of a gate driving circuit according to an embodiment of the present disclosure.
  • the method 1100 can be used to drive the gate driving circuit 1000 shown in FIG. 10.
  • step S1110 a frame start signal is provided to the first input signal terminal in the first-pole shift register unit in the first-stage shift register unit group.
  • a clock signal is provided to the clock signal terminal in the shift register unit group of each level through the N ⁇ K (for example, 2 ⁇ 4-8) clock signal lines, wherein, through the N ⁇ K clock signal lines, The first edge of the first period of the clock signal provided by the first clock signal line in the signal lines lags behind the first edge of the frame start signal by 1/N ⁇ K clock periods.
  • N ⁇ K for example, 2 ⁇ 4-8
  • the duty cycle of the first clock signal to the N ⁇ Kth clock signal is 1/N ⁇ K, and is sequentially delayed by 1/N ⁇ K clock cycles.
  • Fig. 12 shows a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display device 1200 includes a gate driving circuit 1210.
  • the gate driving circuit 1210 may be implemented by a gate driving circuit according to any embodiment of the present disclosure.
  • the display device 1200 according to the embodiment of the present disclosure may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

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Abstract

一种移位寄存器单元(200, SR1, SR2, SR3, SR4)及其驱动方法、栅极驱动电路(1000,1210)及其驱动方法(1100)和显示装置(1200)。移位寄存器单元(200, SR1, SR2, SR3, SR4)包括第一输入子电路(210-1)至第N输入子电路(210-N)和第一输出子电路(220-1)至第N输出子电路(220-N)，N为大于或等于2的整数。对于n＝1、2、...、N，第n输入子电路（210-n）与第n输入信号端(INn)、第一电平信号端(VDDA)和上拉节点(PU)电连接，并且第n输出子电路(210-n)与第n时钟信号端(CLKn)、上拉节点(PU)和第n输出信号端(OUTn)电连接。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置
交叉引用
本公开要求于2019年2月22日提交的发明名称为“移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置”的中国专利申请201910135181.1的优先权益，在此引出以将其一并并入本文。
技术领域
本公开涉及显示技术领域，具体地涉及一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。
背景技术
在基于薄膜晶体管(Thin Film Transistor，TFT)的液晶显示器(Liquid Crystal Device，LCD)或有源矩阵有机发光显示器(Active Matrix Organic Light Emitting Display，AMOLED)中，可以将驱动栅极的栅极驱动电路形成于显示面板上，构成阵列基板栅极驱动电路(Gate drive On Array，GOA)。该栅极驱动电路包括多个级联的移位寄存器单元，每个移位寄存器单元中包括多个TFT，以分别用于实现输入、下拉和下拉控制、输出、复位和降噪等功能。然而，随着对分辨率等面板参数的要求不断提高，较多的晶体管数目对面板的改进造成了阻碍。
发明内容
本公开提出了一种移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置。
根据本公开的一个方面，提供了一种移位寄存器单元。所述移位寄存器包括第一输入子电路至第N输入子电路和第一输出子电路至第N输出子电路，所述第一输出子电路至第N输出子电路与第一输入子电路至第N输入子电路一一对应，其中，N为大于或等于2的整数。第n输入 子电路与第n输入信号端、第一电平信号端和上拉节点电连接，被配置为在来自所述第n输入信号端的第n输入信号的控制下将来自所述第一电平信号端的第一电平信号传送到所述上拉节点。第n输出子电路与第n时钟信号端、所述上拉节点和第n输出信号端电连接，被配置为在所述上拉节点的电压的控制下将来自所述第n时钟信号端的第n时钟信号传送到所述第n输出信号端，其中，n＝1、2、...、N。
在一些实施例中，所述移位寄存器单元还包括与第一输出子电路至第N输出子电路一一对应的第一下拉子电路至第N下拉子电路。第n下拉子电路与下拉节点、第二电平信号端和所述第n输出信号端电连接，被配置为在所述下拉节点的电压的控制下将来自所述第二电平信号端的第二电平信号传送到所述第n输出信号端。
在一些实施例中，所述移位寄存器单元还包括控制子电路。所述控制子电路与所述上拉节点、所述第二电平信号端、第三电平信号端和所述下拉节点电连接，被配置为在所述上拉节点的电压的控制下将所述第二电平信号或来自所述第三电平信号端的第三电平信号传送到所述下拉节点，
在一些实施例中，所述移位寄存器单元还包括与第一输出子电路至第N输出子电路一一对应的第一复位子电路至第N复位子电路。第n复位子电路与第n复位信号端、所述第二电平信号端和所述上拉节点电连接，被配置为在来自所述第n复位信号端的第n复位信号的控制下将所述第二电平信号传送到所述上拉节点。
在一些实施例中，所述移位寄存器单元还包括总复位子电路。所述总复位子电路与总复位信号端、所述第二电平信号端和所述上拉节点电连接，被配置为在来自所述总复位信号端的总复位信号的控制下将所述第二电平信号传送到所述上拉节点。
在一些实施例中，所述移位寄存器单元还包括外部补偿驱动子电路。所述外部补偿驱动子电路与补偿输入信号端、随机输出使能信号端、补偿时钟信号端、所述第二电平信号端和所述上拉节点电连接，被配置为在来自所述随机输出使能信号端的随机输出使能信号和来自所述补偿时钟信号端的补偿时钟信号的控制下，将所述补偿时钟信号传送到所述上 拉节点。
在一些实施例中，第n输入子电路包括第n输入晶体管。所述第n输入晶体管的控制极与所述第n输入信号端电连接，所述第n输入晶体管的第一极与所述第一电平信号端电连接，所述第n输入晶体管的第二极与所述上拉节点电连接。
在一些实施例中，第n输出子电路包括第n输出晶体管和第n存储电容。所述第n输出晶体管的控制极与所述上拉节点电连接，所述第n输出晶体管的第一极与所述第n时钟信号端电连接，所述第n输出晶体管的第二极与所述第n输出信号端电连接。所述第n存储电容的第一极与所述上拉节点电连接，所述第n存储电容的第二极与所述第n输出信号端电连接。
在一些实施例中，第n下拉子电路包括第n下拉晶体管。所述第n下拉晶体管的控制极与所述下拉节点电连接，所述第n下拉晶体管的第一极与所述第二电平信号端电连接，所述第n下拉晶体管的第二极与所述第n输出信号端电连接。
在一些实施例中，所述控制子电路包括第一控制晶体管和第二控制晶体管。所述第一控制晶体管的控制极和第一极与所述第三电平信号端电连接，所述第一控制晶体管的第二极与所述下拉节点电连接。所述第二控制晶体管的控制极与所述上拉节点电连接，所述第二控制晶体管的第一极与所述第二电平信号端电连接，所述第二控制晶体管的第二极与所述下拉节点电连接。
在一些实施例中，所述控制子电路还包括第三控制晶体管。所述第三控制晶体管的控制极与所述下拉节点电连接，所述第三控制晶体管的第一极与所述第二电平信号端电连接，所述第三控制晶体管的第二极与所述上拉节点电连接。
在一些实施例中，所述第n复位子电路包括第n复位晶体管。所述第n复位晶体管的控制极与所述第n复位信号端电连接，所述第n复位晶体管的第一极与所述第二电平信号端电连接，所述第n复位晶体管的第二极与所述上拉节点电连接。
在一些实施例中，所述总复位子电路包括总复位晶体管。所述总复 位晶体管的控制极与所述总复位信号端电连接，所述总复位晶体管的第一极与所述第二电平信号端电连接，所述总复位晶体管的第二极与所述上拉节点电连接。
在一些实施例中，所述外部补偿驱动子电路包括第一补偿驱动晶体管、第二补偿驱动晶体管、第三补偿驱动晶体管和补偿驱动电容。所述第一补偿驱动晶体管的控制极与所述随机输出使能信号端电连接，所述第一补偿驱动晶体管的第一极与所述补偿输入信号端电连接，所述第一补偿驱动晶体管的第二极与所述补偿驱动电容的第一极电连接。所述第二补偿驱动晶体管的控制极与所述补偿驱动电容的第一极电连接，所述第二补偿驱动晶体管的第一极与所述补偿时钟信号端电连接，所述第二补偿驱动晶体管的第二极与所述第三补偿驱动晶体管的第一极电连接。所述第三补偿驱动晶体管的控制极与所述补偿时钟信号端电连接，所述第三补偿驱动晶体管的第二极与所述上拉节点电连接。所述补偿驱动电容的第二极与所述第二电平信号端电连接。
根据本公开的另一方面，提供了一种根据上述任一实施例所述的移位寄存器单元的驱动方法。其中，每一帧包括第一驱动时段至第N驱动时段。所述方法包括：在第n驱动时段期间，通过第n输入子电路、第n输出子电路和第n复位子电路进行驱动，其中，所述第n驱动时段包括第n输入时段、第n输出时段和第n复位时段。具体地，在第n输入时段期间，通过所述第n输入子电路将所述上拉节点充电至第一有效电平；在第n输出时段期间，在所述上拉节点的电压的控制下，将第n时钟信号传送到第n输出信号端；以及在第n复位时段期间，在第n复位信号的控制下，通过第二电平信号将所述上拉节点复位至无效电平。
在一些实施例中，每一帧还包括位于所述第一驱动时段至第N驱动时段之后的空白阶段。所述方法还包括：在所述随机输出使能信号的控制下，在所述第一输出时段至所述第N输出时段中的一个随机时段期间，使得来自补偿输入信号端的补偿输入信号将所述第二补偿驱动晶体管导通；在空白阶段期间，通过所述补偿时钟信号将所述上拉节点提升到有效电平，以使得第一时钟信号至第N时钟信号能够分别传送到所述第一输出信号端至所述第N输出信号端；以及根据所述随机输出使能信号， 使第一时钟信号至第N时钟信号之一在所述空白阶段的至少部分时段具有高电平，以使得所述第一输出信号端至所述第N输出信号端之一能够在所述空白阶段输出高电平信号。
根据本公开的又一方面，提供了一种栅极驱动电路。所述栅极驱动电路包括多个级联的移位寄存器单元组，每个移位寄存器单元组中包括K个级联的移位寄存器单元，其中，每个移位寄存器单元是根据上述任一实施例所述的移位寄存器单元，其中，K为大于或等于3的整数。每级移位寄存器单元组中的K个级联的移位寄存器单元用于驱动相邻的N×K条栅线，其中，所述N×K条栅线包括按顺序排列的第一栅线组至第N栅线组，每个栅线组中包括K条按顺序排列的栅线，其中，每个移位寄存器单元组中的K个级联的移位寄存器单元中的第n输出信号端分别与第n栅线组中的K条栅线一一对应地电连接。除第一级移位寄存器单元组中的第一级移位寄存器单元的第一输入信号端之外，每个输入信号端与电连接到该输入信号端所对应的栅线的前一栅线的输出信号端电连接。第一级移位寄存器单元组中的第一级移位寄存器单元的第一输入信号端与帧起始信号端电连接。
在一些实施例中，所述栅极驱动电路中的每级移位寄存器单元组与第一时钟信号线至第N×K时钟信号线电连接以分别接收第一时钟信号至第N×K时钟信号。第m时钟信号线与所述移位寄存器单元组驱动的所述N×K条栅线中的第m条栅线连接到相同的输出子电路，其中，m＝1、2、...、N×K。
在一些实施例中，除最后一级移位寄存器单元组中的最后一级移位寄存器单元的第N复位信号端之外，每个复位信号端与电连接到该复位信号端所对应的输出子电路驱动的栅线的后一栅线的输出信号端电连接。最后一级移位寄存器单元组中的最后一级移位寄存器单元的第N复位信号端与帧起始信号端电连接。
根据本公开的又一方面，提供了一种根据上述任一实施例所述的栅极驱动电路的驱动方法。所述驱动方法包括：向所述第一级移位寄存器单元组中的第一极移位寄存器单元中的第一输入信号端提供帧起始信号；以及通过所述N×K个时钟信号线向各级移位寄存器单元组中的时钟信 号端提供时钟信号，其中，通过所述N×K个时钟信号线中的第一时钟信号线提供的时钟信号在第一个周期的第一沿比所述帧起始信号的第一沿滞后1/N×K个时钟周期。
在一些实施例中，所述第一时钟信号至第N×K时钟信号的占空比为1/N×K，并且依次滞后1/N×K个时钟周期。
根据本公开的又一方面.提供了一种显示装置。所述显示装置包括根据上述任一实施例所述的栅极驱动电路。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，图中：
图1示出了相关技术的移位寄存器单元的示意电路图。
图2示出了根据本公开一个实施例的移位寄存器单元的示意结构图。
图3示出了图2所示的移位寄存器单元的进一步实施例的结构框图。
图4示出了图3所示的移位寄存器单元的示例电路图。
图5示出了如图4所示的移位寄存器单元的时序图。
图6示出了图3所示的移位寄存器单元的进一步实施例的结构框图。
图7示出了图6中的移位寄存器单元的示例电路图。
图8示出了图7所示的移位寄存器单元的时序图。
图9示出了根据本公开实施例的移位寄存器单元的驱动方法的流程图。
图10示出了根据本公开实施例的栅极驱动电路的级联结构图。
图11示出了根据本公开实施例的栅极驱动电路的驱动方法的流程图。
图12示出了根据本公开实施例的显示装置的示意方框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“连接”或“电连接”可以是指两个组件直接连接或电连接，也可以是指两个组件之间经由一个或多个其他组件连接或电连接。此外，这两个组件可以通过有线或无线方式电连接或电连接。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。根据在电路中的作用，本公开实施例使用的晶体管主要为开关晶体管。本公开中使用的晶体管包括“控制极”、“第一极”和“第二极”。在使用薄膜晶体管的实施例中，控制极指的是薄膜晶体管的栅极，第一极指代薄膜晶体管的源极和漏极中的一个，第二极指代薄膜晶体管的源极和漏极中的另一个。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在以下示例中以N型薄膜晶体管作为示例进行描述。类似地，在其他实施例中，也可以以P型薄膜晶体管来实现本公开的技术方案。本领域技术人员能够理解的是，在这种情况下，通过将输入信号、时钟信号和恒定电压信号等反相(和/或进行其他适应性修改)，同样能够实现本公开的技术方案。
在本公开实施例中，时钟信号是周期信号。在一个周期中，通过两 个信号沿(第一沿和滞后于第一沿的第二沿)将时钟信号分为相继出现的高电平时段和低电平时段。此外，在本公开实施例的描述中，术语“有效电平”和“无效电平”分别是使相关晶体管导通和截止的电平。在本公开中，“第一有效电平”和“第二有效电平”仅用于区分两个有效电平的幅值不同。在下文中，由于采用N型薄膜晶体管作为示例，因此“有效电平”为高电平，“无效电平”为低电平。
以下参考附图对本公开进行具体描述。
图1示出了相关技术的移位寄存器单元100的示意电路图。如图1所示，在上拉节点PU的控制下，来自时钟信号端CLK1的时钟信号能够通过薄膜晶体管T8向输出信号端OUT提供高电平，在下拉节点PD的控制下，来自恒定电压信号端VSS的信号能够通过薄膜晶体管T9向输出信号端OUT提供低电平。从而，通过控制上拉节点PU和下拉节点PD的电位时序，能够实现对输出信号端OUT输出的信号的控制。为了实现对上拉节点PU的电压的适当控制，在输入阶段，通过输入晶体管T1来使用输入信号将上拉节点PU充电到高电平；在复位阶段，通过复位晶体管T2来使用来自VSS的低电平信号将上拉节点PU复位为低电平；并且还通过薄膜晶体管T3来实现对上拉节点PU的降噪功能。
此外，为了实现对下拉节点PD的电压的适当控制，通过薄膜晶体管T4、T5、T6和T7连接成的子电路结构来将来自VDD的高电平和来自VSS的低电平分别传送到下拉节点PD。下拉节点PD的最终电压是由T6和T7的沟道宽长比决定的，通过适当的设置宽长比，可以实现PD点电压的恰当设定。
可见，移位寄存器单元100中为了实现对输出信号端的输出的控制，采用了多个薄膜晶体管，以分别实现输入、复位、降噪、下拉控制等功能，薄膜晶体管的数量较多，不利于后续设计中面板性能的改善。
图2示出了根据本公开一个实施例的移位寄存器单元200的示意结构图。
如图2所示，移位寄存器单元200包括第一输入子电路210-1至第 N输入子电路210-N，以及第一输出子电路220-1至第N输出子电路220-N。第一输出子电路210-1至第N输出子电路210-N与第一输入子电路220-1至第N输入子电路220-N一一对应。其中，N为大于或等于2的整数。移位寄存器单元200还具有第一输入信号端IN1至第N输入信号端INN、第一输出信号端OUT1至第N输出信号端OUTN、第一时钟信号端CLK1至第N时钟信号端CLKN以及第一电平信号端VDDA。
对于1至N中的任何一个(即对于n＝1、2、...、N)，第n输入子电路210-n与第n输入信号端INn、第一电平信号端VDDA和上拉节点PU电连接。第n输入子电路210-n被配置为在来自第n输入信号端INn的第n输入信号的控制下将来自第一电平信号端VDDA的第一电平信号传送到上拉节点PU。
第n输出子电路220-n与第n时钟信号端CLKn、上拉节点PU和第n输出信号端OUTn电连接。第n输出子电路220-n被配置为在上拉节点PU的电压的控制下将来自第n时钟信号端CLKn的第n时钟信号传送到第n输出信号端OUTn。
在其他实施例中，对于1至N中的任何一个(即对于n＝1、2、...、N)，第n输入子电路210-n可以不与第一电平信号端VDDA电连接，而只与第n输入信号端INn和上拉节点PU电连接。在如此的实施例中，第n输入子电路210-n被配置为在来自第n输入信号端INn的第n输入信号的控制下将第n输入信号传送到上拉节点PU。
图3示出了图2的移位寄存器单元200的进一步实施例的结构框图。
如图3所示，移位寄存器单元200还包括第一下拉子电路230-1至第N下拉子电路230-N，第一下拉子电路230-1至第N下拉子电路230-N与第一输出子电路220-1至第N输出子电路220-N一一对应。
第n下拉子电路230-n与下拉节点PD、第二电平信号端VSS和第n输出信号端220-n电连接。第n下拉子电路230-n被配置为在下拉节点PD的电压的控制下将来自第二电平信号端VSS的第二电平信号传送到第n输出信号端220-n。
在图3所示的实施例中，移位寄存器单元200还包括控制子电路240。
控制子电路240与上拉节点PU、第二电平信号端VSS、第三电平 信号端VDDB和下拉节点PD电连接。控制子电路240被配置为在上拉节点PU的电压的控制下将第二电平信号或来自第三电平信号端VDDB的第三电平信号传送到下拉节点PD。
在图3所示的实施例中，移位寄存器单元200还包括第一复位子电路250-1至第N复位子电路250-N，第一复位子电路250-1至第N复位子电路250-N与第一输出子电路220-1至第N输出子电路220-N一一对应。
第n复位子电路250-n与第n复位信号端RSTn、第二电平信号端VSS和上拉节点PU电连接。第n复位子电路250-n被配置为在来自第n复位信号端RSTn的第n复位信号的控制下将第二电平信号传送到上拉节点PU。
图4示出了图3中的移位寄存器单元200的示例电路图。为了便于说明，图4中只示出了N等于2的情况下的电路图。应该理解的是，本公开不限于此，在其他实施例中，N可以为大于2的任何整数。本领域技术人员能够在以下说明和描述的基础上获知在N为其他数值的情况下的电路结构和工作流程。
如图4所示，第一输入子电路210-1包括第一输入晶体管T11。第一输入晶体管T11的控制极与第一输入信号端IN1电连接，第一输入晶体管T11的第一极与第一电平信号端VDDA电连接，第一输入晶体管T11的第二极与上拉节点PU电连接。
类似地，第二输入子电路210-2包括第二输入晶体管T12。第二输入晶体管T12的控制极与第二输入信号端IN2电连接，第二输入晶体管T12的第一极与第一电平信号端VDDA电连接，第二输入晶体管T12的第二极与上拉节点PU电连接。
在其他实施例中，第一输入晶体管T11和第二输入晶体管T12可以具有二极管连接形式。具体地，第一输入晶体管T11的控制极和第一极都与第一输入信号端IN1电连接，第一输入晶体管T11的第二极与上拉节点PU电连接。类似地，第二输入晶体管T12的控制极和第一极都与第二输入信号端IN2电连接，第二输入晶体管T12的第二极与上拉节点PU电连接。
第一输出子电路220-1包括第一输出晶体管T21和第一存储电容C1。第一输出晶体管T21的控制极与上拉节点PU电连接，第一输出晶体管T21的第一极与第一时钟信号端CLK1电连接，第一输出晶体管T21的第二极与第一输出信号端OUT1电连接。第一存储电容C1的第一极与上拉节点PU电连接，第一存储电容C1的第二极与第一输出信号端OUT1电连接。
类似地，第二输出子电路220-2包括第二输出晶体管T22和第二存储电容C2。第二输出晶体管T22的控制极与上拉节点PU电连接，第二输出晶体管T22的第一极与第二时钟信号端CLK2电连接，第二输出晶体管T22的第二极与第二输出信号端OUT2电连接。第二存储电容C2的第一极与上拉节点PU电连接，第二存储电容C2的第二极与第二输出信号端OUT2电连接。
第一下拉子电路230-1包括第一下拉晶体管T31。第一下拉晶体管T31的控制极与下拉节点PD电连接，第一下拉晶体管T31的第一极与第二电平信号端VSS电连接，第一下拉晶体管T31的第二极与第一输出信号端OUT1电连接。
类似地，第二下拉子电路230-2包括第二下拉晶体管T32。第二下拉晶体管T32的控制极与下拉节点PD电连接，第二下拉晶体管T32的第一极与第二电平信号端VSS电连接，第二下拉晶体管T32的第二极与第二输出信号端OUT2电连接。
控制子电路240包括第一控制晶体管Tc1和第二控制晶体管Tc2。第一控制晶体管Tc1的控制极和第一极与第三电平信号端VDDB电连接，第一控制晶体管Tc1的第二极与下拉节点PD电连接。第二控制晶体管Tc2的控制极与上拉节点PU电连接，第二控制晶体管Tc2的第一极与第二电平信号端VSS电连接，第二控制晶体管Tc2的第二极与下拉节点PD电连接。
在一些实施例中(如图4所示)，控制子电路240还包括第三控制晶体管Tc3。第三控制晶体管Tc3的控制极与下拉节点PD电连接，第三控制晶体管Tc3的第一极与第二电平信号端VSS电连接，第三控制晶体管Tc3的第二极与上拉节点PU电连接。
第一复位子电路250-1包括第一复位晶体管T51。第一复位晶体管T51的控制极与第一复位信号端RST1电连接，第一复位晶体管T51的第一极与第二电平信号端VSS电连接，第一复位晶体管T51的第二极与上拉节点PU电连接。
类似地，第二复位子电路250-2包括第二复位晶体管T52。第二复位晶体管T52的控制极与第二复位信号端RST2电连接，第二复位晶体管T52的第一极与第二电平信号端VSS电连接，第二复位晶体管T52的第二极与上拉节点PU电连接。
图5示出了图4所示的移位寄存器单元200的时序图。以下结合图5对图4中的移位寄存器单元200的操作流程进行描述。
根据图5中的时序图，一个时钟周期被等分为8个时段，第二时钟信号端CLK2的时钟信号比第一时钟信号端CLK1的时钟信号滞后4个时段，即半个时钟周期，第二输入信号端IN2的信号比第一输入信号端IN1的时钟信号滞后4个时段，并且第二复位信号端RST2的信号比第一复位信号端RST1的信号滞后4个时段。应该注意的是，在图5的时序图中第一电平信号端VDDA和第三电平信号端VDDB的信号都被示为恒定高电平信号。在其他实施例中，可以只设置VDDB，而将第一输入晶体管T11和第二输入晶体管T12实现为二极管连接，此时，通过第一输入信号端IN1和第二输入信号端IN2来起到VDDA的作用。
在t1时段之前，移位寄存器单元200的第一输入信号端IN1和第二输入信号端IN2处没有输入信号输入，即移位寄存器单元200在时段t1开始工作。
在t1时段内，输入信号端IN1的信号从低电平(例如，vgl)变为高电平(例如，vgh)，将第一输入晶体管T11导通。此时，第一电平信号端VDDA的高电平传送到上拉节点PU，将上拉节点PU的电压上拉至第一有效电平，即高电平vgh。在上拉节点PU的高电平作用下，第一输出晶体管T21和第二输出晶体管T22都被导通，但此时第一时钟信号端CLK1和第二时钟信号端CLK2仍提供低电平vgl，因此，第一输出信号端OUT1和第二输出信号端OUT2从第一时钟信号端CLK1和第二 时钟信号端CLK2接收低电平信号。
应该指出的是，在设置了第三控制晶体管Tc3(用于在复位后保持对PU进行降噪)的电路结构中，在t1时段开始之前，由于第三恒定电压信号端VDDB一直向第一控制晶体管Tc1的控制极和第一极提供高电平，因此，来自VDDB的高电平信号保持PD点的电平为高电平，这使得第三晶体管Tc3导通，从而来自VSS的低电平在t1之前使PU保持为低电平。若使得来自VDDA的高电平信号能够将PU点拉高，需要对第一输入晶体管T11的沟道宽长比和第三晶体管Tc3的沟道宽长比进行设置。
在PU的高电平作用下，第二控制晶体管Tc2导通，来自第二电平信号端VSS的低电平信号能够传送到下拉节点PD。另一方面，如上文所述，第三电平信号端VDDB向下拉节点PD提供高电平信号。在这种情况下，根据Tc1与Tc2的沟道宽长比设置可以使得下拉节点PD最终被置为低电平。进而，下拉节点PD处的低电平使得第一下拉晶体管T31和第二下拉晶体管T32截止。
此时，第一输出信号端OUT1和第二输出信号端OUT2的输出信号均为低电平信号。
在t2时段内，第一时钟信号端CLK1的信号变为高电平，第二时钟信号端CLK2保持低电平，第一输入信号端IN1的信号变为低电平。第一时钟信号端CLK1的信号的高电平使得第一输出信号端OUT1接收到高电平信号。由于第一输入信号端IN1的低电平使得第一输入晶体管T11截止，所以上拉节点PU被浮置。通过第一电容C1的自举作用，PU点的电压将进一步提升至第二有效电平，例如2vgh。此外，由于第二时钟信号端CLK2仍输出低电平信号，所以第二输出信号端OUT2保持接收低电平信号。
此时，第一下拉晶体管T31和第二下拉晶体管T32截止。因此，第一输出信号端OUT1输出高电平信号并且第二输出信号端OUT2输出低电平信号。
在t3时段内，第一时钟信号端CLK1的信号变为低电平，第二时钟信号端CLK2的信号保持低电平，第一复位信号端RST1的信号变为高 电平。在高电平的第一复位信号的作用下，第一复位晶体管T51导通，将上拉节点PU拉至低电平，实现对PU点的复位。这使得第一输出晶体管T21和第二晶体管T22截止。此外，PU点的复位使得第二控制晶体管Tc2截止，导致下拉节点PD在来自VDDB的信号的作用下变为高电平。进而，第一下拉晶体管T31和第二下拉晶体管T32都导通，将VSS的低电平信号进一步传送到第一输出信号端OUT1和第二输出信号端OUT2，使二者输出低电平。
在t4时段内，第一时钟信号端CLK1的信号和第二时钟信号端CLK2的信号保持低电平，第一复位信号端RST1的信号变为低电平。PD点在t3时段已经变为高电平，从而，在设置了第三控制晶体管Tc3的实施例中，来自VSS的低电平信号通过第三控制晶体管Tc3对PU点进行降噪。
在t5时段内，输入信号端IN2的信号从低电平(例如，vgl)变为高电平(例如，vgh)，将第二输入晶体管T12导通。此时，第一电平信号端VDDA的高电平传送到上拉节点PU，将上拉节点PU的电压上拉至第一有效电平，即高电平vgh。在上拉节点PU的高电平作用下，第一输出晶体管T21和第二输出晶体管T22都被导通，但此时第一时钟信号端CLK1和第二时钟信号端CLK2仍提供低电平vgl，因此，第一输出信号端OUT1和第二输出信号端OUT2从第一时钟信号端CLK1和第二时钟信号端CLK2接收低电平信号。
应该指出的是，在设置了第三控制晶体管Tc3的电路结构中，在t4时段中，来自VSS的低电平保持对PU的降噪，使其为低电平。若使得来自VDDA的高电平信号能够将PU点拉高，需要对第二输入晶体管T12的沟道宽长比和第三晶体管Tc3的沟道宽长比进行设置。
在PU的高电平作用下，第二控制晶体管Tc2导通，来自第二电平信号端VSS的低电平信号能够传送到下拉节点PD。另一方面，如上文所述，第三电平信号端VDDB向下拉节点PD提供高电平信号。在这种情况下，根据Tc1与Tc2的沟道宽长比设置可以使得下拉节点PD最终被置为低电平。进而，下拉节点PD处的低电平使得第一下拉晶体管T31和第二下拉晶体管T32截止。
此时，第一输出信号端OUT1和第二输出信号端OUT2的输出信号均为低电平信号。
在t6时段内，第二时钟信号端CLK2的信号变为高电平，第一时钟信号端CLK1的信号保持低电平，第二输入信号端IN2的信号变为低电平。第二时钟信号端CLK2的信号的高电平使得第二输出信号端OUT2接收到高电平信号。由于第二输入信号端IN2的低电平使得第二输入晶体管T12截止，所以上拉节点PU被浮置。通过第二电容C2的自举作用，PU点的电压将进一步提升至第二有效电平，例如2vgh。此外，由于第一时钟信号端CLK1仍输出低电平信号，所以第一输出信号端OUT1保持接收低电平信号。
此时，第一下拉晶体管T31和第二下拉晶体管T32截止。因此，第一输出信号端OUT1输出低电平信号并且第二输出信号端OUT2输出高电平信号。
在t7时段内，第二时钟信号端CLK2的信号变为低电平，第一时钟信号端CLK1的信号保持低电平，第二复位信号端RST2的信号变为高电平。在高电平的第二复位信号的作用下，第二复位晶体管T52导通，将上拉节点PU拉至低电平，实现对PU点的复位。这使得第一输出晶体管T21和第二晶体管T22截止。此外，PU点的复位使得第二控制晶体管Tc2截止，导致下拉节点PD在来自VDDB的信号的作用下变为高电平。进而，第一下拉晶体管T31和第二下拉晶体管T32都导通，将VSS的低电平信号进一步传送到第一输出信号端OUT1和第二输出信号端OUT2，使二者输出低电平。
在t8时段内，第一时钟信号端CLK1的信号和第二时钟信号端CLK2的信号保持低电平，第二复位信号端RST2的信号变为低电平。PD点在t7时段已经变为高电平，从而，在设置了第三控制晶体管Tc3的实施例中，来自VSS的低电平信号通过第三控制晶体管Tc3对PU点进行降噪。
应该指出的是，图5中的时序只是示例性的，在其他实施例中，移位寄存器单元200还可以根据其他时序进行操作。例如，在另一时序中， 可以将一个时钟周期分为6个时段，第二时钟信号端CLK2的时钟信号比第一时钟信号端CLK1的时钟信号滞后3个时段，即半个时钟周期，第二输入信号端IN2的信号比第一输入信号端IN1的时钟信号滞后3个时段，并且第二复位信号端RST2的信号比第一复位信号端RST1的信号滞后3个时段。在这一时序中，将不具有与图5中的t4和t8相对应的时段。
类似地，在另一时序中，可以一般性地将一个时钟周期分为2k个时段(k为大于4的整数)，第二时钟信号端CLK2的时钟信号比第一时钟信号端CLK1的时钟信号滞后k个时段，即半个时钟周期，第二输入信号端IN2的信号比第一输入信号端IN1的时钟信号滞后k个时段，并且第二复位信号端RST2的信号比第一复位信号端RST1的信号滞后k个时段。在这一时序中，t4和t8阶段将分别覆盖k-3个连续的时段。
图6示出了图3所示的移位寄存器单元200的进一步实施例的结构框图。与图3中的结构相比，图6中的移位寄存器单元还包括总复位子电路260和外部补偿驱动子电路270。
总复位子电路260与总复位信号端TRST、第二电平信号端VSS和上拉节点PU电连接。总复位子电路260被配置为在来自总复位信号端TRST的总复位信号的控制下将第二电平信号传送到上拉节点PU。
外部补偿驱动子电路270与补偿输入信号端INA、随机输出使能信号端OE、补偿时钟信号端CLKA、第二电平信号端VSS和上拉节点PU电连接。外部补偿驱动子电路270被配置为在来自随机输出使能信号端OE的随机输出使能信号和来自补偿时钟信号端CLKA的补偿时钟信号的控制下，将补偿时钟信号CLKA传送到上拉节点PU。
图7示出了图6中的移位寄存器单元的示例电路图。为了便于说明，图6中只示出了N等于2的情况下的电路图。应该理解的是，本公开不限于此，在其他实施例中，N可以为大于2的任何整数。本领域技术人员能够在以下说明和描述的基础上获知在N为其他数值的情况下的电路结构和工作流程。
如图7所示，总复位子电路260包括总复位晶体管T61。总复位晶体管T61的控制极与总复位信号端TRST电连接，总复位晶体管T61的第一极与第二电平信号端VSS电连接，总复位晶体管T61的第二极与上拉节点PU电连接。
外部补偿驱动子电路270包括第一补偿驱动晶体管T71、第二补偿驱动晶体管T72、第三补偿驱动晶体管T73和补偿驱动电容CA。第一补偿驱动晶体管T71的控制极与随机输出使能信号端OE电连接，第一补偿驱动晶体管T71的第一极与补偿输入信号端INA电连接，第一补偿驱动晶体管T71的第二极与补偿驱动电容CA的第一极电连接于节点H。
第二补偿驱动晶体管T72的控制极与节点H电连接，第二补偿驱动晶体管T72的第一极与补偿时钟信号端CLKA电连接，第二补偿驱动晶体管T72的第二极与第三补偿驱动晶体管T73的第一极电连接。
第三补偿驱动晶体管T73的控制极与补偿时钟信号端CLKA电连接，第三补偿驱动晶体管T73的第二极与上拉节点PU电连接。
补偿驱动电容CA的第二极与第二电平信号端VSS电连接。
图8示出了图7所示的移位寄存器单元的时序图。以下结合图8对图7中的移位寄存器单元的操作流程进行描述。从图8可见，一帧被分为两个阶段，即显示阶段和空白(Blank)阶段。显示阶段包括t1-t8，空白阶段包括t9-t11。各输入子电路、输出子电路、下拉子电路、控制子电路和复位子电路在显示阶段的时序与图5相同，以下只针对总复位子电路260和外部补偿驱动子电路270的操作进行描述。
总复位子电路260的操作只存在于t12中，通过将总复位信号端TRST的信号变为高电平，总复位晶体管T61接通，从而，VSS的信号对PU进行复位。应该指出的是，图7所示的移位寄存器单元所在的栅极驱动电路中的所有移位寄存器单元共用同一个TRST，因此，在t12中，对栅极驱动电路中的所有移位寄存器单元进行总体复位。
外部补偿驱动子电路270的操作开始于t2时段，在t2时段中，补偿输入信号端INA开始接收高电平，随机输出使能信号端OE输入高电平。在OE的高电平的作用下，第一补偿驱动晶体管T71导通，将节点 H提升到高电平。因此，第二补偿驱动晶体管T72导通将CLKA的信号传送到第三补偿驱动晶体管T73的第一极。此时，CLKA的信号为低电平，第三补偿驱动晶体管T73截止，CLKA的信号不会传送到上拉节点PU。
在随后的t3-t8时段，补偿输入信号端INA接收低电平，随机输出使能信号端OE输入低电平，从而T71截止，节点H保持高电平，T72持续导通。
在t9期间，CLKA的信号变为高电平，将第三补偿驱动晶体管T73导通，此时，高电平的CLKA信号将PU点上拉至第一有效电平，例如高电平vgh，这使得第一输出晶体管T21和第二输出晶体管T22都导通。然而，此时第一时钟信号端CLK1和第二时钟信号端CLK2的信号都为低电平，因此，第一输出信号端OUT1和第二输出信号端OUT2的输出都为低电平。
在t10期间，CLKA的信号为低电平，CLK2的信号变为高电平，CLK1的信号保持低电平。PU点处于浮置状态。由于自举作用，PU点的电平提升到第二有效电平，例如，高电平2vgh。此时，由于CLK2的高电平信号，第二输出信号端OUT2输出高电平输出信号。
在t11期间，CLK2的信号由高电平变为低电平，第二输出信号端OUT2的高电平输出信号输出结束。
在t12期间，除了通过TRST的信号对PU进行复位之外，还通过将来自OE的信号变为高电平，使得低电平的INA信号将节点H复位。至此，一帧的操作结束。
应该指出的是，在t10期间OUT2输出的高电平信号用于将像素电路中控制外部补偿的开关晶体管导通，以使得能够对OUT2所对应的像素行中的各个像素进行外部补偿。由于OE信号的相位是由时序控制器随机确定的，在每一帧中，OE信号随机地与栅极驱动电路中的所有移位寄存器单元中的某一个移位寄存器单元的补偿输入信号端INA的信号同步，这使得该移位寄存器单元中的PU点能够在空白阶段得到上拉，从而实现OUT2在空白阶段的高电平输出，实现外部补偿。当然，OUT2 的高电平输出还需要其所对应的时钟信号端(即CLK2)在空白阶段的部分时段(即t10时段)具有高电平，这可以由时序控制器在随机生成了OE信号之后来设置。
由此，在图7所示的移位寄存器单元中外部补偿并不是逐行进行的，而是通过随机产生的OE信号来随机进行的，这能够消除逐行移动的扫描线对显示效果的影响。
图9示出了根据本公开实施例的移位寄存器单元的驱动方法900的流程图。方法900可用于驱动根据图2-4和6-7所示的移位寄存器单元。根据上文所述，一帧中包括显示阶段和空白阶段。在显示阶段中，通过不同的驱动时段依次通过移位寄存器单元中的各个输出信号端对相应的栅线进行驱动，因此，显示阶段可以包括第一驱动时段至第N驱动时段。例如，在以上实施例中，针对如图5所示的N＝2的情况，t1-t4可以对应于第一驱动时段，t5-t8可以对应于第二驱动时段。
在第n驱动时段中，通过第n输入子电路、第n输出子电路和第n复位子电路驱动对应的栅线，其中，所述第n驱动时段还可分为第n输入时段、第n输出时段和第n复位时段。例如，针对如图5所示的N＝2的情况，第一驱动时段包括第一输入时段t1、第一输出时段t2和第一复位时段t3。
具体地，在步骤S910中，在第n输入时段期间，通过所述第n输入子电路将所述上拉节点充电至第一有效电平(例如vgh)。
在步骤S920中，在第n输出时段期间，在上拉节点的电压的控制下，将第n时钟信号传送到第n输出信号端。
在步骤S930中，在第n复位时段期间，在第n复位信号的控制下，通过第二电平信号将所述上拉节点复位至无效电平(例如，vgl)。
在一些实施例中，所述方法还包括：
在随机输出使能信号的控制下，在第一输出时段至第N输出时段中的一个随机时段期间，使得来自补偿输入信号端的补偿输入信号将所述第二补偿驱动晶体管导通；
在空白阶段期间，通过所述补偿时钟信号将上拉节点提升到有效电平，以使得第一时钟信号至第N时钟信号能够分别传送到所述第一输出信号端至所述第N输出信号端；以及
根据所述随机输出使能信号，使第一时钟信号至第N时钟信号中的一个时钟信号在所述空白阶段的至少部分时段期间具有高电平，以使得所述第一输出信号端至所述第N输出信号端之一能够在所述空白阶段输出高电平信号。
应该理解的是，由于驱动方法900可以用于对如上文各实施例所述的移位寄存器单元进行驱动。因此，上文进行的解释和说明在此同样适用，不再进行赘述。
根据本公开实施例的栅极驱动电路包括多个级联的移位寄存器单元组，每个移位寄存器单元组中包括K个级联的移位寄存器单元，其中，每个移位寄存器单元是根据上述任一实施例所述的移位寄存器单元，其中，K为大于或等于3的整数。
图10示出了根据本公开实施例的栅极驱动电路的级联结构图。图10中只示出了栅极驱动电路中的一个移位寄存器单元组作为示例，并且图10中示例性地令K＝4。因此，如图10所示，移位寄存器单元组包括四个级联的移位寄存器单元SR1、SR2、SR3和SR4。这些移位寄存器单元中的每一个可以通过根据上述任一实施例所述的移位寄存器单元实现。
在图10中，每级移位寄存器单元组中的4个级联的移位寄存器单元用于驱动相邻的2×4＝8条栅线，其中，所述8条栅线包括按顺序排列的第一栅线组至第2栅线组，每个栅线组中包括4条按顺序排列的栅线。例如，图10中包括两个栅线组，第一栅线组包括GATE1-GATE4，第二栅线组包括GATE5-GATE8。
每个移位寄存器单元组中的4个级联的移位寄存器单元中的第n输出信号端分别与第n栅线组中的K条栅线一一对应地电连接。例如，SR1-SR4中各包括第一输出信号端OUT1，这四个OUT1分别与第一栅线组中的4条栅线GATE1-GATE4电连接。
假设图10中示出的移位寄存器单元组是栅极驱动电路中的第一级移位寄存器单元组，则除SR1中的第一输入信号端IN1之外，每个输入信号端与电连接到该输入信号端所对应的栅线的前一栅线的输出信号端电连接。例如，SR2的第一输入信号端IN1与电连接到其所对应的栅线GATE2的前一栅线GATE1的输出信号端(即SR1的OUT1)电连接。再例如，SR1的第二输入信号端IN2与电连接到其所对应的栅线GATE5的前一栅线GATE4的输出信号端(即SR4的OUT1)电连接。这里，与输入信号端对应的栅线是指与输入信号端对应的输出信号端电连接的栅线。例如，SR2的第一输入信号端IN1对应的输出信号端是OUT1，输出信号端OUT1与栅线GATE2电连接，因此SR2的第一输入端IN1所对应的栅线是栅线GATE2。
作为例外的是，SR1的第一输入信号端IN1与帧起始信号端STV电连接。
如图10所示，每个移位寄存器单元组与第一时钟信号线CK1至第八时钟信号线CK8电连接(8＝2×4(即N×K))，以分别接收第一时钟信号至第八时钟信号，第m时钟信号线与所述移位寄存器单元组驱动的所述八条栅线中的第m条栅线连接到相同的输出子电路，其中，m＝1、2、...、8。例如，第一时钟信号线CK1与第一条栅线GATE1都与SR1中的第一输出子电路电连接，即，第一时钟信号线CK1与SR1的CLK1电连接，第一条栅线GATE1与OUT1电连接。
在图10所示的移位寄存器单元组中，每个复位信号端与电连接到该复位信号端所对应的输出子电路驱动的栅线的后一栅线的输出信号端电连接。例如，SR1的第一复位信号端RST1与电连接到其所对应的SR1中的第一输出子电路所驱动的栅线GATE1的后一栅线GATE2的输出信号端(即SR2的OUT1)电连接。再例如，SR4的第一复位信号端RST1与电连接到其所对应的SR4中的第一输出子电路所驱动的栅线GATE4的后一栅线GATE5的输出信号端(即SR1的OUT2)电连接。
作为例外的是，栅极驱动电路的最后一级移位寄存器单元组中的最后一级移位寄存器单元的第二复位信号端与帧起始信号端电连接。
图11示出了根据本公开实施例的栅极驱动电路的驱动方法1100的流程图。所述方法1100可用于对如图10所示的栅极驱动电路1000进行驱动。
在步骤S1110中，向第一级移位寄存器单元组中的第一极移位寄存器单元中的第一输入信号端提供帧起始信号。
在步骤S1120中，通过所述N×K(例如2×4-8)个时钟信号线向各级移位寄存器单元组中的时钟信号端提供时钟信号，其中，通过所述N×K个时钟信号线中的第一时钟信号线提供的时钟信号在第一个周期的第一沿比所述帧起始信号的第一沿滞后1/N×K个时钟周期。
在一些实施例中，所述第一时钟信号至第N×K时钟信号的占空比为1/N×K，并且依次滞后1/N×K个时钟周期。
图12示出了根据本公开实施例的显示装置的示意方框图。如图12所示，显示装置1200包括栅极驱动电路1210。所述栅极驱动电路1210可以通过根据本公开任一实施例的栅极驱动电路来实现。根据本公开实施例的显示装置1200可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上的详细描述通过使用示意图、流程图和/或示例，已经阐述了众多实施例。在这种示意图、流程图和/或示例包含一个或多个功能和/或操作的情况下，本领域技术人员应理解，这种示意图、流程图或示例中的每一功能和/或操作可以通过各种结构、硬件、软件、固件或实质上它们的任意组合来单独和/或共同实现。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (22)

  1. 一种移位寄存器单元，包括第一输入子电路至第N输入子电路和第一输出子电路至第N输出子电路，所述第一输出子电路至第N输出子电路与第一输入子电路至第N输入子电路一一对应，其中，N为大于或等于2的整数，
    第n输入子电路与第n输入信号端、第一电平信号端和上拉节点电连接，被配置为在来自所述第n输入信号端的第n输入信号的控制下将来自所述第一电平信号端的第一电平信号传送到所述上拉节点，
    第n输出子电路与第n时钟信号端、所述上拉节点和第n输出信号端电连接，被配置为在所述上拉节点的电压的控制下将来自所述第n时钟信号端的第n时钟信号传送到所述第n输出信号端，其中，n＝1、2、...、N。
  2. 根据权利要求1所述的移位寄存器单元，还包括与第一输出子电路至第N输出子电路一一对应的第一下拉子电路至第N下拉子电路，其中，
    第n下拉子电路与下拉节点、第二电平信号端和所述第n输出信号端电连接，被配置为在所述下拉节点的电压的控制下将来自所述第二电平信号端的第二电平信号传送到所述第n输出信号端。
  3. 根据权利要求2所述的移位寄存器单元，还包括控制子电路，其中，
    所述控制子电路与所述上拉节点、所述第二电平信号端、第三电平信号端和所述下拉节点电连接，被配置为在所述上拉节点的电压的控制下将所述第二电平信号或来自所述第三电平信号端的第三电平信号传送到所述下拉节点。
  4. 根据权利要求3所述的移位寄存器单元，还包括与第一输出子电路至第N输出子电路一一对应的第一复位子电路至第N复位子电路，其中，
    第n复位子电路与第n复位信号端、所述第二电平信号端和所述上拉节点电连接，被配置为在来自所述第n复位信号端的第n复位信号的 控制下将所述第二电平信号传送到所述上拉节点。
  5. 根据权利要求4所述的移位寄存器单元，还包括总复位子电路，其中，
    所述总复位子电路与总复位信号端、所述第二电平信号端和所述上拉节点电连接，被配置为在来自所述总复位信号端的总复位信号的控制下将所述第二电平信号传送到所述上拉节点。
  6. 根据权利要求5所述的移位寄存器单元，还包括外部补偿驱动子电路，其中，
    所述外部补偿驱动子电路与补偿输入信号端、随机输出使能信号端、补偿时钟信号端、所述第二电平信号端和所述上拉节点电连接，被配置为在来自所述随机输出使能信号端的随机输出使能信号和来自所述补偿时钟信号端的补偿时钟信号的控制下，将所述补偿时钟信号传送到所述上拉节点。
  7. 根据权利要求1所述的移位寄存器单元，其中，第n输入子电路包括第n输入晶体管，其中，
    所述第n输入晶体管的控制极与所述第n输入信号端电连接，所述第n输入晶体管的第一极与所述第一电平信号端电连接，所述第n输入晶体管的第二极与所述上拉节点电连接。
  8. 根据权利要求1所述的移位寄存器单元，其中，第n输出子电路包括第n输出晶体管和第n存储电容，其中，
    所述第n输出晶体管的控制极与所述上拉节点电连接，所述第n输出晶体管的第一极与所述第n时钟信号端电连接，所述第n输出晶体管的第二极与所述第n输出信号端电连接，以及
    所述第n存储电容的第一极与所述上拉节点电连接，所述第n存储电容的第二极与所述第n输出信号端电连接。
  9. 根据权利要求2所述的移位寄存器单元，其中，第n下拉子电路包括第n下拉晶体管，其中，
    所述第n下拉晶体管的控制极与所述下拉节点电连接，所述第n下拉晶体管的第一极与所述第二电平信号端电连接，所述第n下拉晶体管的第二极与所述第n输出信号端电连接。
  10. 根据权利要求3所述的移位寄存器单元，其中，所述控制子电路包括第一控制晶体管和第二控制晶体管，其中，
    所述第一控制晶体管的控制极和第一极与所述第三电平信号端电连接，所述第一控制晶体管的第二极与所述下拉节点电连接，
    所述第二控制晶体管的控制极与所述上拉节点电连接，所述第二控制晶体管的第一极与所述第二电平信号端电连接，所述第二控制晶体管的第二极与所述下拉节点电连接。
  11. 根据权利要求10所述的移位寄存器单元，其中，所述控制子电路还包括第三控制晶体管，其中，
    所述第三控制晶体管的控制极与所述下拉节点电连接，所述第三控制晶体管的第一极与所述第二电平信号端电连接，所述第三控制晶体管的第二极与所述上拉节点电连接。
  12. 根据权利要求4所述的移位寄存器单元，其中，所述第n复位子电路包括第n复位晶体管，其中，
    所述第n复位晶体管的控制极与所述第n复位信号端电连接，所述第n复位晶体管的第一极与所述第二电平信号端电连接，所述第n复位晶体管的第二极与所述上拉节点电连接。
  13. 根据权利要求5所述的移位寄存器单元，其中，所述总复位子电路包括总复位晶体管，其中，
    所述总复位晶体管的控制极与所述总复位信号端电连接，所述总复位晶体管的第一极与所述第二电平信号端电连接，所述总复位晶体管的第二极与所述上拉节点电连接。
  14. 根据权利要求6所述的移位寄存器单元，其中，所述外部补偿驱动子电路包括第一补偿驱动晶体管、第二补偿驱动晶体管、第三补偿驱动晶体管和补偿驱动电容，其中，
    所述第一补偿驱动晶体管的控制极与所述随机输出使能信号端电连接，所述第一补偿驱动晶体管的第一极与所述补偿输入信号端电连接，所述第一补偿驱动晶体管的第二极与所述补偿驱动电容的第一极电连接，
    所述第二补偿驱动晶体管的控制极与所述补偿驱动电容的第一极电连接，所述第二补偿驱动晶体管的第一极与所述补偿时钟信号端电连 接，所述第二补偿驱动晶体管的第二极与所述第三补偿驱动晶体管的第一极电连接，
    所述第三补偿驱动晶体管的控制极与所述补偿时钟信号端电连接，所述第三补偿驱动晶体管的第二极与所述上拉节点电连接，
    所述补偿驱动电容的第二极与所述第二电平信号端电连接。
  15. 一种根据权利要求1-14所述的移位寄存器单元的驱动方法，其中，每一帧包括第一驱动时段至第N驱动时段，所述方法包括：
    在第n驱动时段期间，通过第n输入子电路、第n输出子电路和第n复位子电路驱动，其中，所述第n驱动时段包括第n输入时段、第n输出时段和第n复位时段，其中，
    在第n输入时段期间，通过所述第n输入子电路将所述上拉节点充电至第一有效电平；
    在第n输出时段期间，在所述上拉节点的电压的控制下，将第n时钟信号传送到第n输出信号端；以及
    在第n复位时段期间，在第n复位信号的控制下，通过第二电平信号将所述上拉节点复位至无效电平。
  16. 根据权利要求15所述的驱动方法，其中，每一帧还包括位于所述第一驱动时段至第N驱动时段之后的空白阶段，所述方法还包括：
    在所述随机输出使能信号的控制下，在所述第一输出时段至所述第N输出时段中的一个随机时段期间，使得来自补偿输入信号端的补偿输入信号将所述第二补偿驱动晶体管导通；
    在空白阶段期间，通过所述补偿时钟信号将所述上拉节点提升到有效电平，以使得第一时钟信号至第N时钟信号能够分别传送到所述第一输出信号端至所述第N输出信号端；以及
    根据所述随机输出使能信号，使第一时钟信号至第N时钟信号中的一个时钟信号在所述空白阶段的至少部分时段期间具有高电平，以使得所述第一输出信号端至所述第N输出信号端之一能够在所述空白阶段输出高电平信号。
  17. 一种栅极驱动电路，包括多个级联的移位寄存器单元组，每个移位寄存器单元组中包括K个级联的移位寄存器单元，其中，每个移位 寄存器单元是根据权利要求1-14中的任一项所述的移位寄存器单元，其中，K为大于或等于3的整数，其中，
    每级移位寄存器单元组中的K个级联的移位寄存器单元用于驱动相邻的N×K条栅线，其中，所述N×K条栅线包括按顺序排列的第一栅线组至第N栅线组，每个栅线组中包括K条按顺序排列的栅线，其中，每个移位寄存器单元组中的K个级联的移位寄存器单元中的第n输出信号端分别与第n栅线组中的K条栅线一一对应地电连接，
    除第一级移位寄存器单元组中的第一级移位寄存器单元的第一输入信号端之外，每个输入信号端与电连接到该输入信号端所对应的栅线的前一栅线的输出信号端电连接，
    第一级移位寄存器单元组中的第一级移位寄存器单元的第一输入信号端与帧起始信号端电连接。
  18. 根据权利要求17所述的栅极驱动电路，其中，所述栅极驱动电路中的每级移位寄存器单元组与第一时钟信号线至第N×K时钟信号线电连接以分别接收第一时钟信号至第N×K时钟信号，
    其中，第m时钟信号线与所述移位寄存器单元组驱动的所述N×K条栅线中的第m条栅线连接到相同的输出子电路，其中，m＝1、2、...、N×K。
  19. 根据权利要求17所述的栅极驱动电路，其中，
    除最后一级移位寄存器单元组中的最后一级移位寄存器单元的第N复位信号端之外，每个复位信号端与电连接到该复位信号端所对应的输出子电路驱动的栅线的后一栅线的输出信号端电连接，
    最后一级移位寄存器单元组中的最后一级移位寄存器单元的第N复位信号端与帧起始信号端电连接。
  20. 一种根据权利要求17-19中任一项所述的栅极驱动电路的驱动方法，包括：
    向所述第一级移位寄存器单元组中的第一极移位寄存器单元中的第一输入信号端提供帧起始信号；以及
    通过所述N×K个时钟信号线向各级移位寄存器单元组中的时钟信号端提供时钟信号，其中，通过所述N×K个时钟信号线中的第一时钟信 号线提供的时钟信号在第一个周期的第一沿比所述帧起始信号的第一沿滞后1/N×K个时钟周期。
  21. 根据权利要求20所述的驱动方法，其中，所述第一时钟信号至第N×K时钟信号的占空比为1/N×K，并且依次滞后1/N×K个时钟周期。
  22. 一种显示装置，包括根据权利要求17-19中的任一项所述的栅极驱动电路。
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