WO2019033818A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2019033818A1
WO2019033818A1 PCT/CN2018/088416 CN2018088416W WO2019033818A1 WO 2019033818 A1 WO2019033818 A1 WO 2019033818A1 CN 2018088416 W CN2018088416 W CN 2018088416W WO 2019033818 A1 WO2019033818 A1 WO 2019033818A1
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Prior art keywords
pull
circuit
node
transistor
potential
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PCT/CN2018/088416
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English (en)
French (fr)
Inventor
古宏刚
邵贤杰
姚利利
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/303,853 priority Critical patent/US11132927B2/en
Priority to EP18800024.4A priority patent/EP3671708B1/en
Priority to JP2018563671A priority patent/JP7159056B2/ja
Publication of WO2019033818A1 publication Critical patent/WO2019033818A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • a gate turn-on signal is generally supplied to the gates of respective thin film transistors (TFTs) of the pixel region through the gate driving circuit.
  • the gate driving circuit can be formed on the array substrate of the flat panel display panel by an array process, that is, a Gate Driver on Array (GOA) process, which not only saves cost but also can realize a flat panel display panel ( Panel) Symmetrical aesthetic design on both sides.
  • GOA Gate Driver on Array
  • the bonding area of the integrated circuit (IC) and the fan-out wiring space are omitted.
  • the gate driving circuit may be composed of a plurality of cascaded shift registers for providing gate turn-on signals to the gate lines connected to the signal output terminals of the stage shift registers to turn on the pixel areas of the corresponding rows. TFT.
  • the input signal terminals of the remaining stages of shift registers are respectively connected to the signal output ends of the shift register of the previous stage.
  • the control signal output terminal output gate signal node in each stage shift register is called a pull-up node.
  • a plurality of touch time periods are inserted during a time when one frame of the screen is displayed, and each touch time period is set to a time interval of a certain duration.
  • the touch-time period is entered after the output of the gate-on signal of the signal output terminal of the nth-stage shift register is completed, and the potential of the pull-up node in the n+1-th stage shift register has been pulled up to a high potential. Since the touch time interval is long, during this period, the pull-up node in the n+1th stage shift register experiences a leakage condition through the TFT connected thereto, thereby lowering the potential of the pull-up node. When the touch period is over, the n+1th shift register starts to work.
  • the gate turn-on signal output from the signal output of the shift register is attenuated, and may even be The TFT of the pixel area cannot be turned on, which causes an abnormality in the display of the touch display panel.
  • a shift register provided by the embodiment of the present disclosure includes: a first input circuit configured to input an input signal to the pull-up node; a pull-up node state holding circuit, the pull-up The first end of the node state maintaining circuit is connected to the third reference signal end, the second end of the pull-up node state maintaining circuit is connected to the fourth reference signal end, and the third end of the pull-up node state maintaining circuit is connected to The pull-up node, the pull-up node state maintaining circuit is configured to provide a third reference signal of the third reference signal end to the pull-up node when a potential of the pull-up node is a first potential The third reference signal is used to maintain the potential of the pull-up node as a first potential, and when the potential of the pull-up node is a second potential, the fourth reference signal of the fourth reference signal end is provided to the a pull-up node, wherein the fourth reference signal is used to maintain a potential of the pull-up node to a second potential; and an output circuit configured to be
  • the pull-up node state maintaining circuit includes a control sub-circuit, a first potential holding sub-circuit, and a second potential holding sub-circuit, wherein the first end of the control sub-circuit is connected to the third a reference signal end, a second end of the control sub-circuit is connected to the pull-up node, a third end of the control sub-circuit is connected to the fourth reference signal end, and a fourth end of the control sub-circuit is connected Up to a first end of the second potential holding subcircuit, the control subcircuit is configured to output a control signal to control conduction and deactivation of the second potential holding subcircuit under control of a potential of the pull up node a first end of the first potential holding sub-circuit is connected to the third reference signal end, a second end of the first potential holding sub-circuit is connected to the pull-up node and the second potential holding sub-circuit
  • the first potential holding sub-circuit is configured to input the third reference signal to the pull-up node when
  • control sub-circuit includes a first control transistor and a second control transistor, wherein a gate of the first control transistor is coupled to the pull-up node, and a first of the first control transistor a pole connected to the fourth reference signal terminal, a second pole of the first control transistor being connected to the second potential holding sub-circuit and a second pole of the second control transistor; the second control transistor A gate is coupled to the first pole of the second control transistor and to the third reference signal terminal.
  • the first potential holding subcircuit includes a first potential holding transistor, a gate of the first potential holding transistor and a first pole of the first potential holding transistor are connected to and connected to the first And a third reference signal terminal, the second pole of the first potential holding transistor is connected to the pull-up node.
  • the second potential holding subcircuit includes a second potential holding transistor, a gate of the second potential holding transistor is coupled to a second pole of the first control transistor, and the second potential is maintained A first pole of the transistor is coupled to the fourth reference signal terminal, and a second pole of the second potential holding transistor is coupled to the pull-up node.
  • a channel width to length ratio of the first control transistor is greater than a channel width to length ratio of the second control transistor.
  • a channel width to length ratio of the second potential holding transistor is greater than a channel width to length ratio of the first potential holding transistor.
  • the first input circuit includes a first input transistor, wherein a gate of the first input transistor is coupled to an input signal terminal, a first pole of the first input transistor and a first reference signal Connected to the terminals, the second pole of the first input transistor is connected to the pull-up node.
  • the shift register further includes: a second input circuit, a first end of the second input circuit is coupled to the reset signal terminal, and a second end of the second input circuit is coupled to the second reference a signal end, a third end of the second input circuit is connected to the pull-up node, wherein the second input circuit is configured to be at a second reference signal end under the control of a reset signal of the reset signal end A signal is provided to the pull up node.
  • the second input circuit includes a second input transistor, wherein a gate of the second input transistor is coupled to the reset signal terminal, a first pole of the second input transistor and the The second reference signal terminal is connected, and the second pole of the second input transistor is connected to the pull-up node.
  • the shift register further includes: a pull-down control circuit, a first end of the pull-down control circuit is connected to the pull-up node, and a second end of the pull-down control circuit is connected to the third a third end of the pull-down control circuit connected to the fourth reference signal terminal and a fourth end of the pull-down control circuit connected to a pull-down node of the shift register, wherein the pull-down control circuit Configuring to provide a signal of the fourth reference signal end to the pull-down node when the pull-up node is the first potential, and when the pull-up node is the second potential, A signal of the three reference signal terminals is supplied to the pull-down node.
  • the pull-down control circuit includes: a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor; wherein a gate of the first pull-down control transistor a pole connected to the pull-up node, a first pole of the first pull-down control transistor is connected to the fourth reference signal end, and a second pole of the first pull-down control transistor is connected to the pull-down node; a gate of the second pull-down control transistor is connected to the pull-up node, a first pole of the second pull-down control transistor is connected to the fourth reference signal terminal, and a second pole of the second pull-down control transistor Connected to a second pole of the third pull-down control transistor and a gate of the fourth pull-down control transistor, respectively; a gate of the third pull-down control transistor and a second pole of the fourth pull-down control transistor, respectively a second pole of the second pull-down control transistor is connected, a first pole of the third pull-down control transistor,
  • the shift register further includes: a pull-down circuit, a first end of the pull-down circuit is connected to the pull-down node, and a second end of the pull-down circuit is connected to the pull-up node, a third end of the pull-down circuit is connected to the gate signal output end, and a fourth end of the pull-down circuit is connected to the fourth reference signal end, wherein the pull-down circuit is configured to be at a potential of the pull-down node The signal of the fourth reference signal end is supplied to the pull-up node and the gate signal output terminal under control.
  • the pull-down circuit includes: a first pull-down transistor and a second pull-down transistor; wherein a gate of the first pull-down transistor is connected to the pull-down node, the first pull-down transistor a first pole is connected to the fourth reference signal end, a second pole of the first pull-down transistor is connected to the gate signal output end; a gate of the second pull-down transistor is connected to the pull-down node, The first pole of the second pull-down transistor is connected to the fourth reference signal terminal, and the second pole of the second pull-down transistor is connected to the pull-up node.
  • the output circuit includes: an output transistor and a first capacitor; wherein a gate of the output transistor is connected to the pull-up node, and a first pole of the output transistor and a first clock signal end Connected, a second pole of the output transistor is coupled to the gate signal output; and a first end of the first capacitor is coupled to the pull-up node, and a second end of the first capacitor is coupled to the gate Polar signal output.
  • the shift register further includes: a noise canceling circuit, wherein a first end of the noise canceling circuit is connected to the gate signal output end, and a second end of the noise emitting circuit is connected to the a third end of the noise canceling circuit is connected to the fourth reference signal end, and a fourth end of the noise emitting circuit is connected to the noise canceling signal end; the noise emitting circuit is disposed at the noise emitting signal end The signal of the fourth reference signal end is supplied to the gate signal output terminal and the pull-up node under the control of the noise cancellation signal.
  • an embodiment of the present disclosure further provides a gate driving circuit, including a plurality of shift registers provided by the embodiments of the present disclosure.
  • an embodiment of the present disclosure further provides a display device, including the embodiment of the present disclosure, providing any of the above gate driving circuits.
  • an embodiment of the present disclosure further provides a driving method for a shift register as described above, comprising: receiving an input signal, and pulling up the pull-up node to conduct power according to the input signal Using the pull-up node potential holding circuit to maintain the potential of the pull-up node to an on-level; receiving a first clock signal, and based on the first clock signal, at a potential of the pull-up node A gate turn-on signal is output at the output terminal under control.
  • the driving method further includes: receiving a reset signal, pulling the pull-up node to an off level according to the reset signal; using the pull-up node potential holding circuit to pull the pull-up node The potential remains at the cutoff level.
  • the pull-up node state holding circuit provided by the present disclosure is used to maintain the potential of the pull-up node, and the potential of the pull-up node can be kept from decaying with time, thereby ensuring the shift register. Stable output.
  • FIG. 1 is a schematic block diagram of a shift register provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of a shift register provided by an embodiment of the present disclosure
  • FIG. 3 shows a schematic circuit configuration diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic block diagram of another shift register in accordance with an embodiment of the present disclosure
  • FIG. 5 shows a circuit configuration diagram of another shift register provided in accordance with the present disclosure
  • FIG. 6 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of another gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 illustrates a flowchart of a driving method of a shift register according to an embodiment of the present disclosure
  • FIG. 9 illustrates an exemplary timing diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 10 illustrates another exemplary timing diagram of a shift register in accordance with an embodiment of the present disclosure
  • Figure 11 shows a timing diagram of a shift register in accordance with the prior art.
  • FIG. 1 shows a schematic block diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register 100 includes a first input circuit 1, a pull-up node state holding circuit 3, and an output circuit 6.
  • the first end of the first input circuit 1 is connected to the input signal terminal Input
  • the second end of the first input circuit 1 is connected to the first reference signal terminal Vref1
  • the third end of the first input circuit 1 is connected.
  • the first input circuit 1 is configured to provide the first reference signal of the first reference signal terminal Vref1 to the pull-up node PU under the control of the input signal of the input signal terminal Input.
  • FIG. 1 shows only one possible embodiment of the first input circuit 1.
  • the first input circuit 1 can be configured in other forms.
  • the first end and the second end of the first input circuit 1 are both connected to the input signal terminal Input, and the input signal of the input signal terminal Input is controlled to be pulled down. Pull up the potential of the node PU.
  • the first input circuit 1 is configured to provide an input signal of the input signal terminal Input to the pull-up node PU under the control of the first reference signal of the first reference signal terminal Vref1.
  • the first end of the pull-up node state holding circuit 3 is connected to the third reference signal terminal Vref3, the second end of the pull-up node state holding circuit 3 is connected to the fourth reference signal terminal Vref4 and the third of the pull-up node state holding circuit 3
  • the terminal is connected to the pull-up node PU of the shift register 100.
  • the pull-up node state maintaining circuit 3 is configured to provide a signal of the third reference signal terminal Vref3 to the pull-up node PU when the potential of the pull-up node PU is the first potential, and the potential of the pull-up node PU is the second At the potential, the signal of the fourth reference signal terminal Vref4 is supplied to the pull-up node PU.
  • the potential of the first reference signal terminal Vref1 and the third reference signal terminal Vref3 is the first potential
  • the potential of the fourth reference signal terminal Vref4 is the second potential
  • the first end of the output circuit 6 is connected to the pull-up node PU, the second end of the output circuit 6 is connected to the first clock signal terminal CLK, and the third end of the output circuit 6 is connected to the gate signal output terminal of the shift register 100. .
  • the output circuit 6 is configured to supply the first clock signal of the first clock signal terminal CLK to the gate signal output terminal Output under the control of the potential of the pull-up node PU.
  • the pull-up node state holding circuit controls the potential of the pull-up node, so that the potential of the pull-up node can be kept from decaying with time. , to ensure the stable output of the shift register.
  • first potential and the second potential in the above embodiments of the present disclosure refer to a high potential or a low potential, instead of a specific voltage value, and the specific voltage value is not limited herein, as long as it can Ensure that the transistor is turned on or off.
  • the first potential is the on-potential of the transistor used in the shift register 100
  • the second potential may be the turn-off potential of the transistor used in the shift register 100.
  • the node bit holding sub-circuit can maintain the potential of the pull-up node, that is, when the pull-up node is turned off (eg, low potential), Pulling the node to a low potential, when the pull-up node is turned on (such as high potential), keep the pull-up node high, so that the potential of the pull-up node can be kept from attenuating, so the above shift register can be applied to the touch In cell touch screen H-Blank mode (ie insert the touch time period in the display time period).
  • the above shift register provided by the embodiment of the present disclosure is also applicable to the V-Blank mode of the touch in cell touch screen (ie, inserting the touch time period between two frame display periods), in this case, in the previous frame.
  • the output remains at the final stage of the potential until the end of the next frame, and does not affect the signal of the next frame.
  • shift register provided by the embodiment of the present disclosure is also applicable to the conventional gate driving mode (ie, only the display period, no touch period), which is not specifically limited herein.
  • FIG. 2 shows a schematic block diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register 200 may include a first input circuit 1, a pull-up node state holding circuit 3, and an output circuit 6.
  • the first input circuit 1 and the output circuit 6 are the same as the first input circuit 1 and the output circuit 6 shown in FIG. 1, and are not described herein again.
  • the pull-up node state holding circuit 3 may further include a control sub-circuit 31, a first potential holding sub-circuit 32, and a second potential holding sub-circuit 33.
  • the first end of the control sub-circuit 31 is connected to the third reference signal terminal Vref3, the second end of the control sub-circuit 31 is connected to the pull-up node PU, and the third end of the control sub-circuit 31 is connected to the fourth reference signal terminal Vref4.
  • the fourth end of the control sub-circuit 31 is connected to the first end of the second potential holding sub-circuit 33.
  • the control sub-circuit 31 is configured to output a control signal and control the on and off of the second potential holding sub-circuit 33 under the control of the potential of the pull-up node PU.
  • the first end of the first potential holding sub-circuit 32 is connected to the third reference signal terminal Vref3, and the second end of the first potential holding sub-circuit 32 is connected to the pull-up node PU and the second potential holding sub-circuit 33.
  • the first potential holding sub-circuit 32 is configured to input a third reference signal to the pull-up node PU in accordance with the control signal. For example, when the second potential holding sub-circuit 33 is turned off under the control of the control signal output from the control sub-circuit 31, the first potential holding sub-circuit 32 is configured to input the third reference signal to the pull-up node PU.
  • the first end of the second potential holding sub-circuit 33 is connected to the control sub-circuit 31, the second end of the second potential holding sub-circuit 33 is connected to the pull-up node PU, and the third end of the second potential holding sub-circuit 33 is connected to the Four reference signal terminals Vref4.
  • the second potential holding sub-circuit 33 is configured to input a fourth reference signal to the pull-up node PU according to the control signal. For example, when the second potential holding sub-circuit 33 is turned on under the control of the control signal output from the control sub-circuit 31, the fourth reference signal is input to the pull-up node PU through the second potential holding sub-circuit 33.
  • FIG. 3 shows a schematic circuit configuration diagram of a shift register according to an embodiment of the present disclosure.
  • the principle of the present disclosure is described below by taking an example in which all transistors are N-type transistors. However, those skilled in the art can understand that it is also possible to use a P-type transistor for one or more transistors in the shift register, as long as the position of the source and the drain and the corresponding gate access level are adjusted accordingly.
  • all of the transistors used in the embodiments of the present application are N-type transistors, the first potential being a high level and the second potential being a low level. If the N-type transistor is replaced with a P-type transistor, the first potential is a low level and the second potential is a high level.
  • the details are not described herein, but should also be within the scope of the invention.
  • the first input circuit 1 may include a first input transistor M1.
  • the gate of the first input transistor M1 is connected to the input signal terminal Input, the first pole of the first input transistor M1 is connected to the first reference signal terminal Vref1, and the second pole of the first input transistor M1 is connected to the pull-up node PU.
  • the first input transistor M1 When the input signal terminal Input inputs a high level input signal, the first input transistor M1 can be turned on under the control of the input signal, and the signal of the first reference signal terminal is input to the pull-up node PU.
  • the signal at the first reference signal terminal may be a high level on signal.
  • the above is only a specific structure of the first input circuit 1 in the shift register.
  • the specific structure of the first input circuit 1 is not limited to the above structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art. This is not limited.
  • the gate and the first pole of the first input transistor M1 can be connected to the input signal terminal Input.
  • the gate of the first input transistor M1 may be connected to the first reference signal terminal Vref1, and the first input signal terminal Input of the first input transistor M1 may be connected.
  • the control sub-circuit 31 may include a first control transistor M12 and a second control transistor M13.
  • the gate of the first control transistor M12 may be connected to the pull-up node PU
  • the first pole of the first control transistor M12 may be connected to the fourth reference signal terminal Vref4
  • the second pole of the first control transistor M12 may be connected to the first The second potential holding sub-circuit 33 and the second pole of the second control transistor M12.
  • the gate of the second control transistor M13 may be connected to the first electrode of the second control transistor M13 and connected to the third reference signal terminal Vref3.
  • the first potential holding subcircuit 32 includes a first potential holding transistor M14.
  • the gate of the first potential holding transistor M14 is connected to the first electrode of the first potential holding transistor M14 and is connected to the third reference signal terminal Vref3, and the second pole of the first potential holding transistor M14 is connected to the pull-up node PU.
  • the second potential holding sub-circuit 33 may include a second potential holding transistor M11.
  • the gate of the second potential holding transistor M11 may be connected to the second pole of the first control transistor M12, the first pole of the second potential holding transistor M11 may be connected to the fourth reference signal terminal Vref4, and the second potential holding transistor M11 The two poles can be connected to the pull-up node PU.
  • control sub-circuit 31 the first potential holding sub-circuit 32, and the second potential holding sub-circuit 33 in the shift register.
  • the specific structure of the control sub-circuit 31, the first potential holding sub-circuit 32, and the second potential holding sub-circuit 33 is not limited to the above-described structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art, and is not used here. limited.
  • the first control transistor M12 when the pull-up node PU is at an on potential (eg, a high potential), the first control transistor M12 is turned on under the control of the potential of the pull-up node PU. Since the potential of the third reference signal terminal is high, the second control transistor M13 is also turned on under the control of the third reference signal.
  • the channel width to length ratio of the first control transistor M12 can be made larger than the channel width to length ratio of the second control transistor M13 by setting the channel width to length ratio of the first control transistor M12 and the second control transistor M13.
  • the fourth reference signal of the fourth reference signal terminal Vref4 is output to the second potential holding sub-circuit 33 through the first control transistor M12 as a control signal.
  • the potential of the fourth reference signal is an off potential (such as a low potential). Therefore, the second potential holding transistor M11 is turned off under the control of the fourth reference signal.
  • the gate of the first potential holding transistor M14 is connected to the third reference signal terminal Vref3, the first potential holding transistor M14 is turned on under the control of the third reference signal, and the third reference signal terminal is input to the third.
  • the reference signal is supplied to the pull-up node PU, so that the potential of the pull-up node PU is kept at a high potential.
  • the first control transistor M12 When the potential of the pull-up node PU is low, the first control transistor M12 is turned off under the control of the potential of the pull-up node PU. Since the potential of the third reference signal terminal Vref3 is at a high potential, the second control transistor M13 is turned on under the control of the third reference signal, and outputs the third reference signal as a control signal to the second potential holding sub-circuit 33. Under the control of the third reference signal, the second potential holding transistor M11 is turned on, and the channel of the second potential holding transistor M11 can be made by setting the channel width-to-length ratio of the second potential holding transistor M11 and the first potential holding transistor M14.
  • the aspect ratio is greater than the channel width to length ratio of the first potential holding transistor M14 such that when both the first potential holding transistor M14 and the second potential holding transistor M11 are turned on, the fourth reference signal is passed through the second potential holding transistor M11 Input to the pull-up node PU and discharge the pull-up node, thereby keeping the potential of the pull-up node at a low potential.
  • the output circuit 6 can include an output transistor M3 and a first capacitor C1.
  • the gate of the output transistor M3 may be connected to the pull-up node PU
  • the first pole of the output transistor M3 may be connected to the first clock signal terminal CLK
  • the second pole of the output transistor M3 may be coupled to the gate signal of the shift register 100.
  • the output is connected to the output.
  • the first end of the first capacitor C1 may be connected to the pull-up node PU
  • the second end of the first capacitor C2 may be connected to the gate signal output terminal Output of the shift register 100.
  • the output transistor M3 When the first clock signal terminal CLK inputs the first clock signal of the high level, since the output transistor M3 is turned on under the control of the potential of the pull-up node PU, the output transistor M3 can set the first clock signal of the high level. Input to the gate signal output terminal Output, and output a gate turn-on signal at the gate signal output terminal Output. At this time, due to the presence of the first capacitor C1, the pull-up node PU is further pulled up by the bootstrap action.
  • the above is merely an example of a specific structure of the output circuit 6 in the shift register.
  • the specific structure of the output circuit is not limited to the above-described structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art, which are not limited herein.
  • FIG. 4 shows a schematic block diagram of another shift register in accordance with an embodiment of the present disclosure.
  • the shift register 200 may include a first input circuit 1, a second input circuit 2, a pull-up node state holding circuit 3, a pull-down control circuit 4, a pull-down circuit 5, an output circuit 6, and a noise canceling circuit 7.
  • the first input circuit 1, the pull-up node state maintaining circuit 3 and the output circuit 6 shown in FIG. 4 can adopt the first input circuit 1, the pull-up node state maintaining circuit 3 and the output circuit described in FIG. 6, will not repeat them later.
  • the first end of the second input circuit 2 in the shift register 200 is connected to the reset signal terminal Reset, the second end of the second input circuit 2 is connected to the second reference signal terminal Vref2, and the second input circuit The third end of 2 is connected to the pull-up node PU.
  • the second input circuit 2 can be configured to provide the second reference signal of the second reference signal terminal Vref2 to the pull-up node PU under the control of the reset signal of the reset signal terminal Reset.
  • the signal potential input by the second reference signal terminal Vref2 is opposite to the potential of the signal input by the first reference signal terminal Vref1.
  • the second reference signal terminal Vref2 When the first reference signal terminal Vref1 inputs a signal of a high potential, the second reference signal terminal Vref2 inputs a signal of a low potential. When the first reference signal terminal Vref1 inputs a signal of a low potential, the second reference signal terminal Vref2 inputs a signal of a high potential.
  • the above is only an example of the specific structure of the second input circuit in the shift register.
  • the specific structure of the second input circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art, which is not limited herein.
  • the shift register since the first input circuit and the second input circuit are symmetrically designed, the shift register can also implement the function of bidirectional scanning.
  • the first end of the pull-down control circuit 4 in the shift register 200 can be connected to the pull-up node PU, the second end of the pull-down control circuit 4 is connected to the third reference signal terminal VRef3, and the third end of the pull-down control circuit 4 is connected to the The fourth reference signal terminal Vref4 and the fourth terminal of the pull-down control circuit 4 are connected to the pull-down node PD of the shift register 200.
  • the pull-down control circuit 4 is configured to provide a signal of the fourth reference signal terminal Vref4 to the pull-down node PD when the pull-up node PU is at the first potential.
  • the signal of the third reference signal terminal Vref3 is supplied to the pull-down node PD.
  • first potential and the second potential in the above embodiments of the present disclosure refer to a high potential or a low potential, instead of a specific voltage value, and the specific voltage value is not limited herein, as long as it can Ensure that the transistor is turned on or off.
  • the first potential is the on-potential of the transistor used in the shift register 200
  • the second potential may be the turn-off potential of the transistor used in the shift register 200.
  • the first end of the pull-down circuit 5 in the shift register 200 is connected to the pull-down node PD, the second end of the pull-down circuit 5 is connected to the pull-up node PU, and the third end of the pull-down circuit 5 is connected to the gate signal of the shift register 200.
  • the output terminal Output, the fourth end of the pull-down circuit 5 is connected to the fourth reference signal terminal Vref4.
  • the pull-down circuit 5 is configured to provide a signal of the fourth reference signal terminal Vref4 to the pull-up node PU and the gate signal output terminal Output under the control of the potential of the pull-down node PD.
  • the first end of the noise absorbing circuit 7 in the shift register 200 can be connected to the gate signal output terminal Output, the second end of the noise absorbing circuit 7 can be connected to the pull-up node PU, and the third end of the noise absorbing circuit 7 can be connected to the fourth terminal.
  • the fourth end of the noise canceling circuit 7 can be connected to the noise emitting signal terminal S1.
  • the noise canceling circuit 7 can be configured to provide the signal of the fourth reference signal terminal Vref4 to the gate signal output terminal Output and the pull-up node PU under the control of the noise canceling signal of the noise canceling signal terminal S1.
  • the noise cancellation circuit 7 can include a first noise emission sub-circuit 7-1 and a second noise emission sub-circuit 7-2.
  • the first end of the first noise canceling sub-circuit 7-1 can be connected to the gate signal output terminal Output, and the second end of the first noise-cancelling sub-circuit 7-1 can be connected to the noise-cancelling signal terminal S1, the first noise-cancelling device
  • the third end of the circuit 7-1 can be connected to the fourth reference signal terminal Vref4.
  • the first noise canceling sub-circuit 7-1 can be configured to provide the signal of the fourth reference signal terminal Vref4 to the gate signal output terminal Output under the control of the noise-cancelling signal of the noise-cancelling signal terminal S1.
  • the first end of the second noise canceling sub-circuit 7-2 may be connected to the pull-up node PU, and the second end of the second noise-canzing sub-circuit 7-2 may be connected to the noise-cancelling signal terminal S1, and the second noise-cancelling sub-circuit 7
  • the third end of -2 may be connected to the fourth reference signal terminal Vref4.
  • the second noise-cancelling sub-circuit 7-2 is configured to provide the signal of the fourth reference signal terminal Vref4 to the pull-up node PU under the control of the noise-cancelling signal of the noise-cancelling signal terminal S1.
  • FIG. 5 shows a circuit configuration diagram of another shift register provided in accordance with the present disclosure.
  • the shift register 200 may include a first input circuit 1, a second input circuit 2, a pull-up node state holding circuit 3, a pull-down control circuit 4, a pull-down circuit 5, an output circuit 6, and a noise canceling circuit 7.
  • the first input circuit 1, the pull-up node state maintaining circuit 3 and the output circuit 6 shown in FIG. 4 can adopt the first input circuit 1, the pull-up node state maintaining circuit 3 and the output circuit described in FIG. 6, will not repeat them later.
  • the second input circuit 2 can include a second input transistor M2.
  • the gate of the second input transistor M2 may be connected to the reset signal terminal Reset
  • the first pole of the second input transistor M2 may be connected to the second reference signal terminal Vref2
  • the second pole of the second input transistor M2 may be pulled up.
  • the node PU is connected.
  • the pull-down control circuit 4 may include a first pull-down control transistor M6, a second pull-down control transistor M7, a third pull-down control transistor M8, and a fourth pull-down control transistor M9.
  • the gate of the first pull-down control transistor M6 may be connected to the pull-up node PU, and the first pole of the first pull-down control transistor M6 may be connected to the fourth reference signal terminal Vref4, and the first pull-down control transistor M6 The two poles can be connected to the pulldown node PD.
  • the second pull-down control transistor M7 can be connected to the fourth pull-down control terminal Mref
  • the fourth pull-down controls the second pole of the transistor M9 and the gate of the third pull-down control transistor M8.
  • the gate of the third pull-down control transistor M8 may be respectively connected to the second pole of the fourth pull-down control transistor M9 and the second pole of the second pull-down control transistor M7, and the first pole of the third pull-down control transistor M8 may be connected to the third reference
  • the signal terminal Vref3 is connected, and the second pole of the third pull-down control transistor M8 can be connected to the pull-down node PD.
  • the gate of the fourth pull-down control transistor M9 may be connected to the first pole of the fourth pull-down control transistor M9 and connected to the third reference signal terminal Vref3, and the second pole of the fourth pull-down control transistor M9 may be connected to the third pull-down control transistor M8.
  • the gate is connected to the second pole of the second pull-down control transistor M7.
  • the above is merely an example of a specific structure of the pull-down control circuit 4 in the shift register.
  • the specific structure of the pull-down control circuit 4 is not limited to the above-described structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art, which are not limited herein.
  • the pull-down circuit 5 can include a first pull-down transistor M4 and a second pull-down transistor M10.
  • the gate of the first pull-down transistor M4 may be connected to the pull-down node PD
  • the first pole of the first pull-down transistor M4 may be connected to the fourth reference signal terminal Vref4
  • the second pole of the first pull-down transistor M4 may be associated with the signal The gate number output is connected.
  • the gate of the second pull-down transistor M10 may be connected to the pull-down node PD, the first pole of the second pull-down transistor M10 may be connected to the fourth reference signal terminal Vref4, and the second pole of the second pull-down transistor M10 may be connected to the pull-up node PU .
  • the above is merely an example of a specific structure of the pull-down circuit 5 in the shift register.
  • the specific structure of the pull-down circuit 5 is not limited to the above-described structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art, which are not limited herein.
  • the output noise cancellation circuit 7 can include a first noise emission transistor M5.
  • the gate of the first noise canceling transistor M5 may be connected to the noise emitting signal terminal S1, and the first pole of the first noise emitting transistor M5 may be connected to the fourth reference signal terminal Vref4, and the second pole of the first noise emitting transistor M5. It can be connected to the gate signal output terminal Output.
  • the output noise canceling circuit 7 may further include a second noise emitting transistor M15.
  • the gate of the second noise absorbing transistor M15 may be connected to the noise emitting signal terminal S1
  • the first pole of the second noise absorbing transistor M15 may be connected to the fourth reference signal terminal Vref4, and the second pole of the second noise absorbing transistor M15.
  • the above is merely an example of a specific structure of the output noise canceling circuit 7 in the shift register.
  • the specific structure of the output noise-removing circuit 7 is not limited to the above-described structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art, which are not limited herein.
  • the noise-cancelling signal end of the first-stage shift register is connected to a separate signal terminal, that is, the first-stage shift register.
  • the noise-cancelling signal end is connected to the Dummy signal end, and the noise-cancelling signal end of the other-stage shift register except the first stage can be connected to the frame start signal end, so that the frame is received in the first-stage shift register.
  • other stage shift registers other than the first stage shift register also receive the frame start signal, by which the other stage shift registers other than the first stage shift register are placed. noise.
  • the transistors in order to simplify the fabrication process, the transistors generally use transistors of the same material, and therefore, all transistors are N-type transistors or both are P-type transistors. In some embodiments, all transistors are N-type transistors when the potential of the desired gate-on signal is high. When the potential of the required gate-on signal is low, all transistors are P-type transistors.
  • the N-type transistor is turned on under a high potential and turned off at a low potential.
  • the P-type transistor is turned off under a high potential and turned on under a low potential.
  • the transistors mentioned in the above embodiments of the present disclosure are all metal oxide semiconductor field effect transistors (MOS, MetPUl Oxide SPDmiPDonduPDtor).
  • MOS metal oxide semiconductor field effect transistors
  • the first extreme source, the second extreme drain, or the first extreme drain, and the second extreme source of these transistors are not specifically distinguished herein.
  • the first input circuit 1 and the second input circuit 2 are symmetrically designed, and functional interchange can be implemented. Therefore, the above-described shift register 200 provided by the embodiment of the present disclosure is provided. Two-way scanning is possible. In the forward scanning, the input signal terminal Input receives the input signal, the reset signal terminal Reset receives the reset signal, the first input circuit 1 functions as an input, and the second input circuit 2 functions as a reset. In the reverse scan, the input signal terminal Input receives the reset signal, the reset signal terminal Reset receives the input signal, and the second input circuit 2 functions as an input, and the first input circuit 1 functions as a reset.
  • the third reference signal terminal is at a high potential, and the potentials of the second reference signal terminal and the third reference signal terminal are both low.
  • the potentials of the second reference signal terminal and the third reference signal terminal are at a high potential, and the potentials of the first reference signal terminal and the third reference signal terminal are both low.
  • FIG. 6 is a schematic diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit 600 includes a plurality of the above-described shift registers provided by a plurality of cascaded embodiments of the present disclosure: SR(1), SR(2)...SR(n)...SR(N- 1), SR (N) (a total of N shift registers, 1 ⁇ n ⁇ N).
  • each of the shift registers SR(n) are respectively reset signals of the upper stage shift register SR(n-1) adjacent thereto.
  • the end Reset is connected.
  • each stage shift register SR(n) is respectively input signals of the next stage shift register SR(n+1) adjacent thereto.
  • the terminal Input is connected.
  • the input signal terminal Input of the first stage shift register SR(1) is coupled to the frame start signal terminal STV.
  • the first reference signal terminals Vref1 of all the shift registers are connected to the first reference signal line V1, and the second reference signal terminals of all the shift registers are connected.
  • Vref2 is connected to the first reference signal line V2
  • the third reference signal terminals Vref3 of all the shift registers are connected to the third reference signal line V3
  • the fourth reference signal terminals Vref4 of all the shift registers are connected with the fourth reference signal line.
  • V4 is connected.
  • the first clock signal terminals CLK of all odd-numbered shift registers are connected to the first clock signal line C1
  • the second clock signal terminals CLKB of all odd-numbered shift registers are connected to the second clock signal line C2.
  • the first clock signal terminals CLK of all the even-numbered shift registers are connected to the second clock signal line C2 and the second clock signal terminals CLKB of all the even-numbered shift registers are connected to the first clock signal line C1, and The clock signal on one clock signal line C1 is opposite in phase to the clock signal on the second signal line C2.
  • FIG. 7 is a schematic diagram of another gate driving circuit provided by an embodiment of the present disclosure.
  • the shift register in the gate driving circuit has a noise canceling circuit, in addition to the first stage shift register SR(1), the other stages SR(2) to SR(n) are placed.
  • the noise signal terminal S1 is connected to the frame start signal terminal STV, and the noise-cancelling signal terminal S1 of the first-stage shift register SR(1) is connected to the separately set signal terminal, that is, to the Dummy signal terminal.
  • the frame start signal is also received, by which the other stage shift registers SR(2) to SR(n) except the first stage shift register SR(1) are noised.
  • At least one embodiment of the present disclosure also provides a display device including the above-described gate driving circuit, by which a scanning signal is supplied to each gate line on an array substrate in a display device.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display device reference may be made to the embodiment of the above-described gate driving circuit, and the repeated description is omitted.
  • the pull-up node state holding circuit since the pull-up node state holding circuit is provided, the pull-up node state holding circuit performs the potential of the pull-up node during the touch time period. It continues, so that the potential of the pull-up node can be kept from decaying with time, ensuring a stable output of the shift register.
  • FIG. 8 shows a flow chart of a method of driving a shift register according to an embodiment of the present disclosure. As shown in FIG. 8, the driving method 800 can include the following steps:
  • Step S801 receiving an input signal, and pulling up the pull-up node PU to an on level according to the input signal.
  • step S802 the potential of the pull-up node PU is maintained at an on level by the pull-up node potential holding circuit.
  • Step S803 receiving the first clock signal, and outputting a gate-on signal at the output terminal Output under the control of the potential of the pull-up node PU based on the first clock signal.
  • Step S804 receiving a reset signal, and pulling the pull-up node PU to a cut-off level according to the reset signal.
  • step S805 the potential of the pull-up node PU is maintained at the off level by the pull-up node potential holding circuit.
  • the on-potential of the transistor is indicated by 1, such as a high potential signal, and 0 represents the turn-off potential of the transistor, such as a low potential signal.
  • FIG. 9 shows an exemplary timing diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the driving timing shown in FIG. 9 can be applied to any of the shift registers as described above.
  • the transistors in the shift register shown in FIG. 5 are all N-type transistors, the first reference signal terminal Vref1 and the third reference signal terminal Vref3 are both high potential, and the second reference Both the signal terminal Vref2 and the fourth reference signal terminal Vref4 are low.
  • the signal level high level signal of the input signal terminal Input that is, the output signal of the previous stage, turns on the first input transistor M1, and the first reference signal sent by the first reference signal terminal Vref1 is firstly passed through the first input transistor M1.
  • Capacitor C1 is charged to pull the potential of pull-up node PU high.
  • the first pull-down control transistor M6 and the second pull-down control transistor M7 are turned on, and the second pull-down control transistor M7 is turned on to provide the fourth reference signal of the fourth reference signal terminal Vref4 to the upper a third pull-down control transistor M8 and a second pull-down control transistor M9, the first pull-down control transistor M6 is turned on to provide a fourth reference signal of the fourth reference signal terminal Vref4 to the pull-down node PD, which will be pulled down The potential of the node PD is pulled low, so that the first pull-down transistor M4 and the second pull-down transistor M10 are turned off to ensure the stability of the signal outputted by the signal output terminal Output.
  • the potential of the pull-up node PU is high, the first control transistor M12 is turned on, and since the potential of the third reference signal terminal Vref3 is high, the second control transistor M13 and the first potential holding transistor M14 are both turned on, wherein The channel width-to-length ratio of the first control transistor M12 is greater than the channel width-to-length ratio of the second control transistor M13, and the source of the first control transistor M12 is connected to the fourth reference signal terminal Vref4, wherein the fourth reference signal terminal Vref4 is Low potential, so the second potential holding transistor M11 is turned off, since the first potential holding transistor M14 is turned on, the third reference signal from the third reference signal terminal Vref3 is continuously supplied to the pull-up node PU, thus maintaining the pull-up node PU The potential is always at a high potential, causing the pull-up node PU to form a memory high level.
  • the signal signal low level signal of the input signal terminal makes the first input transistor M1 be turned off, the pull-up node PU continues to maintain the high level of the previous stage, and the output transistor M3 remains turned on, at which time the first clock signal terminal CLK is issued.
  • the first clock signal is a high level signal, and the potential of the pull-up node PU is raised due to the bootstrap effect of the first capacitor C1, and the first clock signal is outputted to the signal output terminal Output, and the potential of the pull-up node PU is high.
  • first pull-down control transistor M6 and the second pull-down control transistor M7 are still in an on state, so that the first pull-down transistor M4 and the second pull-down transistor M10 remain in an off state, thereby ensuring the stability of the output signal of the signal output terminal Output. .
  • the signal of the reset signal terminal Reset is a high level signal, that is, the output signal of the next stage, so that the second input transistor M2 is turned on, and the second reference signal sent by the second reference signal terminal Vref2 is passed through the second input that is turned on.
  • the transistor M2 is supplied to the pull-up node PU such that the output transistor M3, the first pull-down transistor M4 and the second pull-down control transistor M7 are in an off state, and the third pull-down control transistor M8 is at a high potential due to the third reference signal terminal Vref3.
  • the fourth pull-down control transistor M9 is turned on, so that the pull-down node PD is at a high potential, so the first pull-down transistor M4 and the second pull-down transistor M10 are turned on, and the signal of the fourth reference signal terminal Vref4 is supplied to the pull-up node PU and the signal The output terminal Output, wherein the signal of the fourth reference signal terminal Vref4 is a low level signal.
  • the second control transistor M13 and the first potential holding transistor M14 are both turned on, wherein the second potential
  • the channel width-to-length ratio of the holding transistor M11 is larger than the channel width-to-length ratio of the first potential holding transistor M14. Therefore, the second potential holding transistor M11 supplies the signal of the fourth reference signal terminal Vref4 to the pull-up node PU, and pulls up The node PU discharges, so that the potential of the pull-up node PU is kept at a low level, so that the pull-up node PU forms a memory low level.
  • the phase is the no-output phase
  • the first input transistor M1 is always in the off state
  • the third pull-down control transistor M8 and the fourth pull-down control transistor M9 are turned on, so that the pull-down node PD Maintaining a high potential
  • the first pull-down transistor M4 and the second pull-down transistor M10 are turned on, and the noise of the pull-up node PU is continuously cancelled, so that the noise voltage generated by the first clock signal terminal CLK is eliminated, thereby achieving low voltage output and ensuring The output of the signal output is stable.
  • the shift register is repeatedly in the T4 phase, and the shift register is continuously noise-cancelled.
  • the noise-cancelling signal terminal S1 is at a high level, the first noise-cancelling transistor M5 is turned on, and the signal output terminal Output is noise-cancelled.
  • the first embodiment described above is suitable for the conventional GOA mode. Of course, it is also suitable for the V-Blank mode of the Touch in cell. The specific application is not limited here.
  • FIG. 10 illustrates another exemplary timing diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the transistors in the shift register shown in FIG. 5 are all N-type transistors, and the first reference signal terminal Vref1 and the third reference signal terminal Vref3 are both high units, and the second reference The signal terminal Vref2 and the fourth reference signal terminal Vref4 are both low potentials, and a corresponding input/output timing diagram is shown in FIG.
  • the shift register provided in this embodiment is also applicable to the H-Blank mode of the touch in cell touch screen (ie, inserting the touch time period in the display time period) to insert a touch signal between the T1 phase and the T2 phase as an example. Description.
  • the potential of the pull-up node PU is at a high potential through the second potential holding transistor M11, the first control transistor M12, the second control transistor 13, and the first potential holding transistor 14, Keeping, that is, holding the potential of the pull-up node PU by the pull-up node state holding circuit 3, avoiding the drop of the PU potential of the pull-up node, thereby ensuring the stable output of the shift register of the next stage, and the first clock at this time
  • the first clock signal sent by the signal terminal CLK is a low level signal, and the shift register has no output, which avoids the interference of the output of the shift register to the touch signal, thereby ensuring the function of the touch.
  • the pull-up node state maintaining circuit 3 performs low-level hold, so the subsequent work of other rows is not affected, and after the touch phase is over, the work of the T2 phase is continued.
  • touch phase may be located between any of the four phases in Embodiment 1, and the foregoing is only an example between the T1 phase and the T2 phase, and the working principle is the same between the other phases. It will not be described in detail here.

Abstract

本公开公开了一种移位寄存器、栅极驱动电路及显示装置，其中移位寄存器中包括第一输入电路(1)，所述第一输入电路(1)配置成在所述输入信号端(Input)的输入信号的控制下将所述第一参考信号端(Vref1)的第一参考信号提供给所述上拉节点(PU)；上拉节点状态保持电路(3)，所述上拉节点状态保持电路(3)配置成在所述上拉节点(PU)的电位为第一电位时，将所述第三参考信号端(Vref3)的第三参考信号提供给所述上拉节点(PU)，在所述上拉节点(PU)的电位为第二电位时，将第四参考信号端(Vref4)的第四参考信号提供给所述上拉节点(PU)；以及输出电路(6)，所述输出电路(6)配置成在所述上拉节点(PU)的电位的控制下将所述第一时钟信号端(Vref1)的第一时钟信号提供给所述栅极信号输出端(Output)。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
相关申请的交叉引用
本申请要求于2017年8月17日提交的中国专利申请第201710707773.7的优先权，该中国专利申请的全文通过引用的方式结合于此以作为本申请的一部分。
技术领域
本公开涉及一种移位寄存器及其驱动方法、栅极驱动电路及显示装置。
背景技术
在显示面板中，通常通过栅极驱动电路向像素区域的各个薄膜晶体管(TFT，Thin Film Transistor)的栅极提供栅极开启信号。栅极驱动电路可以通过阵列工艺形成在平板显示面板的阵列基板上，即阵列基板行驱动(Gate Driver on array，GOA)工艺，这种集成工艺不仅节省了成本，而且可以做到平板显示面板(Panel)两边对称的美观设计。同时，也省去了栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)的布线空间。
栅极驱动电路可以由多个级联的移位寄存器组成，各级移位寄存器用于向与该级移位寄存器的信号输出端相连的栅线提供栅极开启信号以开启对应行的像素区域的TFT。其中，除第一级移位寄存器之外，其余各级移位寄存器的输入信号端分别与上一级移位寄存器的信号输出端相连。其中各级移位寄存器中控制信号输出端输出栅极开启信号节点被称作上拉节点。在现有的触控与显示分时驱动的触控显示面板中，在显示一帧画面的时间内插入多个触控时间段，并且各触控时间段设置为一定时长的时间间隔。假设在第n级移位寄存器的信号输出端输出栅极开启信号完成后进入触控时间段，此时第n+1级移位寄存器中的上拉节点的电位已经被上拉为高电位。由于触控时间段间隔的时间较长，在此期间第n+1级移位寄存器中的上拉节点会经过与其连接的TFT而出现漏电情况，从而使该上拉节点的电位降低。当该触控时间段 结束后，第n+1级移位寄存器开始工作，由于其上拉节点的电位衰减，会造成该移位寄存器的信号输出端输出的栅极开启信号产生衰减，甚至可能导致无法开启像素区域的TFT，进而造成触控显示面板显示出现异常。
发明内容
本公开的实施例提供的一种移位寄存器，包括：第一输入电路，所述第一输入电路配置成将输入信号输入至所述上拉节点；上拉节点状态保持电路，所述上拉节点状态保持电路的第一端连接到第三参考信号端，所述上拉节点状态保持电路的第二端连接到第四参考信号端，所述上拉节点状态保持电路的第三端连接到所述上拉节点，所述上拉节点状态保持电路配置成在所述上拉节点的电位为第一电位时，将所述第三参考信号端的第三参考信号提供给所述上拉节点，其中所述第三参考信号用于将所述上拉节点的电位保持为第一电位，在所述上拉节点的电位为第二电位时，将第四参考信号端的第四参考信号提供给所述上拉节点，其中所述第四参考信号用于将所述上拉节点的电位保持为第二电位；以及输出电路，所述输出电路配置成在所述上拉节点的电位的控制下在栅极信号输出端输出栅极开启信号。
在一些实施例中，所述上拉节点状态保持电路包括控制子电路、第一电位保持子电路以及第二电位保持子电路，其中，所述控制子电路的第一端连接到所述第三参考信号端，所述控制子电路的第二端连接到所述上拉节点，所述控制子电路的第三端连接到所述第四参考信号端，所述控制子电路的第四端连接到所述第二电位保持子电路的第一端，所述控制子电路配置成在所述上拉节点的电位的控制下输出控制信号以控制所述第二电位保持子电路的导通和关断；所述第一电位保持子电路的第一端连接到所述第三参考信号端，所述第一电位保持子电路的第二端连接到上拉节点以及所述第二电位保持子电路，所述第一电位保持子电路配置成当所述第二电位保持子电路关断时，将所述第三参考信号输入到所述上拉节点；以及所述第二电位保持子电路的第一端连接到所述控制子电路，所述第二电位保持子电路的第二端连接到所述上拉节点，所述第二电位保持子电路的第三端连接到所述第四参考信号端，当所述第二电位保持子电路在所述控制信号的控制下导通时，所述第二电位 保持子电路将所述第四参考信号输入到所述上拉节点。
在一些实施例中，所述控制子电路包括第一控制晶体管和第二控制晶体管，其中，所述第一控制晶体管的栅极与所述上拉节点相连，所述第一控制晶体管的第一极与所述第四参考信号端相连，所述第一控制晶体管的第二极连接到所述第二电位保持子电路和所述第二控制晶体管的第二极；所述第二控制晶体管的栅极和所述第二控制晶体管的第一极相连并连接到所述第三参考信号端。
在一些实施例中，所述第一电位保持子电路包括第一电位保持晶体管，所述第一电位保持晶体管的栅极和所述第一电位保持晶体管的第一极相连并连接到所述第三参考信号端，所述第一电位保持晶体管的第二极与所述上拉节点相连。
在一些实施例中，所述第二电位保持子电路包括第二电位保持晶体管，所述第二电位保持晶体管的栅极连接到所述第一控制晶体管的第二极，所述第二电位保持晶体管的第一极与所述第四参考信号端相连，所述第二电位保持晶体管的第二极与所述上拉节点相连。
在一些实施例中，所述第一控制晶体管的沟道宽长比大于所述第二控制晶体管的沟道宽长比。
在一些实施例中，所述第二电位保持晶体管的沟道宽长比大于所述第一电位保持晶体管的沟道宽长比。
在一些实施例中，所述第一输入电路包括第一输入晶体管，其中，所述第一输入晶体管的栅极与输入信号端相连，所述第一输入晶体管的第一极与第一参考信号端相连，所述第一输入晶体管的第二极与所述上拉节点相连。
在一些实施例中，所述移位寄存器还包括：第二输入电路，所述第二输入电路的第一端连接到复位信号端，所述第二输入电路的第二端连接到第二参考信号端，所述第二输入电路的第三端连接到所述上拉节点，其中，所述第二输入电路配置成在所述复位信号端的复位信号的控制下将所述第二参考信号端的信号提供给所述上拉节点。
在一些实施例中，所述第二输入电路包括第二输入晶体管，其中，所述第二输入晶体管的栅极与所述复位信号端相连，所述第二输入晶体管的第一 极与所述第二参考信号端相连，所述第二输入晶体管的第二极与所述上拉节点相连。
在一些实施例中，所述移位寄存器还包括：下拉控制电路，所述下拉控制电路的第一端连接到所述上拉节点，所述下拉控制电路的第二端连接到所述第三参考信号端，所述下拉控制电路的第三端连接到所述第四参考信号端以及所述下拉控制电路的第四端连接到所述移位寄存器的下拉节点，其中，所述下拉控制电路配置成在所述上拉节点为所述第一电位时，将所述第四参考信号端的信号提供给所述下拉节点，在所述上拉节点为所述第二电位时，将所述第三参考信号端的信号提供给所述下拉节点。
在一些实施例中，所述下拉控制电路包括：第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管和第四下拉控制晶体管；其中，所述第一下拉控制晶体管的栅极与所述上拉节点相连，所述第一下拉控制晶体管的第一极与所述第四参考信号端相连，所述第一下拉控制晶体管的第二极与所述下拉节点相连；所述第二下拉控制晶体管的栅极与所述上拉节点相连，所述第二下拉控制晶体管的第一极与所述第四参考信号端相连，所述第二下拉控制晶体管的第二极分别与所述第三下拉控制晶体管的第二极和所述第四下拉控制晶体管的栅极相连；所述第三下拉控制晶体管的栅极分别与所述第四下拉控制晶体管的第二极和所述第二下拉控制晶体管的第二极相连，所述第三下拉控制晶体管的第一极与所述第三参考信号端相连，所述第三下拉控制晶体管的第二极与所述下拉节点相连；所述第四下拉控制晶体管的栅极和所述第四下拉控制晶体管第一极相连并连接到所述第三参考信号端，所述第四下拉控制晶体管第二极连接到所述第三下拉控制晶体管的栅极和所述第二下拉控制晶体管的第二极。
在一些实施例中，所述移位寄存器还包括：下拉电路，所述下拉电路的第一端连接到所述下拉节点，所述下拉电路的第二端连接到所述上拉节点，所述下拉电路的第三端连接到所述栅极信号输出端，所述下拉电路的第四端连接到所述第四参考信号端，其中，所述下拉电路配置成在所述下拉节点的电位的控制下将所述第四参考信号端的信号提供给所述上拉节点和所述栅极信号输出端。
在一些实施例中，所述下拉电路包括：第一下拉晶体管和第二下拉晶体管；其中，所述第一下拉晶体管的栅极与所述下拉节点相连，所述第一下拉晶体管的第一极与所述第四参考信号端相连，所述第一下拉晶体管的第二极与所述栅极信号输出端相连；所述第二下拉晶体管的栅极与所述下拉节点相连，所述第二下拉晶体管的第一极与所述第四参考信号端相连，所述第二下拉晶体管的第二极与所述上拉节点相连。
在一些实施例中，所述输出电路包括：输出晶体管和第一电容；其中，所述输出晶体管的栅极与所述上拉节点相连，所述输出晶体管的第一极与第一时钟信号端相连，所述输出晶体管的第二极与所述栅极信号输出端相连；以及所述第一电容的第一端连接所述上拉节点，所述第一电容的第二端连接所述栅极信号输出端。
在一些实施例中，所述移位寄存器还包括：放噪电路，其中，所述放噪电路的第一端连接所述栅极信号输出端，所述放噪电路的第二端连接所述上拉节点，所述放噪电路的第三端连接所述第四参考信号端，所述放噪电路的第四端连接放噪信号端；所述放噪电路配置在所述放噪信号端的放噪信号的控制下将所述第四参考信号端的信号提供给所述栅极信号输出端和所述上拉节点。
相应地，本公开实施例还提供了一种栅极驱动电路，包括多个本公开实施例提供的移位寄存器。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供上述任一种栅极驱动电路。
相应地，本公开实施例还提供了一种用于如前所述的移位寄存器的驱动方法，包括：接收输入信号，并根据所述输入信号将所述上拉节点上拉至导通电平；利用所述上拉节点电位保持电路将所述上拉节点的电位保持为导通电平；接收第一时钟信号，并基于所述第一时钟信号，在所述上拉节点的电位的控制下在所述输出端处输出栅极开启信号。
在一些实施例中，所述驱动方法还包括：接收复位信号，根据所述复位信号将所述上拉节点下拉至截止电平；利用所述上拉节点电位保持电路将所述上拉节点的电位保持为截止电平。
利用本公开实施例提供的移位寄存器，利用本公开提供的上拉节点状态保持电路对上拉节点的电位进行保持，可以保持上拉节点的电位不会随时间衰减，保证了移位寄存器的稳定输出。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员而言，在没有做出创造性劳动的前提下，还可以根据这些附图获得其他的附图。以下附图并未刻意按实际尺寸等比例缩放绘制，重点在于示出本公开的主旨。
图1示出了本公开的实施例提供的一种移位寄存器的示意性的框图；
图2示出了本公开实施例提供的一种移位寄存器的示意性的框图；
图3示出了根据本公开实施例的移位寄存器的示意性的电路结构图；
图4示出了根据本公开实施例的另一种移位寄存器的示意性框图；
图5示出了根据本公开提供的另一种移位寄存器的电路结构图；
图6示出了本公开实施例提供的一种栅极驱动电路的示意图；
图7示出了本公开实施例提供的另一种栅极驱动电路的示意图；
图8示出了根据本公开实施例的移位寄存器的驱动方法的流程图；
图9示出了根据本公开的实施例的移位寄存器的示例性的时序图；
图10示出了根据本公开的实施例的移位寄存器的另一种示例性的时序图；以及
图11示出了根据现有技术的移位寄存器的时序图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1示出了本公开的实施例提供的一种移位寄存器的示意性的框图。如图1所示，移位寄存器100包括第一输入电路1、上拉节点状态保持电路3以及输出电路6。
如图1所示，第一输入电路1的第一端连接到输入信号端Input，第一输入电路1的第二端连接到第一参考信号端Vref1，第一输入电路1的第三端连接到上拉节点PU，第一输入电路1配置成在输入信号端Input的输入信号的控制下将第一参考信号端Vref1的第一参考信号提供给上拉节点PU。
应当注意的是，图1仅示出了第一输入电路1的一种可能的实施方式。根据实际情况第一输入电路1可以配置成其他形式，例如，第一输入电路1的第一端和第二端均连接到输入信号端Input，并在输入信号端Input的输入信号的控制下拉高上拉节点PU的电位。又例如，第一输入电路1配置成在第一参考信号端Vref1的第一参考信号的控制下将输入信号端Input的输入信号提供给上拉节点PU。
上拉节点状态保持电路3的第一端连接到第三参考信号端Vref3，上拉节点状态保持电路3的第二端连接到第四参考信号端Vref4以及上拉节点状态保持电路3的第三端连接到移位寄存器100的上拉节点PU。
上拉节点状态保持电路3配置成用于在上拉节点PU的电位为第一电位时，将第三参考信号端Vref3的信号提供给上拉节点PU，在上拉节点PU的电位为第二电位时，将第四参考信号端Vref4的信号提供给上拉节点PU。
在一些实施例中，第一参考信号端Vref1、第三参考信号端Vref3的电位 为第一电位，第四参考信号端Vref4的电位为第二电位。
输出电路6的第一端连接到上拉节点PU，输出电路6的第二端连接到第一时钟信号端CLK，输出电路6的第三端连接到移位寄存器100的栅极信号输出端Output。输出电路6配置成在上拉节点PU的电位的控制下将第一时钟信号端CLK的第一时钟信号提供给栅极信号输出端Output。
利用本公开实施例提供的上述移位寄存器，由于设置了上拉节点状态保持电路，利用上拉节点状态保持电路控制上拉节点的电位，从而可以保持上拉节点的电位不会随时间发生衰减，保证了移位寄存器的稳定输出。
需要说明的是，本公开上述实施例所说的第一电位和第二电位均指的是高电位或低电位，而不是具体的电压值，其具体的电压值在此不做限定，只要能保证晶体管的打开或者关闭即可。例如，当第一电位是是移位寄存器100中使用的晶体管的导通电位时，第二电位可以是移位寄存器100中使用的晶体管的关断电位。
在一些实施例中，本公开实施例提供的上述移位寄存器中，由于节点位保持子电路可以保持上拉节点的电位，即在上拉节点为关断电位(如低电位)时，保持上拉节点为低电位，当上拉节点为导通电位(如高电位)时，保持上拉节点为高电位，从而可以保持上拉节点的电位不会衰减，因此上述移位寄存器可以适用于Touch in cell触摸屏的H-Blank模式(即在显示时间段中插入触控时间段)。在触控时间段，移位寄存器单元的栅极输出端无输出，避免栅极开启信号对触控信号的影响，保证了触控的正常功能。并且由于上拉节点状态保持电路对上拉节点电位的保持，保证了在触控结束后，移位寄存器不会出现无输出或者输出电压过低的现象，可以恢复正常的后续工作。
当然，本公开实施例提供的上述移位寄存器也适用于Touch in cell触摸屏的V-Blank模式(即在两帧显示时间段之间插入触控时间段)，这种情况下，在上一帧结束下一帧开始之前输出端一直保持最后阶段的电位，不会对下一帧的信号产生影响。
当然，本公开实施例提供的上述移位寄存器，也适用于传统的栅极驱动模式(即仅有显示时间段，没有触控时间段)，在此不作具体限定。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施 例是为了更好的解释本公开，但不限制本公开。
图2示出了本公开实施例提供的一种移位寄存器的示意性的框图。如图2所示，移位寄存器200可以包括第一输入电路1、上拉节点状态保持电路3以及输出电路6。其中第一输入电路1和输出电路6与图1中示出的第一输入电路1和输出电路6相同，在此不再赘述。
如图2所示，上拉节点状态保持电路3可以进一步包括控制子电路31、第一电位保持子电路32以及第二电位保持子电路33。其中，控制子电路31的第一端连接到第三参考信号端Vref3，控制子电路31的第二端连接到上拉节点PU，控制子电路31的第三端连接到第四参考信号端Vref4，控制子电路31的第四端连接到第二电位保持子电路33的第一端。控制子电路31配置成在上拉节点PU的电位的控制下输出控制信号并控制第二电位保持子电路33的导通和关断。
第一电位保持子电路32的第一端连接到第三参考信号端Vref3，第一电位保持子电路32的第二端连接到上拉节点PU以及第二电位保持子电路33。第一电位保持子电路32配置成根据控制信号将第三参考信号输入到上拉节点PU。例如，当第二电位保持子电路33在控制子电路31输出的控制信号的控制下关断时，第一电位保持子电路32配置成将第三参考信号输入到上拉节点PU。
第二电位保持子电路33的第一端连接到控制子电路31，第二电位保持子电路33的第二端连接到上拉节点PU，第二电位保持子电路33的第三端连接到第四参考信号端Vref4。第二电位保持子电路33配置成根据控制信号将第四参考信号输入到上拉节点PU。例如，当第二电位保持子电路33在控制子电路31输出的控制信号的控制下导通时，通过第二电位保持子电路33将第四参考信号输入到上拉节点PU。
图3示出了根据本公开实施例的移位寄存器的示意性的电路结构图。以下以所有晶体管均是N型晶体管为例描述实现本公开的原理。但本领域技术人员可以理解，该移位寄存器中的一个或者多个晶体管采用P型晶体管也是可能的，只要相应地调整源极和漏极的位置以及相应的栅极接入的电平即可。例如，在本申请中的实施例中使用的所有晶体管均是N型晶体管，则第一电 位是高电平，第二电位是低电平。如果将N型晶体管替换为P型晶体管，则第一电位是低电平，第二电位是高电平。具体细节不在此赘述，但也应该在本发明的保护范围内。
如图3所示，在一个实施例中，第一输入电路1可以包括：第一输入晶体管M1。其中，第一输入晶体管M1的栅极与输入信号端Input相连，第一输入晶体管M1的第一极与第一参考信号端Vref1相连，第一输入晶体管M1的第二极与上拉节点PU相连。当输入信号端Input输入高电平的输入信号时，第一输入晶体管M1可以在输入信号的控制下导通，并将第一参考信号端的信号输入到上拉节点PU。第一参考信号端的信号可以是高电平的导通信号。
以上仅是举例说明移位寄存器中第一输入电路1的具体结构，第一输入电路1的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。例如，可以将第一输入晶体管M1的栅极和第一极均连接到输入信号端Input。又例如，可以将第一输入晶体管M1的栅极与第一参考信号端Vref1相连，第一输入晶体管M1的第一极输入信号端Input相连。
在一个实施例中，控制子电路31可以包括第一控制晶体管M12和第二控制晶体管M13。例如，第一控制晶体管M12的栅极可以与上拉节点PU相连，第一控制晶体管M12的第一极可以与第四参考信号端Vref4相连，第一控制晶体管M12的第二极可以连接到第二电位保持子电路33和第二控制晶体管M12的第二极。第二控制晶体管M13的栅极可以和第二控制晶体管M13的第一极相连并连接到第三参考信号端Vref3。
在一个实施例中，第一电位保持子电路32包括第一电位保持晶体管M14。第一电位保持晶体管M14的栅极和第一电位保持晶体管M14的第一极相连并连接到第三参考信号端Vref3，第一电位保持晶体管M14的第二极与上拉节点PU相连。
在一个实施例中，第二电位保持子电路33可以包括第二电位保持晶体管M11。第二电位保持晶体管M11的栅极可以连接到第一控制晶体管M12的第二极，第二电位保持晶体管M11的第一极可以与第四参考信号端Vref4相连，第二电位保持晶体管M11的第二极可以与上拉节点PU相连。
以上仅是举例说明移位寄存器中控制子电路31、第一电位保持子电路32、第二电位保持子电路33的具体结构。控制子电路31、第一电位保持子电路32、第二电位保持子电路33的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在一些实施例中，当上拉节点PU为导通电位(如高电位)时，第一控制晶体管M12在上拉节点PU的电位的控制下打开。由于第三参考信号端的电位为高电位，因此第二控制晶体管M13在第三参考信号的控制下也是打开的。在一些实施例中，可以通过设置第一控制晶体管M12和第二控制晶体管M13的沟道宽长比使得第一控制晶体管M12的沟道宽长比大于第二控制晶体管M13的沟道宽长比，从而使得当第一控制晶体管M12和第二控制晶体管M13均导通时，通过第一控制晶体管M12向第二电位保持子电路33输出第四参考信号端Vref4的第四参考信号作为控制信号。其中，第四参考信号的电位为关断电位(如低电位)。因此第二电位保持晶体管M11在第四参考信号的控制下截止。此时，由于第一电位保持晶体管M14的栅极连接到第三参考信号端Vref3，因此第一电位保持晶体管M14在第三参考信号的控制下打开，并将第三参考信号端输入的第三参考信号提供给上拉节点PU，因此保持上拉节点PU的电位一直处于高电位。
当上拉节点PU的电位为低电位时，第一控制晶体管M12在上拉节点PU的电位的控制下截止。由于第三参考信号端Vref3的电位为高电位，第二控制晶体管M13在第三参考信号的控制下导通，并将第三参考信号作为控制信号输出到第二电位保持子电路33。在第三参考信号的控制下，第二电位保持晶体管M11导通，可以通过设置第二电位保持晶体管M11和第一电位保持晶体管M14的沟道宽长比使得第二电位保持晶体管M11的沟道宽长比大于第一电位保持晶体管M14的沟道宽长比，从而使得当第一电位保持晶体管M14和第二电位保持晶体管M11均导通时，通过第二电位保持晶体管M11将第四参考信号输入到上拉节点PU，并对上拉节点进行放电，从而保持上拉节点的电位一直处于低电位。
在一些实施例中，如图3所示，输出电路6可以包括输出晶体管M3和第一电容C1。例如，输出晶体管M3的栅极可以与上拉节点PU相连，输出 晶体管M3的第一极可以与第一时钟信号端CLK相连，输出晶体管M3的第二极可以与移位寄存器100的栅极信号输出端Output相连。第一电容C1的第一端可以连接上拉节点PU，第一电容C2的第二端可以连接移位寄存器100的栅极信号输出端Output。
当第一时钟信号端CLK输入高电平的第一时钟信号时，由于输出晶体管M3在上拉节点PU的电位的控制下是导通的，输出晶体管M3可以将高电平的第一时钟信号输入到栅极信号输出端Output，并在栅极信号输出端Output处输出栅极开启信号。此时由于第一电容C1的存在，上拉节点PU在自举作用下电位进一步被拉高。
以上仅是举例说明移位寄存器中输出电路6的具体结构。输出电路的具体结构不限于本发明本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
图4示出了根据本公开实施例的另一种移位寄存器的示意性框图。如图4所示，移位寄存器200可以包括第一输入电路1、第二输入电路2、上拉节点状态保持电路3、下拉控制电路4、下拉电路5、输出电路6、放噪电路7。其中，图4中示出的第一输入电路1、上拉节点状态保持电路3和输出电路6可以采用图1-3中描述的第一输入电路1、上拉节点状态保持电路3和输出电路6，此后不再赘述。
如图4所示，移位寄存器200中的第二输入电路2的第一端连接到复位信号端Reset，第二输入电路2的第二端连接到第二参考信号端Vref2，第二输入电路2的第三端连接到上拉节点PU。在一些实施例中，第二输入电路2可以配置成在复位信号端Reset的复位信号的控制下将第二参考信号端Vref2的第二参考信号提供给上拉节点PU。其中第二参考信号端Vref2输入的信号电位与第一参考信号端Vref1输入的信号的电位相反。例如。当第一参考信号端Vref1输入高电位的信号时，第二参考信号端Vref2输入低电位的信号。当第一参考信号端Vref1输入低电位的信号时，第二参考信号端Vref2输入高电位的信号。
以上仅是举例说明移位寄存器中第二输入电路的具体结构。第二输入电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人 员可知的其他结构，在此不做限定。并且，在本公开实施例提供的上述移位寄存器中，由于第一输入电路与第二输入电路是对称设计，因此该移位寄存器还能实现双向扫描的功能。
移位寄存器200中的下拉控制电路4的第一端可以连接到上拉节点PU，下拉控制电路4的第二端连接到第三参考信号端VRef3，下拉控制电路4的第三端连接到第四参考信号端Vref4以及下拉控制电路4的第四端连接到移位寄存器200的下拉节点PD。在一些实施例中，下拉控制电路4配置成在上拉节点PU为所述第一电位时，将第四参考信号端Vref4的信号提供给下拉节点PD。在上拉节点PU为第二电位时，将第三参考信号端Vref3的信号提供给下拉节点PD。
需要说明的是，本公开上述实施例所说的第一电位和第二电位均指的是高电位或低电位，而不是具体的电压值，其具体的电压值在此不做限定，只要能保证晶体管的打开或者关闭即可。例如，当第一电位是是移位寄存器200中使用的晶体管的导通电位时，第二电位可以是移位寄存器200中使用的晶体管的关断电位。
移位寄存器200中的下拉电路5的第一端连接到下拉节点PD，下拉电路5的第二端连接到上拉节点PU，下拉电路5的第三端连接到移位寄存器200的栅极信号输出端Output，下拉电路5的第四端连接到第四参考信号端Vref4。在一些实施例中，下拉电路5配置成在下拉节点PD的电位的控制下将第四参考信号端Vref4的信号提供给上拉节点PU和栅极信号输出端Output。
移位寄存器200中的放噪电路7的第一端可以连接栅极信号输出端Output，放噪电路7的第二端可以连接上拉节点PU，放噪电路7的第三端可以连接第四参考信号端Vref4，放噪电路7的第四端可以连接放噪信号端S1。在一些实施例中，放噪电路7可以配置在放噪信号端S1的放噪信号的控制下将第四参考信号端Vref4的信号提供给栅极信号输出端Output和上拉节点PU。
如图4所示，在一些实施例中，放噪电路7可以包括第一放噪子电路7-1和第二放噪子电路7-2。
第一放噪子电路7-1的第一端可以连接到栅极信号输出端Output，第一 放噪子电路7-1的第二端可以连接到放噪信号端S1，第一放噪子电路7-1的第三端可以连接到第四参考信号端Vref4。第一放噪子电路7-1可以配置在放噪信号端S1的放噪信号的控制下将第四参考信号端Vref4的信号提供给栅极信号输出端Output。
第二放噪子电路7-2的第一端可以连接到上拉节点PU，第二放噪子电路7-2的第二端可以连接到放噪信号端S1，第二放噪子电路7-2的第三端可以连接到第四参考信号端Vref4。第二放噪子电路7-2配置在放噪信号端S1的放噪信号的控制下将第四参考信号端Vref4的信号提供给上拉节点PU。
图5示出了根据本公开提供的另一种移位寄存器的电路结构图。如图5所示，移位寄存器200可以包括第一输入电路1、第二输入电路2、上拉节点状态保持电路3、下拉控制电路4、下拉电路5、输出电路6、放噪电路7。其中，图4中示出的第一输入电路1、上拉节点状态保持电路3和输出电路6可以采用图1-3中描述的第一输入电路1、上拉节点状态保持电路3和输出电路6，此后不再赘述。
在一些实施例中，第二输入电路2可以包括第二输入晶体管M2。例如，第二输入晶体管M2的栅极可以与复位信号端Reset相连，第二输入晶体管M2的第一极可以与第二参考信号端Vref2相连，第二输入晶体管M2的第二极可以与上拉节点PU相连。
在一些实施例中，下拉控制电路4可以包括：第一下拉控制晶体管M6、第二下拉控制晶体管M7、第三下拉控制晶体管M8和第四下拉控制晶体管M9。例如，第一下拉控制晶体管M6的栅极可以与上拉节点PU相连，第一下拉控制晶体管M6的第一极可以与第四参考信号端Vref4相连，第一下拉控制晶体管M6的第二极可以与下拉节点PD相连。
第二下拉控制晶体管M7的栅极可以与上拉节点PU相连，第二下拉控制晶体管M7的第一极可以与第四参考信号端Vref4相连，第二下拉控制晶体管M7的第二极可以连接到第四下拉控制晶体管M9的第二极和第三下拉控制晶体管M8的栅极。
第三下拉控制晶体管M8的栅极可以分别与第四下拉控制晶体管M9的第二极和第二下拉控制晶体管M7的第二极相连，第三下拉控制晶体管M8的第 一极可以与第三参考信号端Vref3相连，第三下拉控制晶体管M8的第二极可以与下拉节点PD相连。
第四下拉控制晶体管M9的栅极可以和第四下拉控制晶体管M9第一极相连并连接到第三参考信号端Vref3，第四下拉控制晶体管M9的第二极可以连接到第三下拉控制晶体管M8的栅极和第二下拉控制晶体管M7的第二极相连。
以上仅是举例说明移位寄存器中下拉控制电路4的具体结构。下拉控制电路4的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在一些实施例中，下拉电路5可以包括：第一下拉晶体管M4和第二下拉晶体管M10。例如，第一下拉晶体管M4的栅极可以与下拉节点PD相连，第一下拉晶体管M4的第一极可以与第四参考信号端Vref4相连，第一下拉晶体管M4的第二极可以与信栅极号输出端Output相连。
第二下拉晶体管M10的栅极可以与下拉节点PD相连，第二下拉晶体管M10的第一极可以与第四参考信号端Vref4相连，第二下拉晶体管M10的第二极可以与上拉节点PU相连。
以上仅是举例说明移位寄存器中下拉电路5的具体结构。下拉电路5的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在一些实施例中，输出放噪电路7可以包括第一放噪晶体管M5。例如，第一放噪晶体管M5的栅极可以与放噪信号端S1相连，第一放噪晶体管M5的第一极可以与第四参考信号端Vref4相连，第一放噪晶体管M5的第二极可以与栅极信号输出端Output相连。
输出放噪电路7还可以包括第二放噪晶体管M15。例如，第二放噪晶体管M15的栅极可以与放噪信号端S1相连，第二放噪晶体管M15的第一极可以与第四参考信号端Vref4相连，第二放噪晶体管M15的第二极可以与上拉节点PU相连。
以上仅是举例说明移位寄存器中输出放噪电路7的具体结构。输出放噪电路7的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技 术人员可知的其他结构，在此不做限定。
在一些实施例中，在本公开实施例提供的移位寄存器应用到栅极驱动电路中时，第一级移位寄存器的放噪信号端与单独的信号端相连，即第一级移位寄存器的放噪信号端与Dummy信号端相连，除第一级之外的其他级移位寄存器的放噪信号端可以与帧起始信号端相连，这样设置在第一级移位寄存器接收到帧起始信号的同时，除第一级移位寄存器之外的其他级移位寄存器也接收到该帧起始信号，通过该信号对除第一级移位寄存器之外的其他级移位寄存器进行放噪。
在一些实施例中，在本公开实施例提供的上述移位寄存器中，为了简化制作工艺，晶体管一般均采用相同材质的晶体管，因此，所有晶体管均为N型晶体管或均为P型晶体管。在一些实施例中，当需要的栅极开启信号的电位为高电位时，所有晶体管均为N型晶体管。当需要的栅极开启信号的电位为低电位时，所有晶体管均为P型晶体管。
进一步的，在一些示例中，N型晶体管在高电位作用下导通，在低电位作用下截止。P型晶体管在高电位作用下截止，在低电位作用下导通。
需要说明的是本公开上述实施例中提到的晶体管均为金属氧化物半导体场效应管(MOS，MetPUl Oxide SPDmiPDonduPDtor)。在具体实施中，这些晶体管的第一极为源极，第二极为漏极，或者第一极为漏极，第二极为源极，在此不做具体区分。
进一步地，由于在本公开实施例提供的上述移位寄存器中，第一输入电路1与第二输入电路2为对称设计，可以实现功能互换，因此本公开实施例提供的上述移位寄存器200可以实现双向扫描。在正向扫描时，输入信号端Input接收输入信号，复位信号端Reset接收复位信号，将第一输入电路1作为输入的功能，第二输入电路2作为复位的功能。在反向扫描时，输入信号端Input接收复位信号，复位信号端Reset接收输入信号，将第二输入电路2作为输入的功能，第一输入电路1作为复位的功能。
在一些实施例中，在本公开实施例提供的上述移位寄存器中，当需要的栅极开启信号的电位为高电位时，其中，在正向扫描时，第一参考信号端的电位为高电位，第三参考信号端为高电位，第二参考信号端和第三参考信号 端的电位均为低电位。在反向扫描时，第二参考信号端和第三参考信号端的电位为高电位，第一参考信号端和第三参考信号端的电位均为低电位。
在一些实施例中，在本公开实施例提供的上述移位寄存器中，当需要的栅极开启信号的电位为低电位时，其中，在正向扫描时，第一参考信号端和第四参考信号端的电位为低电位，第二参考信号端和第四参考信号端的电位均为高电位。在反向扫描时，第二参考信号端和第三参考信号端的电位为低电位，第一参考信号端和第三参考信号端的电位均为高电位。
图6示出了本公开实施例提供的一种栅极驱动电路的示意图。如图6所示，栅极驱动电路600包括级联的多个本公开实施例提供的上述任一种移位寄存器：SR(1)、SR(2)…SR(n)…SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N)。
除第一级移位寄存器SR(1)之外，其余每一级移位寄存器SR(n)的信号输出端Output分别与其相邻的上一级移位寄存器SR(n-1)的复位信号端Reset相连。
除最后一级移位寄存器SR(N)之外，其余每一级移位寄存器SR(n)的信号输出端Output分别与其相邻的下一级移位寄存器SR(n+1)的输入信号端Input相连。
在一个示例中，第一级移位寄存器SR(1)的输入信号端Input与帧起始信号端STV相连。
在一个示例中，在本公开实施例提供的栅极驱动电路600中，所有移位寄存器的第一参考信号端Vref1均与第一参考信号线V1相连，所有移位寄存器的第二参考信号端Vref2均与第一参考信号线V2相连，所有移位寄存器的第三参考信号端Vref3均与第三参考信号线V3相连，所有移位寄存器的第四参考信号端Vref4均与第四参考信号线V4相连。所有奇数级的移位寄存器的第一时钟信号端CLK均与第一时钟信号线C1相连，所有奇数级的移位寄存器的第二时钟信号端CLKB均与第二时钟信号线C2相连。所有偶数级的移位寄存器的第一时钟信号端CLK均与第二时钟信号线C2相连，所有偶数级的移位寄存器的第二时钟信号端CLKB均与第一时钟信号线C1相连，并且第一时钟信号线C1上的时钟信号与第二信号线C2上的时钟信号的相位相反。
图7示出了本公开实施例提供的另一种栅极驱动电路的示意图。如图7所示，当栅极驱动电路中的移位寄存器具有放噪电路时，除第一级移位寄存器SR(1)之外，其他各级SR(2)至SR(n)的放噪信号端S1均与帧起始信号端STV相连，而第一级移位寄存器SR(1)的放噪信号端S1与单独设置的信号端相连，即与Dummy信号端相连。这样设置在第一级移位寄存器SR(1)接收到帧起始信号的同时，除第一级移位寄存器SR(1)之外的其他级移位寄存器SR(2)至SR(n)也接收到该帧起始信号，通过该信号对除第一级移位寄存器SR(1)之外的其他级移位寄存器SR(2)至SR(n)进行放噪。
本公开至少一实施例还提供了一种显示装置，包括上述的栅极驱动电路，通过该栅极驱动电路为显示装置中阵列基板上的各栅线提供扫描信号。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述栅极驱动电路的实施例，重复之处不再赘述。
利用本公开实施例提供的上述移位寄存器、栅极驱动电路及显示装置，由于设置了上拉节点状态保持电路，利用上拉节点状态保持电路在触控时间段时对上拉节点的电位进行持续，从而可以保持上拉节点的电位不会随时间衰减，保证了移位寄存器的稳定输出。
图8示出了根据本公开实施例的移位寄存器的驱动方法的流程图。如图8所示，驱动方法800可以包括以下步骤：
步骤S801，接收输入信号，并根据输入信号将上拉节点PU上拉至导通电平。
步骤S802，利用上拉节点电位保持电路将上拉节点PU的电位保持为导通电平。
步骤S803，接收第一时钟信号，并基于第一时钟信号在上拉节点PU的电位的控制下在输出端Output处输出栅极开启信号。
步骤S804，接收复位信号，根据复位信号将上拉节点PU下拉至截止电平。
步骤S805，利用上拉节点电位保持电路将上拉节点PU的电位保持为截止电平。
下面分别结合电路时序图，以正向扫描为例对本公开实施例提供的上述移位寄存器的工作过程作以描述。下述描述中以1表示晶体管的导通电位，如高电位信号，0表示晶体管的关断电位，如低电位信号。
图9示出了根据本公开的实施例的移位寄存器的示例性的时序图。图9中示出的驱动时序可以应用于如前所述的任一移位寄存器。
以图5所示的移位寄存器为例，其中图5所示的移位寄存器中晶体管均为N型晶体管，第一参考信号端Vref1和第三参考信号端Vref3均为高电位，第二参考信号端Vref2和第四参考信号端Vref4均为低电位。
在TI阶段，Input＝1，Reset＝0，CLK＝0。
输入信号端Input的信号位高电平信号，即上一级的输出信号，使第一输入晶体管M1导通，第一参考信号端Vref1发出的第一参考信号通过第一输入晶体管M1给第一电容C1进行充电，从而使上拉节点PU的电位拉高。由于上拉节点PU为高电平，第一下拉控制晶体管M6和第二下拉控制晶体管M7导通，第二下拉控制晶体管M7导通将第四参考信号端Vref4的第四参考信号分别提供给第三下拉控制晶体管M8的栅极和第四下拉控制晶体管M9的第二极，第一下拉控制晶体管M6导通将第四参考信号端Vref4的第四参考信号提供给下拉节点PD，将下拉节点PD的电位拉低，从而使得第一下拉晶体管M4和第二下拉晶体管M10截止，以保证信号输出端Output所输出信号的稳定性。
此时，上拉节点PU的电位为高电位，第一控制晶体管M12打开，由于第三参考信号端Vref3的电位为高电位，第二控制晶体管M13和第一电位保持晶体管M14均打开，其中，第一控制晶体管M12的沟道宽长比大于第二控制晶体管M13的沟道宽长比，第一控制晶体管M12的源极与第四参考信号端Vref4连接，其中第四参考信号端Vref4的为低电位，因此第二电位保持晶体管M11截止，由于第一电位保持晶体管M14打开，将第三参考信号端Vref3发出的第三参考信号不断地提供给上拉节点PU，因此保持上拉节点PU的电位一直处于高电位，使上拉节点PU形成记忆性高电平。
在T2阶段，Input＝0，Reset＝0，CLK＝1。
输入信号端Input的信号位低电平信号，使第一输入晶体管M1截止，上 拉节点PU继续保持上一阶段的高电位，输出晶体管M3保持开启状态，此时第一时钟信号端CLK发出的第一时钟信号为高电平信号，由于第一电容C1的自举效应使上拉节点PU的电位升高，向信号输出端Output输出第一时钟信号，此时上拉节点PU的电位为高电位，第一下拉控制晶体管M6和第二下拉控制晶体管M7仍处于开启状态，从而第一下拉晶体管M4和第二下拉晶体管M10保持截止状态，保证了信号输出端Output的输出信号的稳定性。
在T3阶段，Input＝0，Reset＝1，CLK＝0。
复位信号端Reset的信号为高电平信号，即为下一级的输出信号，使得第二输入晶体管M2导通，将第二参考信号端Vref2发出的第二参考信号通过导通的第二输入晶体管M2提供给上拉节点PU，从而使得输出晶体管M3、第一下拉晶体管M4和第二下拉控制晶体管M7处于截止状态，由于第三参考信号端Vref3的为高电位，第三下拉控制晶体管M8和第四下拉控制晶体管M9打开，使得下拉节点PD处于高电位，因此第一下拉晶体管M4和第二下拉晶体管M10导通，将第四参考信号端Vref4的信号提供给上拉节点PU和信号输出端Output，其中，此时第四参考信号端Vref4的信号为低电平信号。
由于上拉节点PU的电位为低电位，第一控制晶体管M12截止，由于第三参考信号端Vref3为高电位，因此第二控制晶体管M13和第一电位保持晶体管M14均导通，其中第二电位保持晶体管M11的沟道宽长比大于第一电位保持晶体管M14的沟道宽长比，因此，第二电位保持晶体管M11将第四参考信号端Vref4的信号提供给上拉节点PU，对上拉节点PU进行放电，从而保持上拉节点PU的电位一直处于低电位，使上拉节点PU形成记忆性低电平。
在T4阶段，Input＝0，Reset＝0，CLK＝1。
该阶段为无输出阶段，第一输入晶体管M1一直处于截止状态，由于第三参考信号端Vref3的电位为高电位，第三下拉控制晶体管M8和第四下拉控制晶体管M9导通，使得下拉节点PD保持高电位，第一下拉晶体管M4和第二下拉晶体管M10导通，不断对上拉节点PU进行放噪，使得第一时钟信号端CLK产生的噪声电压得以消除，从而实现低电压输出，保证信号输出端Output输出信号的稳定性。
其中，在T4阶段之后，下一帧的信号到来之前，该移位寄存器一直在重 复T4阶段，不断地对移位寄存器进行放噪。并且，在上一帧结束下一帧到来之前，放噪信号端S1为高电平，第一放噪晶体管M5打开，对信号输出端Output进行放噪。
上述实施例一适合传统的GOA模式。当然也适合Touch in cell的V-Blank模式。具体应用在此不做限定。
图10示出了根据本公开的实施例的移位寄存器的另一种示例性的时序图。
以图5所示的移位寄存器为例，其中图5所示的移位寄存器中晶体管均为N型晶体管，第一参考信号端Vref1和第三参考信号端Vref3均为高单位，第二参考信号端Vref2和第四参考信号端Vref4均为低电位，对应的一种输入输出时序图如图10所示。
本实施例提供的移位寄存器还适用于Touch in cell触摸屏的H-Blank模式(即在显示时间段中插入触控时间段)，以在T1阶段与T2阶段之间插入触控信号为例进行说明。
当T1阶段之后，有触控信号来时，由于此时上拉节点PU的电位通过第二电位保持晶体管M11、第一控制晶体管M12、第二控制晶体管13和第一电位保持晶体管14进行高电位保持，即通过上拉节点状态保持电路3对上拉节点PU的电位进行保持，避免了上拉节点PU电位的下降，从而保证了下一阶段移位寄存器的稳定输出，而此时第一时钟信号端CLK发出的第一时钟信号为低电平信号，移位寄存器无输出，避免了移位寄存器的输出对触控信号进行干扰，保证了触控的功能。同时，由于其他行的上拉节点PU处于低电平，上拉节点状态保持电路3进行低电平保持，所以不影响其他行的后续工作，触控阶段结束后，继续T2阶段的工作。
若无上拉节点状态保持电路3对上拉节点PU的电位进行保持，由于第二输入晶体管M2和第二下拉晶体管M10会有漏电现象，使上拉节点PU的电位被拉低，这样触控阶段结束后。移位寄存器会出现无输出或者输出电压过低的问题，具体时序图如图11所示。
需要说明的是，触控阶段可以位于实施例1中4个阶段中任意阶段之间，上述仅是以在T1阶段和T2阶段之间为例进行说明，在其他阶段之间时工作 原理相同，在此不再详述。
在上述移位寄存器应用于Touch in cell触摸屏的H-Blank模式时，移位寄存器各阶段的工作过程与实施例1中的各阶段的工作过程相同，在此就不再赘述。
除非另有定义，这里使用的所有术语(包括技术和科学术语)具有与本发明本公开所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
上面是对本发明本公开的说明，而不应被认为是对其的限制。尽管描述了本发明本公开的若干示例性实施例，但本领域技术人员将容易地理解，在不背离本发明本公开的新颖教学和优点的前提下可以对示例性实施例进行许多修改。因此，所有这些修改都意图包含在权利要求书所限定的本发明本公开范围内。应当理解，上面是对本发明本公开的说明，而不应被认为是限于所公开的特定实施例，并且对所公开的实施例以及其他实施例的修改意图包含在所附权利要求书的范围内。本发明本公开由权利要求书及其等效物限定。

Claims (20)

  1. 一种移位寄存器，包括：
    第一输入电路，所述第一输入电路配置成将输入信号输入至上拉节点；
    上拉节点状态保持电路，所述上拉节点状态保持电路的第一端连接到第三参考信号端，所述上拉节点状态保持电路的第二端连接到第四参考信号端，所述上拉节点状态保持电路的第三端连接到所述上拉节点，所述上拉节点状态保持电路配置成在所述上拉节点的电位为第一电位时，将所述第三参考信号端的第三参考信号提供给所述上拉节点，其中所述第三参考信号用于将所述上拉节点的电位保持为第一电位，在所述上拉节点的电位为第二电位时，将第四参考信号端的第四参考信号提供给所述上拉节点，其中所述第四参考信号用于将所述上拉节点的电位保持为第二电位；以及
    输出电路，所述输出电路配置成在所述上拉节点的电位的控制下在栅极信号输出端输出栅极开启信号。
  2. 如权利要求1所述的移位寄存器，其中所述上拉节点状态保持电路包括控制子电路、第一电位保持子电路以及第二电位保持子电路，其中，
    所述控制子电路的第一端连接到所述第三参考信号端，所述控制子电路的第二端连接到所述上拉节点，所述控制子电路的第三端连接到所述第四参考信号端，所述控制子电路的第四端连接到所述第二电位保持子电路的第一端，所述控制子电路配置成在所述上拉节点的电位的控制下输出控制信号并控制所述第二电位保持子电路的导通和关断；
    所述第一电位保持子电路的第一端连接到所述第三参考信号端，所述第一电位保持子电路的第二端连接到上拉节点以及所述第二电位保持子电路，所述第一电位保持子电路配置成当所述第二电位保持子电路关断时，将所述第三参考信号输入到所述上拉节点；以及
    所述第二电位保持子电路的第一端连接到所述控制子电路，所述第二电位保持子电路的第二端连接到所述上拉节点，所述第二电位保持子电路的第三端连接到所述第四参考信号端，第二电位保持子电路配置成当所述第二电位保持子电路在所述控制信号的控制下导通时，所述第二电位保持子电路将所述第四参考信号输入到所述上拉节点。
  3. 如权利要求2所述的移位寄存器，其中所述控制子电路包括第一控制晶体管和第二控制晶体管，其中，
    所述第一控制晶体管的栅极与所述上拉节点相连，所述第一控制晶体管的第一极与所述第四参考信号端相连，所述第一控制晶体管的第二极连接到所述第二电位保持子电路和所述第二控制晶体管的第二极；
    所述第二控制晶体管的栅极和所述第二控制晶体管的第一极相连并连接到所述第三参考信号端。
  4. 如权利要求2或3所述的移位寄存器，其中所述第一电位保持子电路包括第一电位保持晶体管，所述第一电位保持晶体管的栅极和所述第一电位保持晶体管的第一极相连并连接到所述第三参考信号端，所述第一电位保持晶体管的第二极与所述上拉节点相连。
  5. 如权利要求2-4所述的移位寄存器，其中所述第二电位保持子电路包括第二电位保持晶体管，所述第二电位保持晶体管的栅极连接到所述第一控制晶体管的第二极，所述第二电位保持晶体管的第一极与所述第四参考信号端相连，所述第二电位保持晶体管的第二极与所述上拉节点相连。
  6. 如权利要求3所述的移位寄存器，其中所述第一控制晶体管的沟道宽长比大于所述第二控制晶体管的沟道宽长比。
  7. 如权利要求5所述的移位寄存器，其中所述第二电位保持晶体管的沟道宽长比大于所述第一电位保持晶体管的沟道宽长比。
  8. 如权利要求1-7所述的移位寄存器，其中所述第一输入电路包括第一输入晶体管，其中，
    所述第一输入晶体管的栅极与输入信号端相连，所述第一输入晶体管的第一极与第一参考信号端相连，所述第一输入晶体管的第二极与所述上拉节点相连。
  9. 如权利要求1-8所述的移位寄存器，还包括：第二输入电路，所述第二输入电路的第一端连接到复位信号端，所述第二输入电路的第二端连接到第二参考信号端，所述第二输入电路的第三端连接到所述上拉节点，其中，
    所述第二输入电路配置成在所述复位信号端的复位信号的控制下将所述第二参考信号端的信号提供给所述上拉节点。
  10. 如权利要求9所述的移位寄存器，其中所述第二输入电路包括第二输入晶体管，其中，
    所述第二输入晶体管的栅极与所述复位信号端相连，所述第二输入晶体管的第一极与所述第二参考信号端相连，所述第二输入晶体管的第二极与所述上拉节点相连。
  11. 如权利要求1-10所述的移位寄存器，还包括：下拉控制电路，所述下拉控制电路的第一端连接到所述上拉节点，所述下拉控制电路的第二端连接到所述第三参考信号端，所述下拉控制电路的第三端连接到所述第四参考信号端以及所述下拉控制电路的第四端连接到所述移位寄存器的下拉节点，其中，
    所述下拉控制电路配置成在所述上拉节点为所述第一电位时，将所述第四参考信号端的信号提供给所述下拉节点，在所述上拉节点为所述第二电位时，将所述第三参考信号端的信号提供给所述下拉节点。
  12. 如权利要求11所述的移位寄存器，其中，所述下拉控制电路包括：第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管和第四下拉控制晶体管；其中，
    所述第一下拉控制晶体管的栅极与所述上拉节点相连，所述第一下拉控制晶体管的第一极与所述第四参考信号端相连，所述第一下拉控制晶体管的第二极与所述下拉节点相连；
    所述第二下拉控制晶体管的栅极与所述上拉节点相连，所述第二下拉控制晶体管的第一极与所述第四参考信号端相连，所述第二下拉控制晶体管的第二极分别与所述第三下拉控制晶体管的第二极和所述第四下拉控制晶体管的栅极相连；
    所述第三下拉控制晶体管的栅极分别与所述第四下拉控制晶体管的第二极和所述第二下拉控制晶体管的第二极相连，所述第三下拉控制晶体管的第一极与所述第三参考信号端相连，所述第三下拉控制晶体管的第二极与所述下拉节点相连；
    所述第四下拉控制晶体管的栅极和所述第四下拉控制晶体管第一极相连并连接到所述第三参考信号端，所述第四下拉控制晶体管第二极连接到所述 第三下拉控制晶体管的栅极和所述第二下拉控制晶体管的第二极。
  13. 如权利要求1-12所述的移位寄存器，还包括：下拉电路，所述下拉电路的第一端连接到所述下拉节点，所述下拉电路的第二端连接到所述上拉节点，所述下拉电路的第三端连接到所述栅极信号输出端，所述下拉电路的第四端连接到所述第四参考信号端，其中，
    所述下拉电路配置成在所述下拉节点的电位的控制下将所述第四参考信号端的信号提供给所述上拉节点和所述栅极信号输出端。
  14. 如权利要求13所述的移位寄存器，其中，所述下拉电路包括：第一下拉晶体管和第二下拉晶体管；其中，
    所述第一下拉晶体管的栅极与所述下拉节点相连，所述第一下拉晶体管的第一极与所述第四参考信号端相连，所述第一下拉晶体管的第二极与所述栅极信号输出端相连；
    所述第二下拉晶体管的栅极与所述下拉节点相连，所述第二下拉晶体管的第一极与所述第四参考信号端相连，所述第二下拉晶体管的第二极与所述上拉节点相连。
  15. 如权利要求1-14所述的移位寄存器，其中，所述输出电路包括：输出晶体管和第一电容；其中，
    所述输出晶体管的栅极与所述上拉节点相连，所述输出晶体管的第一极与第一时钟信号端相连，所述输出晶体管的第二极与所述栅极信号输出端相连；以及
    所述第一电容的第一端连接所述上拉节点，所述第一电容的第二端连接所述栅极信号输出端。
  16. 如权利要求1-15所述的移位寄存器，还包括：放噪电路，其中，所述放噪电路的第一端连接所述栅极信号输出端，所述放噪电路的第二端连接所述上拉节点，所述放噪电路的第三端连接所述第四参考信号端，所述放噪电路的第四端连接放噪信号端；
    所述放噪电路配置在所述放噪信号端的放噪信号的控制下将所述第四参考信号端的信号提供给所述栅极信号输出端和所述上拉节点。
  17. 一种栅极驱动电路，所述栅极驱动电路包括级联的多个如权利要求 1-16任一项所述的移位寄存器。
  18. 一种显示装置，所述显示装置包括如权利要求17所述的栅极驱动电路。
  19. 一种用于如权利要求1-16所述的移位寄存器的驱动方法，包括：
    接收输入信号，并根据所述输入信号将所述上拉节点上拉至导通电平；
    利用所述上拉节点电位保持电路将所述上拉节点的电位保持为导通电平；
    接收第一时钟信号，并基于所述第一时钟信号，在所述上拉节点的电位的控制下在所述输出端处输出栅极开启信号。
  20. 如权利要求19所述的驱动方法，还包括：
    接收复位信号，根据所述复位信号将所述上拉节点下拉至截止电平；
    利用所述上拉节点电位保持电路将所述上拉节点的电位保持为截止电平。
PCT/CN2018/088416 2017-08-17 2018-05-25 移位寄存器及其驱动方法、栅极驱动电路、显示装置 WO2019033818A1 (zh)

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