WO2019205962A1 - 一种移位寄存器单元、栅极驱动电路、驱动方法及显示装置 - Google Patents

一种移位寄存器单元、栅极驱动电路、驱动方法及显示装置 Download PDF

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Publication number
WO2019205962A1
WO2019205962A1 PCT/CN2019/082438 CN2019082438W WO2019205962A1 WO 2019205962 A1 WO2019205962 A1 WO 2019205962A1 CN 2019082438 W CN2019082438 W CN 2019082438W WO 2019205962 A1 WO2019205962 A1 WO 2019205962A1
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Prior art keywords
node
electrically connected
voltage
circuit
transistor
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PCT/CN2019/082438
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English (en)
French (fr)
Inventor
王志冲
韩承佑
商广良
郑皓亮
袁丽君
姚星
韩明夫
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/497,199 priority Critical patent/US11069274B2/en
Publication of WO2019205962A1 publication Critical patent/WO2019205962A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • Embodiments of the present disclosure relate to the field of display, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the gate driving circuit may include a multi-stage shift register unit GOA, and each stage shift register unit drives one line of pixels.
  • GOA multi-stage shift register unit
  • each stage shift register unit drives one line of pixels.
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a shift register unit including:
  • a first control sub-circuit configured to receive the first voltage signal and write the first voltage signal to the first node under control of the first voltage signal; and receive the second voltage signal and at the second voltage Writing the second voltage signal to the second node under control of the signal;
  • a first voltage dividing sub-circuit electrically connected to the first control sub-circuit and an output signal terminal, the first voltage dividing sub-circuit being configured to receive an output signal from the output signal end, and under the control of the output signal, Writing a third voltage signal to the first node; and writing the third voltage signal to the second node under control of the output signal;
  • the charging and discharging electronic circuit is configured to receive the first clock Signaling, and under the control of the first clock signal, the voltage of the first node, and the voltage of the second node, writing a first input signal from the first input signal terminal to the third node or a second input signal from the second input signal terminal is written to the third node;
  • An output sub-circuit electrically connected to the charging and discharging electronic circuit and the output signal terminal, the output sub-circuit being configured to output a second clock signal at the output signal end under voltage control of the third node .
  • the first control sub-circuit includes a first transistor and a second transistor; a gate of the first transistor and a first electrode are electrically connected to provide a first voltage signal end of the first voltage signal, and a second polarity Connecting the first node; a gate and a first pole of the second transistor are respectively electrically connected to a second voltage signal end that provides the second voltage signal, and a second pole is electrically connected to the second node.
  • the first voltage dividing sub-circuit includes a third transistor and a fourth transistor; a gate of the third transistor is electrically connected to the output signal terminal, a first pole is electrically connected to the first node, and a second pole is electrically connected Connecting a third voltage signal end that provides the third voltage signal; a gate of the fourth transistor is electrically connected to the output signal end, a first pole is electrically connected to the second node, and a second pole is electrically connected to the first Three voltage signal terminals.
  • the charging and discharging electronic circuit includes a forward charging and discharging electronic circuit and a negative charging and discharging electronic circuit.
  • the forward charging and discharging electronic circuit includes a fifth transistor and a sixth transistor, wherein a gate of the fifth transistor is electrically connected to provide a first clock signal end of the first clock signal, and a first pole is electrically connected to the first An input signal terminal, the second pole is electrically connected to the first pole of the sixth transistor; the gate of the sixth transistor is electrically connected to the first node, and the second pole is electrically connected to the third node;
  • the charging and discharging electronic circuit includes a seventh transistor and a eighth transistor, wherein a gate of the seventh transistor is electrically connected to the first clock signal end, a first pole is electrically connected to the second input signal end, and a second pole is electrically connected a first pole of the eighth transistor; a gate of the eighth transistor electrically connected to the second node, and a second pole electrically connected to the third node.
  • the output subcircuit includes a first capacitor and a ninth transistor.
  • the first pole of the first capacitor is electrically connected to the third node, and the second pole is electrically connected to the output signal end;
  • the gate of the ninth transistor is electrically connected to the third node, the first pole is electrically connected to provide a second clock signal end of the second clock signal, and the second pole is electrically connected to the output signal end.
  • the shift register unit further includes: a first noise reduction sub-circuit configured to write the third voltage signal under control of a voltage of the first node or a voltage of the second node Said output signal terminal.
  • the first noise reduction sub-circuit includes a tenth transistor and a eleventh transistor, a gate of the tenth transistor is electrically connected to the first node, and a first pole is electrically connected to the output signal end, and the second pole Electrically connecting the third voltage signal end; the gate of the eleventh transistor is electrically connected to the second node, the first pole is electrically connected to the output signal end, and the second pole is electrically connected to the third voltage signal end .
  • the shift register unit further includes a second control sub-circuit, a second voltage dividing sub-circuit, and a second noise reduction sub-circuit; the second control sub-circuit is configured to receive the first voltage signal, and in the Writing the first voltage signal to the fourth node under control of the first voltage signal; and receiving the second voltage signal, and writing the second voltage signal under the control of the second voltage signal Five nodes
  • the second voltage dividing sub-circuit is configured to write a voltage of the third voltage signal to the fourth node under voltage control of the third node; and under voltage control of the third node Writing the third voltage signal to the fifth node;
  • the second noise reduction sub-circuit is configured to write the third voltage signal to the third node under control of a voltage of the fourth node or the fifth node.
  • An embodiment of the present disclosure further provides a gate driving circuit comprising: N stages of a shift register unit according to an embodiment of the present disclosure; wherein a first input signal end of the nth stage shift register unit is electrically connected to an nth- The output signal terminal of the shift register unit is electrically connected to the output signal terminal of the n+1th shift register unit, N is an integer greater than or equal to 4, and n is greater than 1 and an integer less than N.
  • Embodiments of the present disclosure also provide a display device including a gate driving circuit according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a driving method applied to a shift register unit according to an embodiment of the present disclosure, where the driving method includes:
  • the output signal circuit is controlled to output the second clock signal by the output sub-circuit under the voltage control of the third node.
  • Figure 1 is a block diagram showing the structure of a bidirectional scanning GOA unit
  • FIG. 2A shows a schematic block diagram of an example structure of a shift register unit in accordance with an embodiment of the present disclosure
  • 2B shows an example structural diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 3A illustrates a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3B illustrates a signal timing diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 4 illustrates an equivalent circuit diagram of a shift register unit in a first time period in accordance with an embodiment of the present disclosure
  • FIG. 5 illustrates an equivalent circuit diagram of a shift register unit in a second time period in accordance with an embodiment of the present disclosure
  • FIG. 6 illustrates a structural diagram of another example shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 7 illustrates a structural diagram of another example shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 8 is a block diagram showing a structure of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic structural view of a display device according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic structural diagram of a bidirectional scan shift register unit.
  • one end of the charge and discharge circuit 10, that is, the first pole of the first transistor M1 is directly connected to the DC voltage terminal VDD.
  • VDD is high during forward scanning and VDD is low during negative scanning, which causes the active layer of transistor M1 in charging and discharging circuit 10 to withstand stress stress for a long time, resulting in easy threshold voltage Vth of M1.
  • a negative offset occurs. Therefore, the transistor M1 is prone to generate leakage current, which affects the voltage of the PU point, thereby affecting the output signal voltage of the output signal terminal Output.
  • the Vth of the first transistor M1 is negatively shifted.
  • the three transistors M3 are not turned on, which in turn affects the normal output of the shift register unit.
  • the source and the drain of the switching transistor are used symmetrically, so that the source and the drain thereof are interchangeable.
  • the gate may be referred to as a gate, one of the source and the drain is referred to as a "first pole", and the other of the source and the drain is referred to as " The second pole.”
  • a description will be given by taking a switching transistor as an N-type thin film transistor as an example. Those skilled in the art will appreciate that embodiments of the present disclosure are obviously applicable to the case where the switching transistor is a P-type thin film transistor.
  • the "first pole" is the source
  • the “second pole” is the drain; of course, the "first pole” may be the drain and the “second pole” may be the source.
  • the shift register unit may include a first control sub-circuit 21, a first voltage dividing sub-circuit 22, a charging and discharging electronic circuit 23, and an output sub-circuit 24.
  • the first control sub-circuit 21 can be electrically connected to the first voltage signal input terminal VDD_A, the second voltage signal input terminal VDD_B, and the first node PD_A and the second node PD_B, and configured as the first at the first voltage signal input terminal VDD_A. Under the control of the voltage signal, the first voltage signal of the first voltage signal input terminal VDD_A is written into the first node PD_A; and under the control of the second voltage signal of the second voltage signal input terminal VDD_B, the second voltage signal is input to the terminal VDD_B The second voltage signal is written to the second node PD_B.
  • the first voltage dividing sub-circuit 22 is electrically connected to the first control sub-circuit 21 and the output signal terminal Output, the third voltage signal input terminal VGL, the first node PD_A and the second node PD_B, respectively, and configured to be at the output signal terminal Output. Under the control of the output signal, the third voltage signal of the third voltage signal input terminal VGL is written to the first node PD_A, and the third voltage signal is written to the second node PD_B.
  • the input terminal CLKB and the third node PU are electrically connected, and are configured to control the first input signal under the control of the first clock signal of the first clock signal input terminal CLKB, the voltage of the first node PD_A, and the voltage of the second node PD_B.
  • the voltage of the terminal Forward is written to the third node PU or the voltage of the second input signal terminal Backward is written to the third node PU.
  • the output sub-circuit 24 is electrically connected to the charging and discharging electronic circuit 23, the third node PU, the second clock signal input terminal CLK and the output signal terminal Output, respectively, and is configured to be under the voltage control of the third node PU at the output signal terminal Output.
  • a second clock signal from the second clock signal input CLK is output.
  • the first input signal Forward or the second input signal Backward is used as the input of the charging and discharging electronic circuit 23 by the first control sub-circuit 21 under the control of the first voltage signal VDD_A and the second voltage signal VDD_B, respectively.
  • the signal which in turn controls the shift register unit, performs a forward scan or a negative scan.
  • the shift register unit SR for the present n-stage shift register unit SR, the shift register unit SR a signal output Output n-1, a first input signal terminal is electrically connected to the shift register unit SR n-Forward, and a lower The output signal terminal Output of the shift register unit SR n+1 is electrically connected to the second input signal terminal Backward of the shift register unit SR n .
  • the forward scan the output signal of the shift register unit SR n-1 of the previous stage is used as the input signal of the charge and discharge electronic circuit 23 of the shift register unit SR n .
  • the output signal of the shift register unit SR n+1 of the next stage is used as the input signal of the charge and discharge electronic circuit 23 of the shift register unit SR n .
  • FIG. 2B illustrates an example structural diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • the first control sub-circuit 21 may include a first transistor M1 and a second transistor M2.
  • the gate and the first pole of the first transistor M1 are electrically connected to provide a first voltage signal end of the first voltage signal VDD_A, and the second pole is electrically connected to the first node PD_A;
  • the gate and the first pole of the second transistor M2 are respectively electrically A second voltage signal terminal that supplies the second voltage signal VDD_B is connected, and the second electrode is electrically connected to the second node PD_B.
  • the first voltage dividing sub-circuit 22 may include a third transistor M3 and a fourth transistor M4.
  • the gate of the third transistor M3 is electrically connected to the output signal terminal Output, the first pole is electrically connected to the first node PD_A, the second pole is electrically connected to provide the third voltage signal end of the third voltage signal VGL; and the gate of the fourth transistor M4 is electrically The output signal terminal Output is connected, the first pole is electrically connected to the second node PD_B, and the second pole is electrically connected to the third voltage signal terminal.
  • the charging and discharging electronic circuit 23 may include a forward charging and discharging electronic circuit and a negative charging and discharging electronic circuit.
  • the forward charging and discharging electronic circuit is configured to write the voltage of the first input signal Forward to the third node PU under the control of the voltage of the first clock signal CLKB and the first node PD_A.
  • the positive charging and discharging electronic circuit includes a fifth transistor M5 and a sixth transistor M6.
  • the gate of the fifth transistor M5 is electrically connected to provide a first clock signal end of the first clock signal CLKB, and the first pole is electrically connected to the first input signal terminal Forward.
  • the second pole is electrically connected to the first pole of the sixth transistor M6.
  • the gate of the sixth transistor M6 is electrically connected to the first node PD_A, and the second pole is electrically connected to the third node PU.
  • the negative charging and discharging electronic circuit is configured to write the second input signal Backward to the third node PU under the control of the voltages of the first clock signal CLKB and the second node PD_B.
  • the negative charging and discharging electronic circuit includes a seventh transistor M7 and an eighth transistor M8.
  • the gate of the seventh transistor M7 is electrically connected to the first clock signal terminal CLKB, the first electrode is electrically connected to the second input signal terminal Backward, and the second electrode is electrically connected.
  • the first pole of the eighth transistor M8; the gate of the eighth transistor M8 is electrically connected to the second node PD_B, and the second pole is electrically connected to the third node PU.
  • the output sub-circuit 24 may include a first capacitor C1 and a ninth transistor M9.
  • the first pole of the first capacitor C1 is electrically connected to the third node PU, and the second pole is electrically connected to the output signal terminal.
  • the gate of the ninth transistor M9 is electrically connected.
  • the third node PU, the first pole is electrically connected to provide a second clock signal end of the second clock signal CLK, and the second pole is electrically connected to the output signal end Output.
  • Another embodiment of the present application also provides a driving method applied to a shift register unit according to an embodiment of the present disclosure.
  • the driving method 30 can include the following steps.
  • step S301 the first input signal or the second input signal is written to the third node under control of the first input signal or the second input signal during a first time period.
  • the step can be performed by the first control sub-circuit, the first partial voltage sub-circuit, and the charge and discharge electronic circuit.
  • step S302 in the second period, under the voltage control of the third node, the output signal terminal is controlled to output the second clock signal.
  • this step can be performed by an output sub-circuit.
  • the first control sub-circuit 21 writes the first voltage signal to the first node PD_A under the control of the first voltage signal VDD_A; meanwhile, the charging and discharging electronic circuit 23 is at the first
  • the first input signal Forward is written to the third node PU under the control of the clock signal CLKB and the voltage of the first node PD_A. Therefore, at this time, the first input signal Forward is used as an input signal of the shift register unit.
  • the first time period can be referred to as an "input time period.”
  • the output sub-circuit 24 outputs the second clock signal CLK at the output signal terminal Output under the voltage control of the third node PU.
  • the first voltage dividing sub-circuit 22 writes the third voltage signal VGL to the first node PD_A under the voltage control of the output signal terminal Output.
  • the second time period can be referred to as an "output period.”
  • the charging and discharging electronic circuit 23 can also write the first input signal Forward into the third node PU under the control of the voltage of the first clock signal and the first node PD_A to implement resetting of the third node PU.
  • the first control sub-circuit 21 writes the second voltage signal to the second node PD_B under the control of the second voltage signal VDD_B; meanwhile, the charging and discharging electronic circuit 23 is in the The second input signal Backward is written to the third node PU under the control of the voltage of the clock signal CLKB and the second node PD_B. Therefore, at this time, the second input signal Backward is used as an input signal of the shift register unit.
  • the output sub-circuit 24 outputs the second clock signal CLK at the output signal terminal Output under the voltage control of the third node PU; meanwhile, the first voltage dividing sub-circuit 22 is controlled by the output signal Output.
  • the three voltage signal VGL is written to the second node PD_B.
  • the charging and discharging electronic circuit 23 can also write the second input signal Backward into the third node PU according to the voltage control of the first clock signal and the second node PD_B, thereby implementing the Reset of the three-node PU.
  • the driving method may further include:
  • the first input signal or the second input signal is written to the third node, and the third node is reset.
  • this step can be performed by a charge and discharge electronic circuit.
  • the first input signal is written to the third node by the charging and discharging electronic circuit control, and the third node is reset.
  • the negative scan the second input signal is written to the third node by the charge and discharge electronic circuit control, and the third node is reset.
  • the output signal of the shift register unit of the next stage can also be used as the reset signal of the shift register unit of the previous stage, and in the negative scan, the shift register unit of the previous stage can also be used.
  • the output signal is used as a reset signal of the shift register unit of the next stage, etc., and the reset signal is not specifically limited in this application.
  • the first input signal Forward and the second input signal Backward may be, for example, a pulse signal such as an STV frame start signal, wherein the pulse signal is, for example, high in a scanning period of one line in a display period of one frame.
  • the effective level of the level may be, for example, the active layer of the TFT in the charging and discharging electronic circuit 23 .
  • the threshold voltage of the TFT is not negatively shifted, thereby facilitating the third node PU voltage, that is, the output sub-circuit 24.
  • the gate voltage remains stable, allowing the shift register unit to output normally.
  • FIG. 3B shows a signal timing diagram of one cycle in which the drive gate performs forward scanning, in which STV represents the first input signal Forward as an example in the forward scanning.
  • 4 illustrates an equivalent circuit diagram of a shift register unit in a first time period according to an embodiment of the present disclosure
  • FIG. 5 illustrates an equivalent circuit schematic of a shift register unit in a second time period according to an embodiment of the present disclosure. The operation timing of the shift register unit according to an embodiment of the present disclosure will be described next with reference to FIGS. 2A, 2B, 3A, 3B, 4, and 5.
  • the first voltage signal VDD_A is at a high level
  • the second voltage signal VDD_B is at a low level.
  • the transistor M1 is turned on, and the voltage of the first node PD_A is at a high level.
  • the sixth transistor M6 is controlled to be turned on, while the first clock signal CLKB is at a high level, and the fifth transistor M5 is also turned on, and the first input is turned on.
  • the signal Forward (STV signal) is written to the third node PU, and the STV signal of the T1 period is high, so the voltage of the third node PU in the T1 period is high.
  • the first clock signal CLKB becomes a low level
  • the fifth transistor M5 is controlled to be turned off. Since the second clock signal CLK of the T2 period is at a high level, the voltage of the third node PU continues to rise under the bootstrap effect of the first capacitor C1, and the ninth transistor M9 is controlled to be turned on, so the output signal is output in the T2 period.
  • the terminal output outputs a second clock signal of a high level.
  • the third transistor M3 is controlled to be turned on, and the third voltage signal VGL is written into the first node PD_A, and the voltage of the first node PD_A is lowered due to the voltage division of the third transistor M3.
  • An equivalent circuit diagram of the shift register unit in the second period is shown with reference to FIG.
  • the output signal terminal Output has no output
  • the third transistor M3 is turned off, that is, the voltage division of the third transistor M3 is eliminated
  • the voltage of the first node PD_A is raised
  • the sixth transistor M6 is controlled to be turned on.
  • the first clock signal CLKB is at a high level
  • the fifth transistor M5 is also controlled to be turned on. Therefore, the first input signal Forward is written into the third node PU during this period, and the first input signal Forward of the period is low. Therefore, the voltage of the third node PU is at a low level during this period, thereby realizing resetting of the third node PU.
  • the shift register unit When the shift register unit according to an embodiment of the present disclosure is used for negative scanning, it is only necessary to input a low level to the first voltage signal input terminal VDD_A and a high level to the second voltage signal input terminal VDD_B, at this time, the second The input signal Backward will be used as the input signal of the charging and discharging electronic circuit 23.
  • the second The input signal Backward will be used as the input signal of the charging and discharging electronic circuit 23.
  • the first pole of the fifth transistor is electrically connected to the first input signal terminal Forward
  • the first pole of the seventh transistor is electrically connected to the second input signal end Backward
  • the STV frame start signal input by the signal terminal Backward is a pulse signal.
  • the active layer of the TFT in the charging and discharging electronic circuit 23 is not subjected to stress for a long time, and the threshold voltage thereof is not negatively shifted, thereby facilitating the voltage of the third node PU, that is, the gate of the output sub-circuit 24.
  • the pole control voltage is maintained so that the shift register unit outputs normally.
  • the shift register unit may further include a first noise reduction sub-circuit 61, respectively, with an output signal terminal Output, a first node PD_A, a second node PD_B, and a third voltage signal.
  • the input terminal VGL is electrically connected, and is configured to write the third voltage signal VGL to the output signal terminal Output under the control of the voltage of the first node PD_A or the voltage of the second node PD_B.
  • the first noise reduction sub-circuit 61 is mainly used to write a low-level third voltage signal VGL to the output signal terminal Output during the reset period after the first period and the second period, thereby performing noise reduction on the output signal terminal Output, Avoid outputting signals during non-output periods.
  • the first noise reduction sub-circuit 61 may include a tenth transistor M10 and an eleventh transistor M11, the gate of the tenth transistor M10 is electrically connected to the first node PD_A, the first pole is electrically connected to the output signal terminal Output, and the second pole is electrically The connection is to receive the third voltage signal VGL; the gate of the eleventh transistor M11 is electrically connected to the second node PD_B, the first pole is electrically connected to the output signal terminal Output, and the second pole is electrically connected to receive the third voltage signal VGL.
  • the forward scanning is taken as an example for description.
  • the voltage of the first node PD_A is at a high level, and the tenth transistor M10 is turned on, so the third level of the low level is
  • the voltage signal VGL is written to the output signal terminal Output to denoise the output signal terminal Output to avoid outputting the signal during the non-output period.
  • the shift register unit may further include a second control sub-circuit 62, a second voltage dividing sub-circuit 63, and a second noise reduction sub-circuit 64.
  • the second control sub-circuit 62 is electrically connected to the first voltage signal input terminal VDD_A, the second voltage signal input terminal VDD_B, and the fourth node PD_Aa and the fifth node PD_Bb, respectively, and configured to be under the control of the first voltage signal VDD_A
  • the first voltage signal VDD_A is written to the fourth node PD_Aa; under the control of the second voltage signal VDD_B, the second voltage signal VDD_B is written to the fifth node PD_Bb.
  • the second voltage dividing sub-circuit 63 is electrically connected to the third node PU, the fourth node PD_Aa, the fifth node PD_Bb, and the third voltage signal input terminal VGL, respectively, and is configured to be third under the voltage control of the third node PU.
  • the voltage signal VGL is written to the fourth node PD_Aa, and the third voltage signal VGL is written to the fifth node PD_Bb.
  • the second noise reduction sub-circuit 64 is electrically connected to the third node PU, the fourth node PD_Aa, the fifth node PD_Bb, and the third voltage signal input terminal VGL, respectively, and configured to be voltage-controlled at the fourth node PD_Aa or the fifth node PD_Bb.
  • the third voltage signal VGL is written to the third node PU.
  • the second control sub-circuit 62 and the second voltage dividing sub-circuit 63 are mainly used to control the voltages written in the fourth node PD_Aa and the fifth node PD_Bb; the second noise reduction sub-circuit 64 is mainly used in the fourth node PD_Aa or the fifth Under the voltage control of the node PD_Bb, the third voltage signal VGL is written into the third node PU, so that the third node PU is denoised to avoid the pulse fluctuation of the third node PU, so that the ninth transistor M9 is turned on, avoiding the non- Output period output signal.
  • the second control sub-circuit 62 may include a twelfth transistor M12 and a thirteenth transistor M13.
  • the gate and the first pole of the twelfth transistor M12 are electrically connected to the first voltage signal input terminal VDD_A, respectively, and the second electrode is electrically connected to the fourth node PD_Aa; the gate and the first pole of the thirteenth transistor M13 are electrically connected to The second voltage signal is input to the VDD_B, and the second electrode is electrically connected to the fifth node PD_Bb.
  • the second voltage dividing sub-circuit 63 includes a fourteenth transistor M14 and a fifteenth transistor M15.
  • the gate of the fourteenth transistor M14 is electrically connected to the third node PU, the first pole is electrically connected to the fourth node PD_Aa, and the second pole is electrically connected.
  • the third voltage signal input terminal VGL; the gate of the fifteenth transistor M15 is electrically connected to the third node PU, the first pole is electrically connected to the fifth node PD_Bb, and the second pole is electrically connected to the third voltage signal input terminal VGL.
  • the second noise reduction sub-circuit 64 includes a sixteenth transistor M16 and a seventeenth transistor M17.
  • the gate of the sixteenth transistor M16 is electrically connected to the fourth node PD_Aa, the first pole is electrically connected to the third node PU, and the second pole is electrically connected.
  • the gate of the seventeenth transistor M17 is electrically connected to the fifth node PD_Bb, the first pole is electrically connected to the third node PU, and the second pole is electrically connected to the third voltage signal input terminal VGL.
  • the forward scan is taken as an example.
  • the first voltage signal VDD_A is at a high level
  • the second voltage signal VDD_B is at a low level.
  • the twelfth transistor M12 is turned on, and the voltage of the fourth node PD_Aa is at a high level.
  • the fourteenth transistor M14 is turned on, and the control writes the third voltage signal VGL to the fourth node PD_Aa.
  • the fourteenth transistor M14 is divided, the voltage of the fourth node PD_Aa is low, and the sixteen transistor M16 is turned off, and the third node PU is not denoised during this period.
  • the voltage of the third node PU is at a low level, turning off the fourteenth transistor M14, that is, the voltage division of the fourteenth transistor M14 is eliminated, so that the voltage of the fourth node PD_Aa rises.
  • the sixteen transistor M16 is turned on.
  • the third node PU is denoised to avoid the pulse fluctuation of the third node PU to turn on the ninth transistor M9 to avoid outputting the signal during the non-output period.
  • the shift register unit may further include a third voltage dividing sub-circuit 71, respectively, with the first input signal terminal Forward and the second input.
  • the signal end Backward, the fourth node PD_Aa, the fifth node PD_Bb, and the third voltage signal input terminal VGL are electrically connected, and configured to write the third voltage signal VGL into the fourth node PD_Aa according to the voltage of the first input signal Forward, according to The voltage of the second input signal Backward writes the third voltage signal VGL to the fifth node PD_Bb.
  • the third voltage dividing sub-circuit 71 may include an eighteenth transistor M18 and a nineteenth transistor M19.
  • the gate of the eighteenth transistor M18 is electrically connected to the first input signal terminal Forward, the first pole is electrically connected to the fourth node PD_Aa, the second pole is electrically connected to the third voltage signal input terminal VGL; the gate of the nineteenth transistor M19 is electrically connected The second input signal end is Backward, the first pole is electrically connected to the fifth node PD_Bb, and the second pole is electrically connected to the third voltage signal input terminal VGL.
  • the forward scanning is taken as an example for example.
  • the voltage input by the first input signal terminal Forward is a high level
  • the eighteenth transistor M18 is turned on, and the third voltage signal VGL is written into the fourth node PD_Aa. That is, the voltage of the fourth node PD_Aa is lowered due to the existence of the divided voltage, and therefore, the voltage of the fourth node PD_Aa is commonly controlled by the fourteenth transistor M14 and the eighteenth transistor M18, thereby making the threshold voltage of the fourteenth transistor M14 Limited to Vth Margin.
  • the step of the third period may further include:
  • the control writes the third voltage signal to the third node, and performs noise reduction on the third node.
  • this step can be performed by the second control sub-circuit, the second voltage dividing sub-circuit, and the second noise reduction sub-circuit.
  • the driving method may include:
  • the control writes the third voltage signal to the output signal end, and performs noise reduction on the output signal end;
  • control writes the third voltage signal to the output signal end, and performs noise reduction on the output signal end.
  • this step can be performed by the first noise reduction sub-circuit.
  • each transistor is not limited to an N-type tube. It can be understood that when each transistor is a P-type tube, the timing of each input signal and the timing of each signal shown in FIG. in contrast.
  • FIG. 8 shows a schematic structural diagram of a gate driving circuit 80 according to an embodiment of the present disclosure.
  • a gate driving circuit according to an embodiment of the present disclosure may include N stages of shift register units according to embodiments.
  • the first input signal terminal Forward of the nth stage shift register unit SR n is electrically connected to the output signal terminal Output of the n-1th shift register unit SR n-1 , and the nth stage shift register unit SR n
  • the two input signal terminals Backward are electrically connected to the output signal terminal Output of the n+1th shift register unit SR n+1
  • N is an integer greater than or equal to 4
  • n is an integer greater than 1 and less than N.
  • the display device 90 can include a gate drive circuit 910 in accordance with an embodiment of the present disclosure.
  • the display device in this embodiment may be any product or component having a display function, such as a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present application provide a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the shift register unit includes a first control sub-circuit, a first voltage dividing sub-circuit, a charging and discharging electronic circuit, and an output sub-circuit.
  • the gate control voltage of the output sub-circuit that is, the voltage of the third node is controlled by the charging and discharging electronic circuit, and the voltage signal input by the first input signal terminal and the second input signal terminal electrically connected to the charging and discharging electronic circuit is pulsed.
  • the signal, in the display period of one frame, the pulse signal is high level only in the scanning duration of one line, and the remaining periods are all low level.
  • the active layer of the TFT in the charging and discharging electronic circuit does not bear stress for a long time, and the threshold voltage thereof does not negatively shift, thereby facilitating the third node voltage, that is, the gate control voltage of the output sub-circuit. Hold, the shift register unit is output normally.
  • a shift register unit, a driving method thereof, a gate driving circuit and a display device are described in detail above.
  • the principles and embodiments of the embodiments of the present disclosure have been described herein with reference to specific examples.
  • the description of the above embodiments is only to assist in understanding the method of the embodiments of the present disclosure and its core idea.
  • the present invention is not limited to the embodiments of the present disclosure.

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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路（80）及显示装置，其中移位寄存器单元包括第一控制子电路（21）、第一分压子电路（22）、充放电子电路（23）和输出子电路（24）。其中，由充放电子电路（23）控制输出子电路（24）的输出信号。与充放电子电路（23）电连接的第一输入信号端和第二输入信号端输入的第一输入信号和第二输入信号为脉冲信号。该移位寄存器单元能保证输出子电路（24）的栅极电压稳定。

Description

一种移位寄存器单元、栅极驱动电路、驱动方法及显示装置
本申请要求于2018年4月26日提交的、申请号为201810385925.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及显示领域，特别是涉及一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
背景技术
在显示装置中，栅极驱动电路可以包括多级移位寄存器单元GOA，每一级移位寄存器单元驱动一行像素。随着显示面板尺寸增大，不能保证移位寄存器单元中各个节点的电压稳定，导致影响GOA单元的正常输出，进而影响显示装置的显示质量。
发明内容
本公开实施例提供了一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。
根据本公开实施例的一个方面，提供了一种移位寄存器单元，包括：
第一控制子电路，被配置为接收第一电压信号，并在第一电压信号的控制下，将所述第一电压信号写入第一节点；以及接收第二电压信号，并在第二电压信号的控制下，将所述第二电压信号写入第二节点；
第一分压子电路，电连接至所述第一控制子电路和输出信号端，第一分压子电路被配置为接收来自输出信号端的输出信号，并在所述输出信号的控制下，将第三电压信号写入所述第一节点；以及在所述输出信号的控制下，将所述第三电压信号写入所述第二节点；
充放电子电路，电连接至所述第一控制子电路、所述第一分压子电路和第一输入信号端、第二输入信号端，所述充放电子电路被配置为接收第一时钟信号，并在所述第一时钟信号、所述第一节点的电压以及所述第二节点的电压的控制下，将来自第一输入信号端的第一输入信号写入所述第三节点或者将来自第二输入信号端的第二输入信号写入所述第三节点；以及
输出子电路，电连接至所述充放电子电路和所述输出信号端，所述输出子电路被配置为在所述第三节点的电压控制下，在所述输出信号端输出第二时钟信号。
例如，所述第一控制子电路包括第一晶体管和第二晶体管；所述第一晶体管的栅极和第一极电连接提供所述第一电压信号的第一电压信号端，第二极电连接所述第一节点；所述第二晶体管的栅极和第一极分别电连接提供所述第二电压信号的第二电压信号端，第二极电连接所述第二节点。
例如，所述第一分压子电路包括第三晶体管和第四晶体管；所述第三晶体管的栅极电连接所述输出信号端，第一极电连接所述第一节点，第二极电连接提供所述第三电压信号的第三电压信号端；所述第四晶体管的栅极电连接所述输出信号端，第一极电连接所述第二节点，第二极电连接所述第三电压信号端。
例如，所述充放电子电路包括正向充放电子电路和负向充放电子电路。所述正向充放电子电路包括第五晶体管和第六晶体管，所述第五晶体管的栅极电连接提供所述第一时钟信号的第一时钟信号端，第一极电连接所述第一输入信号端，第二极电连接所述第六晶体管的第一极；所述第六晶体管的栅极电连接所述第一节点，第二极电连接所述第三节点；所述负向充放电子电路包括第七晶体管和第八晶体管，所述第七晶体管的栅极电连接所述第一时钟信号端，第一极电连接所述第二输入信号端，第二极电连接所述第八晶体管的第一极；所述第八晶体管的栅极电连接所述第二节点，第二极电连接所述第三节点。
例如，所述输出子电路包括第一电容和第九晶体管。所述第一电容的第一极电连接所述第三节点，第二极电连接所述输出信号端；
所述第九晶体管的栅极电连接所述第三节点，第一极电连接提供所述第二时钟信号的第二时钟信号端，第二极电连接所述输出信号端。
例如，所述移位寄存器单元还包括：第一降噪子电路，被配置为在所述第一节点的电压或所述第二节点的电压控制下，将所述第三电压信号写入所述输出信号端。
例如，所述第一降噪子电路包括第十晶体管和第十一晶体管，所述第十晶体管的栅极电连接所述第一节点，第一极电连接所述输出信号端，第二极电连接所述第三电压信号端；所述第十一晶体管的栅极电连接所述第二节点，第一极电连接所述输出信号端，第二极电连接所述第三电压信号端。
例如，所述移位寄存器单元还包括第二控制子电路、第二分压子电路和第二降噪子 电路；所述第二控制子电路被配置为接收第一电压信号，并在所述第一电压信号的控制下，将所述第一电压信号写入第四节点；以及接收第二电压信号，并在所述第二电压信号的控制下，将所述第二电压信号写入第五节点；
所述第二分压子电路被配置为在所述第三节点的电压控制下，将所述第三电压信号的电压写入所述第四节点；以及在所述第三节点的电压控制下，将所述第三电压信号写入所述第五节点；
所述第二降噪子电路，被配置为在所述第四节点或所述第五节点的电压的控制下，将所述第三电压信号写入所述第三节点。
本公开实施例还提供了一种栅极驱动电路，包括：N级根据本公开实施例的移位寄存器单元；其中，第n级移位寄存器单元的第一输入信号端电连接至第n-1移位寄存器单元的输出信号端，第n级移位寄存器单元的第二输入信号端电连接至第n+1移位寄存器单元的输出信号端，N是大于等于4的整数，n是大于1且小于N的整数。
本公开实施例还提供了一种显示装置，包括根据本公开实施例的栅极驱动电路。
本公开实施例还提供了一种驱动方法，应用于根据本公开实施例的移位寄存器单元，所述驱动方法包括：
在第一时段，通过所述第一控制子电路、所述第一分压子电路和所述充放电子电路，在所述第一输入信号或所述第二输入信号的控制下，将所述第一输入信号或者所述第二输入信号写入所述第三节点；以及
在第二时段，通过所述输出子电路，在第三节点的电压控制下，控制所述输出信号端输出所述第二时钟信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出了一种双向扫描GOA单元的结构示意图；
图2A示出了根据本公开实施例的移位寄存器单元的一种示例结构示意框图；
图2B示出了根据本公开实施例的移位寄存器单元的一种示例结构示意图；
图3A示出了根据本公开实施例的移位寄存器单元的驱动方法的流程图；
图3B示出了根据本公开实施例的移位寄存器单元的信号时序图；
图4示出了根据本公开实施例的移位寄存器单元在第一时段的等效电路示意图；
图5示出了根据本公开实施例的移位寄存器单元在第二时段的等效电路示意图；
图6示出了根据本公开实施例的另一示例移位寄存器单元的结构示意图；
图7示出了根据本公开实施例的另一示例移位寄存器单元的结构示意图；
图8示出了根据本公开实施例的栅极驱动电路的结构示意图；以及
图9示出了根据本公开实施例的显示装置的结构示意图。
具体实施方式
为使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
图1示出了一种双向扫描移位寄存器单元的结构示意图。如图1所示，充放电电路10的一端，也就是第一晶体管M1的第一极直接连接直流电压端VDD。在正向扫描过程中VDD为高电平，负向扫描过程中VDD为低电平，这使得充放电电路10内的晶体管M1的有源层长时间承受应力stress，导致M1的阈值电压Vth容易发生负向偏移。因此晶体管M1容易产生漏电流，影响PU点的电压，进而影响输出信号端Output的输出信号电压保持。例如在长时间的正向扫描后第一晶体管M1的Vth发生负向偏移，当再切换为负向扫描时，PU点的电压就会因为M1漏电而不能保持，导致输出模块11中的第三晶体管M3不能导通，进而影响移位寄存器单元的正常输出。
本公开实施例中使用开关晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，根据其功能，可以将栅极称作控制极，将源极和漏极中的一个称为“第一极”，将源极和漏极中的另一个称为“第二极”。在以下示例中以开关晶体管为N型薄膜晶体管为例进行描述。本领域技术人员可以理解，本公开实施例显然可以应用于开关晶体管为P型薄膜晶体管的情况。“第一极”为源极，“第二极”为漏极；当然，也可以是“第一极”为漏极，“第二极”为源极。
本公开实施例提供了一种移位寄存器单元。如图2A所示，该移位寄存器单元可以包括第一控制子电路21、第一分压子电路22、充放电子电路23和输出子电路24。
第一控制子电路21可以与第一电压信号输入端VDD_A、第二电压信号输入端 VDD_B以及第一节点PD_A、第二节点PD_B电连接，被配置为在第一电压信号输入端VDD_A的第一电压信号控制下，将第一电压信号输入端VDD_A的第一电压信号写入第一节点PD_A；以及在第二电压信号输入端VDD_B的第二电压信号控制下，将第二电压信号输入端VDD_B的第二电压信号写入第二节点PD_B。
第一分压子电路22分别与第一控制子电路21和输出信号端Output、第三电压信号输入端VGL、第一节点PD_A以及第二节点PD_B电连接，被配置为在输出信号端Output的输出信号控制下，将第三电压信号输入端VGL的第三电压信号写入第一节点PD_A，以及将第三电压信号写入第二节点PD_B。
充放电子电路23分别与第一控制子电路21、第一分压子电路22、第一输入信号端Forward、第一输入信号端Backward、第一节点PD_A、第二节点PD_B、第一时钟信号输入端CLKB以及第三节点PU电连接，被配置为在第一时钟信号输入端CLKB的第一时钟信号、第一节点PD_A的电压以及第二节点PD_B的电压的控制下，将第一输入信号端Forward的电压写入第三节点PU或者将第二输入信号端Backward的电压写入第三节点PU。
输出子电路24分别与充放电子电路23、第三节点PU、第二时钟信号输入端CLK以及输出信号端Output电连接，被配置为在第三节点PU的电压控制下，在输出信号端Output输出来自第二时钟信号输入端CLK的第二时钟信号。
根据本公开实施例，由第一控制子电路21分别在第一电压信号VDD_A和第二电压信号VDD_B的控制下，将第一输入信号Forward或第二输入信号Backward作为充放电子电路23的输入信号，进而控制该移位寄存器单元进行正向扫描或负向扫描。参照图8，对于本级移位寄存器单元SR n，上一级移位寄存器单元SR n-1的输出信号端Output电连接移位寄存器单元SR n的第一输入信号端Forward，以及下一级移位寄存器单元SR n+1的输出信号端Output电连接移位寄存器单元SR n的第二输入信号端Backward。在执行正向扫描时，将上一级移位寄存器单元SR n-1的输出信号作为移位寄存器单元SR n的充放电子电路23的输入信号。在执行负向扫描时，将下一级移位寄存器单元SR n+1的输出信号作为移位寄存器单元SR n的充放电子电路23的输入信号。
图2B示出了根据本公开实施例的移位寄存器单元的一种示例结构示意图。参照图2B，第一控制子电路21可以包括第一晶体管M1和第二晶体管M2。第一晶体管M1的栅极和第一极分别电连接提供第一电压信号VDD_A的第一电压信号端，第二极电连 接第一节点PD_A；第二晶体管M2的栅极和第一极分别电连接提供第二电压信号VDD_B的第二电压信号端，第二极电连接第二节点PD_B。
第一分压子电路22可以包括第三晶体管M3和第四晶体管M4。第三晶体管M3的栅极电连接输出信号端Output，第一极电连接第一节点PD_A，第二极电连接提供第三电压信号VGL的第三电压信号端；第四晶体管M4的栅极电连接输出信号端Output，第一极电连接第二节点PD_B，第二极电连接第三电压信号端。
充放电子电路23可以包括正向充放电子电路和负向充放电子电路。正向充放电子电路被配置为在第一时钟信号CLKB以及第一节点PD_A的电压的控制下，将第一输入信号Forward的电压写入第三节点PU。正向充放电子电路包括第五晶体管M5和第六晶体管M6，第五晶体管M5的栅极电连接提供第一时钟信号CLKB的第一时钟信号端，第一极电连接第一输入信号端Forward，第二极电连接第六晶体管M6的第一极。第六晶体管M6的栅极电连接第一节点PD_A，第二极电连接第三节点PU。负向充放电子电路被配置为在第一时钟信号CLKB以及第二节点PD_B的电压控制下，将第二输入信号Backward写入第三节点PU。负向充放电子电路包括第七晶体管M7和第八晶体管M8，第七晶体管M7的栅极电连接第一时钟信号端CLKB，第一极电连接第二输入信号端Backward，第二极电连接第八晶体管M8的第一极；第八晶体管M8的栅极电连接第二节点PD_B，第二极电连接第三节点PU。
输出子电路24可以包括第一电容C1和第九晶体管M9，第一电容C1的第一极电连接第三节点PU，第二极电连接输出信号端Output；第九晶体管M9的栅极电连接第三节点PU，第一极电连接提供第二时钟信号CLK的第二时钟信号端，第二极电连接输出信号端Output。
本申请另一实施例还提供了一种驱动方法，应用于根据本公开实施例的移位寄存器单元。如图3A所示，该驱动方法30可以包括以下步骤。
在步骤S301，在第一时段，在所述第一输入信号或所述第二输入信号的控制下，将所述第一输入信号或者所述第二输入信号写入所述第三节点。
例如，该步骤可以由第一控制子电路、第一分压子电路和充放电子电路执行。
在步骤S302，在第二时段，在第三节点的电压控制下，控制所述输出信号端输出所述第二时钟信号。
例如，该步骤可以由输出子电路执行。
以正向扫描为例，在第一时段，第一控制子电路21在第一电压信号VDD_A的控制下，将第一电压信号写入第一节点PD_A；同时，充放电子电路23在第一时钟信号CLKB和第一节点PD_A的电压的控制下，将第一输入信号Forward写入第三节点PU。因此，此时第一输入信号Forward用作移位寄存器单元的输入信号。可以将第一时段称为“输入时段”。
在第二时段，输出子电路24在第三节点PU的电压控制下，在输出信号端Output输出第二时钟信号CLK。同时，第一分压子电路22在输出信号端Output的电压控制下，将第三电压信号VGL写入第一节点PD_A。可以将第二时段称为“输出时段”。
第二时段之后，充放电子电路23还可以在第一时钟信号和第一节点PD_A的电压控制下，将第一输入信号Forward写入第三节点PU，实现对第三节点PU的复位。
以负向扫描为例，在第一时段，第一控制子电路21在第二电压信号VDD_B的控制下，将第二电压信号写入至第二节点PD_B；同时，充放电子电路23在第一时钟信号CLKB和第二节点PD_B的电压控制下，将第二输入信号Backward写入第三节点PU。因此，此时第二输入信号Backward用作移位寄存器单元的输入信号
在第二时段，输出子电路24在第三节点PU的电压控制下，在输出信号端Output输出第二时钟信号CLK；同时，第一分压子电路22在输出信号Output的控制下，将第三电压信号VGL写入第二节点PD_B。
在第二时段之后的第三时段T3，充放电子电路23还可以根据在第一时钟信号和第二节点PD_B的电压控制下，将第二输入信号Backward写入第三节点PU，实现对第三节点PU的复位。
因此，根据本公开实施例，上述的驱动方法还可以包括：
在第三时段T3，将第一输入信号或第二输入信号写入第三节点，对第三节点进行复位。
例如，该步骤可以由充放电子电路执行。在正向扫描时，由充放电子电路控制将第一输入信号写入第三节点，对第三节点进行复位。在负向扫描时，由充放电子电路控制将第二输入信号写入第三节点，对第三节点进行复位。当然，例如在正向扫描时，还可以将下一级移位寄存器单元的输出信号作为上一级移位寄存器单元的复位信号，在负向扫描时，还可以将上一级移位寄存器单元的输出信号作为下一级移位寄存器单元的复位信号等，本申请对复位信号不作具体限定。
在实际应用中，第一输入信号Forward和第二输入信号Backward例如可以是STV帧起始信号等脉冲信号，其中在一帧的显示周期中，该脉冲信号仅在一行的扫描时段内为例如高电平的有效电平。这样，充放电子电路23中的TFT的有源层不会长时间承受应力，TFT的阈值电压也就不会发生负向偏移，从而有利于第三节点PU电压也就是输出子电路24的栅极电压的保持稳定，使移位寄存器单元正常输出。
图3B示出了在驱动栅极进行正向扫描的一个周期的信号时序图，其中以正向扫描时STV表示第一输入信号Forward为例。图4示出了根据本公开实施例的移位寄存器单元在第一时段的等效电路示意图，图5示出了根据本公开实施例的移位寄存器单元在第二时段的等效电路示意图。接下来将参考图2A、图2B、图3A、图3B、图4和图5来描述根据本公开实施例的移位寄存器单元的操作时序。
下面以上述各晶体管均为N型晶体管为例，结合在此情况下各输入信号的时序，对本实施例提供的移位寄存器单元驱动栅极进行正向扫描的过程和原理进行详细介绍。
正向扫描时，第一电压信号VDD_A为高电平，第二电压信号VDD_B为低电平，此时晶体管M1导通，第一节点PD_A的电压为高电平。在第一时段T1，由于第一节点PD_A的电压为高电平，控制第六晶体管M6导通，同时第一时钟信号CLKB为高电平，控制第五晶体管M5也导通，将第一输入信号Forward(STV信号)写入第三节点PU，而T1时段的STV信号为高电平，因此T1时段中第三节点PU的电压为高电平。其中，在第一时段T1，虽然第三节点PU的电压为高电平，控制第九晶体管M9导通，但第二时钟信号CLK为低电平，所以输出信号端Output仍然无输出。参考图4示出了移位寄存器单元在第一时段的等效电路示意图。
在第二时段T2，第一时钟信号CLKB变为低电平，控制第五晶体管M5关断。由于T2时段的第二时钟信号CLK为高电平，在第一电容C1的自举效应作用下第三节点PU的电压继续升高，控制第九晶体管M9导通，所以，T2时段中输出信号端Output输出高电平的第二时钟信号。同时，由于输出信号端Output输出高电平，控制第三晶体管M3导通，将第三电压信号VGL写入第一节点PD_A，由于第三晶体管M3的分压，使第一节点PD_A的电压降低。参考图5示出了移位寄存器单元在第二时段的等效电路示意图。
第二时段T2之后，输出信号端Output无输出，第三晶体管M3关断，也就是第三晶体管M3的分压消除，第一节点PD_A的电压升高，控制第六晶体管M6导通。同时 第一时钟信号CLKB为高电平，控制第五晶体管M5也导通，所以这一时段第一输入信号Forward写入第三节点PU，而此时段的第一输入信号Forward为低电平，因此这一时段第三节点PU的电压为低电平，从而实现对第三节点PU的复位。
当根据本公开实施例的移位寄存器单元用于负向扫描时，只需向第一电压信号输入端VDD_A输入低电平，向第二电压信号输入端VDD_B输入高电平，此时第二输入信号Backward将作为充放电子电路23的输入信号，具体的工作过程和原理可以参考以上对正向扫描的描述，这里不再赘述。
根据本公开实施例，由于第五晶体管的第一极电连接第一输入信号端Forward，第七晶体管的第一极电连接第二输入信号端Backward，而第一输入信号端Forward和第二输入信号端Backward输入的例如STV帧起始信号为脉冲信号。这样，充放电子电路23中的TFT有源层不会长时间承受应力，其阈值电压也就不会发生负向偏移，从而有利于第三节点PU电压，也就是输出子电路24的栅极控制电压的保持，使移位寄存器单元正常输出。
本申请另一实施例中，参照图6，上述的移位寄存器单元还可以包括第一降噪子电路61，分别与输出信号端Output、第一节点PD_A、第二节点PD_B以及第三电压信号输入端VGL电连接，被配置为在第一节点PD_A的电压或第二节点PD_B的电压控制下，将第三电压信号VGL写入输出信号端Output。第一降噪子电路61主要用于在第一时段和第二时段之后的复位时段，将低电平的第三电压信号VGL写入输出信号端Output，从而对输出信号端Output进行降噪，避免在非输出时段输出信号。
例如，第一降噪子电路61可以包括第十晶体管M10和第十一晶体管M11，第十晶体管M10的栅极电连接第一节点PD_A，第一极电连接输出信号端Output，第二极电连接为接收第三电压信号VGL；第十一晶体管M11的栅极电连接第二节点PD_B，第一极电连接输出信号端Output，第二极电连接为接收第三电压信号VGL。
同样以正向扫描为例进行说明，在输入时段T1和输出时段T2之后的复位时段，第一节点PD_A的电压均为高电平，第十晶体管M10导通，因此将低电平的第三电压信号VGL写入输出信号端Output，从而对输出信号端Output进行降噪，避免在非输出时段输出信号。
本申请另一实施例中，参照图6，上述移位寄存器单元还可以包括第二控制子电路62、第二分压子电路63和第二降噪子电路64。
第二控制子电路62分别与第一电压信号输入端VDD_A、第二电压信号输入端VDD_B以及第四节点PD_Aa、第五节点PD_Bb电连接，被配置为在第一电压信号VDD_A的控制下，将第一电压信号VDD_A写入第四节点PD_Aa；在第二电压信号VDD_B的控制下，将第二电压信号VDD_B写入第五节点PD_Bb。
第二分压子电路63分别与第三节点PU、第四节点PD_Aa、第五节点PD_Bb以及第三电压信号输入端VGL电连接，被配置为在第三节点PU的电压控制下，将第三电压信号VGL写入第四节点PD_Aa，将第三电压信号VGL写入第五节点PD_Bb。
第二降噪子电路64分别与第三节点PU、第四节点PD_Aa、第五节点PD_Bb以及第三电压信号输入端VGL电连接，被配置为在第四节点PD_Aa或第五节点PD_Bb的电压控制下，将第三电压信号VGL写入第三节点PU。
第二控制子电路62和第二分压子电路63主要用于控制写入第四节点PD_Aa和第五节点PD_Bb的电压；第二降噪子电路64主要用于在第四节点PD_Aa或第五节点PD_Bb的电压控制下，将第三电压信号VGL写入第三节点PU，从而在对第三节点PU进行降噪，避免第三节点PU出现脉冲波动使第九晶体管M9导通，避免在非输出时段输出信号。
例如，第二控制子电路62可以包括第十二晶体管M12和第十三晶体管M13。第十二晶体管M12的栅极和第一极分别电连接至第一电压信号输入端VDD_A，第二极电连接第四节点PD_Aa；第十三晶体管M13的栅极和第一极分别电连接至第二电压信号输入端VDD_B，第二极电连接第五节点PD_Bb。
第二分压子电路63包括第十四晶体管M14和第十五晶体管M15，第十四晶体管M14的栅极电连接第三节点PU，第一极电连接第四节点PD_Aa，第二极电连接第三电压信号输入端VGL；第十五晶体管M15的栅极电连接第三节点PU，第一极电连接第五节点PD_Bb，第二极电连接第三电压信号输入端VGL。
第二降噪子电路64包括第十六晶体管M16和第十七晶体管M17，第十六晶体管M16的栅极电连接第四节点PD_Aa，第一极电连接第三节点PU，第二极电连接第三电压信号输入端VGL；第十七晶体管M17的栅极电连接第五节点PD_Bb，第一极电连接第三节点PU，第二极电连接第三电压信号输入端VGL。
同样以正向扫描为例进行说明，第一电压信号VDD_A为高电平，第二电压信号VDD_B为低电平，此时第十二晶体管M12导通，第四节点PD_Aa的电压为高电平。在 第一时段T1和第二时段T2，由于第三节点PU的电压为高电平，使第十四晶体管M14导通，控制将第三电压信号VGL写入第四节点PD_Aa。因为第十四晶体管M14分压，使得第四节点PD_Aa的电压为低电平，十六晶体管M16关断，此时段不对第三节点PU进行降噪。在第二时段T2之后的复位时段，第三节点PU的电压为低电平，使第十四晶体管M14关断，也就是第十四晶体管M14分压消除，使得第四节点PD_Aa的电压升高为高电平，十六晶体管M16导通，此时段对第三节点PU进行降噪，避免第三节点PU出现脉冲波动使第九晶体管M9导通，避免在非输出时段输出信号。
为了提升第二分压子电路63的阈值电压容限Vth Margin，参照图7，上述的移位寄存器单元还可以包括第三分压子电路71，分别与第一输入信号端Forward、第二输入信号端Backward、第四节点PD_Aa、第五节点PD_Bb以及第三电压信号输入端VGL电连接，被配置为根据第一输入信号Forward的电压，将第三电压信号VGL写入第四节点PD_Aa，根据第二输入信号Backward的电压，将第三电压信号VGL写入第五节点PD_Bb。
例如，第三分压子电路71可以包括第十八晶体管M18和第十九晶体管M19。第十八晶体管M18的栅极电连接第一输入信号端Forward，第一极电连接第四节点PD_Aa，第二极电连接第三电压信号输入端VGL；第十九晶体管M19的栅极电连接第二输入信号端Backward，第一极电连接第五节点PD_Bb，第二极电连接第三电压信号输入端VGL。
同样以正向扫描为例进行说明，在第一时段，第一输入信号端Forward输入的电压为高电平，第十八晶体管M18导通，将第三电压信号VGL写入第四节点PD_Aa，也就是由于分压的存在使第四节点PD_Aa的电压降低，因此，第四节点PD_Aa的电压由第十四晶体管M14和第十八晶体管M18共同控制，从而使第十四晶体管M14的阈值电压容限Vth Margin提升。
因此，为了避免在非输出时段第三节点出现脉冲波动使第九晶体管导通，上述第三时段的步骤还可以进一步包括：
控制将第三电压信号写入第三节点，对第三节点进行降噪。
例如，这一步骤可以由第二控制子电路、第二分压子电路和第二降噪子电路执行。
进一步地，为了避免在非输出时段输出信号端输出高电平信号，根据本公开实施例的驱动方法可以包括：
在第一时段，控制将第三电压信号写入输出信号端，对输出信号端进行降噪；
在第三时段，控制将第三电压信号写入输出信号端，对输出信号端进行降噪。
例如，这一步骤可以由第一降噪子电路执行。
需要说明的是，在本实施方式中，各晶体管的类型并不限于采用N型管，可以理解，当各晶体管为P型管时，各输入信号的时序与图3所示的各信号的时序相反。
根据本公开实施例的另一方面，还提供了一种栅极驱动电路。图8示出了根据本公开实施例的栅极驱动电路80的结构示意图。如图8所示，根据本公开实施例的栅极驱动电路可以包括N级根据实施例所述的移位寄存器单元。其中，第n级移位寄存器单元SR n的第一输入信号端Forward电连接至第n-1移位寄存器单元SR n-1的输出信号端Output，第n级移位寄存器单元SR n的第二输入信号端Backward电连接至第n+1移位寄存器单元SR n+1的输出信号端Output，N是大于等于4的整数，n是大于1且小于N的整数。
根据本公开实施例的另一方面，还提供了一种显示装置。如图9所示，该显示装置90可以包括根据本公开实施例的栅极驱动电路910。
需要说明的是，本实施例中的显示装置可以为：显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请实施例提供了一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。其中移位寄存器单元包括第一控制子电路、第一分压子电路、充放电子电路和输出子电路。输出子电路的栅极控制电压，也就是第三节点的电压是由充放电子电路控制，由于与充放电子电路电连接的第一输入信号端和第二输入信号端输入的电压信号为脉冲信号，在一帧的显示周期中，该脉冲信号仅在一行的扫描时长中为高电平，其余时段均为低电平。因此，充放电子电路中的TFT有源层不会长时间承受应力，其阈值电压也就不会发生负向偏移，从而有利于第三节点电压也就是输出子电路的栅极控制电压的保持，使移位寄存器单元正常输出。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、 方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对根据本公开实施例提供的一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置进行了详细介绍。本文中应用了具体个例对本公开实施例的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开实施例的方法及其核心思想。对于本领域的一般技术人员，依据本公开实施例的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开实施例的限制。

Claims (11)

  1. 一种移位寄存器单元，包括：
    第一控制子电路，被配置为接收第一电压信号，并在第一电压信号的控制下，将所述第一电压信号写入第一节点；以及接收第二电压信号，并在第二电压信号的控制下，将所述第二电压信号写入第二节点；
    第一分压子电路，电连接至所述第一控制子电路和输出信号端，第一分压子电路被配置为接收第三电压信号和来自输出信号端的输出信号，并在所述输出信号的控制下，将第三电压信号写入所述第一节点；以及在所述输出信号的控制下，将所述第三电压信号写入所述第二节点；
    充放电子电路，电连接至所述第一控制子电路、所述第一分压子电路和第一输入信号端、第二输入信号端，所述充放电子电路被配置为接收第一时钟信号，并在所述第一时钟信号、所述第一节点的电压以及所述第二节点的电压的控制下，将来自第一输入信号端的第一输入信号写入所述第三节点或者将来自第二输入信号端的第二输入信号写入所述第三节点；以及
    输出子电路，电连接至所述充放电子电路和所述输出信号端，所述输出子电路被配置为接收第二时钟信号，并在所述第三节点的电压控制下，在所述输出信号端输出所述第二时钟信号。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一控制子电路包括第一晶体管和第二晶体管；
    其中，所述第一晶体管的栅极和第一极分别电连接提供所述第一电压信号的第一电压信号端，第二极电连接所述第一节点；以及
    所述第二晶体管的栅极和第一极分别电连接提供第二电压信号的第二电压信号端，第二极电连接所述第二节点。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述第一分压子电路包括第三晶体管和第四晶体管；
    其中，所述第三晶体管的栅极电连接所述输出信号端，第一极电连接所述第一节点，第二极电连接提供第三电压信号的第三电压信号端；
    所述第四晶体管的栅极电连接所述输出信号端，第一极电连接所述第二节点，第二 极电连接第三电压信号端。
  4. 根据权利要求1至3之一所述的移位寄存器单元，其中，所述充放电子电路包括正向充放电子电路和负向充放电子电路，
    所述正向充放电子电路包括第五晶体管和第六晶体管，所述第五晶体管的栅极电连接提供第一时钟信号的第一时钟信号端，第一极电连接所述第一输入信号端，第二极电连接所述第六晶体管的第一极；所述第六晶体管的栅极电连接所述第一节点，第二极电连接所述第三节点；以及
    所述负向充放电子电路包括第七晶体管和第八晶体管，所述第七晶体管的栅极电连接所述第一时钟信号端，第一极电连接所述第二输入信号端，第二极电连接所述第八晶体管的第一极；所述第八晶体管的栅极电连接所述第二节点，第二极电连接所述第三节点。
  5. 根据权利要求1至4之一所述的移位寄存器单元，其中，所述输出子电路包括第一电容和第九晶体管，
    所述第一电容的第一极电连接所述第三节点，第二极电连接所述输出信号端；
    所述第九晶体管的栅极电连接所述第三节点，第一极电连接提供所述第二时钟信号的第二时钟信号端，第二极电连接所述输出信号端。
  6. 根据权利要求1至5任一项所述的移位寄存器单元，还包括：
    第一降噪子电路，被配置为在所述第一节点的电压或所述第二节点的电压的控制下，将所述第三电压信号写入所述输出信号端。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述第一降噪子电路包括第十晶体管和第十一晶体管，
    所述第十晶体管的栅极电连接所述第一节点，第一极电连接所述输出信号端，第二极电连接所述第三电压信号端；
    所述第十一晶体管的栅极电连接所述第二节点，第一极电连接所述输出信号端，第二极电连接所述第三电压信号端。
  8. 根据权利要求1至5任一项所述的移位寄存器单元，还包括：
    第二控制子电路，被配置为接收所述第一电压信号，并在所述第一电压信号的控制下，将第一电压信号写入第四节点；以及接收所述第二电压信号，并在所述第二电压信号的控制下，将所述第二电压信号写入第五节点；
    第二分压子电路，被配置为接收第三电压信号，并在所述第三节点的电压控制下，将所述第三电压信号写入所述第四节点；以及在所述第三节点的电压控制下，将所述第三电压信号写入所述第五节点；以及
    第二降噪子电路，被配置为在所述第四节点或所述第五节点的电压控制下，将所述第三电压信号写入所述第三节点。
  9. 一种栅极驱动电路，包括：
    N级如权利要求1至8之一所述的移位寄存器单元；
    其中，第n级移位寄存器单元的第一输入信号端电连接至第n-1移位寄存器单元的输出信号端，第n级移位寄存器单元的第二输入信号端电连接至第n+1移位寄存器单元的输出信号端，N是大于等于4的整数，n是大于1且小于N的整数。
  10. 一种显示装置，包括权利要求9所述的栅极驱动电路。
  11. 一种驱动方法，应用于权利要求1至8任一项所述的移位寄存器单元，所述驱动方法包括：
    在第一时段，通过所述第一控制子电路、所述第一分压子电路和所述充放电子电路，在所述第一输入信号或所述第二输入信号的控制下，将所述第一输入信号或者所述第二输入信号写入所述第三节点；以及
    在第二时段，通过所述输出子电路，在第三节点的电压控制下，控制所述输出信号端输出所述第二时钟信号。
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