WO2018218886A1 - 移位寄存器、栅极驱动电路、显示装置 - Google Patents

移位寄存器、栅极驱动电路、显示装置 Download PDF

Info

Publication number
WO2018218886A1
WO2018218886A1 PCT/CN2017/111559 CN2017111559W WO2018218886A1 WO 2018218886 A1 WO2018218886 A1 WO 2018218886A1 CN 2017111559 W CN2017111559 W CN 2017111559W WO 2018218886 A1 WO2018218886 A1 WO 2018218886A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
pull
pole
node
shift register
Prior art date
Application number
PCT/CN2017/111559
Other languages
English (en)
French (fr)
Inventor
古宏刚
陈俊生
邵贤杰
宋洁
姚利利
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP17863286.5A priority Critical patent/EP3633664A4/en
Priority to US15/773,013 priority patent/US10891913B2/en
Publication of WO2018218886A1 publication Critical patent/WO2018218886A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present disclosure relates to a shift register, a gate drive circuit, and a display device.
  • the gate driver GOA design can make the LCD panel cost less, while reducing one process and increasing throughput.
  • high resolution and narrow bezel have become the trend of development.
  • the integrated gate drive circuit on the panel is the most important solution.
  • the present disclosure provides a shift register including: a first shift register unit, a second shift register unit, a pull-down control sub-circuit, and a pull-down sub-circuit; wherein the first shift register unit includes: a first input sub- a circuit, a first output sub-circuit, a first reset sub-circuit, and a first noise reduction sub-circuit; the second shift register unit includes: a second input sub-circuit, a second output sub-circuit, a second reset sub-circuit, and a second Two noise reduction subcircuits;
  • the first input sub-circuit is configured to pre-charge the first pull-up node under control of the first input signal;
  • the first pull-up node is a first input sub-circuit, a first output sub-circuit, and a pull-down a connection node between the sub-circuit, the first reset sub-circuit, and the first noise reduction sub-circuit;
  • the first output sub-circuit is configured to output the first clock signal through the first signal output end under the control of the potential of the first pull-up node;
  • the first reset sub-circuit is configured to reset a potential of the first pull-up node and the first signal output end by using a first voltage signal under control of a first reset signal;
  • the second input sub-circuit is configured to perform the second pull-up node under the control of the second input signal Pre-charging;
  • the second pull-up node is a connection node between the second input sub-circuit, the second output sub-circuit, and the pull-down sub-circuit;
  • the second output sub-circuit is configured to output the second clock signal through the second signal output end under the control of the potential of the second pull-up node;
  • the second reset sub-circuit is configured to reset potentials of the second pull-up node and the second signal output end by using the first voltage signal under control of a second reset signal;
  • the pull-down control sub-circuit is configured to control a potential of the pull-down node under control of the first clock signal or the second clock signal;
  • the pull-down node is the pull-down control sub-circuit, the pull-down sub-circuit a connection node between the first noise reduction sub-circuit and the second noise reduction sub-circuit;
  • the pull-down sub-circuit is configured to pull down a potential of the pull-down node by using the first voltage signal under the control of a potential of the first pull-up node and a potential of the second pull-up node; a first noise reduction sub-circuit, configured to reduce output noise of the first pull-up node and the first signal output by the first voltage signal under control of the pull-down node;
  • the second noise reduction sub-circuit is configured to reduce output noise of the second pull-up node and the second signal output by the first voltage signal under control of the pull-down node.
  • the shift register further includes a storage sub-circuit for maintaining a potential of the pull-down node.
  • the first input sub-circuit includes a first transistor; wherein
  • the first pole and the control pole of the first transistor are both connected to the first input signal end, and the second pole of the first transistor is connected to the first pull-up node.
  • the first output sub-circuit includes a third transistor and a first storage capacitor; wherein
  • the first pole of the third transistor is connected to the first clock signal end, the second pole of the third transistor is connected to the first signal output end, and the control pole of the third transistor is connected to the first pull-up node;
  • the first end of the first storage capacitor is connected to the first pull-up node, and the second end of the first storage capacitor is connected to the first signal output end.
  • the first reset sub-circuit includes: a second transistor and a thirteenth transistor; wherein
  • a first pole of the second transistor is connected to the first pull-up node, a second pole of the second transistor is connected to a first voltage signal end, and a control pole of the second transistor is connected to a first reset signal end;
  • a first pole of the thirteenth transistor is connected to the first signal output end, a second pole of the thirteenth transistor is connected to a first voltage signal end, and a control pole of the thirteenth transistor is connected to a second clock signal end.
  • the first reset sub-circuit includes: a second transistor and a thirteenth transistor; wherein
  • a first pole of the second transistor is connected to the first pull-up node, a second pole of the second transistor is connected to a first voltage signal end, and a control pole of the second transistor is connected to a first reset signal end;
  • a first pole of the thirteenth transistor is connected to the first signal output end, a second pole of the thirteenth transistor is connected to a first voltage signal end, and a control pole of the thirteenth transistor is connected to the first reset signal end.
  • the first noise reduction sub-circuit includes a fourth transistor and a fifteenth transistor; wherein
  • a first pole of the fourth transistor is connected to the first signal output end, a second pole of the fourth transistor is connected to a first voltage signal end, and a control pole of the fourth transistor is connected to the pull-down node;
  • a first pole of the fifteenth transistor is connected to the first pull-up node, a second pole of the fifteenth transistor is connected to a first voltage signal end, and a control pole of the fifteenth transistor is connected to the pull-down node .
  • the second input sub-circuit includes a fifth transistor; wherein
  • the first pole and the control pole of the fifth transistor are both connected to the second input signal end, and the second pole of the fifth transistor is connected to the second pull-up node.
  • the second output sub-circuit includes a seventh transistor and a second storage capacitor; wherein
  • a first pole of the seventh transistor is connected to the second clock signal end, a second pole of the seventh transistor is connected to the second signal output end, and a control pole of the seventh transistor is connected to the second pull-up node ;
  • the first end of the second storage capacitor is connected to the second pull-up node, and the second end of the second storage capacitor is connected to the second signal output end.
  • the second reset sub-circuit includes a sixth transistor and a fourteenth transistor; wherein
  • a first pole of the sixth transistor is connected to the second pull-up node, a second pole of the sixth transistor is connected to the first voltage signal end, and a control pole of the sixth transistor is connected to the second reset signal end;
  • a first pole of the fourteenth transistor is connected to the second signal output end, a second pole of the fourteenth transistor is connected to a first voltage signal end, and a control pole of the fourteenth transistor is connected to the first clock signal end.
  • the second reset sub-circuit includes a sixth transistor and a fourteenth transistor; wherein
  • a first pole of the sixth transistor is connected to the second pull-up node, a second pole of the sixth transistor is connected to the first voltage signal end, and a control pole of the sixth transistor is connected to the second reset signal end;
  • a first pole of the fourteenth transistor is connected to the second signal output end, a second pole of the fourteenth transistor is connected to a first voltage signal end, and a control pole of the fourteenth transistor is connected to a second reset signal end.
  • the second noise reduction sub-circuit includes an eighth transistor and a sixteenth transistor; wherein
  • the first pole of the eighth transistor is connected to the second signal output end, and the second transistor is second a pole is connected to the first voltage signal end, and a control pole of the eighth transistor is connected to the pull-down node;
  • the first of the sixteenth transistors is connected to the second pull-up node, the second pole of the sixteenth transistor is connected to the first voltage signal end, and the control electrode of the sixteenth transistor is connected to the pull-down node.
  • the pull-down sub-circuit includes a ninth transistor, a tenth transistor, and a twelfth transistor; wherein
  • the first pole and the control pole of the ninth transistor are both connected to the first pull-up node, and the second pole of the ninth transistor is connected to the control pole of the twelfth transistor;
  • the first pole and the control pole of the tenth transistor are both connected to the second pull-up node, and the second pole of the tenth transistor is connected to the control pole of the twelfth transistor;
  • a first pole of the twelfth transistor is connected to the pull-down node, a second pole of the twelfth transistor is connected to a first voltage signal end, and a control pole of the twelfth transistor is connected to a first a second pole and a second pole of the tenth transistor.
  • the pull-down control sub-circuit includes an eleventh transistor; wherein
  • the first pole and the control pole of the eleventh transistor are both connected to the second clock signal end, and the second pole of the eleventh transistor is connected to the pull-down node.
  • the pull-down control sub-circuit includes an eleventh transistor; wherein
  • the first pole and the control pole of the eleventh transistor are both connected to the first clock signal end, and the second pole of the eleventh transistor is connected to the pull-down node.
  • the storage subcircuit includes a third storage capacitor; wherein
  • the first end of the third storage capacitor is connected to the pull-down node, and the second end of the third storage capacitor is connected to the first voltage signal end.
  • the present disclosure provides a gate drive circuit that includes the shift register described above.
  • a first input signal end of the first shift register unit in each stage shift register is connected to a second signal output end of the second shift register unit in the first stage shift register;
  • a first reset signal end of the first shift register unit in each stage shift register is connected to a second signal output end of the second shift register unit in the shift register of the first stage;
  • a first signal output end of the first shift register unit in each stage shift register is connected to a second input signal end of the second shift register unit in the shift register of the first stage;
  • a second signal output end of the second shift register unit in each stage shift register is connected to the first signal input end of the first shift register unit in the next stage shift register;
  • a second reset signal terminal of the second shift register unit in each stage shift register is coupled to the first signal output terminal of the first shift register unit in the next stage shift register.
  • the present disclosure provides a display device including the above-described gate driving circuit.
  • 1-3 are schematic diagrams of shift registers of an exemplary embodiment of the present disclosure
  • FIG. 4 is an operational timing diagram corresponding to the shift register of FIG. 1 in an exemplary embodiment of the present disclosure
  • FIG. 5 is an operational timing diagram corresponding to the shift register of FIG. 3 in an exemplary embodiment of the present disclosure
  • FIG. 6 is a cascade schematic diagram of a gate driving circuit of an exemplary embodiment of the present disclosure.
  • the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or the like having the same characteristics. Since the source and the drain of the transistor used are interchangeable under certain conditions, the source thereof, There is no difference in the description of the drain from the connection relationship.
  • one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a gate.
  • the transistor can be classified into an N-type and a P-type according to the characteristics of the transistor. In the following embodiment, the transistor is an N-type transistor.
  • the drain of the first very N-type transistor and the source of the second N-type transistor have a source-drain conduction when the gate input is high, and the P-type is opposite. It is conceivable that the implementation of the transistor as a P-type transistor is easily conceivable by those skilled in the art without any inventive effort, and is therefore within the scope of the embodiments of the present disclosure.
  • the first voltage signal is a low level signal
  • the first voltage signal end is a low level signal terminal. It should be understood that if the thin film transistor adopts a P-type transistor, the first voltage signal at this time is a high level signal, and the first voltage signal end is a high level signal end.
  • the present disclosure aims to at least solve or alleviate one of the technical problems existing in the prior art, and provides a shift register, a gate drive circuit, and a display device which are low in power consumption and simple in structure.
  • the shift register in the present disclosure includes two shift register sheets that provide signals for different row gate lines a first shift register unit and a second shift register unit, and the two shift register units share a pull-down sub-circuit and a pull-down control sub-circuit, that is, the first shift register unit and the second shift
  • the bit register unit is connected to the same pull-down node, and the storage sub-circuit is added to maintain the potential of the pull-down node, thereby realizing that after the two shift register units are reset, the pull-down node continuously pulls up the node and outputs two signals.
  • the end discharge solves the noise voltage problem caused by the clock signal and improves the yield.
  • the two shift register units share a pull-down node, which reduces the number of transistors compared to the existing shift register, thereby effectively reducing power consumption.
  • a shift register including: a first shift register unit, a second shift register unit, a pull-down control sub-circuit 20, and a pull-down sub-circuit
  • the first shift register unit includes: a first input sub-circuit 11, a first output sub-circuit 12, a first reset sub-circuit, a first noise reduction sub-circuit 14; and a second shift register unit comprising: a second The sub-circuit 21, the second output sub-circuit 22, the second reset sub-circuit, and the second noise reduction sub-circuit 24 are input.
  • the first input sub-circuit 11 is configured to pre-charge the first pull-up node PU(N) under the control of the first input signal;
  • the first pull-up node PU(N) is the first input sub-circuit 11, a connection node between the first output sub-circuit 12, the pull-down sub-circuit 30, the first reset sub-circuit, and the first noise reduction sub-circuit 14;
  • the first output sub-circuit 12 is used at the first pull-up node PU(N) Under the control of the potential, the first clock signal is output through the first signal output terminal Output(N);
  • the first reset sub-circuit is configured to pass the low-level signal to the first pull-up node under the control of the first reset signal The potential of the PU (N) and the first signal output terminal Output (N) is reset;
  • the second input sub-circuit 21 is configured to pre-populate the second pull-up node PU (N+1) under the control of the second input signal Charging;
  • the shift register in some embodiments of the present disclosure includes two shift register units that provide signals for different row gate lines, namely, a first shift register unit and a second shift register unit, and the two shift registers
  • the unit shares a pull-down sub-circuit 30 and a pull-down control sub-circuit 20, that is, the first shift register unit and the second shift register unit are connected to the same pull-down node PD, that is, share a pull-down node PD, and the existing shift Compared with the bit register, the number of transistors is reduced, thereby effectively reducing power consumption.
  • a storage sub-circuit may be further added to maintain a potential of the pull-down node, so that after both shift register units are reset, the pull-down node PD is continuously a pull-up node and two signal outputs.
  • the discharge solves the noise voltage problem caused by the clock signal and improves the yield.
  • a shift register including: a first shift register unit, a second shift register unit, a pull-down control sub-circuit 20, and a pull-down sub-circuit 30, and a storage capacitor; wherein the first shift register unit comprises: a first input sub-circuit 11, a first output sub-circuit 12, a first reset sub-circuit, a first noise reduction sub-circuit 14; a second shift register unit The second input sub-circuit 21, the second output sub-circuit 22, the second reset sub-circuit, and the second noise reduction sub-circuit 24 are included.
  • the first input sub-circuit 11 is connected to the first input signal terminal Input(N) and the first pull-up node PU(N) for inputting the first input signal through the first input signal terminal Input(N) , pre-charging the first pull-up node PU(N).
  • the first input sub-circuit 11 optionally includes a first transistor M1; wherein the first pole and the control pole of the first transistor M1 are both connected to the first input signal terminal Input(N), and the second pole of the first transistor M1
  • the first pull-up node PU(N) is connected.
  • the first transistor M1 In the precharge phase of the first shift register unit, when the first input signal input by the first input signal terminal Input(N) is at a high level, the first transistor M1 is turned on, and at this time, the high level signal can pass The first transistor M1 is precharged for the first pull-up node PU(N).
  • the first output sub-circuit 12 is connected to the first clock signal terminal CLK, the first pull-up node PU(N), and the first signal output terminal Output(N) for the first pull-up node PU(N). Under the control of the potential, the first clock signal input by the first clock signal terminal CLK is output through the first signal output terminal Output(N).
  • the first output sub-circuit 12 optionally includes a third transistor M3 and a first storage capacitor C1;
  • the first pole of the third transistor M3 is connected to the first clock signal terminal CLK, the second pole of the third transistor M3 is connected to the first signal output terminal Output (N), and the control electrode of the third transistor M3 is connected to the first Pulling the node PU(N);
  • the first end of the first storage capacitor C1 is connected to the first pull-up node PU(N), and the second end of the first storage capacitor C1 is connected to the first signal output terminal Output(N) .
  • the third transistor M3 is turned on; the first clock signal terminal CLK is input.
  • a clock signal is a high level signal, so the first signal output terminal Output(N) outputs a high level signal; meanwhile, due to the bootstrap effect of the first storage capacitor C1, the potential of the first pull-up node PU(N) is further Raise.
  • the first pull-up node reset unit 131 in the first reset sub-circuit is connected to the first reset signal terminal RESET(N), the first pull-up node PU(N), and the low-level signal terminal VGL, for Under the control of the first reset signal input by the reset signal terminal RESET(N), the low-level signal input through the low-level signal terminal VGL pulls down the potential of the first pull-up node to complete the first pull-up node.
  • the first pull-up node PU(N) reset unit 131 optionally includes a second transistor M2; the first pole of the second transistor M2 is coupled to the first pull-up node PU(N), the second transistor M2 The second pole is connected to the low level signal terminal VGL, the control electrode of the second transistor M2 is connected to the first reset signal terminal RESET (N); the first signal output terminal Output (N) reset unit 132 optionally includes the thirteenth The transistor M13; the first pole of the thirteenth transistor M13 is connected to the first signal output terminal Output (N), the second pole of the thirteenth transistor M13 is connected to the low-level signal terminal VGL, and the control of the thirteenth transistor M13 The pole is connected to the second clock signal terminal CLKB.
  • the first reset signal input by the first reset signal terminal RESET(N) is a high level signal
  • the second transistor M2 is turned on, and the low input signal through the low level signal terminal VGL is input.
  • the level signal pulls down the potential of the first pull-up node PU(N) to complete the reset of the first pull-up node PU(N); at the same time, the second clock signal input by the second clock signal terminal CLKB is high.
  • the flat signal, the thirteenth transistor M13 is turned on, and the potential of the first signal output terminal Output(N) is pulled down by the low level signal input by the low level signal terminal VGL to complete the reset of the first signal output terminal Output(N) .
  • the first signal output terminal Output(N) in the first reset sub-circuit may not be connected to the second clock signal terminal CLKB, but may be connected to the first reset signal terminal RESET(N) and the first signal output. End Output (N), low-level signal terminal VGL connection.
  • the first pole of the thirteenth transistor M13 included in the first signal output terminal Output(N) reset unit 132 is connected to the first signal output terminal Output(N), and the second pole of the thirteenth transistor M13 is connected to the low voltage.
  • the signal terminal VGL, the control electrode of the thirteenth transistor M13 is connected to the first reset signal terminal RESET (N).
  • the first reset signal input by the first reset signal terminal RESET(N) is a high level signal, and the second transistor M2 and the thirteenth transistor M13 are both turned on, passing the low level.
  • the low level signal input by the signal terminal VGL pulls down the potential of the first pull-up node PU(N) and the first signal output terminal Output(N) to complete the first pull-up node PU(N) and the first signal output end. Reset of Output(N).
  • the first noise reduction sub-circuit 14 is connected to the first pull-up node PU(N), the first signal output terminal Output(N), the pull-down node PD, and the low-level signal terminal VGL for the potential of the pull-down node PD. Under the control, the output noise of the first pull-up node PU(N) and the first signal output terminal Output(N) is reduced by the low-level signal input by the low-level signal terminal VGL.
  • the first noise reduction sub-circuit 14 includes a fourth transistor M4 and a fifteenth transistor M15; wherein the first electrode of the fourth transistor M4 is connected to the first signal output terminal OutputN, and the second electrode of the fourth transistor M4 Connected to the low-level signal terminal VGL, the control electrode of the fourth transistor M4 is connected to the pull-down node PD; the first pole of the fifteenth transistor M15 is connected to the first pull-up node PU(N), and the second of the fifteenth transistor M15 The pole is connected to the low-level signal terminal VGL, and the control electrode of the fifteenth transistor M15 is connected to the pull-down node PD.
  • the pull-down node PD is pulled up to a high level while charging the memory sub-circuit 40, at which time the fifteenth transistor M15 is turned on to lower the first pull-up node PU ( The output noise of N); the fourth transistor M4 is turned on to reduce the noise of the first signal output terminal Output (N).
  • the second input sub-circuit 21 is connected to the second input signal terminal Input(N+1) and the second pull-up node PU(N+1) for passing through the second input signal terminal Input(N+1).
  • the input second input signal precharges the second pull-up node PU(N+1).
  • the second input sub-circuit 21 optionally includes a fifth transistor M5; wherein the first pole and the control pole of the fifth transistor M5 are both connected to the second input signal terminal Input(N+1), and the fifth transistor M5 The second pole is connected to the second pull-up node PU(N+1).
  • the second input signal terminal Input(N+1) is input with a high level signal, and the second pull-up node PU(N+1) is performed by the high-point flat signal. Precharged.
  • the second output sub-circuit 22 is connected to the second clock signal terminal CLKB, the second pull-up node PU(N+1), a second signal output terminal Output(N+1); for controlling the second clock signal input by the second clock signal terminal CLKB under the control of the potential of the second pull-up node PU(N+1), The second signal output terminal Output(N+1) is output.
  • the second output sub-circuit 22 optionally includes a seventh transistor M7 and a second storage capacitor C2; wherein the first pole of the seventh transistor M7 is coupled to the second clock signal terminal CLKB, and the second transistor of the seventh transistor M7 is coupled.
  • the second signal output terminal Output(N+1), the control electrode of the seventh transistor M7 is connected to the second pull-up node PU(N+1); the first end of the second storage capacitor C2 is connected to the second pull-up node PU (N +1), the second end of the second storage capacitor C2 is connected to the second signal output terminal Output(N+1).
  • the fifth transistor M5 is turned on; the second clock signal terminal CLKB is input.
  • the first clock signal is a high level signal, so the second signal output terminal Output(N+1) outputs a high level signal; meanwhile, due to the bootstrap effect of the second storage capacitor C2, the second pull-up node PU(N The potential of +1) is further increased.
  • the second pull-up node reset unit 231 in the second reset sub-circuit is connected to the second reset signal terminal RESET (N+1), the second pull-up node PU (N+1), and the low-level signal terminal VGL.
  • the low-level signal input through the low-level signal terminal VGL pulls down the second pull-up node PU (N+ a potential of 1) to complete resetting of the second pull-up node PU(N+1);
  • a second signal output terminal Output(N+1) in the second reset sub-circuit is connected to the first clock signal terminal CLK, a low level signal terminal VGL and a second signal output terminal Output(N+1) for inputting through the low level signal terminal VGL under the control of the first clock signal input by the first clock signal terminal CLK
  • the low level signal pulls down the potential of the second signal output terminal (N+1) to complete the reset of the second signal output terminal Output (N+1).
  • the second pull-up node PU(N+1) reset unit 231 optionally includes a sixth transistor M6; the second signal output terminal Output(N+1) reset unit 232 optionally includes a fourteenth transistor M14;
  • the first pole of the sixth transistor M6 is connected to the second pull-up node PU(N+1), the second pole of the sixth transistor M6 is connected to the low-level signal terminal VGL, and the control pole of the sixth transistor M6 is connected to the second reset signal.
  • the reset signal input by the second reset signal terminal RESET(N+1) is a high level signal
  • the sixth transistor M6 is turned on, and the second pull-up node PU(N+1) Pulled down to low battery Ping, that is, the reset of the second pull-up node PU(N+1) is completed
  • the signal written by the first clock signal terminal CLK is also a high level signal
  • the fourteenth transistor M14 is turned on, and the second signal output terminal is Output (N+1) is pulled down to the low level, that is, the reset of the second signal output terminal Output (N+1) is completed.
  • the second signal output terminal Output(N+1) reset unit 232 in the second reset sub-circuit may not be connected to the first clock signal terminal CLK, but to the second reset signal terminal RESET(N+1), The second signal output terminal Output(N+1) and the low level signal terminal VGL are connected.
  • the first pole of the fourteenth transistor M14 included in the second signal output terminal Output(N+1) reset unit 232 is connected to the second signal output terminal Output(N+1), and the second electrode of the fourteenth transistor M14 The pole is connected to the low-level signal terminal VGL, and the control electrode of the fourteenth transistor M14 is connected to the second reset signal terminal RESET(N+1).
  • the second reset signal input by the second reset signal terminal RESET(N+1) is a high level signal
  • the sixth transistor M6 and the fourteenth transistor M14 are both turned on, and the low pass
  • the low level signal input by the level signal terminal VGL pulls down the potential of the second pull-up node PU(N+1) and the second signal output terminal Output(N+1) to complete the second pull-up node PU (N+ 1) and reset of the second signal output Output(N+1).
  • the second noise reduction sub-circuit 24 is connected to the second pull-up node PU (N+1), the second signal output terminal Output (N+1), the pull-down node PD, and the low-level signal terminal VGL for Under the control of the potential of the node PD, the output noise of the second pull-up node PU(N+1) and the second signal output terminal Output(N+1) is reduced by the low-level signal input by the low-level signal terminal VGL. .
  • the second noise reduction sub-circuit 24 includes an eighth transistor M8 and a sixteenth transistor M16; wherein the first electrode of the eighth transistor M8 is connected to the second signal output terminal Output(N+1), and the eighth transistor M8 is The diode is connected to the low-level signal terminal VGL, the gate of the eighth transistor M8 is connected to the pull-down node PD; the first pole of the sixteenth transistor M16 is connected to the second pull-up node PU(N+1), the sixteenth transistor The second pole of M16 is connected to the low-level signal terminal VGL, and the control pole of the sixteenth transistor M16 is connected to the pull-down node PD.
  • the pull-down node PD is pulled up to a high level while charging the memory sub-circuit 40, at which time the sixteenth transistor M16 is turned on to lower the second pull-up node PU ( Output noise of N+1); the eighth transistor M8 is turned on to reduce the noise of the second signal output terminal (N+1).
  • the storage sub-circuit 40 in the shift register includes a third storage capacitor C3; the first end of the third storage capacitor C3 is connected to the pull-down node PD, and the second end of the third storage capacitor C3 The low-level signal terminal VGL is connected; the third storage capacitor C3 functions to maintain the potential of the pull-down node PD.
  • the pull-down control sub-circuit 20 is connected to the second clock signal input end and the pull-down node PD for charging the pull-down node PD under the control of the second clock signal input by the second clock signal input end, that is, the third The storage capacitor C3 is charged, so that the third storage capacitor C3 maintains the pull-down node PD high after the first shift register unit and the second shift register unit are completed, so that the first noise reduction sub-circuit 14 and the first
  • the second noise reduction sub-circuit 24 can continuously reduce the first pull-up node PU(N), the second pull-up node PU(N+1), the first signal output terminal Output(N), and the second signal output terminal Output(N+ 1) The noise of the output signal.
  • the pull-down control sub-circuit 20 optionally includes an eleventh transistor M11; wherein the first pole and the control pole of the eleventh transistor M11 are both connected to the second clock signal terminal CLKB, and the second pole of the eleventh transistor M11 is connected.
  • the pulldown node PD optionally includes an eleventh transistor M11; wherein the first pole and the control pole of the eleventh transistor M11 are both connected to the second clock signal terminal CLKB, and the second pole of the eleventh transistor M11 is connected.
  • the pulldown node PD The pulldown node PD.
  • the second clock signal written by the second clock signal terminal CLKB is a high level signal, and the eleventh transistor M11 is turned on, and the pull-down node PD It is pulled high to charge the storage capacitor C3.
  • the pull-down control sub-circuit 20 can also be connected to the first clock signal input terminal and the pull-down node PD for charging the pull-down node PD under the control of the first clock signal input by the first clock signal input terminal, that is, The third storage capacitor C3 is charged, so that the third storage capacitor C3 maintains the pull-down node PD to maintain a high potential after the first shift register unit and the second shift register unit are completed, so that the first noise reduction sub-circuit 14
  • the second noise reduction sub-circuit 24 can continuously reduce the first pull-up node PU(N), the second pull-up node PU(N+1), the first signal output terminal Output(N), and the second signal output terminal Output ( N+1) The noise of the signal output.
  • the pull-down control sub-circuit 20 optionally includes an eleventh transistor M11; wherein the first pole and the control pole of the eleventh transistor M11 are both connected to the first clock signal terminal CLK, and the second pole of the eleventh transistor M11 is connected.
  • the pulldown node PD optionally includes an eleventh transistor M11; wherein the first pole and the control pole of the eleventh transistor M11 are both connected to the first clock signal terminal CLK, and the second pole of the eleventh transistor M11 is connected.
  • the pulldown node PD The pulldown node PD.
  • the first clock signal written by the first clock signal terminal CLK is a high level signal
  • the eleventh transistor M11 is turned on
  • the pull-down node PD It is pulled high to charge the storage capacitor C3.
  • the pull-down sub-circuit 30 is connected to the first pull-up node PU(N), the second pull-up node PU(N+1), the low-level signal end VGL, and the pull-down node PD; for the first pull-up node PU ( Under the control of the potential of the N) and the second pull-up node PU(N+1), the low-level signal input through the low-level signal terminal VGL pulls down the pull-down node PD Potential.
  • the pull-down sub-circuit 30 optionally includes a ninth transistor M9, a tenth transistor M10, and a twelfth transistor M12; wherein the first pole and the control pole of the ninth transistor M9 are both connected to the first pull-up node PU(N)
  • the second pole of the ninth transistor M9 is connected to the control electrode of the twelfth transistor M12; the first pole and the control pole of the tenth transistor M10 are both connected to the second pull-up node PU(N+1), and the tenth transistor M10
  • the second pole is connected to the control electrode of the twelfth transistor M12; the first pole of the twelfth transistor M12 is connected to the pull-down node PD, the second pole of the twelfth transistor M12 is connected to the low-level signal terminal VGL, and the control of the twelfth transistor M12
  • the pole is connected to the second pole of the ninth transistor M9 and the second pole of the tenth transistor M10.
  • the turning on and off of the ninth transistor M9 and the tenth transistor M10 are respectively controlled by the potentials of the first pull-up node PU(N) and the second pull-up node PU(N+1), and the twelfth transistor M12 Is controlled by the potential of the first pull-up node PU(N) output by the ninth transistor M9 and the potential of the second pull-up node PU(N+1) output by the tenth transistor M10, so as long as the first
  • the potential of one of the pull node PU (N) and the second pull-up node PU (N+1) is a high level signal, and the twelfth transistor M12 is turned on, at which time the potential of the pull-down node PD is lowered.
  • the low level signal input by the level signal terminal VGL is pulled low.
  • the first stage (pre-charge phase of the first shift register unit): the first input signal written by the first input signal terminal Input(N) is a high level signal, the first transistor M1 is turned on, and the first input is at this time.
  • the signal charges the first storage capacitor C1 through the first transistor M1, so that the potential of the first pull-up node PU(N) is pulled high; since the first pull-up node PU(N) is at a high level at this time, making the ninth
  • the transistor M9 and the twelfth transistor M12 are turned on, discharge the storage capacitor C3, and pull down the potential of the pull-down node PD to a low level; at this time, the potential of the pull-down node PD is a low level, so the fourth transistor M4 and the tenth
  • the five-transistor M15 is turned off, and at the same time, the first clock signal is low, thereby ensuring that the first signal output terminal Output(N) outputs a stable low-level signal.
  • a second phase (the output phase of the first shift register unit and the precharge phase of the second shift register unit): the first input signal written by the first input signal terminal Input(N) is a low level signal, The first transistor M1 is turned off, the first pull-up node PU(N) continues to maintain a high potential, and the third transistor M3 remains in an on state.
  • the first clock signal input by the first clock signal terminal CLK is a high level signal.
  • the first pull-up node PU(N) further boosts the potential of the first pull-up node PU(N) due to the bootstrapping effect of the first storage capacitor C1, so that the output of the first signal output terminal Output(N) is high.
  • the pull-up node PU(N) is high, so the ninth transistor M9 and the twelfth transistor M12 are in an on state, so the pull-down node PD is a low level signal, and the fourth transistor M4 and the fifteenth transistor M15 remain turned off.
  • the second clock signal written by the second clock signal terminal CLKB is a low level signal, and the thirteenth transistor M13 is in a closed state to ensure the stability of the output signal of the first signal output terminal Output(N).
  • a high level signal output by the first signal output terminal Output(N) in the first shift register unit may serve as a second input signal in the second shift register unit in the stage shift register.
  • the second pull-up node PU(N+1) is pulled high, so that the tenth transistor M10 and the twelfth transistor M12 are turned on, so the pull-down node PD is at a low level, the eighth transistor M8 and the sixteenth The transistor M16 is turned off, thereby ensuring that the second signal output terminal Output(N+1) outputs a stable low level signal.
  • the third stage (the reset phase of the first shift register unit and the output stage of the second shift register unit): the reset signal written by the first reset signal terminal RESET(N) is a high level, and the second clock signal The second clock signal written by the terminal CLKB is at a high level.
  • the second transistor M2 and the fifteenth transistor M15 are turned on, and the first pull-up node PU(N) is pulled down to a low level, that is, the first step is completed.
  • a reset of the pull-down node PD; the thirteenth transistor M13 is turned on, and the first signal output terminal Output(N) is pulled down to a low level, at which time the reset of the first signal output terminal Output(N) is completed.
  • the fifth transistor M5 is turned off, and the second storage capacitor C2 is discharged. Due to the bootstrap effect of the second storage capacitor C2, the potential of the second pull-up node PU(N+1) is amplified, and the second clock signal is at a high level.
  • the seven-transistor M7 is turned on, so the second signal output terminal Output(N+1) outputs a high-level signal.
  • the second pull-up node PU(N+1) is at a high level at this time, the tenth transistor M10 and the twelfth transistor M12 are turned on, so the pull-down node PD is pulled low, although the second clock The clock signal is high, the eleventh transistor M11 is turned on, but the pull-down node PD is not pulled high. This is so because the width-to-length ratio of the selected eleventh transistor M11 is smaller than that of the tenth transistor M10 and the twelfth transistor M12.
  • the signal input by the first reset signal terminal RESET(N) is a high level signal at this stage
  • the signal outputted by the second signal output terminal Output(N+1) is just at this stage. Is a high level signal, so it can be provided by the second signal output terminal Output(N+1) for the first reset signal terminal RESET(N) Bit signal.
  • the fourth stage (the reset phase of the second shift register unit): the reset signal written by the second reset signal terminal RESET(N+1) is a high level signal, the sixth transistor M6 is turned on, and the second pull-up node PU (N+1) is pulled down to a low level, that is, the reset of the second pull-up node PU(N+1) is completed; the first clock signal written by the first clock signal terminal CLK is also a high level signal, The fourteenth transistor M14 is turned on, and the second signal output terminal Output(N+1) is pulled down to a low level, that is, the reset of the second signal output terminal Output(N+1) is completed.
  • the fifth stage (the noise reduction phase of the first shift register unit and the second shift register unit): the second clock signal written by the second clock signal terminal CLKB is a high level signal, and the eleventh transistor M11 is turned on
  • the pull-down node PD is pulled up to a high level while charging the third storage capacitor C3, at which time the fifteenth transistor M15 is turned on to reduce the output noise of the first pull-up node PU(N); the fourth transistor M4 Turning on to reduce the noise of the first signal output terminal (N); the sixth transistor M6 is turned on to reduce the output noise of the second pull-up node PU(N+1); the eighth transistor M8 is turned on to lower the second signal
  • the noise of the output terminal (N+1); of course, the thirteenth transistor M13 is controlled by the second clock signal, and is also turned on at this time to stably reduce the noise of the first signal output terminal Output (N).
  • the high potential of the pull-down node PD can be maintained by the third storage capacitor C3, thereby continuing to the first pull-up node PU(N) and the second pull-up.
  • the node PU (N+1), the first signal output terminal Output (N), and the second signal output terminal Output (N+1) perform pull-down noise reduction.
  • the first clock signal written by the first clock signal terminal CLK is a high level signal
  • the fourteenth transistor M14 is turned on to stably lower the second signal output terminal Output (N+1) noise.
  • the eleventh transistor M11 of the pull-down control sub-circuit 20 in the shift register unit used are connected to the first clock signal terminal CLK, the eleventh transistor M11 When the two poles are connected to the pull-down node PD, the driving method of the shift register is similar to the above method, except that the fourth stage (the reset phase of the second shift register unit) and the fifth stage (the first shift register)
  • the noise reduction phase of the unit and the second shift register unit, as shown in FIG. 3 and FIG. 5, the fourth stage and the fifth stage specifically include:
  • the fourth stage (the reset phase of the second shift register unit): the reset signal written by the second reset signal terminal RESET(N+1) is a high level signal, the sixth transistor M6 is turned on, and the second pull-up node PU (N+1) is pulled down to a low level, that is, the reset of the second pull-up node PU(N+1) is completed; the first clock signal written by the first clock signal terminal CLK is also a high level signal, The fourteenth transistor M14 is turned on, and the second signal output terminal Output(N+1) is pulled low to complete the reset of the second signal output Output(N+1).
  • the eleventh transistor M11 is also turned on, and at this time, the pull-down node PD is pulled up to a high level, and at the same time The third storage capacitor C3 is charged.
  • the fifth stage (the noise reduction phase of the first shift register unit and the second shift register unit): since the third storage capacitor C3 is charged in the fourth stage, the pull-down node PD can be maintained by the third storage capacitor C3 at this time.
  • the fifteenth transistor M15 is turned on to reduce the output noise of the first pull-up node PU(N); the fourth transistor M4 is turned on to reduce the noise of the first signal output terminal Output(N);
  • the transistor M6 is turned on to reduce the output noise of the second pull-up node PU(N+1);
  • the eighth transistor M8 is turned on to reduce the noise of the second signal output terminal (N+1); of course, the thirteenth transistor M13 It is controlled by the second clock signal and is also turned on at this time to stably reduce the noise of the first signal output terminal Output(N).
  • the high potential of the pull-down node PD may be maintained by the third storage capacitor C3, thereby continuing to the first pull-up node PU(N) and the second pull-up node.
  • PU (N+1), the first signal output terminal Output (N), and the second signal output terminal Output (N+1) perform pull-down noise reduction.
  • the fourteenth transistor M14 is turned on to stably lower the second signal output end Output (N+1) noise.
  • a gate driving circuit including the shift register in the above embodiment, wherein the first shift register in each stage shift register
  • the first input signal terminal Input(N) of the unit is connected to the second signal output terminal Output(N+1) of the second shift register unit in the upper stage shift register; the first shift in each stage shift register
  • the first reset signal terminal RESET(N) of the bit register unit is connected to the second signal output terminal Output(N+1) of the second shift register unit in the shift register of the first stage;
  • the first of each stage shift register The first signal output terminal Output(N) of the shift register unit is connected to the second input signal terminal Input(N+1) of the second shift register unit in the shift register of the current stage;
  • the second signal output terminal Output(N+1) of the second shift register unit is connected to the first signal input end of the first shift register unit in the next stage shift register; the second shift in each stage shift register
  • the second reset signal terminal RESET(N+1) of the bit register unit is connected to the next level shift
  • the gate driving circuit in some embodiments of the present disclosure includes the shift register described in the above embodiment, the power consumption is small and the cost is low.
  • a display device including the above-described gate driving circuit is also disclosed in some embodiments of the present disclosure. Since the above-described gate driving circuit is included, it can realize a narrow-edge design.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device in some embodiments of the present disclosure may also include other conventional structures such as a power supply unit, a display driving unit, and the like.

Abstract

一种移位寄存器、栅极驱动电路、显示装置。移位寄存器包括：第一移位寄存器单元、第二移位寄存器单元、下拉控制子电路(20)、下拉子电路(30)；其中，第一移位寄存器单元包括：第一输入子电路(11)、第一输出子电路(12)、第一复位子电路、第一降噪子电路(14)；第二移位寄存器单元包括：第二输入子电路(21)、第二输出子电路(22)、第二复位子电路、第二降噪子电路(24)。

Description

移位寄存器、栅极驱动电路、显示装置
相关申请的交叉引用
本申请要求于2017年5月27日提交的中国专利申请第201710390668.5号的优先权，该申请的公开通过引用被全部合并于此。
技术领域
本公开涉及一种移位寄存器、栅极驱动电路、显示装置。
背景技术
随着液晶显示不断的发展，高分辨率、窄边框成为液晶显示发展的趋势，而栅极移位寄存器在面板中的应用，是实现窄边框与高分辨率的重要方法之一。
栅极驱动器GOA设计可以使得液晶显示面板成本更低，同时减少了一道工序，提高了产量。随着平板显示的发展，高分辨率、窄边框成为发展的潮流，而要实现高分辨率、窄边框显示，面板上集成栅极驱动电路是最重要的解决办法。
发明内容
本公开提供一种移位寄存器，包括：第一移位寄存器单元、第二移位寄存器单元、下拉控制子电路、下拉子电路；其中，所述第一移位寄存器单元包括：第一输入子电路、第一输出子电路、第一复位子电路、第一降噪子电路；所述第二移位寄存器单元包括：第二输入子电路、第二输出子电路、第二复位子电路、第二降噪子电路；
所述第一输入子电路，用于在第一输入信号的控制下，对第一上拉节点进行预充电；所述第一上拉节点为第一输入子电路、第一输出子电路、下拉子电路、第一复位子电路、第一降噪子电路之间的连接节点；
所述第一输出子电路，用于在所述第一上拉节点的电位的控制下，将第一时钟信号通过第一信号输出端进行输出；
所述第一复位子电路，用于在第一复位信号的控制下，通过第一电压信号对所述第一上拉节点和所述第一信号输出端的电位进行复位；
所述第二输入子电路，用于在第二输入信号的控制下，对第二上拉节点进行 预充电；所述第二上拉节点为第二输入子电路、第二输出子电路、下拉子电路之间的连接节点；
所述第二输出子电路，用于在所述第二上拉节点的电位的控制下，将第二时钟信号通过第二信号输出端进行输出；
所述第二复位子电路，用于在第二复位信号的控制下，通过所述第一电压信号对所述第二上拉节点和所述第二信号输出端的电位进行复位；
所述下拉控制子电路，用于在所述第一时钟信号或者所述第二时钟信号的控制下，控制下拉节点的电位；所述下拉节点为所述下拉控制子电路、所述下拉子电路、所述第一降噪子电路、所述第二降噪子电路之间的连接节点；
所述下拉子电路，用于在所述第一上拉节点的电位和所述第二上拉节点的电位的控制下，通过所述第一电压信号对所述下拉节点的电位进行下拉；所述第一降噪子电路，用于在所述下拉节点的控制下，通过所述第一电压信号降低所述第一上拉节点和所述第一信号输出端的输出噪声；
所述第二降噪子电路，用于在所述下拉节点的控制下，通过所述第一电压信号降低所述第二上拉节点和所述第二信号输出端的输出噪声。
可选地，所述移位寄存器还包括存储子电路，所述存储子电路，用于维持所述下拉节点的电位。
可选地，所述第一输入子电路包括第一晶体管；其中，
所述第一晶体管的第一极和控制极均连接第一输入信号端，所述第一晶体管的第二极连接所述第一上拉节点。
可选地，所述第一输出子电路包括第三晶体管和第一存储电容；其中，
所述第三晶体管的第一极连接第一时钟信号端，所述第三晶体管的第二极连接第一信号输出端，所述第三晶体管的控制极连接所述第一上拉节点；
所述第一存储电容的第一端连接所述第一上拉节点，所述第一存储电容的第二端连接所述第一信号输出端。
可选地，所述第一复位子电路包括：第二晶体管和第十三晶体管；其中，
所述第二晶体管的第一极连接所述第一上拉节点，所述第二晶体管的第二极连接第一电压信号端，所述第二晶体管的控制极连接第一复位信号端；
所述第十三晶体管的第一极连接所述第一信号输出端，所述第十三晶体管的第二极连接第一电压信号端，所述第十三晶体管的控制极连接第二时钟信号端。
可选地，所述第一复位子电路包括：第二晶体管和第十三晶体管；其中，
所述第二晶体管的第一极连接所述第一上拉节点，所述第二晶体管的第二极连接第一电压信号端，所述第二晶体管的控制极连接第一复位信号端；
所述第十三晶体管的第一极连接所述第一信号输出端，所述第十三晶体管的第二极连接第一电压信号端，所述第十三晶体管的控制极连接第一复位信号端。
可选地，所述第一降噪子电路包括第四晶体管和第十五晶体管；其中，
所述第四晶体管的第一极连接所述第一信号输出端，所述第四晶体管的第二极连接第一电压信号端，所述第四晶体管的控制极连接所述下拉节点；
所述第十五晶体管的第一极连接所述第一上拉节点，所述第十五晶体管的第二极连接第一电压信号端，所述第十五晶体管的控制极连接所述下拉节点。
可选地，所述第二输入子电路包括第五晶体管；其中，
所述第五晶体管的第一极和控制极均连接第二输入信号端，所述第五晶体管的第二极连接所述第二上拉节点。
可选地，所述第二输出子电路包括第七晶体管和第二存储电容；其中，
所述第七晶体管的第一极连接第二时钟信号端，所述第七晶体管的第二极连接所述第二信号输出端，所述第七晶体管的控制极连接所述第二上拉节点；
所述第二存储电容的第一端连接所述第二上拉节点，所述第二存储电容的第二端连接所述第二信号输出端。
可选地，所述第二复位子电路包括第六晶体管和第十四晶体管；其中，
所述第六晶体管的第一极连接所述第二上拉节点，所述第六晶体管的第二极连接第一电压信号端，所述第六晶体管的控制极连接第二复位信号端；
所述第十四晶体管的第一极连接所述第二信号输出端，所述第十四晶体管的第二极连接第一电压信号端，所述第十四晶体管的控制极连接第一时钟信号端。
可选地，所述第二复位子电路包括第六晶体管和第十四晶体管；其中，
所述第六晶体管的第一极连接所述第二上拉节点，所述第六晶体管的第二极连接第一电压信号端，所述第六晶体管的控制极连接第二复位信号端；
所述第十四晶体管的第一极连接所述第二信号输出端，所述第十四晶体管的第二极连接第一电压信号端，所述第十四晶体管的控制极连接第二复位信号端。
可选地，所述第二降噪子电路包括第八晶体管和第十六晶体管；其中，
所述第八晶体管的第一极连接所述第二信号输出端，所述第八晶体管的第二 极连接第一电压信号端，所述第八晶体管的控制极连接所述下拉节点；
所述第十六晶体管的第一连接所述第二上拉节点，所述第十六晶体管的第二极连接第一电压信号端，所述第十六晶体管的控制极连接所述下拉节点。
可选地，所述下拉子电路包括第九晶体管、第十晶体管、第十二晶体管；其中，
所述第九晶体管的第一极和控制极均连接所述第一上拉节点，所述第九晶体管的第二极连接所述第十二晶体管的控制极；
所述第十晶体管的第一极和控制极均连接所述第二上拉节点，所述第十晶体管的第二极连接第十二晶体管的控制极；
所述第十二晶体管的第一极连接所述下拉节点，所述第十二晶体管的第二极连接第一电压信号端，所述第十二晶体管的控制极连接所述第九晶体管的第二极和所述第十晶体管的第二极。
可选地，所述下拉控制子电路包括第十一晶体管；其中，
所述第十一晶体管的第一极和控制极均连接第二时钟信号端，所述第十一晶体管的第二极连接所述下拉节点。
可选地，所述下拉控制子电路包括第十一晶体管；其中，
所述第十一晶体管的第一极和控制极均连接第一时钟信号端，所述第十一晶体管的第二极连接所述下拉节点。
可选地，所述存储子电路包括第三存储电容；其中，
所述第三存储电容的第一端连接所述下拉节点，所述第三存储电容的第二端连接第一电压信号端。
本公开提供一种栅极驱动电路，其包括上述的移位寄存器。
可选地，每一级移位寄存器中的第一移位寄存器单元的第一输入信号端连接上一级移位寄存器中的第二移位寄存器单元的第二信号输出端；
每一级移位寄存器中的第一移位寄存器单元的第一复位信号端连接本级移位寄存器中的第二移位寄存器单元的第二信号输出端；
每一级移位寄存器中的第一移位寄存器单元的第一信号输出端连接本级移位寄存器中的第二移位寄存器单元的第二输入信号端；
每一级移位寄存器中的第二移位寄存器单元的第二信号输出端连接下一级移位寄存器中的第一移位寄存器单元的第一信号输入端；
每一级移位寄存器中的第二移位寄存器单元的第二复位信号端连接下一级移位寄存器中的第一移位寄存器单元的第一信号输出端。
本公开提供一种显示装置，其包括上述的栅极驱动电路。
附图说明
图1-3均为本公开的示例性实施例的移位寄存器的示意图；
图4为本公开的示例性实施例中与图1的移位寄存器对应的工作时序图；
图5为本公开的示例性实施例中与图3的移位寄存器对应的工作时序图；
图6为本公开的示例性实施例的栅极驱动电路的级联示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
本公开的实施例中所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极在一定条件下是可以互换的，所以其源极、漏极从连接关系的描述上是没有区别的。在本公开的实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性可以将晶体管分为N型和P型，以下实施例中是以晶体管为N型晶体管进行说明的。当采用N型晶体管时，第一极为N型晶体管的漏极，第二极为N型晶体管的源极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是，采用晶体管为P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开的实施例的保护范围内的。
由于本公开的实施例中是以薄膜晶体管为N型晶体管为例进行说明的，因此在下面的描述中，第一电压信号为低电平信号，第一电压信号端为低电平信号端。应当理解的是，如果薄膜晶体管采用P型晶体管，则此时的第一电压信号为高电平信号，第一电压信号端为高电平信号端。
本公开旨在至少解决或减轻现有技术中存在的技术问题之一，提供一种功耗较低、结构简单的移位寄存器、栅极驱动电路、显示装置。
本公开具有如下有益效果：
由于本公开中的移位寄存器包括两个为不同行栅线提供信号的移位寄存器单 元，即第一移位寄存器单元和第二移位寄存器单元，且这两个移位寄存器单元共用一个下拉子电路和一个下拉控制子电路，也就说第一移位寄存器单元和第二移位寄存器单元连接同一个下拉节点，同时增加了存储子电路，可以维持下拉节点的电位，从而实现了在两个移位寄存器单元均复位之后，下拉节点不断的为上拉节点和两个信号输出端放电，解决了时钟信号所引起的噪音电压问题，提高了良率。同时，两个移位寄存器单元共用一个下拉节点，与现有的移位寄存器相比，减少了晶体管的个数，从而有效的降低了功耗。
结合图1至图3所示，在本公开的一些实施例中，提供一种移位寄存器，包括：第一移位寄存器单元、第二移位寄存器单元、下拉控制子电路20、下拉子电路30；其中，第一移位寄存器单元包括：第一输入子电路11、第一输出子电路12、第一复位子电路、第一降噪子电路14；第二移位寄存器单元包括：第二输入子电路21、第二输出子电路22、第二复位子电路、第二降噪子电路24。
例如，第一输入子电路11用于在第一输入信号的控制下，对第一上拉节点PU(N)进行预充电；第一上拉节点PU(N)为第一输入子电路11、第一输出子电路12、下拉子电路30、第一复位子电路、第一降噪子电路14之间的连接节点；第一输出子电路12用于在第一上拉节点PU(N)的电位的控制下，将第一时钟信号通过第一信号输出端Output(N)进行输出；第一复位子电路用于在第一复位信号的控制下，通过低电平信号对第一上拉节点PU(N)和第一信号输出端Output(N)的电位进行复位；第二输入子电路21用于在第二输入信号的控制下，对第二上拉节点PU(N+1)进行预充电；第二上拉节点PU(N+1)为第二输入子电路21、第二输出子电路22、下拉子电路30之间的连接节点；第二输出子电路22用于在第二上拉节点PU(N+1)的电位的控制下，将第二时钟信号通过第二信号输出端Output(N+1)进行输出；第二复位子电路用于在第二复位信号的控制下，通过低电平信号对第二上拉节点PU(N+1)和第二信号输出端Output(N+1)的电位进行复位；下拉控制子电路20用于在第一时钟信号或者第二时钟信号的控制下，控制下拉节点PD的电位；下拉子电路30用于在第一上拉节点PU(N)的电位和第二上拉节点PU(N+1)的电位的控制下，通过低电平信号对下拉节点PD的电位进行下拉；下拉节点PD为下拉子电路30、下拉控制子电路20、第一复位降噪子电路以及第二复位降噪子电路之间的连接节点；第一降噪子电路14用于在下拉节点PD的控制下，通过低电平信号降低第一上拉节点PU(N)和第一信号输出端Output(N)的输出噪声；第二降噪子电路24用 于在下拉节点PD的控制下，通过低电平信号降低第二上拉节点PU(N+1)和第二信号输出端Output(N+1)的输出噪声。
由于本公开的一些实施例中的移位寄存器包括两个为不同行栅线提供信号的移位寄存器单元，即第一移位寄存器单元和第二移位寄存器单元，且这两个移位寄存器单元共用一个下拉子电路30和一个下拉控制子电路20，也就说第一移位寄存器单元和第二移位寄存器单元连接同一个下拉节点PD，即共用一个下拉节点PD，与现有的移位寄存器相比，减少了晶体管的个数，从而有效的降低了功耗。可选地，还可以增加存储子电路，用于维持所述下拉节点的电位，从而实现了在两个移位寄存器单元均复位之后，下拉节点PD不断的为上拉节点和两个信号输出端放电，解决了时钟信号所引起的噪音电压问题，提高了良率。
结合图1至图3所示，在本公开的一些实施例中，提供一种移位寄存器，包括：第一移位寄存器单元、第二移位寄存器单元、下拉控制子电路20、下拉子电路30，以及存储电容；其中，第一移位寄存器单元包括：第一输入子电路11、第一输出子电路12、第一复位子电路、第一降噪子电路14；第二移位寄存器单元包括：第二输入子电路21、第二输出子电路22、第二复位子电路、第二降噪子电路24。
对于第一移位寄存器单元的结构的具体介绍如下所述：
其中，第一输入子电路11，连接第一输入信号端Input(N)和第一上拉节点PU(N)，用于通过该第一输入信号端Input(N)所输入的第一输入信号，对第一上拉节点PU(N)进行预充电。
例如，第一输入子电路11可选地包括第一晶体管M1；其中，第一晶体管M1的第一极和控制极均连接第一输入信号端Input(N)，第一晶体管M1的第二极连接第一上拉节点PU(N)。
在第一移位寄存器单元的预充阶段，当第一输入信号端Input(N)所输入的第一输入信号为高电平时，第一晶体管M1被打开，此时该高电平信号可以通过第一晶体管M1为第一上拉节点PU(N)进行预充电。
其中，第一输出子电路12，连接第一时钟信号端CLK、第一上拉节点PU(N)、第一信号输出端Output(N)，用于在第一上拉节点PU(N)的电位的控制下，将第一时钟信号端CLK所输入的第一时钟信号，通过第一信号输出端Output(N)进行输出。
例如，第一输出子电路12可选地包括第三晶体管M3和第一存储电容C1；其 中，第三晶体管M3的第一极连接第一时钟信号端CLK，第三晶体管M3的第二极连接第一信号输出端Output(N)，第三晶体管M3的控制极连接所述第一上拉节点PU(N)；第一存储电容C1的第一端连接所述第一上拉节点PU(N)，第一存储电容C1的第二端连接所述第一信号输出端Output(N)。
在第一移位寄存器单元的输出阶段，由于第一上拉节点PU(N)在预充阶段被上拉至高电平，此时第三晶体管M3打开；第一时钟信号端CLK所输入的第一时钟信号为高电平信号，故第一信号输出端Output(N)输出高电平信号；同时，由于第一存储电容C1的自举效应，第一上拉节点PU(N)的电位进一步升高。
其中，第一复位子电路中的第一上拉节点复位单元131，连接第一复位信号端RESET(N)、第一上拉节点PU(N)和低电平信号端VGL，用于在第一复位信号端RESET(N)所输入的第一复位信号的控制下，通过低电平信号端VGL所输入的低电平信号拉低第一上拉节点的电位，以完成第一上拉节点PU(N)的复位；第一复位子电路中的第一信号输出端Output(N)复位单元132，连接第二时钟信号端CLKB、第一信号输出端Output(N)、低电平信号端VGL，用于在第二时钟信号端CLKB所输入的第二时钟信号的控制下，通过低电平信号端VGL所输入的低电平信号拉低第一信号输出端Output(N)的电位，以完成第一信号输出端Output(N)的复位。
例如，第一上拉节点PU(N)复位单元131可选地包括第二晶体管M2；该第二晶体管M2的第一极连接所述第一上拉节点PU(N)，该第二晶体管M2的第二极连接低电平信号端VGL，该第二晶体管M2的控制极连接第一复位信号端RESET(N)；第一信号输出端Output(N)复位单元132可选地包括第十三晶体管M13；该第十三晶体管M13的第一极连接第一信号输出端Output(N)，该第十三晶体管M13的第二极连接低电平信号端VGL，该第十三晶体管M13的控制极连接第二时钟信号端CLKB。
在第一移位寄存器单元的复位阶段，第一复位信号端RESET(N)所输入的第一复位信号为高电平信号，第二晶体管M2打开，通过低电平信号端VGL所输入的低电平信号下拉第一上拉节点PU(N)的电位，以完成第一上拉节点PU(N)的复位；与此同时，第二时钟信号端CLKB所输入的第二时钟信号为高电平信号，第十三晶体管M13打开，通过低电平信号端VGL所输入的低电平信号下拉第一信号输出端Output(N)的电位，以完成第一信号输出端Output(N)的复位。
当然，第一复位子电路中的第一信号输出端Output(N)复位单元132，也可以不连接第二时钟信号端CLKB，而是与第一复位信号端RESET(N)、第一信号输出端 Output(N)、低电平信号端VGL连接。此时第一信号输出端Output(N)复位单元132中所包括的第十三晶体管M13的第一极连接第一信号输出端Output(N)，第十三晶体管M13的第二极连接低电平信号端VGL，第十三晶体管M13的控制极连接第一复位信号端RESET(N)。在第一移位寄存器单元的复位阶段，第一复位信号端RESET(N)所输入的第一复位信号为高电平信号，第二晶体管M2和第十三晶体管M13均打开，通过低电平信号端VGL所输入的低电平信号下拉第一上拉节点PU(N)和第一信号输出端Output(N)的电位，以完成第一上拉节点PU(N)和第一信号输出端Output(N)的复位。
其中，第一降噪子电路14连接第一上拉节点PU(N)、第一信号输出端Output(N)、下拉节点PD，以及低电平信号端VGL，用于在下拉节点PD的电位的控制下，通过低电平信号端VGL所输入的低电平信号，降低第一上拉节点PU(N)和第一信号输出端Output(N)的输出噪声。
例如，第一降噪子电路14包括第四晶体管M4和第十五晶体管M15；其中，第四晶体管M4的第一极连接第一信号输出端Output(N)，第四晶体管M4的第二极连接低电平信号端VGL，第四晶体管M4的控制极连接下拉节点PD；第十五晶体管M15的第一极连接所述第一上拉节点PU(N)，第十五晶体管M15的第二极连接低电平信号端VGL，第十五晶体管M15的控制极连接所述下拉节点PD。
在第一移位寄存器单元的降噪阶段，下拉节点PD被上拉至高电平，同时对存储子电路40进行充电，此时第十五晶体管M15被打开，以降低第一上拉节点PU(N)的输出噪声；第四晶体管M4打开，以降低第一信号输出端Output(N)的噪声。
对于第二移位寄存器单元的结构的具体介绍如下所述：
其中，第二输入子电路21，连接第二输入信号端Input(N+1)、第二上拉节点PU(N+1)，用于通过该第二输入信号端Input(N+1)所输入的第二输入信号，对第二上拉节点PU(N+1)进行预充电。
例如，所述第二输入子电路21可选地包括第五晶体管M5；其中，第五晶体管M5的第一极和控制极均连接第二输入信号端Input(N+1)，第五晶体管M5的第二极连接所述第二上拉节点PU(N+1)。
在第二移位寄存器单元的预充阶段，第二输入信号端Input(N+1)被输入高电平信号，并通过该高点平信号对第二上拉节点PU(N+1)进行预充电。
其中，第二输出子电路22，连接第二时钟信号端CLKB、第二上拉节点PU(N+1)、 第二信号输出端Output(N+1)；用于在所述第二上拉节点PU(N+1)的电位的控制下，控制第二时钟信号端CLKB所输入的第二时钟信号，通过第二信号输出端Output(N+1)进行输出。
例如，第二输出子电路22可选地包括第七晶体管M7和第二存储电容C2；其中，第七晶体管M7的第一极连接第二时钟信号端CLKB，第七晶体管M7的第二极连接第二信号输出端Output(N+1)，第七晶体管M7的控制极连接第二上拉节点PU(N+1)；第二存储电容C2的第一端连接第二上拉节点PU(N+1)，第二存储电容C2的第二端连接第二信号输出端Output(N+1)。
在第二移位寄存器单元的输出阶段，由于第二上拉节点PU(N+1)在预充阶段被上拉至高电平，此时第五晶体管M5打开；第二时钟信号端CLKB所输入的第一时钟信号为高电平信号，故第二信号输出端Output(N+1)输出高电平信号；同时，由于第二存储电容C2的自举效应，第二上拉节点PU(N+1)的电位进一步升高。
其中，第二复位子电路中的第二上拉节点复位单元231，连接第二复位信号端RESET(N+1)、第二上拉节点PU(N+1)、低电平信号端VGL，用于在第二复位信号端RESET(N+1)所输入的第二复位信号的控制下，通过低电平信号端VGL所输入的低电平信号拉低第二上拉节点PU(N+1)的电位，以完成第二上拉节点PU(N+1)的复位；第二复位子电路中的第二信号输出端Output(N+1)复位单元232连接第一时钟信号端CLK、低电平信号端VGL和第二信号输出端Output(N+1)，用于在所述第一时钟信号端CLK所输入的第一时钟信号的控制下，通过低电平信号端VGL所输入的低电平信号拉低第二信号输出端Output(N+1)的电位，以完成第二信号输出端Output(N+1)的复位。
例如，第二上拉节点PU(N+1)复位单元231可选地包括第六晶体管M6；第二信号输出端Output(N+1)复位单元232可选地包括第十四晶体管M14；其中，第六晶体管M6的第一极连接第二上拉节点PU(N+1)，第六晶体管M6的第二极连接低电平信号端VGL，第六晶体管M6的控制极连接第二复位信号端RESET(N+1)；第十四晶体管M14的第一极连接所述第二信号输出端Output(N+1)，第十四晶体管M14的第二极连接低电平信号端VGL，第十四晶体管M14的控制极连接第一时钟信号端CLK。
在第二移位寄存器单元的复位阶段，第二复位信号端RESET(N+1)所输入的复位信号为高电平信号，第六晶体管M6打开，第二上拉节点PU(N+1)被下拉至低电 平，也即完成第二上拉节点PU(N+1)的复位；第一时钟信号端CLK所写入的信号也为高电平信号，第十四晶体管M14打开，第二信号输出端Output(N+1)被下拉至低电平，也即完成第二信号输出端Output(N+1)的复位。
当然，第二复位子电路中的第二信号输出端Output(N+1)复位单元232，也可以不连接第一时钟信号端CLK，而是与第二复位信号端RESET(N+1)、第二信号输出端Output(N+1)、低电平信号端VGL连接。此时第二信号输出端Output(N+1)复位单元232中所包括的第十四晶体管M14的第一极连接第二信号输出端Output(N+1)，第十四晶体管M14的第二极连接低电平信号端VGL，第十四晶体管M14的控制极连接第二复位信号端RESET(N+1)。在第二移位寄存器单元的复位阶段，第二复位信号端RESET(N+1)所输入的第二复位信号为高电平信号，第六晶体管M6和第十四晶体管M14均打开，通过低电平信号端VGL所输入的低电平信号下拉第二上拉节点PU(N+1)和第二信号输出端Output(N+1)的电位，以完成第二上拉节点PU(N+1)和第二信号输出端Output(N+1)的复位。
其中，第二降噪子电路24连接第二上拉节点PU(N+1)、第二信号输出端Output(N+1)、下拉节点PD，以及低电平信号端VGL，用于在下拉节点PD的电位的控制下，通过低电平信号端VGL所输入的低电平信号，降低第二上拉节点PU(N+1)和第二信号输出端Output(N+1)的输出噪声。
例如，第二降噪子电路24包括第八晶体管M8和第十六晶体管M16；其中，第八晶体管M8的第一极连接第二信号输出端Output(N+1)，第八晶体管M8的第二极连接低电平信号端VGL，第八晶体管M8的控制极连接下拉节点PD；第十六晶体管M16的第一极连接所述第二上拉节点PU(N+1)，第十六晶体管M16的第二极连接低电平信号端VGL，第十六晶体管M16的控制极连接所述下拉节点PD。
在第二移位寄存器单元的降噪阶段，下拉节点PD被上拉至高电平，同时对存储子电路40进行充电，此时第十六晶体管M16被打开，以降低第二上拉节点PU(N+1)的输出噪声；第八晶体管M8打开，以降低第二信号输出端Output(N+1)的噪声。
以上是对本公开的一些实施例中的移位寄存器中的第一移位寄存器单元和第二移位寄存器单元的介绍；接下来，对本公开的一些实施例中的存储子电路40、下拉子电路30、下拉控制子电路20的具体结构进行说明：
在本公开的一些实施例中，移位寄存器中的存储子电路40包括第三存储电容C3；该第三存储电容C3的第一端连接下拉节点PD，该第三存储电容C3的第二端 连接低电平信号端VGL；该第三存储电容C3的作用是用于维持下拉节点PD的电位。
其中，下拉控制子电路20连接第二时钟信号输入端和下拉节点PD，用于在第二时钟信号输入端所输入的第二时钟信号控制下，为下拉节点PD进行充电，也即为第三存储电容C3进行充电，以供第三存储电容C3在第一移位寄存器单元和第二移位寄存器单元均完成后，维持下拉节点PD保持高电位，以使第一降噪子电路14和第二降噪子电路24可以持续降低第一上拉节点PU(N)、第二上拉节点PU(N+1)、第一信号输出端Output(N)、第二信号输出端Output(N+1)所输出的信号的噪声。
例如，下拉控制子电路20可选地包括第十一晶体管M11；其中，第十一晶体管M11的第一极和控制极均连接第二时钟信号端CLKB，第十一晶体管M11的第二极连接所述下拉节点PD。
在第一移位寄存器单元和第二移位寄存器单元的降噪阶段，第二时钟信号端CLKB所写入的第二时钟信号为高电平信号，第十一晶体管M11被打开，下拉节点PD被上拉至高电平，同时对存储电容C3进行充电。
当然，下拉控制子电路20也可以连接第一时钟信号输入端和下拉节点PD，用于在第一时钟信号输入端所输入的第一时钟信号控制下，为下拉节点PD进行充电，也即为第三存储电容C3进行充电，以供第三存储电容C3在第一移位寄存器单元和第二移位寄存器单元均完成后，维持下拉节点PD保持高电位，以使第一降噪子电路14和第二降噪子电路24可以持续降低第一上拉节点PU(N)、第二上拉节点PU(N+1)、第一信号输出端Output(N)、第二信号输出端Output(N+1)所输出的信号的噪声。
例如，下拉控制子电路20可选地包括第十一晶体管M11；其中，第十一晶体管M11的第一极和控制极均连接第一时钟信号端CLK，第十一晶体管M11的第二极连接所述下拉节点PD。
在第一移位寄存器单元和第二移位寄存器单元的降噪阶段，第一时钟信号端CLK所写入的第一时钟信号为高电平信号，第十一晶体管M11被打开，下拉节点PD被上拉至高电平，同时对存储电容C3进行充电。
其中，下拉子电路30连接第一上拉节点PU(N)、第二上拉节点PU(N+1)、低电平信号端VGL和下拉节点PD；用于在第一上拉节点PU(N)和第二上拉节点PU(N+1)的电位的控制下，通过低电平信号端VGL所输入的低电平信号，拉低下拉节点PD 的电位。
例如，下拉子电路30可选地包括第九晶体管M9、第十晶体管M10、第十二晶体管M12；其中，第九晶体管M9的第一极和控制极均连接第一上拉节点PU(N)，第九晶体管M9的第二极连接第十二晶体管M12的控制极；第十晶体管M10的第一极和控制极均连接第二上拉节点PU(N+1)，第十晶体管M10的第二极连接第十二晶体管M12的控制极；第十二晶体管M12的第一极连接下拉节点PD，第十二晶体管M12的第二极连接低电平信号端VGL，第十二晶体管M12的控制极连接第九晶体管M9的第二极和第十晶体管M10的第二极。
由于第九晶体管M9和第十晶体管M10的开启与关断是分别由第一上拉节点PU(N)和第二上拉节点PU(N+1)的电位控制的，而第十二晶体管M12是由第九晶体管M9所输出的第一上拉节点PU(N)的电位和第十晶体管M10所输出的第二上拉节点PU(N+1)的电位控制的，因此，只要第一上拉节点PU(N)和第二上拉节点PU(N+1)中一者的电位为高电平信号，第十二晶体管M12就会被打开，此时下拉节点PD的电位就会被低电平信号端VGL所输入的低电平信号拉低。
以下结合图1和图4所示，对本公开的一些实施例中的移位寄存器的工作原理进行说明。
第一阶段(第一移位寄存器单元的预充阶段)：第一输入信号端Input(N)所写入的第一输入信号为高电平信号，第一晶体管M1打开，此时第一输入信号通过第一晶体管M1给第一存储电容C1充电，使得第一上拉节点PU(N)的电位被拉高；由于第一上拉节点PU(N)此时处于高电平，使得第九晶体管M9和第十二晶体管M12打开，对存储电容C3进行放电，将下拉节点PD的电位下拉为低电平；而此时下拉节点PD的电位为低电平，因此第四晶体管M4和第十五晶体管M15关断，与此同时第一时钟信号为低电平，从而保证第一信号输出端Output(N)输出稳定的低电平信号。
第二阶段(第一移位寄存器单元的输出阶段，以及第二移位寄存器单元的预充阶段)：第一输入信号端Input(N)所写入的第一输入信号为低电平信号，第一晶体管M1关断，第一上拉节点PU(N)继续保持高电位，第三晶体管M3保持开启状态，此时，第一时钟信号端CLK所输入的第一时钟信号为高电平信号，第一上拉节点PU(N)由于第一存储电容C1的自举效应(bootstrapping)进一步拉高第一上拉节点PU(N)的电位，使得第一信号输出端Output(N)输出高电平信号；由于第一 上拉节点PU(N)为高电位，因此第九晶体管M9和第十二晶体管M12处于开启状态，故下拉节点PD为低电平信号，第四晶体管M4和第十五晶体管M15继续保持关断，同时第二时钟信号端CLKB所写入的第二时钟信号为低电平信号，第十三晶体管M13处于关闭状态，保证第一信号输出端Output(N)输出信号的稳定性。
可选地，第一移位寄存器单元中的第一信号输出端Output(N)所输出的高电平信号，可以作为该级移位寄存器中的第二移位寄存器单元中的第二输入信号端Input(N+1)所写入的第二输入信号，此时第五晶体管M5打开，第二上拉节点PU(N+1)被拉高，同时对第二存储电容C2进行充电，由于此时第二时钟信号端CLKB所写入的第二时钟信号为低电平信号，因此第二信号输出端Output(N+1)输出低电平信号。与此同时，第二上拉节点PU(N+1)被拉高，使得第十晶体管M10和第十二晶体管M12被打开，故下拉节点PD处于低电平，第八晶体管M8和第十六晶体管M16关断，从而保证第二信号输出端Output(N+1)输出稳定的低电平信号。
第三阶段(第一移位寄存器单元的复位阶段，以及第二移位寄存器单元的输出阶段)：第一复位信号端RESET(N)所写入得复位信号为高电平，第二时钟信号端CLKB所写入的第二时钟信号为高电平，此时第二晶体管M2和第十五晶体管M15被打开，第一上拉节点PU(N)被下拉至低电平，也即完成第一下拉节点PD的复位；第十三晶体管M13打开，第一信号输出端Output(N)被下拉至低电平，此时完成第一信号输出端Output(N)的复位。
与此同时，由于第一移位寄存器单元中的第一信号输出端Output(N)所输出的信号作为第二移位寄存器单元中的第二输入信号端Input(N+1)的输入，因此，第五晶体管M5关闭，第二存储电容C2放电，由于第二存储电容C2的自举效应，放大第二上拉节点PU(N+1)的电位，第二时钟信号为高电平，第七晶体管M7打开，因此第二信号输出端Output(N+1)输出高电平信号。此处需要注意的是，由于此时第二上拉节点PU(N+1)为高电平，第十晶体管M10和第十二晶体管M12打开，因此下拉节点PD被拉低，虽然第二时钟时钟信号为高电平，第十一晶体管M11被打开，但是下拉节点PD也不会被拉高。之所以如此是因为，所选取的第十一晶体管M11的宽长比是小于第十晶体管M10和第十二晶体管M12的。
在此要说明的是，由于在此阶段第一复位信号端RESET(N)所输入的信号为高电平信号，而在该阶段第二信号输出端Output(N+1)所输出的信号刚好为高电平信号，因此可以由第二信号输出端Output(N+1)为第一复位信号端RESET(N)提供复 位信号。
第四阶段(第二移位寄存器单元的复位阶段)：第二复位信号端RESET(N+1)所写入的复位信号为高电平信号，第六晶体管M6打开，第二上拉节点PU(N+1)被下拉至低电平，也即完成第二上拉节点PU(N+1)的复位；第一时钟信号端CLK所写入的第一时钟信号也为高电平信号，第十四晶体管M14打开，第二信号输出端Output(N+1)被下拉至低电平，也即完成第二信号输出端Output(N+1)的复位。
第五阶段(第一移位寄存器单元和第二移位寄存器单元的降噪阶段)：第二时钟信号端CLKB所写入的第二时钟信号为高电平信号，第十一晶体管M11被打开，下拉节点PD被上拉至高电平，同时对第三存储电容C3进行充电，此时第十五晶体管M15被打开，以降低第一上拉节点PU(N)的输出噪声；第四晶体管M4打开，以降低第一信号输出端Output(N)的噪声；第六晶体管M6打开，以降低第二上拉节点PU(N+1)的输出噪声；第八晶体管M8打开，以降低第二信号输出端Output(N+1)的噪声；当然，第十三晶体管M13被第二时钟信号控制，此时也是被打开的，用以稳定的降低第一信号输出端Output(N)的噪声。之后，虽然第二时钟信号会间隔一定时间变为低电平，但是可以通过第三存储电容C3维持下拉节点PD的高电位，从而继续对第一上拉节点PU(N)、第二上拉节点PU(N+1)、第一信号输出端Output(N)、第二信号输出端Output(N+1)进行下拉降噪。其中，在第二时钟信号为低电平时，第一时钟信号端CLK所写入的第一钟信号为高电平信号，第十四晶体管M14打开，用以稳定的降低第二信号输出端Output(N+1)的噪声。
之后，重复步骤五，直至下一帧的到来。
在此需要说明的是，当所采用的移位寄存器单元中的下拉控制子电路20的第十一晶体管M11的第一极和控制极均连接第一时钟信号端CLK，第十一晶体管M11的第二极连接所述下拉节点PD时，该移位寄存器的驱动方法与上述方法相类似，区别仅在于第四阶段(第二移位寄存器单元的复位阶段)和第五阶段(第一移位寄存器单元和第二移位寄存器单元的降噪阶段)，结合图3和图5所示，第四阶段和第五阶段具体包括：
第四阶段(第二移位寄存器单元的复位阶段)：第二复位信号端RESET(N+1)所写入的复位信号为高电平信号，第六晶体管M6打开，第二上拉节点PU(N+1)被下拉至低电平，也即完成第二上拉节点PU(N+1)的复位；第一时钟信号端CLK所写入的第一时钟信号也为高电平信号，第十四晶体管M14打开，第二信号输出端 Output(N+1)被下拉至低电平，也即完成第二信号输出端Output(N+1)的复位。与此同时，由于第一时钟信号端CLK所写入的第一时钟信号为高电平信号，故第十一晶体管M11也是被打开的，此时下拉节点PD被上拉至高电平，同时对第三存储电容C3进行充电。
第五阶段(第一移位寄存器单元和第二移位寄存器单元的降噪阶段)：由于在第四阶段第三存储电容C3被充电，此时可以通过第三存储电容C3维持下拉节点PD的高电位，此时第十五晶体管M15被打开，以降低第一上拉节点PU(N)的输出噪声；第四晶体管M4打开，以降低第一信号输出端Output(N)的噪声；第六晶体管M6打开，以降低第二上拉节点PU(N+1)的输出噪声；第八晶体管M8打开，以降低第二信号输出端Output(N+1)的噪声；当然，第十三晶体管M13被第二时钟信号控制，此时也是被打开的，用以稳定的降低第一信号输出端Output(N)的噪声。之后，虽然第一时钟信号间隔一定时间变为低电平，但是可以通过第三存储电容C3维持下拉节点PD的高电位，从而继续对第一上拉节点PU(N)、第二上拉节点PU(N+1)、第一信号输出端Output(N)、第二信号输出端Output(N+1)进行下拉降噪。其中，在第一时钟信号为低电平时，第一时钟信号端CLK所写入的第一时钟信号为高电平信号，第十四晶体管M14打开，用以稳定的降低第二信号输出端Output(N+1)的噪声。
如图6所示，在本公开的一些实施例中，提供了一种栅极驱动电路，其包括上述实施例中的移位寄存器，其中，每一级移位寄存器中的第一移位寄存器单元的第一输入信号端Input(N)连接上一级移位寄存器中的第二移位寄存器单元的第二信号输出端Output(N+1)；每一级移位寄存器中的第一移位寄存器单元的第一复位信号端RESET(N)连接本级移位寄存器中的第二移位寄存器单元的第二信号输出端Output(N+1)；每一级移位寄存器中的第一移位寄存器单元的第一信号输出端Output(N)连接本级移位寄存器中的第二移位寄存器单元的第二输入信号端Input(N+1)；每一级移位寄存器中的第二移位寄存器单元的第二信号输出端Output(N+1)连接下一级移位寄存器中的第一移位寄存器单元的第一信号输入端；每一级移位寄存器中的第二移位寄存器单元的第二复位信号端RESET(N+1)连接下一级移位寄存器中的第一移位寄存器单元的第一信号输出端。
由于本公开的一些实施例中的栅极驱动电路包括上述实施例中所述的移位寄存器，故其功耗较小，成本较低。
相应的，在本公开的一些实施例中还公开了一种显示装置，其包括上述的栅极驱动电路。由于包括上述的栅极驱动电路，故其可以实现窄边化设计。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本公开的一些实施例中的显示装置还可以包括其他常规结构，如电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种移位寄存器，包括：第一移位寄存器单元、第二移位寄存器单元、下拉控制子电路、下拉子电路；其中，所述第一移位寄存器单元包括：第一输入子电路、第一输出子电路、第一复位子电路、第一降噪子电路；所述第二移位寄存器单元包括：第二输入子电路、第二输出子电路、第二复位子电路、第二降噪子电路；
    所述第一输入子电路，用于在第一输入信号的控制下，对第一上拉节点进行预充电；所述第一上拉节点为第一输入子电路、第一输出子电路、下拉子电路、第一复位子电路、第一降噪子电路之间的连接节点；
    所述第一输出子电路，用于在所述第一上拉节点的电位的控制下，将第一时钟信号通过第一信号输出端进行输出；
    所述第一复位子电路，用于在第一复位信号的控制下，通过第一电压信号对所述第一上拉节点和所述第一信号输出端的电位进行复位；
    所述第二输入子电路，用于在第二输入信号的控制下，对第二上拉节点进行预充电；所述第二上拉节点为第二输入子电路、第二输出子电路、下拉子电路之间的连接节点；
    所述第二输出子电路，用于在所述第二上拉节点的电位的控制下，将第二时钟信号通过第二信号输出端进行输出；
    所述第二复位子电路，用于在第二复位信号的控制下，通过所述第一电压信号对所述第二上拉节点和所述第二信号输出端的电位进行复位；
    所述下拉控制子电路，用于在所述第一时钟信号或者所述第二时钟信号的控制下，控制下拉节点的电位；所述下拉节点为所述下拉控制子电路、所述下拉子电路、所述第一降噪子电路、所述第二降噪子电路之间的连接节点；
    所述下拉子电路，用于在所述第一上拉节点的电位和所述第二上拉节点的电位的控制下，通过所述第一电压信号对所述下拉节点的电位进行下拉；
    所述第一降噪子电路，用于在所述下拉节点的控制下，通过所述第一电压信号降低所述第一上拉节点和所述第一信号输出端的输出噪声；
    所述第二降噪子电路，用于在所述下拉节点的控制下，通过所述第一电压信号降低所述第二上拉节点和所述第二信号输出端的输出噪声。
  2. 根据权利要求1所述的移位寄存器，还包括存储子电路，所述存储子电路，用于维持所述下拉节点的电位。
  3. 根据权利要求1所述的移位寄存器，其中，所述第一输入子电路包括第一晶体管；其中，
    所述第一晶体管的第一极和控制极均连接第一输入信号端，所述第一晶体管的第二极连接所述第一上拉节点。
  4. 根据权利要求1所述的移位寄存器，其中，所述第一输出子电路包括第三晶体管和第一存储电容；其中，
    所述第三晶体管的第一极连接第一时钟信号端，所述第三晶体管的第二极连接第一信号输出端，所述第三晶体管的控制极连接所述第一上拉节点；
    所述第一存储电容的第一端连接所述第一上拉节点，所述第一存储电容的第二端连接所述第一信号输出端。
  5. 根据权利要求1所述的移位寄存器，其中，所述第一复位子电路包括：第二晶体管和第十三晶体管；其中，
    所述第二晶体管的第一极连接所述第一上拉节点，所述第二晶体管的第二极连接第一电压信号端，所述第二晶体管的控制极连接第一复位信号端；
    所述第十三晶体管的第一极连接所述第一信号输出端，所述第十三晶体管的第二极连接第一电压信号端，所述第十三晶体管的控制极连接第二时钟信号端。
  6. 根据权利要求1所述的移位寄存器，其中，所述第一复位子电路包括：第二晶体管和第十三晶体管；其中，
    所述第二晶体管的第一极连接所述第一上拉节点，所述第二晶体管的第二极连接第一电压信号端，控制极连接第一复位信号端；
    所述第十三晶体管的第一极连接所述第一信号输出端，所述第十三晶体管的第二极连接第一电压信号端，所述第十三晶体管的控制极连接第一复位信号端。
  7. 根据权利要求1所述的移位寄存器，其中，所述第一降噪子电路包括第四晶体管和第十五晶体管；其中，
    所述第四晶体管的第一极连接所述第一信号输出端，所述第四晶体管的第二极连接第一电压信号端，所述第四晶体管的控制极连接所述下拉节点；
    所述第十五晶体管的第一极连接所述第一上拉节点，所述第十五晶体管的第二极连接第一电压信号端，所述第十五晶体管的控制极连接所述下拉节点。
  8. 根据权利要求1所述的移位寄存器，其中，所述第二输入子电路包括第五晶体管；其中，
    所述第五晶体管的第一极和控制极均连接第二输入信号端，所述第五晶体管的第二极连接所述第二上拉节点。
  9. 根据权利要求1所述的移位寄存器，其中，所述第二输出子电路包括第七晶体管和第二存储电容；其中，
    所述第七晶体管的第一极连接第二时钟信号端，所述第七晶体管的第二极连接所述第二信号输出端，所述第七晶体管的控制极连接所述第二上拉节点；
    所述第二存储电容的第一端连接所述第二上拉节点，所述第二存储电容的第二端连接所述第二信号输出端。
  10. 根据权利要求1所述的移位寄存器，其中，所述第二复位子电路包括第六晶体管和第十四晶体管；其中，
    所述第六晶体管的第一极连接所述第二上拉节点，所述第六晶体管的第二极连接第一电压信号端，所述第六晶体管的控制极连接第二复位信号端；
    所述第十四晶体管的第一极连接所述第二信号输出端，所述第十四晶体管的第二极连接第一电压信号端，所述第十四晶体管的控制极连接第一时钟信号端。
  11. 根据权利要求1所述的移位寄存器，其中，所述第二复位子电路包括第六晶体管和第十四晶体管；其中，
    所述第六晶体管的第一极连接所述第二上拉节点，所述第六晶体管的第二极连接第一电压信号端，所述第六晶体管的控制极连接第二复位信号端；
    所述第十四晶体管的第一极连接所述第二信号输出端，所述第十四晶体管的第二极连接第一电压信号端，所述第十四晶体管的控制极连接第二复位信号端。
  12. 根据权利要求1所述的移位寄存器，其中，所述第二降噪子电路包括第八晶体管和第十六晶体管；其中，
    所述第八晶体管的第一极连接所述第二信号输出端，所述第八晶体管的第二极连接第一电压信号端，所述第八晶体管的控制极连接所述下拉节点；
    所述第十六晶体管的第一极连接所述第二上拉节点，所述第十六晶体管的第二极连接第一电压信号端，所述第十六晶体管的控制极连接所述下拉节点。
  13. 根据权利要求1所述的移位寄存器，其中，所述下拉子电路包括第九晶体管、第十晶体管、第十二晶体管；其中，
    所述第九晶体管的第一极和控制极均连接所述第一上拉节点，所述第九晶体管的第二极连接所述第十二晶体管的控制极；
    所述第十晶体管的第一极和控制极均连接所述第二上拉节点，所述第十晶体管的第二极连接第十二晶体管的控制极；
    所述第十二晶体管的第一极连接所述下拉节点，所述第十二晶体管的第二极连接第一电压信号端，所述第十二晶体管的控制极连接所述第九晶体管的第二极和所述第十晶体管的第二极。
  14. 根据权利要求1所述的移位寄存器，其中，所述下拉控制子电路包括第十一晶体管；其中，
    所述第十一晶体管的第一极和控制极均连接第二时钟信号端，所述第十一晶体管的第二极连接所述下拉节点。
  15. 根据权利要求1所述的移位寄存器，其中，所述下拉控制子电路包括第十一晶体管；其中，
    所述第十一晶体管的第一极和控制极均连接第一时钟信号端，所述第十一晶体管的第二极连接所述下拉节点。
  16. 根据权利要求2所述的移位寄存器，其中，所述存储子电路包括第三存储电容；其中，
    所述第三存储电容的第一端连接所述下拉节点，所述第三存储电容的第二端连接第一电压信号端。
  17. 一种栅极驱动电路，包括权利要求1-16中任一项所述的移位寄存器。
  18. 根据权利要求17所述的栅极驱动电路，其中，每一级移位寄存器中的第一移位寄存器单元的第一输入信号端连接上一级移位寄存器中的第二移位寄存器单元的第二信号输出端；
    每一级移位寄存器中的第一移位寄存器单元的第一复位信号端连接本级移位寄存器中的第二移位寄存器单元的第二信号输出端；
    每一级移位寄存器中的第一移位寄存器单元的第一信号输出端连接本级移位寄存器中的第二移位寄存器单元的第二信号输入端；
    每一级移位寄存器中的第二移位寄存器单元的第二信号输出端连接下一级移位寄存器中的第一移位寄存器单元的第一信号输入端；
    每一级移位寄存器中的第二移位寄存器单元的第二复位信号端连接下一级移位寄存器中的第一移位寄存器单元的第一信号输出端。
  19. 一种显示装置，包括权利要求17或18所述的栅极驱动电路。
PCT/CN2017/111559 2017-05-27 2017-11-17 移位寄存器、栅极驱动电路、显示装置 WO2018218886A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP17863286.5A EP3633664A4 (en) 2017-05-27 2017-11-17 SLIDING REGISTER, GATE DRIVER CIRCUIT, DISPLAY DEVICE
US15/773,013 US10891913B2 (en) 2017-05-27 2017-11-17 Shift register circuitry, gate driving circuit, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710390668.5A CN108932933B (zh) 2017-05-27 2017-05-27 移位寄存器、栅极驱动电路、显示装置
CN201710390668.5 2017-05-27

Publications (1)

Publication Number Publication Date
WO2018218886A1 true WO2018218886A1 (zh) 2018-12-06

Family

ID=64451436

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/111559 WO2018218886A1 (zh) 2017-05-27 2017-11-17 移位寄存器、栅极驱动电路、显示装置

Country Status (4)

Country Link
US (1) US10891913B2 (zh)
EP (1) EP3633664A4 (zh)
CN (1) CN108932933B (zh)
WO (1) WO2018218886A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109872699A (zh) * 2019-04-15 2019-06-11 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107068106B (zh) * 2017-06-21 2019-06-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN109817182B (zh) * 2019-04-10 2021-04-23 京东方科技集团股份有限公司 一种显示面板及显示装置
CN110223648B (zh) * 2019-05-09 2020-07-10 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路
CN110136653B (zh) * 2019-05-29 2022-05-13 合肥京东方卓印科技有限公司 移位寄存器、栅极驱动电路及显示装置
CN110264939A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示控制方法
CN110459185B (zh) * 2019-07-19 2021-09-17 信利半导体有限公司 一种低噪声的goa驱动电路、驱动方法、和显示装置
WO2021022437A1 (zh) * 2019-08-05 2021-02-11 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示面板、显示装置以及驱动方法
CN110459190B (zh) 2019-08-26 2021-11-05 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN110706639A (zh) * 2019-11-15 2020-01-17 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
WO2021120166A1 (zh) * 2019-12-20 2021-06-24 京东方科技集团股份有限公司 显示基板及其制作方法、和显示装置
CN112382239B (zh) * 2020-11-05 2022-07-29 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN113035258A (zh) * 2021-03-09 2021-06-25 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示面板
CN113450861B (zh) * 2021-06-28 2024-03-12 上海中航光电子有限公司 移位寄存单元、电路及驱动方法、显示面板和显示装置
CN114093332B (zh) * 2021-11-26 2023-09-29 合肥京东方光电科技有限公司 移位寄存器单元及其控制方法、栅极驱动电路、阵列基板
WO2024065658A1 (zh) * 2022-09-30 2024-04-04 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2360650B (en) * 1998-10-21 2002-03-13 Lg Philips Lcd Co Ltd Shift register
CN102842278A (zh) * 2012-08-06 2012-12-26 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示器
CN102956269A (zh) * 2012-07-05 2013-03-06 友达光电股份有限公司 移位寄存器
CN103208311A (zh) * 2008-12-15 2013-07-17 友达光电股份有限公司 移位寄存器
CN104376825A (zh) * 2014-11-20 2015-02-25 深圳市华星光电技术有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN106157912A (zh) * 2016-08-30 2016-11-23 合肥京东方光电科技有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8344989B2 (en) * 2007-12-31 2013-01-01 Lg Display Co., Ltd. Shift register
CN103035298B (zh) * 2012-12-14 2015-07-15 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN103345941B (zh) * 2013-07-03 2016-12-28 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、移位寄存器电路及显示装置
CN103761954B (zh) * 2014-02-17 2016-10-19 友达光电(厦门)有限公司 显示面板与栅极驱动器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2360650B (en) * 1998-10-21 2002-03-13 Lg Philips Lcd Co Ltd Shift register
CN103208311A (zh) * 2008-12-15 2013-07-17 友达光电股份有限公司 移位寄存器
CN102956269A (zh) * 2012-07-05 2013-03-06 友达光电股份有限公司 移位寄存器
CN102842278A (zh) * 2012-08-06 2012-12-26 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示器
CN104376825A (zh) * 2014-11-20 2015-02-25 深圳市华星光电技术有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN106157912A (zh) * 2016-08-30 2016-11-23 合肥京东方光电科技有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109872699A (zh) * 2019-04-15 2019-06-11 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路和显示装置

Also Published As

Publication number Publication date
CN108932933A (zh) 2018-12-04
US10891913B2 (en) 2021-01-12
EP3633664A1 (en) 2020-04-08
CN108932933B (zh) 2020-01-21
US20200243034A1 (en) 2020-07-30
EP3633664A4 (en) 2020-12-16

Similar Documents

Publication Publication Date Title
WO2018218886A1 (zh) 移位寄存器、栅极驱动电路、显示装置
US10593284B2 (en) Shift register unit and method for driving same, shift register circuit and display apparatus
WO2018059075A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US10140910B2 (en) Shift register, a gate line driving circuit, an array substrate and a display apparatus
CN107833552B (zh) 栅极驱动单元、栅极驱动电路及其驱动方法、显示装置
WO2017028488A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动装置和显示装置
WO2017121176A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
US11380280B2 (en) Shift register and driving method effectively avoiding threshold value drift of thin film transistor and better noise reduction
CN108962154B (zh) 移位寄存器单元、阵列基板栅极驱动电路、显示器以及栅极驱动方法
WO2016188287A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN107331418B (zh) 移位寄存器及其驱动方法、栅极驱动电路及显示装置
WO2018209937A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN104715734A (zh) 移位寄存器、栅极驱动电路及显示装置
WO2019184905A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路及显示装置
WO2018059159A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
WO2020019426A1 (zh) 包括goa电路的液晶面板及其驱动方法
WO2020019433A1 (zh) 包括goa电路的液晶面板及其驱动方法
CN108573668A (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US20210209993A1 (en) Shift register, gate driver-on-array circuit and driving method thereof, display device
WO2018166215A1 (zh) 移位寄存器单元、阵列基板和显示装置
WO2019205962A1 (zh) 一种移位寄存器单元、栅极驱动电路、驱动方法及显示装置
WO2019153864A1 (zh) 移位寄存器单元及其控制方法、栅极驱动电路、显示装置
US20130177128A1 (en) Shift register and method thereof
WO2018177047A1 (zh) 移位寄存单元及其驱动方法、栅极驱动电路及显示装置
WO2019010956A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17863286

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE