WO2018166215A1 - 移位寄存器单元、阵列基板和显示装置 - Google Patents

移位寄存器单元、阵列基板和显示装置 Download PDF

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Publication number
WO2018166215A1
WO2018166215A1 PCT/CN2017/109287 CN2017109287W WO2018166215A1 WO 2018166215 A1 WO2018166215 A1 WO 2018166215A1 CN 2017109287 W CN2017109287 W CN 2017109287W WO 2018166215 A1 WO2018166215 A1 WO 2018166215A1
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WIPO (PCT)
Prior art keywords
transistor
node
clock signal
shift register
register unit
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PCT/CN2017/109287
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English (en)
French (fr)
Inventor
钱先锐
李博
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/770,798 priority Critical patent/US10672491B2/en
Publication of WO2018166215A1 publication Critical patent/WO2018166215A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display, and in particular to a shift register unit, an array substrate, and a display device.
  • the Gate Driver On Array (GOA) technology not only saves cost, but also realizes symmetric design on both sides of the display panel, and also eliminates the bonding area of the chip and the wiring such as the fan-out area.
  • the area is conducive to the realization of the narrow bezel design.
  • GOA technology can eliminate the chip bonding process in the row direction, it will also greatly help the overall productivity and yield improvement.
  • the first node of the control signal output and the second node of the control signal reset are provided in the shift register unit, and the second signal is used by the diode-connected thin film transistor (TFT)
  • TFT thin film transistor
  • the node performs a periodic reset. Therefore, the TFT will be in a state of alternating switch for a long time under the action of the clock signal, so that a large threshold voltage drift is likely to occur, affecting the potential of the second node, causing the output signal of the current stage to be abnormal, and will be in the shift register unit.
  • the cascading relationship passes the exception signal down, causing a wide range of display anomalies.
  • the gate voltage of the TFT can be reduced by means of voltage division or the like to reduce the threshold voltage drift and enhance the stability of the shift register unit.
  • the TFT that needs to be added to lower the gate voltage is also connected to the clock signal, so there is still a problem of threshold voltage drift, and the output signal is still abnormal under long-term effects. That is to say, the above means can only alleviate the signal distortion to a certain extent, and cannot solve the problem of the abnormality of the output signal caused thereby.
  • the present disclosure provides a shift register unit including a second node for controlling a reset of a signal, the shift register unit further comprising:
  • a gate of the first transistor is connected to a third node, one of a source and a drain is connected to a first clock signal line, and the other is connected to the second node;
  • a gate of the second transistor is connected to the third node, one of a source and a drain is connected to the third node, and the other is connected to the first clock signal line;
  • a charging module respectively connected to the third node and the second clock signal line, configured to set a level at the third node to an active level when the second clock signal line is an active level;
  • a storage module respectively connecting the third node and the first clock signal line, configured to store a threshold voltage of the second transistor, and compensating a threshold voltage of the first transistor by using a stored threshold voltage
  • the threshold voltages of the first transistor and the second transistor are the same; one of a positive phase clock signal and an inverted clock signal is respectively loaded on the first clock signal line and the second clock signal line.
  • the storage module is configured to store a threshold voltage of the second transistor when the third node discharges the first clock signal line by using the second transistor;
  • the memory module is configured to compensate a threshold voltage of the first transistor with a stored threshold voltage when the first clock signal line changes a level at the second node by the first transistor.
  • the time from the active level to the inactive level on the first clock signal line is earlier than the second clock signal line by the invalid power The moment of turning to the active level.
  • the storage module includes a first capacitor, a first end of the first capacitor is connected to the third node, and a second end is connected to the first clock signal line.
  • the charging module includes a third transistor, a gate of the third transistor is connected to the second clock signal line, and one of a source and a drain is connected to the second clock signal. The other line connects the third node.
  • the shift register unit includes an output end and a first node for controlling a signal output, and the shift register unit further includes:
  • a gate of the fourth transistor is connected to the first node, one of a source and a drain is connected to the second clock signal line, and the other is connected to the output end;
  • the first end of the second capacitor is connected to the first node, and the second end is connected to the output end.
  • the shift register unit further has an input end and a reset end, and the shift register unit further includes:
  • a gate of the fifth transistor is connected to the input end, one of the source and the drain is connected to the input end, and the other is connected to the first node;
  • a gate of the sixth transistor is connected to the reset terminal, one of a source and a drain is connected to the first node, and the other is connected to an inactive level voltage line;
  • a seventh transistor a gate of the seventh transistor is connected to the reset terminal, one of a source and a drain is connected to the output terminal, and the other is connected to an inactive level voltage line.
  • the shift register unit further includes:
  • the eighth transistor, the gate of the eighth transistor is connected to the first clock signal line, one of the source and the drain is connected to the input end, and the other is connected to the first node;
  • the ninth transistor a gate of the ninth transistor is connected to the first clock signal line, one of a source and a drain is connected to the output terminal, and the other is connected to the invalid level voltage line.
  • the shift register unit includes an output end and a first node for controlling a signal output, and the shift register unit further includes:
  • a gate of the tenth transistor is connected to the second node, one of a source and a drain is connected to the first node, and the other is connected to an inactive level voltage line;
  • An eleventh transistor a gate of the eleventh transistor is connected to the second node, one of a source and a drain is connected to the output end, and the other is connected to an inactive level voltage line;
  • a gate of the twelfth transistor is connected to the first node, one of a source and a drain is connected to the second node, and the other is connected to an inactive level voltage line
  • the present disclosure also provides an array substrate comprising the shift register unit of any of the above.
  • the present disclosure also provides a display device including a display panel and an array substrate of any of the above.
  • FIG. 1 is a structural block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit timing diagram of the shift register unit shown in FIG. 1;
  • FIG. 3 is a circuit structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit timing diagram of the shift register unit shown in FIG. 3;
  • FIG. 5 is a circuit timing diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram showing a connection relationship between shift register units in a gate driving circuit according to an embodiment of the present invention.
  • FIG. 1 is a structural block diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit includes an output terminal OUT, a first node PU for controlling signal output at the output terminal OUT, and a second for controlling signal reset at the output terminal OUT and at the first node PU.
  • Node PD Node PD.
  • the high level and the low level at the first node PU can respectively turn on and off the connection between the output terminal OUT and the high level voltage line, thereby achieving control of the signal output; at the second node PD
  • the high level and the low level respectively can turn on and off the connection between the output terminal OUT and the low level voltage line and the connection between the first node PU and the low level voltage line, thereby realizing the control of the signal reset.
  • the high level and the low level at the first node PU may respectively turn on and off the connection between the output terminal OUT and the second clock signal line CK2 to match the clock on the second clock signal line CK2.
  • control signal output refers to a process of controlling the shift register unit to output a signal outward
  • control signal reset refers to controlling the shift register unit from the state of the outward output signal to the reset state. process.
  • the shift register unit further includes a first transistor M1, a second transistor M2, a memory module 11, and a charging module 12, wherein:
  • the first transistor M1 and the second transistor M2 are N-type transistors having the same threshold voltage, that is, a current between the source and the drain can be formed when the gate is connected to a high level voltage.
  • the gate of the first transistor M1 is connected to the third node NET1, one of the source and the drain is connected to the first clock signal line CK1, and the other is connected to the second node PD.
  • the gate of the second transistor M2 is connected to the third node NET1, one of the source and the drain is connected to the third node NET1, and the other is connected to the first clock signal line CK1.
  • the first clock signal line CK1 and the second clock signal line CK2 are respectively loaded with one of the positive phase clock signal CLK and the inverted clock signal CLKB.
  • connection relationship between the source and the drain may be respectively set to match the direction of the current flowing through the transistor; and the transistor has a structure in which the source and the drain are symmetric.
  • the source and drain can be considered as two electrodes that are not particularly distinguished.
  • the charging module 12 is connected to the third node NET1 and the second clock signal line CK2, respectively.
  • the charging module 12 is configured to set the level of the third node NET1 to a high level when the second clock signal line CK2 is at a high level.
  • the storage module 11 is connected to the third node NET1 and the first clock signal line CK1, respectively.
  • the storage module 11 is configured to store the threshold voltage of the second transistor M2, and compensate the threshold voltage of the first transistor M1 by using the stored threshold voltage.
  • the memory module 11 is configured to store the threshold voltage of the second transistor M2 when the third node NET1 discharges the first clock signal line CK1 through the second transistor M2, and pass the first clock signal line CK1.
  • the threshold voltage of the first transistor M1 is compensated by the stored threshold voltage.
  • the first transistor M1 and the second transistor M2 are both P-type transistors, and the storage module 11 is configured to store the second when the first clock signal line CK1 discharges the third node NET1 through the second transistor M2.
  • the threshold voltage of the transistor M2 is used to compensate the threshold voltage of the first transistor M1 with the stored threshold voltage when the first clock signal line CK1 pulls down the potential at the second node PD through the first transistor M1.
  • high level and low level are two preset potentials or preset potential ranges which are higher and lower with respect to each other, and may have different setting manners at different circuit nodes. Those skilled in the art can make settings according to application requirements, and the disclosure does not limit this.
  • the storage module 11 can store the threshold voltage of the second transistor M2 in cooperation with the charging module 12 to perform threshold voltage compensation of the first transistor M1, so that the threshold voltage drift of the first transistor M1 does not affect the second node PD.
  • the pull-up affects, thus eliminating the effect of the threshold voltage drift of the transistor on the potential at the pull-down node, helping to solve the problem of the resulting output signal anomaly.
  • FIG. 2 is a circuit timing diagram of the shift register unit shown in FIG. 1.
  • the first clock signal line CK1 is loaded with an inverted clock signal having a duty ratio of less than 50%
  • the second clock signal line CK2 is loaded with a positive phase clock signal having a duty ratio of less than 50% (as an example).
  • the duty ratio of the positive phase clock signal and the inverted clock signal may both be 40%).
  • the time from the high level to the low level on the second clock signal line CK2 is earlier than the time from the low level to the high level on the first clock signal line CK1.
  • the first clock signal line CK1 is loaded with a low level
  • the second clock signal line CK2 is loaded with a high level.
  • the charging module 12 sets the third node NET1 to a high level initial voltage Vini. And causing both the first transistor M1 and the second transistor M2 to be turned on.
  • the third node NET1 in the first phase I can be maintained at the initial voltage Vini, which is a result of dynamic balance between the potential pull-up of the charging module 12 and the potential pull-down of the second transistor M2.
  • the initial voltage Vini should be higher than the threshold voltage Vth of the first transistor M1 and the second transistor M2 so that the third node NET1 can reach a high level in the first phase I.
  • the initial voltage Vini in this embodiment is higher than the low-level voltage V0 of the clock signal (ie, the reference voltage of the circuit, which is convenient for description, and its value is zero) and the threshold voltage Vth of the two transistors, And lower than the high level voltage Vck of the clock signal.
  • the first clock signal line CK1 is still at a low level, and the second clock signal line CK2 is turned from a high level to a low level.
  • the charging module 12 stops pulling up the third node NET1.
  • the potential causes the third node NET1 to discharge the first clock signal line CK1 through the second transistor M2. Root According to the device characteristics of the transistor, the discharge process will continue until the voltage at the third node NET1 is higher than the low level voltage V0 on the first clock signal line CK1 by Vth, so that the memory module 11 can store the third node at this time.
  • a potential difference Vth between the NET1 and the first clock signal line CK1 is used for threshold voltage compensation in a subsequent process.
  • the second clock signal line CK2 is still at a low level, and the first clock signal line CK1 is turned from a low level to a high level.
  • the memory module 11 can maintain the third node NET1 and the first node.
  • the potential difference Vth between the clock signal lines CK1 causes the third node NET1 to jump to a high level voltage equal to Vck+Vth, thereby causing both the first transistor M1 and the second transistor M2 to be turned on.
  • the potential difference between the third node NET1 and the first clock signal line CK1 remains at Vth, so the second transistor M2 does not form a current between the third node NET1 and the first clock signal line CK1. Since there is no inflow and outflow of current, the third node NET1 at this stage will remain at a high level voltage equal to Vck+Vth.
  • the first transistor M1 is turned on by the high-level voltage of the third node NET1, and the current flowing from the first clock signal line CK1 to the second node PD can be formed. That is, the first clock signal line CK1 can pull up the potential at the second node PD through the first transistor M1, and the magnitude of the pull-up current Ids can be expressed as:
  • the carrier mobility ⁇ and the capacitance value C ox per unit area of the gate insulating layer are usually determined by the formation material, and the channel width to length ratio W/L is determined by the internal structure of the transistor, and can be regarded as a constant here. .
  • the threshold voltages Vth cancel each other, the pull-up current Ids is no longer related to the magnitude of the threshold voltage Vth of the first transistor M1 and the second transistor M2, that is, the threshold voltage stored by the memory unit 11 is realized to the first transistor M1. Threshold voltage compensation.
  • the second clock signal line CK2 is still at a low level, and the first clock signal line CK1 is turned from a high level to a low level.
  • the memory module 11 can maintain the third node NET1 and the The potential difference Vth between the clock signal lines CK1 causes the third node NET1 to jump to a low level voltage of a magnitude equal to Vth. It can be understood that, when entering the first phase I in the next clock cycle, the third node NET1 is again set to the initial voltage Vini under the action of the charging module 12, thereby repeating the above first phase I to fourth.
  • the process of stage IV is again set to the initial voltage Vini under the action of the charging module 12, thereby repeating the above first phase I to fourth.
  • the setting of the memory module 11 is removed on the basis of the above-described shift register unit.
  • the workflow of the shift register unit is the same as that of the shift register unit described above.
  • the voltage of the third node NET1 in the third phase III is Vck instead of Vck+Vth.
  • the pull-up current Ids flowing through the source and drain of the first transistor M1 in the comparative example will be related to the magnitude of the threshold voltage Vth of the first transistor M1.
  • the magnitude of the threshold voltage Vth of the first transistor M1 changes with the use time of the product (threshold voltage drift), thereby affecting the pull-up of the second node PD.
  • the pull-up current Ids is too small, the level at the second node PD cannot reach a high level in the third phase III, the signal reset of the shift register unit cannot be performed normally, and the signal output from the shift register unit will An exception occurs.
  • the embodiment of the present invention can eliminate the first when the potential of the second node PD is pulled up by the first transistor M1.
  • the influence of the threshold voltage of the transistor M1 causes the threshold voltage drift of the first transistor M1 to not affect the pull-up of the second node PD, thereby eliminating the influence of the threshold voltage drift of the transistor on the potential at the pull-down node, and helping to solve The resulting output signal is abnormal.
  • the embodiment of the invention can improve the stability of the shift register unit and achieve better product performance.
  • the duration of the second phase II needs to be not shorter than the third node NET1.
  • a clock signal on the signal line CK2 (such as setting a parameter including a duty ratio), so that the time from the high level to the low level on the second clock signal line during the same clock flipping is on the first clock signal line
  • the time difference between the times when the low level is turned to the high level is greater than the time required for the third node to fall from the initial voltage to the threshold voltage, thereby further improving the operational stability of the shift register unit.
  • the process described in the first stage I to the fourth stage IV described above can also be realized by setting the forward clock signal and the inverted clock signal to a duty ratio of 50% and strictly inverting each other.
  • FIG. 3 is a circuit structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit of the embodiment of the present disclosure has not only the output terminal OUT but also the input terminal IN and the reset terminal Reset.
  • the external signal line is in addition to the first clock signal line CK1 and the second clock signal line CK2. Includes low level voltage line Vss.
  • the storage module 11 specifically includes a first capacitor C1.
  • the first end of the first capacitor C1 is connected to the third node NET1, and the second end is connected to the first clock signal line CK1. Therefore, the function of the memory module 11 can be realized by the property that the capacitor can store the charge and the voltage at both ends does not abruptly, including: in the first phase I, the voltage at both ends is changed to the initial voltage Vini by charging, in the above In the second phase II, the voltage at both ends is lowered to the threshold voltage Vth by discharge, and the voltage at both ends is maintained at the threshold voltage Vth in the third phase III.
  • the charging module 12 specifically includes a third transistor M3.
  • the gate of the third transistor M3 is connected to the second clock signal line CK2, and one of the source and the drain is connected to the second clock signal line CK2, and the other is connected.
  • the shift register unit further includes a fourth transistor M4 and a second capacitor C2.
  • the gate of the fourth transistor M4 is connected to the first node PU, and one of the source and the drain is connected to the second clock signal line CK2.
  • the other end is connected to the output terminal OUT;
  • the first end of the second capacitor C2 is connected to the first node PU, and the second end is connected to the output end OUT.
  • the bootstrap signal output under the potential control of the first node PU can be realized, which is beneficial to improving the signal output quality and optimizing the circuit performance.
  • the shift register unit further includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7.
  • the gate of the fifth transistor M5 is connected to the input terminal IN, and one of the source and the drain is connected to the input terminal. IN, the other is connected to the first node PU;
  • the gate of the sixth transistor M6 is connected to the reset terminal Reset, one of the source and the drain is connected to the first node PU, and the other is connected to the low-voltage voltage line Vss;
  • the gate of the transistor M7 is connected to the reset terminal Reset, one of the source and the drain is connected to the output terminal OUT, and the other is connected to the low-voltage voltage line Vss.
  • the pull-up of the first node PU under the potential control at the input terminal IN can be realized, that is, the signal input of the shift register unit is realized.
  • signal reset at the first node PU and the output terminal OUT under the potential control at the reset terminal Reset can be realized.
  • the shift register unit further includes an eighth transistor M8 and a ninth transistor M9.
  • the gate of the eighth transistor M8 is connected to the first clock signal line CK1, and one of the source and the drain is connected.
  • the input terminal IN is connected to the first node PU;
  • the gate of the ninth transistor M9 is connected to the first clock signal line CK1, one of the source and the drain is connected to the output terminal OUT, and the other is connected to the low-voltage voltage line Vss .
  • the eighth transistor M8 and the ninth transistor M9 are respectively capable of setting the level at the first node and the output terminal to an inactive level when the first clock signal line is at an active level, thereby assisting with the first clock signal line CK1.
  • the potential pull-up at the first node PU and the signal at the output terminal OUT are reset, which is beneficial to reduce signal delay and improve circuit performance.
  • the shift register unit further includes a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12.
  • the gate of the tenth transistor M10 is connected to the second node PD, one of the source and the drain.
  • the gate of the eleventh transistor M11 is connected to the second node PD, one of the source and the drain is connected to the output terminal OUT, and the other is connected to the low level The voltage line Vss; the gate of the twelfth transistor M12 is connected to the first node PU, one of the source and the drain is connected to the second node PD, and the other is connected to the low-level voltage line Vss.
  • the transistors shown in FIG. 3 are all N-type transistors, that is, they can be formed by the same fabrication process to reduce the manufacturing cost.
  • the connection relationship between the source and the drain can be set to match the direction of the current flowing through the transistor; when the transistor has a symmetrical structure of the source and the drain, the source and The drain can be regarded as two electrodes that are not particularly distinguished.
  • FIG. 4 is a circuit timing diagram of the shift register unit shown in FIG. Referring to FIG. 4, the operation phase of the above shift register unit mainly includes an input period Tn-1, an output period Tn, and a reset period Tn+1. Referring to Figures 3 and 4, the working principle of the above shift register unit is as follows:
  • the circuit structure composed of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be in the third stage of each clock cycle according to the timing shown in FIG.
  • the potential at the second node PD is internally pulled up so that the second node PD remains high at all times.
  • the tenth transistor M10 and the eleventh transistor M11 can maintain the low level provided by the low-level voltage line Vss at the first node PU and the output terminal OUT under the action of the high level at the second node PD.
  • the bit register unit does not output a signal.
  • the input terminal IN is turned to a high level, at which time the first clock signal line CK1 is at a high level, the second clock signal line CK2 is at a low level, and the fifth transistor M5 and the eighth transistor are at a low level.
  • the transistor M8 is in an on state such that the first node PU is pulled up to a high level provided at the input terminal IN; and the ninth transistor M9 is also in an on state, so that the output terminal OUT is maintained at a low level voltage line Vss The low level provided.
  • the fourth transistor M4 and the twelfth crystal under the action of the high level at the first node PU The body tube M12 is in an on state, such that the second node PD is forcibly set to a low level provided by the low level voltage line Vss (for example, by setting the aspect ratio of the twelfth transistor M12 to be larger than the width and length of the first transistor M1) The ratio is realized), and at the same time, the second clock signal line CK2 is turned on between the output terminal OUT. During this period, both ends of the second capacitor C2 have a potential difference equal to Vck after the end of charging.
  • the first clock signal line CK1 is turned from a high level to a low level, and the fifth transistor M5 and the eighth transistor M8 are turned off to stop the potential at the first node PU. Pulling; the ninth transistor M9 is turned off, stopping the pull-down of the potential at the output terminal OUT, so that other circuit nodes except the third node NET1 in the shift register unit maintain the original potential, and the shift register unit does not perform signal Output.
  • the first clock signal line CK1 is still at a low level, and the second clock signal line CK2 is turned from a low level to a high level, so that the charge of the second node C2 at the first node PU is maintained.
  • the next hop becomes a voltage approximately equal to twice the Vck. Therefore, the fourth transistor M4 operates in the saturation region, and pulls up the potential at the output terminal OUT with a large pull-up current, so that the output terminal OUT is quickly set to a high level to realize the above-mentioned bootstrap signal output. .
  • the second node PD remains at a low level under the pull-down of the twelfth transistor M12, and the third node NET1 is set to the initial voltage Vini in the first phase I described above.
  • the second clock signal line CK2 changes from a high level to a low level, and the potential at the first node PU jumps back to the state at the input period Tn-1, the output end The OUT is set to a low level by the turned-on fourth transistor M4.
  • the third node NET1 is lowered to the threshold voltage Vth in the second phase II described above, that is, the storage of the threshold voltage is completed.
  • the second clock signal line CK2 is still at a low level, the first clock signal line CK1 is turned from a low level to a high level, and the reset end Reset is turned to a high level, so that the first The six-transistor M6 and the seventh transistor M7 are turned on, and the level at the first node PU and the output terminal OUT is set to a low level provided by the low-level voltage line Vss.
  • the fourth transistor M4 is turned off, and the conduction between the second clock signal line CK2 and the output terminal OUT is interrupted; the twelfth transistor M12 is turned off, and the pull-down of the potential at the second node PD is stopped.
  • the third node NET1 is set to a high level voltage of a magnitude equal to (Vck+Vth) in the third phase III described above, so that the first transistor M1 pulls up the second node PD to the high level without being affected by the threshold voltage. Level.
  • the tenth transistor M10 and the eleventh transistor M11 are turned on to maintain the low level provided by the low-level voltage line Vss at the first node PU and the output terminal OUT.
  • the eighth transistor M8 and the ninth transistor M9 are also in an on state, so that the first node PU can It is kept at the low level provided at the input terminal IN, and the output terminal OUT is kept at the low level provided by the low-level voltage line Vss.
  • the reset of the signal is completed at the first node PD and the output terminal OUT, and the shift register unit returns to the same working state as before the input period Tn-1.
  • the circuit structure of the shift register unit shown in FIG. 3 can realize its function under the circuit timing shown in FIG. 4, and can form a gate driver as a circuit repeating unit to realize row driving on the array substrate.
  • the threshold voltage drift condition can be considered to be equivalent.
  • the influence of the threshold voltage drift of the first transistor M1 on the potential at the second node PD can be eliminated by compensating the threshold voltage of the first transistor M1, thereby helping to solve the problem of the abnormality of the output signal caused thereby.
  • the embodiments of the present disclosure can improve the stability of the shift register unit and achieve better product performance.
  • the changed shift register unit can also solve the problem of abnormality of the output signal caused by the threshold voltage drift of the first transistor, and can improve the stability of the shift register unit and realize more than the prior art. Excellent product performance.
  • an embodiment of the present disclosure further provides an array substrate including the shift register unit of any of the above.
  • the array substrate is provided with a plurality of gate driving circuits outside the display region, and each of the gate driving circuits includes a plurality of stages of the shift register unit of any one of the above.
  • FIG. 6 is a schematic diagram showing a connection relationship between shift register units in a gate driving circuit according to an embodiment of the present invention. As shown in FIG. 6, in each gate driving circuit, except for the first stage shift register unit UN, the input terminal IN of any one stage shift register unit UN is the same as the shift register unit UN of the previous stage.
  • the output terminal OUT is connected (the input terminal IN of the first stage shift register unit UN is connected to the frame start signal STV); except for the first stage shift register unit UN, The output terminal OUT of the stage shift register unit UN is connected to the reset terminal Reset of the shift register unit UN of the previous stage.
  • the first clock signal line CK1 to which the odd-numbered shift register unit UN is connected is the second clock signal line CK2 to which the even-numbered shift register unit UN is connected
  • the second clock signal line CK2 to which the unit UN is connected is the first clock signal line CK1 to which the even-numbered stage shift register unit UN is connected.
  • the clock signal of the shift register unit of any stage is connected in the opposite manner to that of the shift register unit of the previous stage.
  • the odd-numbered shift register cells UN of FIG. 6 all use the connected positive-phase clock signal line CLK as the first clock signal line CK1 and the connected inverted clock signal line CLKB as the second clock signal.
  • the line CK2; the even-numbered shift register unit UN all uses the connected inverted clock signal line CLKB as the first clock signal line CK1, and the connected positive-phase clock signal line CLK as the second clock signal line CK2 .
  • the operational stability of the circuit on the array substrate can be improved, and better product performance can be achieved.
  • an embodiment of the present disclosure further provides a display device including any array substrate.
  • the display device in the embodiment of the present disclosure may be any product or component having a display function such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Based on the operational stability of the circuit on the array substrate, the operational stability of the display device can be improved, and better product performance can be achieved.

Abstract

一种移位寄存器单元（UN）、阵列基板和显示装置，属于显示领域。移位寄存器单元（UN）中：第一晶体管（M1）的栅极连接第三节点（NET1），源极和漏极中的一个连接第一时钟信号线（CK1），另一个连接第二节点（PD）；第二晶体管（M2）的栅极连接第三节点（NET1），源极和漏极中的一个连接第三节点（NET1），另一个连接第一时钟信号线（CK1）；充电模块（12）用于在第二时钟信号线（CK2）上为有效电平时将第三节点（NET1）处的电平置为有效电平；存储模块（11）用于存储第二晶体管（M2）的阈值电压（Vth），并利用已存储的阈值电压（Vth）补偿第一晶体管（M1）的阈值电压（Vth）。

Description

移位寄存器单元、阵列基板和显示装置
本公开要求于2017年3月17日提交中国国家知识产权局、申请号为201710161291.6、发明名称为“移位寄存器单元、阵列基板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示领域，特别涉及一种移位寄存器单元、阵列基板和显示装置。
背景技术
阵列基板行驱动(Gate driver On Array，GOA)技术相较于传统工艺而言，不仅节约了成本，实现显示面板两边对称的设计，还省去了芯片的绑定区域和例如扇出区的布线区域，有利于窄边框设计的实现。同时，由于GOA技术可以省去行方向上的芯片绑定工艺，对整体的产能、良率提升也有很大的帮助。
在GOA设计中，移位寄存器单元内设有控制信号输出的第一节点和控制信号复位的第二节点，并通过二极管连接方式的薄膜晶体管(Thin Film Transistor，TFT)来利用时钟信号对第二节点进行周期性复位。由此，该TFT会在时钟信号的作用下长期处于开关交替的状态，因而很容易出现大的阈值电压漂移，影响第二节点的电位，导致本级输出信号异常，并会在移位寄存器单元的级联关系下将异常信号向下传递，造成大范围的显示异常。
为了解决这一问题，可以通过分压等手段降低上述TFT的栅极电压，以减轻其阈值电压漂移、增强移位寄存器单元的稳定性。然而，降低栅极电压所需要添加的TFT也会连接时钟信号，因而仍然存在阈值电压漂移的问题，长期作用下依然会造成输出信号异常。即，上述手段只能在一定程度上缓解信号失真，而并不能解决由此造成的输出信号异常的问题。
发明内容
第一方面，本公开提供了一种移位寄存器单元，包括用于控制信号复位的第二节点，所述移位寄存器单元还包括：
第一晶体管，所述第一晶体管的栅极连接第三节点，源极和漏极中的一个连接第一时钟信号线，另一个连接所述第二节点；
第二晶体管，所述第二晶体管的栅极连接所述第三节点，源极和漏极中的一个连接所述第三节点，另一个连接所述第一时钟信号线；
分别连接所述第三节点和第二时钟信号线的充电模块，用于在第二时钟信号线上为有效电平时将所述第三节点处的电平置为有效电平；
分别连接所述第三节点和所述第一时钟信号线的存储模块，用于存储所述第二晶体管的阈值电压，并利用已存储的阈值电压补偿所述第一晶体管的阈值电压；
其中，所述第一晶体管和所述第二晶体管的阈值电压相同；所述第一时钟信号线上和所述第二时钟信号线上分别加载正相时钟信号和反相时钟信号中的一个。
在一种可能的实现方式中，所述存储模块用于在所述第三节点通过所述第二晶体管对所述第一时钟信号线进行放电时存储所述第二晶体管的阈值电压；所述存储模块用于在所述第一时钟信号线通过所述第一晶体管变更所述第二节点处的电平时利用已存储的阈值电压补偿所述第一晶体管的阈值电压。
在一种可能的实现方式中，在同一次时钟翻转的过程中，所述第一时钟信号线上由有效电平转为无效电平的时刻早于所述第二时钟信号线上由无效电平转为有效电平的时刻。
在一种可能的实现方式中，所述存储模块包括第一电容，所述第一电容的第一端连接所述第三节点，第二端连接所述第一时钟信号线。
在一种可能的实现方式中，所述充电模块包括第三晶体管，所述第三晶体管的栅极连接所述第二时钟信号线，源极和漏极中的一个连接所述第二时钟信号线，另一个连接所述第三节点。
在一种可能的实现方式中，所述移位寄存器单元包括输出端和用于控制信号输出的第一节点，所述移位寄存器单元还包括：
第四晶体管，所述第四晶体管的栅极连接所述第一节点，源极和漏极中的一个连接所述第二时钟信号线，另一个连接所述输出端；
第二电容，所述第二电容的第一端连接所述第一节点，第二端连接所述输出端。
在一种可能的实现方式中，所述移位寄存器单元还具有输入端和复位端，所述移位寄存器单元还包括：
第五晶体管，所述第五晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述输入端，另一个连接所述第一节点；
第六晶体管，所述第六晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述第一节点，另一个连接无效电平电压线；
第七晶体管，所述第七晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线。
在一种可能的实现方式中，所述移位寄存器单元还包括：
所述第八晶体管，所述第八晶体管的栅极连接所述第一时钟信号线，源极和漏极中的一个连接所述输入端，另一个连接所述第一节点；
所述第九晶体管，所述第九晶体管的栅极连接所述第一时钟信号线，源极和漏极中的一个连接所述输出端，另一个连接所述无效电平电压线。
在一种可能的实现方式中，所述移位寄存器单元包括输出端和用于控制信号输出的第一节点，所述移位寄存器单元还包括：
第十晶体管，所述第十晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述第一节点，另一个连接无效电平电压线；
第十一晶体管，所述第十一晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线；
第十二晶体管，所述第十二晶体管的栅极连接所述第一节点，源极和漏极中的一个连接所述第二节点，另一个连接无效电平电压线
第二方面，本公开还提供了一种阵列基板，包括上述任意一种的移位寄存器单元。
第三方面，本公开还提供了一种显示装置，包括显示面板和上述任意一种的阵列基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所 需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开一个实施例提供的移位寄存器单元的结构框图；
图2是图1所示的移位寄存器单元的电路时序图；
图3是本公开一个实施例提供的移位寄存器单元的电路结构图；
图4是图3所示的移位寄存器单元的电路时序图；
图5是本公开又一实施例提供的移位寄存器单元的电路时序图；
图6是本发明一个实施例提供的栅极驱动电路中移位寄存器单元彼此间的连接关系示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
图1是本公开一个实施例提供的移位寄存器单元的结构框图。参见图1，该移位寄存器单元包括输出端OUT，用于控制输出端OUT处的信号输出的第一节点PU，以及用于控制输出端OUT处和第一节点PU处的信号复位的第二节点PD。在一个示例中，第一节点PU处的高电平和低电平分别可以导通和截止输出端OUT与高电平电压线之间的连接，从而实现信号输出的控制；第二节点PD处的高电平和低电平分别可以导通和截止输出端OUT与低电平电压线之间的连接以及第一节点PU与低电平电压线之间的连接，从而实现信号复位的控制。在又一示例中，第一节点PU处的高电平和低电平分别可以导通和截止输出端OUT与第二时钟信号线CK2之间的连接，从而配合第二时钟信号线CK2上的时钟信号实现信号输出的控制；第二节点PD处的高电平和低电平分别可以导通和截止输出端OUT与低电平电压线之间的连接，从而实现信号复位的控制。在实施时，可以参照相关技术中的控制信号输出的第一节点的设置方式设置上述第一节点PU，并参照相关技术中的控制信号复位的第二节点的设置方式设置上述第二节点PD，本实施例对此不作具体限制。在一个示例中，“控制信号输出”指的是控制移位寄存器单元向外输出信号的过程，“控制信号复位”指的是控制移位寄存器单元从向外输出信号的状态回到复位状态的过程。
参见图1，上述移位寄存器单元还包括第一晶体管M1、第二晶体管M2、存储模块11和充电模块12，其中：
第一晶体管M1和第二晶体管M2为阈值电压相同的N型晶体管，即可以在栅极连接高电平电压时形成源极与漏极之间的电流。第一晶体管M1的栅极连接第三节点NET1，源极和漏极中的一个连接第一时钟信号线CK1，另一个连接第二节点PD。第二晶体管M2的栅极连接第三节点NET1，源极和漏极中的一个连接第三节点NET1，另一个连接第一时钟信号线CK1。其中，第一时钟信号线CK1上和第二时钟信号线CK2上分别加载正相时钟信号CLK和反相时钟信号CLKB中的一个。需要说明的是，根据晶体管具体类型的不同，可以设置其源极和漏极分别所具有的连接关系，以与流过晶体管的电流的方向相匹配；在晶体管具有源极与漏极对称的结构时，源极和漏极可以视为不作特别区分的两个电极。
上述充电模块12分别连接第三节点NET1和第二时钟信号线CK2，该充电模块12用于在第二时钟信号线CK2上为高电平时将第三节点NET1处的电平置为高电平。上述存储模块11分别连接第三节点NET1和第一时钟信号线CK1，该存储模块11用于存储第二晶体管M2的阈值电压，并利用已存储的阈值电压补偿第一晶体管M1的阈值电压。在一个示例中，该存储模块11用于在第三节点NET1通过第二晶体管M2对第一时钟信号线CK1进行放电时存储第二晶体管M2的阈值电压，并在第一时钟信号线CK1通过第一晶体管M1上拉第二节点PD处的电位时利用已存储的阈值电压补偿第一晶体管M1的阈值电压。在又一示例中，第一晶体管M1和第二晶体管M2均为P型晶体管，该存储模块11用于在第一时钟信号线CK1通过第二晶体管M2对第三节点NET1进行放电时存储第二晶体管M2的阈值电压，并在第一时钟信号线CK1通过第一晶体管M1下拉第二节点PD处的电位时利用已存储的阈值电压补偿第一晶体管M1的阈值电压。
需要说明的是，上述高电平与低电平是相对于彼此而言较高和较低的两个预设电位或预设电位范围，并且在不同的电路节点处可以有不同的设置方式，本领域技术人员可以根据应用需求进行设置，本公开对此不做限制。
可以看出，由于第一晶体管M1与第二晶体管M2的栅极连接同样的信号，并且具有相同的阈值电压(例如在制作两个晶体管时采用镜像或对称结构使两 个晶体管的组成结构和大小尺寸都完全相同)，因此可以认为其阈值电压漂移状况是等同的。从而，上述存储模块11可以在充电模块12的配合下存储第二晶体管M2的阈值电压，来进行第一晶体管M1的阈值电压补偿，使得第一晶体管M1的阈值电压漂移不会对第二节点PD的上拉造成影响，因而可以消除晶体管的阈值电压漂移对下拉节点处电位的影响，帮助解决由此引发的输出信号异常的问题。
作为一种示例，图2是图1所示的移位寄存器单元的电路时序图。参见图2，第一时钟信号线CK1上加载有占空比小于50％的反相时钟信号，第二时钟信号线CK2上加载有占空比小于50％的正相时钟信号(作为一种示例，正相时钟信号和反相时钟信号的占空比可以都为40％)。并且，在同一次时钟翻转的过程中，第二时钟信号线CK2上由高电平转为低电平的时刻早于第一时钟信号线CK1上由低电平转为高电平的时刻，例如图2中一个第二时钟信号线CK2上由高电平转为低电平的第一时刻t1，早于第一时钟信号线CK1上由低电平转为高电平的第二时刻t2，第一时刻t1到第二时刻t2的时间即为一次时钟翻转的过程。参见图1和图2，基于这样的时钟信号，上述移位寄存器单元在一个时钟周期内的工作流程如下所述：
第一阶段Ⅰ中：第一时钟信号线CK1上加载低电平，第二时钟信号线CK2上加载高电平，此时充电模块12将第三节点NET1置为一个高电平的初始电压Vini，并使得第一晶体管M1和第二晶体管M2都开启。此时，由于第二晶体管M2开启，存在由第三节点NET1流向第一时钟信号线CK1的电流。因此，第一阶段I内第三节点NET1处能够维持在初始电压Vini上，是充电模块12的电位上拉作用与第二晶体管M2的电位下拉作用之间动态平衡的结果。需要说明的而是，初始电压Vini应当高于第一晶体管M1和第二晶体管M2的阈值电压Vth，以使第三节点NET1在第一阶段I内能够达到高电平。如图2所示，本实施例中的初始电压Vini高于时钟信号的低电平电压V0(即电路的参考电压，为叙述方便，设其数值为零)和两个晶体管的阈值电压Vth，并且低于时钟信号的高电平电压Vck。
第二阶段Ⅱ中：第一时钟信号线CK1上仍为低电平，第二时钟信号线CK2上由高电平转为低电平，此时充电模块12停止上拉第三节点NET1处的电位，使得第三节点NET1通过第二晶体管M2对第一时钟信号线CK1进行放电。根 据晶体管的器件特性，放电过程将会一直持续到第三节点NET1处的电压比第一时钟信号线CK1上的低电平电压V0高出Vth为止，从而存储模块11可以存储此时第三节点NET1与第一时钟信号线CK1之间的电位差Vth，以用于后续过程中的阈值电压补偿。
第三阶段III中：第二时钟信号线CK2上仍为低电平，第一时钟信号线CK1上由低电平转为高电平，此时存储模块11可以通过保持第三节点NET1与第一时钟信号线CK1之间的电位差Vth，使得第三节点NET1处跳变为大小等于Vck+Vth的高电平电压，从而使得第一晶体管M1和第二晶体管M2都开启。此时，第三节点NET1与第一时钟信号线CK1之间的电位差仍保持为Vth，所以第二晶体管M2不会在第三节点NET1与第一时钟信号线CK1之间形成电流。由于不存在电流的流入和流出，所以此阶段内第三节点NET1处会一直保持在大小等于Vck+Vth的高电平电压上。
如上所述，在第三阶段III中第一晶体管M1会在第三节点NET1的高电平电压作用下开启，能够形成从第一时钟信号线CK1流向第二节点PD的电流。即，第一时钟信号线CK1能够通过第一晶体管M1上拉第二节点PD处的电位，上拉电流Ids的大小可以表示为：
Figure PCTCN2017109287-appb-000001
式中，载流子迁移率μ和单位面积栅绝缘层的电容值Cox通常是由形成材料决定的，沟道宽长比W/L是由晶体管内部结构决定的，这里均可以视为常数。而由于阈值电压Vth的相互抵消，上拉电流Ids不再与第一晶体管M1和第二晶体管M2的阈值电压Vth的大小有关，即实现了存储单元11所存储的阈值电压对第一晶体管M1的阈值电压补偿。
第四阶段Ⅳ中：第二时钟信号线CK2上仍为低电平，第一时钟信号线CK1上由高电平转为低电平，此时存储模块11可以通过保持第三节点NET1与第一时钟信号线CK1之间的电位差Vth，使得第三节点NET1处跳变为大小等于Vth的低电平电压。可理解的是，在进入下一个时钟周期内的第一阶段Ⅰ时，第三节点NET1处又会在充电模块12的作用下被置为初始电压Vini，从而重复上述第一阶段I至第四阶段Ⅳ的过程。
在一个对比示例中，在上述移位寄存器单元的基础上去除了存储模块11的设置。由此，该移位寄存器单元的工作流程与上文所述的移位寄存器单元的工 作流程相比，主要区别在于其第三节点NET1在在第三阶段III内的电压为Vck而不是Vck+Vth。基于这一点，对比示例中流过第一晶体管M1的源漏极的上拉电流Ids将会与第一晶体管M1的阈值电压Vth的大小有关。其结果是，第一晶体管M1的阈值电压Vth的大小会随着产品的使用时间而发生变化(阈值电压漂移)，从而会对第二节点PD的上拉造成影响。例如，上拉电流Ids过小会使得第二节点PD处的电平无法在第三阶段III中达到高电平，移位寄存器单元的信号复位不能正常进行，移位寄存器单元输出的信号将会发生异常。
可以看出的是，基于上述第二晶体管M2、上述存储模块11和上述充电模块12组成的电路结构，本发明实施例可以在通过第一晶体管M1上拉第二节点PD处电位时消除第一晶体管M1的阈值电压所造成的影响，使得第一晶体管M1的阈值电压漂移不会对第二节点PD的上拉造成影响，因而可以消除晶体管的阈值电压漂移对下拉节点处电位的影响，帮助解决由此引发的输出信号异常的问题。相比于现有技术而言，本发明实施例可以提升移位寄存器单元的稳定性，实现更优的产品性能。
关于图2所示的电路时序，需要说明的是：为了使第三节点NET1处能在第三阶段III之前达到阈值电压Vth的大小，第二阶段Ⅱ的时长需要不短于第三节点NET1从初始电压Vini降至阈值电压Vth这一过程需要的时间长短。由于该过程需要的时间长短与(Vini-Vth)的大小、第二晶体管M2的形成材料和结构等因素都有关系，因此在实施时可以根据这些因素设置第一时钟信号线CK1和第二时钟信号线CK2上的时钟信号(比如设置包括占空比的参量)，使得同一次时钟翻转的过程中第二时钟信号线上由高电平转为低电平的时刻与第一时钟信号线上由低电平转为高电平的时刻之间的时间差大于第三节点从初始电压降至阈值电压所需要的时间，从而进一步提升移位寄存器单元的工作稳定性。然而由于第一时钟信号线CK1上由低电平转为高电平也是需要时间的，而且这一时间可能大于第三节点从初始电压降至阈值电压所需要的时间，因而在此情况下可将正向时钟信号和反相时钟信号设置为占空比50％且彼此严格反相，同样可以实现上述第一阶段Ⅰ到第四阶段Ⅳ所述的过程。
图3是本公开一个实施例提供的移位寄存器单元的电路结构图。参见图3，本公开实施例的移位寄存器单元不仅具有输出端OUT，还具有输入端IN和复位端Reset，外部信号线除了第一时钟信号线CK1和第二时钟信号线CK2之外还 包括低电平电压线Vss。
参见图3，存储模块11具体包括第一电容C1，该第一电容C1的第一端连接第三节点NET1，第二端连接第一时钟信号线CK1。由此，可以利用电容能够存储电荷以及两端电压不会发生突变的性质实现上述存储模块11的功能，包括：在上述第一阶段Ⅰ中通过充电使两端电压变为初始电压Vini，在上述第二阶段Ⅱ中通过放电使两端电压降为阈值电压Vth，并在第三阶段III中将两端电压保持为阈值电压Vth。
参见图3，充电模块12具体包括第三晶体管M3，该第三晶体管M3的栅极连接第二时钟信号线CK2，源极和漏极中的一个连接第二时钟信号线CK2，另一个连接第三节点NET1。由此，可以利用二极管连接方式的晶体管实现上述充电模块12的功能，包括：在上述第一阶段Ⅰ中在第二时钟信号线CK2上的高电平电压的作用下将第三节点NET1处的电平置为初始电压Vini，在上述第二阶段Ⅱ和第三阶段III中断开第二时钟信号线CK2与第三节点NET1之间的连接。
参见图3，上述移位寄存器单元还包括第四晶体管M4和第二电容C2，该第四晶体管M4的栅极连接第一节点PU，源极和漏极中的一个连接第二时钟信号线CK2，另一个连接输出端OUT；该第二电容C2的第一端连接第一节点PU，第二端连接输出端OUT。基于第四晶体管M4和第二电容C2所组成的电路结构，能够实现第一节点PU处电位控制下的自举式的信号输出，有利于提升信号输出质量，优化电路性能。
参见图3，上述移位寄存器单元还包括第五晶体管M5、第六晶体管M6和第七晶体管M7，该第五晶体管M5的栅极连接输入端IN，源极和漏极中的一个连接输入端IN，另一个连接第一节点PU；该第六晶体管M6的栅极连接复位端Reset，源极和漏极中的一个连接第一节点PU，另一个连接低电平电压线Vss；该第七晶体管M7的栅极连接复位端Reset，源极和漏极中的一个连接输出端OUT，另一个连接低电平电压线Vss。基于第五晶体管M5，能够实现输入端IN处电位控制下的第一节点PU的上拉，即实现移位寄存器单元的信号输入。基于第六晶体管M6和第七晶体管M7所组成的电路结构，能够实现复位端Reset处电位控制下的第一节点PU处和输出端OUT处的信号复位。
参见图3，上述移位寄存器单元还包括第八晶体管M8和第九晶体管M9，该第八晶体管M8的栅极连接第一时钟信号线CK1，源极和漏极中的一个连接 输入端IN，另一个连接第一节点PU；该第九晶体管M9的栅极连接第一时钟信号线CK1，源极和漏极中的一个连接输出端OUT，另一个连接低电平电压线Vss。第八晶体管M8和第九晶体管M9分别能够在第一时钟信号线上为有效电平时将第一节点处和输出端处的电平置为无效电平，从而利用第一时钟信号线CK1辅助进行第一节点PU处的电位上拉和输出端OUT处的信号复位，有利于减小信号时延，提升电路性能。
参见图3，上述移位寄存器单元还包括第十晶体管M10、第十一晶体管M11和第十二晶体管M12，该第十晶体管M10的栅极连接第二节点PD，源极和漏极中的一个连接第一节点PU，另一个连接低电平电压线Vss；该第十一晶体管M11的栅极连接第二节点PD，源极和漏极中的一个连接输出端OUT，另一个连接低电平电压线Vss；该第十二晶体管M12的栅极连接第一节点PU，源极和漏极中的一个连接第二节点PD，另一个连接低电平电压线Vss。
需要说明的是，图3中示出的晶体管均为N型晶体管，即可以通过相同制作工艺形成以降低制造成本。根据晶体管具体类型的不同，可以设置其源极和漏极分别所具有的连接关系，以与流过晶体管的电流的方向相匹配；在晶体管具有源极与漏极对称的结构时，源极和漏极可以视为不作特别区分的两个电极。
图4是图3所示的移位寄存器单元的电路时序图。参见图4，上述移位寄存器单元的工作阶段主要包括输入时段Tn-1、输出时段Tn和复位时段Tn+1。参见图3和图4，上述移位寄存器单元的工作原理简述如下：
输入时段Tn-1之前，第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4所组成的电路结构能够按照图2所示的时序，在每一个时钟周期的第三阶段III内上拉第二节点PD处的电位，使得第二节点PD处一直保持高电平。在第二节点PD处高电平的作用下，第十晶体管M10和第十一晶体管M11能将第一节点PU处和输出端OUT处保持为低电平电压线Vss提供的低电平，移位寄存器单元不进行信号的输出。
输入时段Tn-1中，输入端IN处转为高电平，此时第一时钟信号线CK1上为高电平，第二时钟信号线CK2上为低电平，第五晶体管M5和第八晶体管M8处于开启状态，使得第一节点PU处被上拉至输入端IN处提供的高电平；同时第九晶体管M9也处于开启状态，使得输出端OUT处被保持为低电平电压线Vss提供的低电平。在第一节点PU处的高电平作用下，第四晶体管M4和第十二晶 体管M12处于开启状态，使得第二节点PD处被强制置为低电平电压线Vss提供的低电平(可以例如通过设置第十二晶体管M12的宽长比大于第一晶体管M1的宽长比实现)，同时第二时钟信号线CK2与输出端OUT之间导通。该时段中，第二电容C2两端在充电结束后具有了大小约等于Vck的电位差。
输入时段Tn-1与输出时段Tn之间，第一时钟信号线CK1上由高电平转为低电平，第五晶体管M5和第八晶体管M8关闭，停止对第一节点PU处的电位上拉；第九晶体管M9关闭，停止对输出端OUT处的电位下拉，从而移位寄存器单元内除第三节点NET1处之外的其他电路节点均保持原有电位，移位寄存器单元不进行信号的输出。
输出时段Tn中，第一时钟信号线CK1上仍为低电平，第二时钟信号线CK2上由低电平转为高电平，使得第一节点PU处在第二电容C2的电荷保持作用下跳变为大小约等于两倍Vck的电压。从而，第四晶体管M4工作在饱和区，以一很大的上拉电流上拉输出端OUT处的电位，使得输出端OUT处很快被置为高电平，实现上述自举式的信号输出。该时段内，第二节点PD处仍在第十二晶体管M12的下拉作用下保持为低电平，第三节点NET1处在上述第一阶段Ⅰ中被置为初始电压Vini。
输出时段Tn与复位时段Tn+1之间，第二时钟信号线CK2上由高电平转为低电平，第一节点PU处的电位跳变回输入时段Tn-1时的状态，输出端OUT处会在开启的第四晶体管M4的作用下被置为低电平。同时，第三节点NET1处在上述第二阶段Ⅱ中降低至阈值电压Vth，即完成了阈值电压的存储。
复位时段Tn+1中，第二时钟信号线CK2上仍为低电平，第一时钟信号线CK1上由低电平转为高电平，同时复位端Reset处转为高电平，使得第六晶体管M6和第七晶体管M7开启，将第一节点PU处和输出端OUT处的电平置为低电平电压线Vss提供的低电平。由此，第四晶体管M4关闭，中断第二时钟信号线CK2与输出端OUT之间的导通；第十二晶体管M12关闭，停止对第二节点PD处电位的下拉。第三节点NET1处在上述第三阶段III被置为大小等于(Vck+Vth)的高电平电压，使得第一晶体管M1在不受阈值电压影响的情况下将第二节点PD处上拉至高电平。从而，第十晶体管M10和第十一晶体管M11开启，将第一节点PU处和输出端OUT处保持为低电平电压线Vss提供的低电平。该阶段中，第八晶体管M8和第九晶体管M9也处于开启状态，使得第一节点PU处能 被保持为输入端IN处提供的低电平，输出端OUT处保持为低电平电压线Vss提供的低电平。在上述多方面的共同作用下，第一节点PD处和输出端OUT处完成信号的复位，移位寄存器单元回到与输入时段Tn-1之前相同的工作状态。
可以看出，图3所示的移位寄存器单元的电路结构可以在图4所示的电路时序下实现其功能，可以作为电路重复单元组成栅极驱动器，实现阵列基板上的行驱动。同时可以看出，由于第一晶体管M1与第二晶体管M2的栅极连接同样的信号，并且具有相同的阈值电压，因此可以认为其阈值电压漂移状况是等同的。从而可以通过对第一晶体管M1的阈值电压补偿，消除第一晶体管M1的阈值电压漂移对第二节点PD处电位的影响，帮助解决由此引发的输出信号异常的问题。相比于现有技术，本公开实施例可以提升移位寄存器单元的稳定性，实现更优的产品性能。
为了便于理解，上述实施例均是以高电平作为有效电平、低电平作为无效电平进行说明的。当然，实施时在也可以采用低电平作为有效电平、高电平作为无效电平的设置。具体地，可以在上述实施例的基础上进行如下变更：将图3中的晶体管全部设置为P型晶体管，将低电平电压线Vss替换为输出高电平的无效电平电压线，并将图4所示的电路时序变更为图5所示的电路时序。容易理解的是，这样的变更会使得电路工作原理中的高电平变为低电平、低电平变为高电平，电位上拉变为电位下拉、电位下拉变为电位上拉，而电路工作原理的实质则保持不变。因此，变更后的电路结构、电路时序和电路工作原理可以比照上述实施例进行理解，在此不再赘述。可以看出，变更后的移位寄存器单元也能够解决由第一晶体管的阈值电压漂移而引发的输出信号异常的问题，并相比于现有技术可以提升移位寄存器单元的稳定性，实现更优的产品性能。
基于同样的发明构思，本公开实施例还提供了一种阵列基板，该阵列基板包括上述任意一种的移位寄存器单元。在一个示例中，该阵列基板在显示区域之外设置有若干个栅极驱动电路，每个栅极驱动电路均包括若干级的上述任意一种的移位寄存器单元。图6是本发明一个实施例提供的栅极驱动电路中移位寄存器单元彼此间的连接关系示意图。如图6所示，在每个栅极驱动电路中：除第一级移位寄存器单元UN之外，任一级移位寄存器单元UN的输入端IN均与上一级移位寄存器单元UN的输出端OUT相连(第一级移位寄存器单元UN的输入端IN连接帧起始信号STV)；除第一级移位寄存器单元UN之外，任一 级移位寄存器单元UN的输出端OUT均与上一级移位寄存器单元UN的复位端Reset相连。而且为了实现正确的信号时序，奇数级的移位寄存器单元UN所连接的第一时钟信号线CK1是偶数级的移位寄存器单元UN所连接的第二时钟信号线CK2，奇数级的移位寄存器单元UN所连接的第二时钟信号线CK2是偶数级移位寄存器单元UN所连接的第一时钟信号线CK1。即除第一级之外，任一级移位寄存器单元的时钟信号的连接方式与上一级移位寄存器单元的相反。例如，图6中奇数级的移位寄存器单元UN全部将所连接的正相时钟信号线CLK用作第一时钟信号线CK1，而将所连接的反相时钟信号线CLKB用作第二时钟信号线CK2；偶数级的移位寄存器单元UN全部将所连接的反相时钟信号线CLKB用作第一时钟信号线CK1，而将所连接的正相时钟信号线CLK用作第二时钟信号线CK2。基于移位寄存器单元所具有的稳定性，可提高阵列基板上电路的工作稳定性，实现更优的产品性能。
基于同样的发明构思，本公开实施例还提供了一种显示装置，该显示装置包括任一种阵列基板。本公开实施例中的显示装置可以为：显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。基于阵列基板上电路的工作稳定性，可提高显示装置的工作稳定性，实现更优的产品性能。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (11)

  1. 一种移位寄存器单元，包括用于控制信号复位的第二节点，其中，所述移位寄存器单元还包括：
    第一晶体管，所述第一晶体管的栅极连接第三节点，源极和漏极中的一个连接第一时钟信号线，另一个连接所述第二节点；
    第二晶体管，所述第二晶体管的栅极连接所述第三节点，源极和漏极中的一个连接所述第三节点，另一个连接所述第一时钟信号线；
    分别连接所述第三节点和第二时钟信号线的充电模块，用于在第二时钟信号线上为有效电平时将所述第三节点处的电平置为有效电平；
    分别连接所述第三节点和所述第一时钟信号线的存储模块，用于存储所述第二晶体管的阈值电压，并利用已存储的阈值电压补偿所述第一晶体管的阈值电压；
    其中，所述第一晶体管和所述第二晶体管的阈值电压相同；所述第一时钟信号线上和所述第二时钟信号线上分别加载正相时钟信号和反相时钟信号中的一个。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述存储模块用于在所述第三节点通过所述第二晶体管对所述第一时钟信号线进行放电时存储所述第二晶体管的阈值电压；所述存储模块用于在所述第一时钟信号线通过所述第一晶体管变更所述第二节点处的电平时利用已存储的阈值电压补偿所述第一晶体管的阈值电压。
  3. 根据权利要求1所述的移位寄存器单元，其中，在同一次时钟翻转的过程中，所述第二时钟信号线上由有效电平转为无效电平的时刻早于所述第一时钟信号线上由无效电平转为有效电平的时刻。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述存储模块包括第一电容，所述第一电容的第一端连接所述第三节点，第二端连接所述第一时钟信号线。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述充电模块包括第三晶体管，所述第三晶体管的栅极连接所述第二时钟信号线，源极和漏极中的一个连接所述第二时钟信号线，另一个连接所述第三节点。
  6. 根据权利要求1至5中任一项所述的移位寄存器单元，其中，所述移位寄存器单元包括输出端和用于控制信号输出的第一节点，所述移位寄存器单元还包括：
    第四晶体管，所述第四晶体管的栅极连接所述第一节点，源极和漏极中的一个连接所述第二时钟信号线，另一个连接所述输出端；
    第二电容，所述第二电容的第一端连接所述第一节点，第二端连接所述输出端。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述移位寄存器单元还具有输入端和复位端，所述移位寄存器单元还包括：
    第五晶体管，所述第五晶体管的栅极连接所述输入端，源极和漏极中的一个连接所述输入端，另一个连接所述第一节点；
    第六晶体管，所述第六晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述第一节点，另一个连接无效电平电压线；
    第七晶体管，所述第七晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线。
  8. 根据权利要求6所述的移位寄存器单元，其中，所述移位寄存器单元还包括：
    所述第八晶体管，所述第八晶体管的栅极连接所述第一时钟信号线，源极和漏极中的一个连接所述输入端，另一个连接所述第一节点；
    所述第九晶体管，所述第九晶体管的栅极连接所述第一时钟信号线，源极和漏极中的一个连接所述输出端，另一个连接所述无效电平电压线。
  9. 根据权利要求1至5中任一项所述的移位寄存器单元，其中，所述移位 寄存器单元包括输出端和用于控制信号输出的第一节点，所述移位寄存器单元还包括：
    第十晶体管，所述第十晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述第一节点，另一个连接无效电平电压线；
    第十一晶体管，所述第十一晶体管的栅极连接所述第二节点，源极和漏极中的一个连接所述输出端，另一个连接无效电平电压线；
    第十二晶体管，所述第十二晶体管的栅极连接所述第一节点，源极和漏极中的一个连接所述第二节点，另一个连接无效电平电压线。
  10. 一种阵列基板，其中，所述阵列基板包括如权利要求1至9中任一项所述的移位寄存器单元。
  11. 一种显示装置，其中，所述显示装置包括如权利要求10所述的阵列基板。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106652882B (zh) 2017-03-17 2019-09-06 京东方科技集团股份有限公司 移位寄存器单元、阵列基板和显示装置
CN107993620B (zh) * 2017-11-17 2020-01-10 武汉华星光电技术有限公司 一种goa电路
CN108230980B (zh) * 2018-01-08 2020-11-13 京东方科技集团股份有限公司 移位寄存器及其放噪控制方法、栅极驱动电路和显示装置
CN108564908B (zh) * 2018-01-31 2021-05-11 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN108447438B (zh) * 2018-04-10 2020-12-08 京东方科技集团股份有限公司 显示装置、栅极驱动电路、移位寄存器及其控制方法
CN108364622B (zh) * 2018-04-24 2020-11-06 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、驱动装置和显示装置
TWI721473B (zh) * 2019-06-28 2021-03-11 友達光電股份有限公司 元件基板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080101529A1 (en) * 2006-10-26 2008-05-01 Mitsubishi Electric Corporation Shift register and image display apparatus containing the same
CN101952875A (zh) * 2008-02-19 2011-01-19 夏普株式会社 显示装置、显示装置的驱动方法、以及扫描信号线驱动电路
CN102132356A (zh) * 2008-10-30 2011-07-20 夏普株式会社 移位寄存器电路和显示装置以及移位寄存器电路的驱动方法
CN102667909A (zh) * 2009-12-15 2012-09-12 夏普株式会社 扫描信号线驱动电路以及具备其的显示装置
CN105096836A (zh) * 2015-09-09 2015-11-25 上海和辉光电有限公司 显示屏驱动装置及包括该驱动装置的amold显示屏
CN106023946A (zh) * 2016-08-04 2016-10-12 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置以及显示装置
CN106128347A (zh) * 2016-07-13 2016-11-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106652882A (zh) * 2017-03-17 2017-05-10 京东方科技集团股份有限公司 移位寄存器单元、阵列基板和显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200703224A (en) * 2005-03-22 2007-01-16 Koninkl Philips Electronics Nv A shift register circuit
JP5079350B2 (ja) * 2006-04-25 2012-11-21 三菱電機株式会社 シフトレジスタ回路
JP4912186B2 (ja) * 2007-03-05 2012-04-11 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
CN101604551B (zh) * 2008-06-10 2012-05-30 北京京东方光电科技有限公司 移位寄存器及其栅线驱动装置
JP5665299B2 (ja) * 2008-10-31 2015-02-04 三菱電機株式会社 シフトレジスタ回路
CN102432356A (zh) 2011-09-16 2012-05-02 浙江大学 利用蚕沙发酵生产设施栽培专用的有机肥的方法
CN102654986A (zh) * 2011-11-25 2012-09-05 京东方科技集团股份有限公司 移位寄存器的级、栅极驱动器、阵列基板以及显示装置
KR101881853B1 (ko) * 2012-02-29 2018-07-26 삼성디스플레이 주식회사 에미션 구동 유닛, 에미션 구동부 및 이를 포함하는 유기 발광 표시 장치
CN104835442B (zh) * 2015-05-28 2017-09-26 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105185287B (zh) * 2015-08-27 2017-10-31 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路和相关显示装置
CN105047124B (zh) * 2015-09-18 2017-11-17 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN106920498B (zh) * 2015-12-25 2019-10-25 昆山工研院新型平板显示技术中心有限公司 Gip电路及其驱动方法和平板显示装置
CN105427793B (zh) * 2016-01-06 2018-03-20 京东方科技集团股份有限公司 电压控制电路、方法、栅极驱动电路和显示装置
CN105654991B (zh) * 2016-01-19 2019-08-02 京东方科技集团股份有限公司 移位寄存器及其驱动方法、goa电路以及显示装置
CN105489156B (zh) * 2016-01-29 2019-01-25 京东方科技集团股份有限公司 移位寄存单元及驱动方法、栅极驱动电路和显示装置
CN106356015B (zh) * 2016-10-31 2020-05-12 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080101529A1 (en) * 2006-10-26 2008-05-01 Mitsubishi Electric Corporation Shift register and image display apparatus containing the same
CN101952875A (zh) * 2008-02-19 2011-01-19 夏普株式会社 显示装置、显示装置的驱动方法、以及扫描信号线驱动电路
CN102132356A (zh) * 2008-10-30 2011-07-20 夏普株式会社 移位寄存器电路和显示装置以及移位寄存器电路的驱动方法
CN102667909A (zh) * 2009-12-15 2012-09-12 夏普株式会社 扫描信号线驱动电路以及具备其的显示装置
CN105096836A (zh) * 2015-09-09 2015-11-25 上海和辉光电有限公司 显示屏驱动装置及包括该驱动装置的amold显示屏
CN106128347A (zh) * 2016-07-13 2016-11-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106023946A (zh) * 2016-08-04 2016-10-12 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置以及显示装置
CN106652882A (zh) * 2017-03-17 2017-05-10 京东方科技集团股份有限公司 移位寄存器单元、阵列基板和显示装置

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