WO2016106888A1 - 一种栅极驱动电路 - Google Patents

一种栅极驱动电路 Download PDF

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Publication number
WO2016106888A1
WO2016106888A1 PCT/CN2015/071134 CN2015071134W WO2016106888A1 WO 2016106888 A1 WO2016106888 A1 WO 2016106888A1 CN 2015071134 W CN2015071134 W CN 2015071134W WO 2016106888 A1 WO2016106888 A1 WO 2016106888A1
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WIPO (PCT)
Prior art keywords
signal
unit
pull
gate
output
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PCT/CN2015/071134
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English (en)
French (fr)
Inventor
戴荣磊
颜尧
肖军城
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深圳市华星光电技术有限公司
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Priority to US14/418,618 priority Critical patent/US9483993B2/en
Publication of WO2016106888A1 publication Critical patent/WO2016106888A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular to a gate driving circuit of a display device.
  • a gate driver circuit is generally fabricated on an array substrate by using a Gate Driver On Array (GOA) technology in an array process stage of a liquid crystal display panel, thereby implementing progressive scan driving of the gate lines.
  • GOA Gate Driver On Array
  • This technology can reduce the bonding process of the external IC and improve the integration of the liquid crystal display panel.
  • LTPS Low Temprature Poly-silicon
  • the LTPS can adjust the TFT type using ion layout technology, and therefore, the GOA circuit can be configured as an NMOS, PMOS or CMOS type.
  • CMOS and NMOS require more reticle processes than PMOS, resulting in a significant increase in manufacturing costs for CMOS and NMOS.
  • the circuit structure of the CMOS type is too complicated, and it is difficult to design an ultra-narrow bezel. Especially for small-sized display devices (such as mobile phone screens), the size of the bezel is particularly important for a better user experience.
  • the power consumption of the GOA circuit is also an important reference indicator for the performance of the display device.
  • the LTPS GOA driving circuit structure is too complicated and consumes a large amount of power.
  • One of the technical problems to be solved by the present invention is that the structure of the GOA driving circuit of the low-temperature polysilicon in the prior art is too complicated.
  • an embodiment of the present invention provides a gate driving circuit including a multi-level GOA drive.
  • each level of the GOA drive unit includes:
  • a signal aggregating unit configured to output a pull-down control signal according to the incoming signal
  • An output unit the control end of which is coupled to the output end of the signal aggregating unit to pull down the potential of the output of the first gate signal according to the pull-down control signal and the first clock signal, and pull down according to the pull-down control signal and the second clock signal a potential of the output of the second gate signal, so that the GOA driving unit of the current stage outputs the first and second gate signals, wherein the first and second gate signals are scanning signals of adjacent two rows of gate lines;
  • a pull-up control unit that outputs a pull-up control signal according to the pull-up signal
  • a pull-up maintaining unit coupled between the output end of the pull-up control unit, the control end of the output unit, the second gate signal output end, and the DC power source to pull up the potential of the control unit control terminal according to the pull-up control signal
  • the DC power supply potential is maintained such that the first gate signal and the second gate signal are maintained at a high potential.
  • the second gate signal output end of each stage of the GOA driving unit is coupled to the input end of the signal aglowing unit of the next stage GOA driving unit to output the second gate signal according to the current stage GOA driving unit. Start the next level of the GOA drive unit.
  • the first and second clock signals of each stage of the GOA drive unit form a clock cycle with the first and second clock signals of the next stage of the GOA drive unit, staggered in sequence and sequentially coupled .
  • the output unit comprises:
  • a first output transistor having a gate coupled to the output end of the signal aggregating unit, a first end receiving the first clock signal, and a second end outputting the first gate signal;
  • the second output transistor has a gate coupled to the output end of the signal incoming unit, a first end receiving the second clock signal, and a second end outputting the second gate signal.
  • a buck unit is further included, and the buck unit includes a first buck capacitor and/or a second buck capacitor, wherein
  • a first end of the first step-down capacitor is coupled to the control unit of the output unit, and a second end is coupled to the second end of the first output transistor to pull down or raise the output unit according to the first clock signal. Potential of the end;
  • a first end of the second step-down capacitor is coupled to the control unit of the output unit, and a second end is coupled to the second end of the second output transistor to pull down the potential of the control unit of the output unit according to the second clock signal .
  • the pull-up signal of each stage of the GOA driving unit is the first clock signal of the next-stage GOA driving unit or the first gate signal output by the next-stage GOA driving unit.
  • the pull-up maintaining unit includes:
  • a first pull-up transistor having a gate coupled to the output end of the pull-up control unit, a first end coupled to the DC power source, and a second end coupled to the control end of the output unit;
  • a second pull-up transistor having a gate coupled to the output end of the pull-up control unit, a first end coupled to the DC power source, and a second end coupled to the second gate signal output end of the output unit;
  • the pull-up control signal when the pull-up control signal is valid, the first and second pull-up transistors are turned on, the potential of the output unit control terminal is pulled up to the DC power supply potential, and the second gate signal is pulled up to the DC power supply potential.
  • the pull-up maintaining unit further includes:
  • a leakage preventing transistor having a gate coupled to the control end of the output unit, a first end coupled to the DC power source, and a second end coupled to the gates of the first pull-up transistor and the second pull-up transistor;
  • the leakage preventing transistor when the control unit of the output unit is at a low potential, the leakage preventing transistor is turned on, so that the gates of the first and second pull-up transistors are kept at a high potential, thereby preventing leakage from the DC power supply to the control terminal of the output unit. Current.
  • the pull-up control unit includes a pull-up control transistor having a gate shorted to the first end to receive the pull-up signal, and a second end coupled to the first and second pull-ups The gate of the transistor.
  • the signal aggregating unit includes a signal afferent transistor having a gate shorted to the first end to receive the incoming signal and a second end coupled to the control terminal of the output unit.
  • the present invention has the following advantages over existing GOA drive units.
  • the invention drives a double-row gate line by using a single-stage GOA driving unit, reduces the number of TFTs used in the gate driving circuit, reduces circuit power consumption, and simplifies the scanning driving circuit, so that the display device can realize a narrow bezel design.
  • the first clock pulse signal and the second clock pulse signal of the adjacent two-stage GOA driving unit of the present invention form one clock cycle, and are staggered in sequence and sequentially connected to complete the pull-up maintaining action to solve the current LTPS GOA circuit.
  • the middle pull-up maintains a lengthy circuit architecture problem during the non-active period of the circuit portion.
  • the invention adopts the high potential of the DC power supply to continuously pull up the Q[N] point potential during the non-active period of the GOA driving unit, and pulls up the output gate scan signal to the high point to ensure the circuit timing function is complete.
  • the present invention provides a leakage preventing transistor in the pull-up maintaining unit, which can prevent leakage current from the DC power supply to the Q[N] point during the operation of the GOA driving unit of the present stage, and ensure the stability of the driving circuit.
  • FIG. 1a is a schematic structural diagram of an Nth stage GOA driving unit according to Embodiment 1 of the present invention.
  • FIG. 1b is a schematic structural diagram of an N+2th stage GOA driving unit according to Embodiment 1 of the present invention.
  • FIG. 2 is a timing chart showing the operation of a GOA driving unit according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic structural diagram of a GOA driving unit according to Embodiment 2 of the present invention.
  • FIG. 4 is a timing chart of operation of a GOA driving unit according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic structural diagram of a GOA driving unit according to Embodiment 3 of the present invention.
  • FIG. 6 is a timing chart showing the operation of a GOA driving unit according to Embodiment 3 of the present invention.
  • FIG. 7 is a schematic structural diagram of a GOA driving unit according to Embodiment 4 of the present invention.
  • the embodiment provides a gate driving circuit including a multi-stage GOA driving unit, and each stage GOA outputs a scanning signal of a double-row gate line.
  • 1a and 1b are schematic structural views of an Nth stage and an N+2th stage GOA driving unit of a gate driving circuit according to the present embodiment, respectively. Only two adjacent stages in a multi-level GOA drive unit are shown. Since each stage of the driving circuit generates scanning signals of two rows of gate lines, for convenience of explanation, the previous stage GOA driving unit is denoted as N, and the adjacent subsequent stage of the GOA driving unit is denoted as N+2.
  • the transistor elements shown in Figures 1a and 1b are both P-type.
  • the Nth stage GOA driving unit includes a signal aggregating unit 100, an output unit 200, a buck unit 400, a pull-up maintaining unit 500, and a pull-up control unit 600.
  • the signal aggregating unit 100 includes a signal afferent transistor T1.
  • the gate of T1 is shorted to the first terminal to receive an incoming signal.
  • the incoming signal is preferably a gate signal G[N-1] output by the N-2th stage GOA driving unit.
  • the second end of T1 is coupled to the control end of the output unit 200 (Q[N] point in the figure). When the incoming signal arrives, the second end of T1 outputs the pull-down control signal KD[N].
  • the control end of the output unit 200 is coupled to the output end of the signal aggregating unit 100 to pull down the first gate signal output terminal according to the pull-down control signal KD[N] and the first clock pulse signal CK1 (O[N] point in the figure)
  • the potential of the second gate signal output terminal (O[N+1] point in the figure) is pulled down according to the pull-down control signal KD[N] and the second clock pulse signal CK2.
  • the Nth stage GOA driving unit outputs the first gate signal G[N] and the second gate signal No. G[N+1], wherein the first gate signal G[N] and the second gate signal G[N+1] are scanning signals of adjacent two rows of gate lines.
  • the output unit 200 includes a first output transistor T2 and a second output transistor T3.
  • the gate of the first output transistor T2 is coupled to the output of the signal aggregating unit 100, and receives the pull-down control signal KD[N].
  • the first end of T2 receives the first clock signal CK1, and the second end thereof serves as the first gate signal output terminal to output the first gate signal G[N].
  • the gate of the second output transistor T3 is coupled to the output of the signal aggregating unit 100, and receives the pull-down control signal KD[N].
  • the first end of T3 receives the second clock signal CK2, and the second end thereof serves as the second gate signal output terminal to output the second gate signal G[N+1].
  • the buck unit 400 includes a first buck capacitor C1.
  • the first end of the C1 is coupled to the control end of the output unit 200, and the second end of the C1 is coupled to the second end of the T2 (the point [O[N] in the figure) to pull down or raise the output unit 200 according to the first clock signal CK1.
  • the control terminal that is, the potential of the Q[N] point.
  • the first step-down capacitor C1 can pull down the potential of the Q[N] point to ensure the normal output of the first output transistor T2; the role of the gate line at the N+1th row During the period, the first step-down capacitor C1 can also appropriately push up the potential of the Q[N] point, thereby ensuring that the second output transistor T3 is quickly turned off when the (N+1)th gate line is switched from the active state to the inactive state.
  • the pull-up control unit 500 outputs a pull-up control signal KU[N] according to the pull-up signal.
  • the pull-up signal is preferably the clock signal CK3.
  • the clock signal CK3 is also the first clock signal input to the N+2th stage GOA driving unit.
  • the pull-up control unit 500 includes a pull-up control transistor T4. The gate of T4 is short-circuited to the first terminal to receive the clock signal CK3. When the clock signal CK3 arrives, the second terminal of T4 outputs a pull-up control signal KU[N].
  • the pull-up maintaining unit 600 is coupled between the output end of the pull-up control unit 500, the control end of the output unit 200, the second gate signal output end (O[N+1] point in the figure), and the DC power source VGH to The Q[N] point is pulled up to the potential of the DC power source VGH according to the pull-up control signal KU[N], T2 and T3 are turned off, and the second gate signal G[N+1] is pulled up to a high potential. Therefore, after the scanning operation of the Nth row and the N+1th gate line is completed by the Nth stage GOA driving unit, the first gate signal G[N] and the second gate signal G[N+ are transmitted through the DC power source VGH. 1] Maintain at high potential until the arrival of an incoming signal in the next frame.
  • the pull-up maintaining unit 600 includes a first pull-up transistor T6 and a second pull-up transistor T7.
  • the gate of the T6 is coupled to the output of the pull-up control unit 500, the first end of which is coupled to the DC power source VGH, and the second end of which is coupled to the control terminal of the output unit 200 (the point Q[N] in the figure).
  • the gate of T7 is coupled to the output of the pull-up control unit 600.
  • the first end is coupled to the DC power source VGH, and the second end is coupled to the second gate signal output end of the output unit 700 (O[N+1] point in the figure).
  • the pull-up maintaining unit 600 further includes a leakage preventing transistor T5.
  • the gate of the T5 is coupled to the control terminal of the output unit 200, the first end of which is coupled to the DC power source VGH, and the second end of which is coupled to the gates of the first pull-up transistor T6 and the second pull-up transistor T7.
  • T5 is turned on, so that the gates of T6 and T7 are kept at a high potential, so that T6 and T7 are turned off, preventing generation of points from the DC power source VGH to Q[N]. Leakage current.
  • the structure of the N+2 stage GOA driving unit is similar to that of the Nth stage, except that the signal and the clock signal are transmitted.
  • the incoming signal received by T1 in the N+2 stage GOA driving unit is the second gate signal G[N+1] output by the Nth stage GOA driving unit.
  • the first clock signal received by the first end of T2 is CK3
  • the second clock signal received by the first end of T3 is CK4.
  • the gate of T4 is short-circuited to its first terminal to receive the clock signal CK1. That is to say, in the current stage and the next stage GOA driving unit, the input positions of CK1 and CK3 are interchanged, and the input positions of CK2 and CK4 are interchanged, and each adjacent stage is configured as such.
  • first clock pulse signal CK1 and the second clock pulse signal CK2 of the Nth stage GOA driving unit and the first clock pulse signal CK3 and the second clock pulse signal CK4 of the N+2th stage GOA driving unit form a
  • the clock cycles are staggered in timing and are sequentially connected. That is, the pulse widths of CK1, CK2, CK3, and CK4 are 25% clock cycles, respectively.
  • the working timings of CK1 to CK4 are properly configured and the voltage of the Q[N] point is adjusted by the buck unit 400, and the Nth row can be completed with fewer transistor elements.
  • the Q[N] point is maintained at a high potential during the inactive period so that the first gate signal G[N] and the second gate signal G[N+1] are maintained at a high potential.
  • the second gate signal output end of the Nth stage GOA driving circuit (O[N+1] point in the figure) is coupled to the signal of the N+2th GOA driving unit.
  • the input terminal of the unit 100 is activated to activate the N+2th GOA driving unit according to the second gate signal G[N+1] output by the Nth stage GOA driving unit.
  • the period t0 to t3 constitute one clock cycle, and the periods t0 to t3 are 25% clock cycles, respectively.
  • the incoming signal G[N-1] transitions from a high potential to a low potential, T1 is turned on, and the pull-down control signal KD[N] of the T1 output is low, that is, the potential of Q[N] is pulled down to The first low potential. Since Q[N] is low, T2, T3 and T5 are turned on. T2 is turned on because CK1 is at a high potential and thus the output first gate signal G[N] is kept at a high potential. T3 is turned on because CK2 is at a high potential and the second gate signal G[N+1] outputted by T3 is kept at a high potential.
  • T4 Since CK3 is high, T4 is turned off. T5 is turned on, so that the gate potentials of T6 and T7 are maintained at a high potential VGH, so that T6 and T7 are turned off. Thus T6 and T7 can be kept in a stable off state, preventing the generation of high-potential DC
  • the leakage current from the power supply VGH to the Q[N] point is beneficial to maintain the stability of the GOA drive unit.
  • the incoming signal G[N-1] transitions from a low potential to a high potential, and T1 is turned off.
  • the Q[N] point is low, and T2, T3 and T5 are turned on.
  • T3 is turned on because CK2 remains high, so that the second gate signal G[N+1] of the T3 output remains high.
  • CK1 transitions from a high potential to a low potential, so that the first gate signal G[N] of the T2 output jumps to a low potential.
  • the first end of the capacitor C1 (the point Q[N] in the figure) is the first low
  • the potential change is a lower second low potential.
  • the gate of T2 is coupled to the Q[N] point, and the first end of T2 is the source to receive the first clock signal CK1. Since T2 is a P-type transistor and the gate potential is lower, the second low potential ensures that a negative voltage difference is maintained between the gate and source of T2 when CK1 transitions to a low potential, so that T2 is still at The open state ensures that T2 can output the first gate signal G[N] normally.
  • the incoming signal G[N-1] remains high, causing T1 to be turned off.
  • the Q[N] point is low, and T2, T3 and T5 are turned on.
  • the Q[N] point is the second low potential, and both T2 and T3 are turned on.
  • T3 is turned on, and CK2 transitions from a high potential to a low potential, thereby causing the output second gate signal G[N+2] to be low.
  • T2 is turned on, CK1 transitions from a low potential to a high potential, thereby causing the output first gate signal G[N] to be at a high potential. Since the potential of the second terminal of the capacitor C1 jumps from the low potential to the high potential, the potential of Q[N] is pushed up from the second low potential to the first low potential.
  • the incoming signal G[N-1] remains high, causing T1 and T5 to be turned off. Since CK3 transitions from a high potential to a low potential, T4 is turned on, so that T6 and T7 are turned on.
  • the DC power source VGH charges the capacitor C1, and pulls the Q[N] point to a high level, thereby turning off T2 and T3. It should be noted that since the potential of Q[N] is pushed up from the second low potential to the first low potential during the period t2, the DC power supply VGH only needs a short charging time to pull up the Q[N] point to the high point. Potential so that T2 and T3 turn off quickly.
  • T2 is turned off, so that the first gate signal G[N] remains at the high potential of the previous period.
  • T7 is turned on, so that the DC power source VGH pulls up the potential of the second gate signal G[N+1] to a high potential.
  • the DC power source VGH continues to pull up the potential of the Q[N] point and the second gate signal G[N+1] until the incoming signal G[N-1] low potential pulse comes in the next frame period.
  • the structure of the N+2 stage GOA driving unit is similar to that of the Nth stage, except that the signal and the clock signal are transmitted.
  • the incoming signal received by the N+2th GOA driving unit is G[N+1]
  • the first clock signal is CK3
  • the second clock signal is CK4.
  • the pull-up signal received by the N+2 stage GOA driving unit is the clock signal CK1.
  • the incoming signal received by the N+2th GOA driving unit is compared with the Nth-level GOA driving unit. Both the number and the clock signal are delayed by two clock pulses. Therefore, the waveform diagram of the Q[N+2] point potential is delayed by two clock pulses from the waveform of the potential of the Q[N] point, and the first gate signal G[N+2] output by the N+2 stage GOA driving unit is Two clock pulses are delayed by G[N]. Similarly, the second gate signal G[N+3] output by the N+2 stage GOA driving unit is delayed by two clock pulses from G[N+1].
  • the gate driving circuit provided in this embodiment can complete the driving scan of four consecutive lines of gate lines according to the periodic changes of CK1, CK2, CK3 and CK4.
  • the number of TFTs can be reduced, the simplified design of the gate driving circuit can be realized, and the power consumption of the circuit can be reduced.
  • the display device can achieve a narrower border design.
  • FIG. 3 is a schematic structural diagram of an Nth stage GOA driving unit of this embodiment.
  • the structure of the N+2th stage GOA driving unit of this embodiment is similar to that of FIG. 3 except for the incoming signal and the clock signal.
  • the buck unit 400 includes a second buck capacitor C2.
  • the first end of the second step-down capacitor C2 is coupled to the control end of the output unit 200 (the point Q[N] in the figure), and the second end is coupled to the second end of the second output transistor T3 (O[N in the figure) ])) to pull down the potential of Q[N] according to the second clock signal CK2.
  • the incoming signal G[N-1] transitions from a high potential to a low potential, T1 is turned on, and the pull-down control signal KD[N] of the T1 output is low, that is, the potential of Q[N] is pulled down to The first low potential. Since Q[N] is low, T2, T3 and T5 are turned on. T2 is turned on because CK1 is at a high potential and thus the output first gate signal G[N] is kept at a high potential. T3 is turned on because CK2 is at a high potential and the second gate signal G[N+1] outputted by T3 is kept at a high potential.
  • T4 Since CK3 is high, T4 is turned off. T5 is turned on, so that the gate potentials of T6 and T7 are maintained at a high potential VGH, so that T6 and T7 are in a stable off state to prevent leakage current.
  • the incoming signal G[N-1] transitions from a low potential to a high potential, and T1 is turned off.
  • the Q[N] point is low, and T2, T3 and T5 are turned on.
  • T3 is turned on, and since CK2 is kept at a high potential, the second gate signal G[N+1] outputted by T3 is kept at a high potential. Since the second end of the capacitor C1 is maintained at a high potential and is the same as the potential of the t0 period, the capacitor C1 does not charge or discharge during the period t1, and thus the potential of the Q[N] point is maintained at the first low potential.
  • T2 is turned on, CK1 transitions from a high potential to a low potential, so that the output first gate signal G[N] jumps to a low potential.
  • the incoming signal G[N-1] remains high, causing T1 to be turned off.
  • Q[N] point is low, T2 T3 and T5 are turned on.
  • the Q[N] point is the first low potential, and both T2 and T3 are turned on.
  • the output second gate signal G[N+2] is low. Since the second end of the capacitor C2 (O[N+1] point in the figure) jumps from a high potential to a low potential, the first end of the capacitor C2 (the point Q[N] in the figure) changes from the first low potential to a lower level. The second low potential.
  • the gate of T3 is coupled to the Q[N] point, and the first end of T3 is the source to receive the second clock signal CK2. Since T3 is a P-type transistor and the gate potential is lower, the second low potential ensures that a negative voltage difference is maintained between the gate and source of T3 when CK2 transitions to a low potential, so that T3 is still at The open state ensures that T3 can output the second gate signal G[N+1] normally. When T2 is turned on, since CK1 transitions from a low potential to a high potential, the output first gate signal G[N] is at a high potential.
  • the incoming signal G[N-1] remains high, causing T1 and T5 to be turned off. Since CK3 transitions from a high potential to a low potential, T4 is turned on, so that T6 and T7 are turned on.
  • T6 is turned on, the DC power source VGH charges the capacitor C1, and pulls the Q[N] point to a high level, thereby turning off T2 and T3.
  • T2 is turned off so that the first gate signal G[N] remains at the high potential of the previous period.
  • T7 is turned on, so that the DC power source VGH pulls up the second gate signal G[N+1] to a high potential.
  • the working process of the N+2 stage GOA driving unit is similar to that of the Nth stage GOA driving unit.
  • the waveform diagram of the Q[N+2] point potential is delayed by two clock pulses than the waveform diagram of the potential of the Q[N] point
  • the first gate signal G output by the N+2 stage GOA driving unit is [ N+2] is delayed by two clock pulses than G[N].
  • the second gate signal G[N+3] output by the N+2th GOA driving unit is delayed by two clocks from G[N+1]. pulse.
  • Fig. 5 is a block diagram showing the circuit structure of the GOA driving unit of the embodiment. This circuit is an integration of the two GOA drive units shown in Figures 1a and 2.
  • the incoming signal G[N-1] transitions from a high potential to a low potential, T1 is turned on, and the pull-down control signal KD[N] of the T1 output is low, that is, the potential of Q[N] is pulled down to The first low potential. Since Q[N] is low, T2, T3 and T5 are turned on. T2 is turned on because CK1 is at a high potential and thus the output first gate signal G[N] is kept at a high potential. T3 is turned on because CK2 is at a high potential and the second gate signal G[N+1] outputted by T3 is kept at a high potential.
  • the incoming signal G[N-1] transitions from a low potential to a high potential, and T1 is turned off.
  • the Q[N] point is low, and T2, T3 and T5 are turned on.
  • T3 is turned on, and since CK2 is kept at a high potential, the second gate signal G[N+1] outputted by T3 is kept at a high potential.
  • CK1 transitions from a high potential to a low potential, so that the output first gate signal G[N] jumps. Is low.
  • the first end of the capacitor C1 (the point [O[N] in the figure) is from the first low potential. Change to a lower second low potential.
  • the gate of T2 is coupled to the Q[N] point, and the first end of T2 is the source to receive the first clock signal CK1.
  • T2 is a P-type transistor and the gate potential is lower, the second low potential ensures that a negative voltage difference is maintained between the gate and source of T2 when CK1 transitions to a low potential, so that T2 is still at The open state ensures that T2 can output the first gate signal G[N] normally.
  • the incoming signal G[N-1] remains high, causing T1 to be turned off.
  • the Q[N] point is low, and T2, T3 and T5 are turned on.
  • the Q[N] point is the second low potential, and both T2 and T3 are turned on.
  • T3 is turned on, and CK2 transitions from a high potential to a low potential, thereby causing the output second gate signal G[N+2] to be low.
  • the second end of the capacitor C2 (O[N+1] point in the figure) jumps from a high potential to a low potential, and has a pull-down effect on the potential of the Q[N] point.
  • T2 is turned on, CK1 transitions from a low potential to a high potential, thereby causing the output first gate signal G[N] to be at a high potential.
  • the second end of the capacitor C1 (the point O[N] in the figure) jumps from a low potential to a high potential, and has an effect of pushing up the potential at the Q[N] point.
  • the transistors T2 and T3 have the same electrical properties, and the capacitors C1 and C2 are preferably configured to have the same capacity.
  • the push-up effect of the clock signal CK1 is canceled by the pull-down action of CK2, so that the potential of the Q[N] point is maintained at the second low potential.
  • the incoming signal G[N-1] remains high, causing T1 and T5 to be turned off. Since CK3 transitions from a high potential to a low potential, T4 is turned on, so that T6 and T7 are turned on.
  • T6 is turned on, the DC power source VGH charges the capacitors C1 and C2, and pulls the Q[N] point to a high level, thereby turning off T2 and T3.
  • T2 is turned off, so that the first gate signal G[N] remains at the high potential of the previous period.
  • T7 is turned on, so that the DC power source VGH pulls up the potential of the second gate signal G[N+1] to a high potential.
  • the capacitances C1 and C2 have an effect of regulating the potential of the Q[N] point.
  • the potential of the Q[N] point can be pulled down during the action of the Nth row and the N+1th row gate line, so that T2 and T3 are normally output, and the N+1th row gate line can be switched from the active state to the inactive state.
  • the second output transistor T3 is turned off quickly.
  • the DC power supply VGH is a constant voltage DC high potential, combined with the cooperation of four clock sources and a buck unit.
  • the pull-down maintenance circuit structure in the prior art LTPS GOA circuit in which the pull-down sustaining portion is redundant during the inactive period can be solved, and the pull-down maintaining function is completed.
  • FIG. 7 is a schematic diagram showing the circuit structure of the Nth stage GOA driving unit of the embodiment. This circuit is a further improvement of the pull-up control unit 500 therein based on the circuit of Figure 1a. It should be noted that the N+2 stage drive unit (not shown) also has corresponding improvements.
  • the pull-up signal received by the pull-up control unit 500 is the first gate signal G[N+2] output by the N+2th stage GOA driving unit.
  • the specific signal timing and the analysis process thereof are referred to FIG. 2 and will not be described again.
  • This embodiment inputs the next-stage output Gate[N+2] signal to the gate of T4 on the basis of the first embodiment, and can maintain the stability of the pull-up control unit 500 and the pull-up maintaining unit 600 during the inactive period.

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Abstract

一种栅极驱动电路，其包括多级GOA驱动单元。每级GOA驱动单元包括：信号传入单元（100），其输出下拉控制信号；输出单元（200），其使本级GOA驱动单元输出第一和第二栅极信号；上拉控制单元（500），其输出上拉控制信号；上拉维持单元（600），将输出单元控制端的电位上拉至直流电源电位，从而使第一栅极信号和第二栅极信号维持在高电位。

Description

一种栅极驱动电路
相关申请的交叉引用
本申请要求享有2014年12月31日提交的名称为“一种栅极驱动电路”的中国专利申请CN201410856592.7的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种显示装置的栅极驱动电路。
背景技术
现有技术中，通常在液晶显示面板的阵列制程阶段采用阵列基板栅极驱动(Gate Driver On Array，GOA)技术将栅极驱动电路制作在阵列基板上，从而实现对栅线逐行扫描驱动。该技术可减少外接IC的绑定(bonding)工序，并提高液晶显示面板的集成度。
自从低温多晶硅(Low Temprature Poly-silicon，LTPS)出现后，由于LTPS半导体本身超高载流子迁移率的特性，面板周边集成电路的设计成为行业关注的焦点。LTPS可采用离子布置技术调节TFT类型，因此，GOA电路可以配置为NMOS、PMOS或者CMOS类型。然而就光罩成本而言，CMOS和NMOS较PMOS需要更多道光罩制程，导致CMOS和NMOS的制造成本会大幅提升。而且CMOS类型的电路结构过于复杂，很难做到超窄边框的设计。特别是对于小尺寸的显示装置(如手机屏幕)来说，为了获得更佳的用户使用体验，边框的尺寸显得尤为重要。
此外，GOA电路的功耗也是显示装置性能的重要参考指标。现有技术中LTPS GOA驱动电路结构过于复杂，功耗较大。
发明内容
本发明所要解决的技术问题之一是现有技术中低温多晶硅的GOA驱动电路结构过于复杂的技术缺陷。
为了解决上述技术问题，本发明的实施例提供一种栅极驱动电路，包括多级GOA驱 动单元，每级GOA驱动单元包括：
信号传入单元，其用于根据传入信号输出下拉控制信号；
输出单元，其控制端耦接在信号传入单元的输出端，以根据下拉控制信号和第一时钟脉冲信号下拉第一栅极信号输出端的电位，以及根据下拉控制信号和第二时钟脉冲信号下拉第二栅极信号输出端的电位，使本级GOA驱动单元输出第一和第二栅极信号，所述第一和第二栅极信号为相邻两行栅线的扫描信号；
上拉控制单元，其根据上拉信号输出上拉控制信号；
上拉维持单元，其耦接在上拉控制单元的输出端、输出单元的控制端、第二栅极信号输出端和直流电源之间，以根据上拉控制信号将输出单元控制端的电位上拉至直流电源电位，从而使第一栅极信号和第二栅极信号维持在高电位。
在一个实施例中，每级GOA驱动单元的第二栅极信号输出端耦接在下一级GOA驱动单元的信号传入单元的输入端，以根据当前级GOA驱动单元输出的第二栅极信号启动下一级GOA驱动单元。
在一个实施例中，每级GOA驱动单元的第一和第二时钟脉冲信号与其下一级GOA驱动单元的第一和第二时钟脉冲信号构成一个时钟周期，在时序上互相错开并且顺次衔接。
在一个实施例中，所述输出单元包括：
第一输出晶体管，其栅极耦接在信号传入单元的输出端，其第一端接收第一时钟信号，其第二端输出第一栅极信号；
第二输出晶体管，其栅极耦接在信号传入单元的输出端，其第一端接收第二时钟信号，其第二端输出第二栅极信号。
在一个实施例中，还包括降压单元，所述降压单元包括第一降压电容和/或第二降压电容，其中，
第一降压电容的第一端耦接在所述输出单元控制端，第二端耦接在所述第一输出晶体管的第二端，以根据第一时钟信号下拉或者抬升所述输出单元控制端的电位；
第二降压电容的第一端耦接在所述输出单元控制端，第二端耦接在所述第二输出晶体管的第二端，以根据第二时钟信号下拉所述输出单元控制端的电位。
在一个实施例中，每级GOA驱动单元的上拉信号为下一级GOA驱动单元的第一时钟信号，或者为下一级GOA驱动单元输出的第一栅极信号。
在一个实施例中，所述上拉维持单元包括：
第一上拉晶体管，其栅极耦接在所述上拉控制单元的输出端，其第一端耦接直流电源，其第二端耦接在输出单元的控制端；
第二上拉晶体管，其栅极耦接在所述上拉控制单元的输出端，其第一端耦接直流电源，其第二端耦接在输出单元的第二栅极信号输出端；
其中，在上拉控制信号有效时第一和第二上拉晶体管导通，将输出单元控制端的电位上拉至直流电源电位，并将第二栅极信号上拉至直流电源电位。
在一个实施例中，所述上拉维持单元进一步包括：
防漏电晶体管，其栅极耦接在输出单元的控制端，其第一端耦接直流电源，其第二端耦接在第一上拉晶体管和第二上拉晶体管的栅极；
其中，在输出单元控制端为低电位的情况下所述防漏电晶体管导通，使第一和第二上拉晶体管的栅极保持在高电位，从而防止产生从直流电源到输出单元控制端的漏电流。
在一个实施例中，所述上拉控制单元包括一上拉控制晶体管，其栅极短接第一端，以接收上拉信号，其第二端耦接在所述第一和第二上拉晶体管的栅极。
在一个实施例中，所述信号传入单元包括一信号传入晶体管，其栅极短接第一端，以接收传入信号，其第二端耦接在所述输出单元的控制端。
与现有的GOA驱动单元相比，本发明具有以下优点。
1、本发明通过采用单级GOA驱动单元驱动双行栅线，减少栅极驱动电路中TFT的使用数量，降低电路功耗，实现扫描驱动电路的简化，使得显示装置能够实现窄边框设计。
2、本发明相邻两级GOA驱动单元的第一时钟脉冲信号和第二时钟脉冲信号构成一个时钟周期，并在时序上互相错开并且顺次衔接，完成上拉维持作用，解决目前LTPS GOA电路中上拉维持电路部分在非作用期间的冗长的电路架构问题。
3、本发明采用直流电源的高电位完成在GOA驱动单元非作用期间持续上拉Q[N]点电位，并将输出的栅极扫描信号上拉至高点位，保证电路时序功能完整。
4、本发明在上拉维持单元中设置防漏电晶体管，可以防止本级GOA驱动单元在作用期间从直流电源到Q[N]点的漏电流，保证驱动电路的稳定。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案或现有技术的进一步理解，并且构成说明书的一部分，但并不构成对本申请技术方案的限制。
图1a是根据本发明实施例一的第N级GOA驱动单元的结构示意图；
图1b是根据本发明实施例一的第N+2级GOA驱动单元的结构示意图；
图2是根据本发明实施例一的GOA驱动单元工作时序图；
图3是根据本发明实施例二的GOA驱动单元的结构示意图；
图4是根据本发明实施例二的GOA驱动单元工作时序图；
图5是根据本发明实施例三的GOA驱动单元的结构示意图；
图6是根据本发明实施例三的GOA驱动单元工作时序图；
图7是根据本发明实施例四的GOA驱动单元的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面以具有P型晶体管的LTPS GOA栅极驱动电路为例，参照附图详细介绍GOA驱动单元的电路结构和工作原理。
实施例一
本实施例提供一种栅极驱动电路，包括多级GOA驱动单元，每级GOA输出双行栅线的扫描信号。图1a和图1b分别是根据本实施例的栅极驱动电路第N级和第N+2级GOA驱动单元的结构示意图。图中仅显示了多级GOA驱动单元中的相邻两级。由于每级驱动电路产生两行栅线的扫描信号，为便于说明，将前一级GOA驱动单元标示为N，相邻的后一级GOA驱动单元标示为N+2。图1a和图1b中所示的晶体管元件均为P型。
如图1a所示，第N级GOA驱动单元包括信号传入单元100、输出单元200、降压单元400、上拉维持单元500和上拉控制单元600。
其中，信号传入单元100包括信号传入晶体管T1。T1的栅极与第一端短路连接，以接收传入信号。在本实施例中，该传入信号优选为第N-2级GOA驱动单元输出的栅极信号G[N-1]。T1的第二端耦接在输出单元200的控制端(图中Q[N]点)，当传入信号到来时，T1的第二端输出下拉控制信号KD[N]。
输出单元200的控制端耦接在信号传入单元100的输出端，以根据下拉控制信号KD[N]和第一时钟脉冲信号CK1下拉第一栅极信号输出端(图中O[N]点)的电位，以及根据下拉控制信号KD[N]和第二时钟脉冲信号CK2下拉第二栅极信号输出端(图中O[N+1]点)的电位。从而使第N级GOA驱动单元输出第一栅极信号G[N]和第二栅极信 号G[N+1]，其中，第一栅极信号G[N]和第二栅极信号G[N+1]为相邻两行栅线的扫描信号。
具体而言，如图1a所示，输出单元200包括第一输出晶体管T2和第二输出晶体管T3。
第一输出晶体管T2的栅极耦接信号传入单元100的输出端，接收下拉控制信号KD[N]。T2的第一端接收第一时钟脉冲信号CK1，其第二端做为第一栅极信号输出端而输出第一栅极信号G[N]。
第二输出晶体管T3的栅极耦接信号传入单元100的输出端，接收下拉控制信号KD[N]。T3的第一端接收第二时钟脉冲信号CK2，其第二端做为第二栅极信号输出端而输出第二栅极信号G[N+1]。
降压单元400包括第一降压电容C1。C1的第一端耦接在输出单元200控制端，C1的第二端耦接在T2的第二端(图中O[N]点)，以根据第一时钟信号CK1下拉或者抬升输出单元200控制端，即Q[N]点的电位。需要强调的是，在第N行栅线的作用期间，第一降压电容C1可下拉Q[N]点的电位以保证第一输出晶体管T2正常输出；在第N+1行栅线的作用期间，第一降压电容C1还可适当推高Q[N]点电位，从而保证在第N+1行栅线由作用状态切换至非作用状态时第二输出晶体管T3快速关闭。
上拉控制单元500根据上拉信号输出上拉控制信号KU[N]。在本实施例中，上拉信号优选为时钟信号CK3。如图1b所示，时钟信号CK3也是输入到第N+2级GOA驱动单元的第一时钟信号。上拉控制单元500包括上拉控制晶体管T4。T4的栅极与第一端短路连接，以接收时钟信号CK3。当时钟信号CK3到来时，T4的第二端输出上拉控制信号KU[N]。
上拉维持单元600耦接在上拉控制单元500的输出端、输出单元200的控制端、第二栅极信号输出端(图中O[N+1]点)和直流电源VGH之间，以根据上拉控制信号KU[N]将Q[N]点上拉至直流电源VGH的电位，使T2和T3关闭，并将第二栅极信号G[N+1]上拉至高电位。从而在第N级GOA驱动单元完成对第N行和第N+1行栅线的扫描驱动之后，通过直流电源VGH将第一栅极信号G[N]和第二栅极信号G[N+1]维持在高电位，直到下一帧内传入信号的到来。
具体而言，上拉维持单元600包括第一上拉晶体管T6和第二上拉晶体管T7。T6的栅极耦接在上拉控制单元500的输出端，其第一端耦接直流电源VGH，其第二端耦接在输出单元200的控制端(图中Q[N]点)。T7的栅极耦接在上拉控制单元600的输出端， 其第一端耦接直流电源VGH，其第二端耦接在输出单元700的第二栅极信号输出端(图中O[N+1]点)。
上拉维持单元600还包括防漏电晶体管T5。T5的栅极耦接在输出单元200的控制端，其第一端耦接直流电源VGH，其第二端耦接在第一上拉晶体管T6的和第二上拉晶体管T7的栅极。在Q[N]点为低电位的情况下，T5导通，使T6和T7的栅极保持在高电位，从而使得T6和T7处于关闭状态，防止产生从直流电源VGH到Q[N]点的漏电流。
第N+2级GOA驱动单元的结构与第N级类似，不同之处在于传入信号和时钟信号。
如图1b所示，第N+2级GOA驱动单元中T1接收的传入信号为第N级GOA驱动单元输出的第二栅极信号G[N+1]。T2的第一端接收的第一时钟信号为CK3，T3的第一端接收的第二时钟信号为CK4。T4的栅极与其第一端短路连接，以接收时钟信号CK1。也就是说，在当前级和下一级GOA驱动单元中，CK1与CK3的输入位置互换，CK2与CK4的输入位置互换，每相邻级均如此配置。
需要说明的是，第N级GOA驱动单元的第一时钟脉冲信号CK1和第二时钟脉冲信号CK2与第N+2级GOA驱动单元的第一时钟脉冲信号CK3和第二时钟脉冲信号CK4构成一个时钟周期，在时序上互相错开并且顺次衔接。即CK1、CK2、CK3和CK4的脉冲宽度分别为25％时钟周期。在本实施例提供的GOA驱动单元中，合理配置CK1至CK4的工作时序并利用降压单元400实现对Q[N]点电位的调整，可以在较少晶体管元件的情况下完成对第N行和第N+1行栅线的扫描驱动。并在非作用期间保证Q[N]点维持在高电位，以使得第一栅极信号G[N]和第二栅极信号G[N+1]维持在高电位。
如图1b所示，在本实施例中，第N级GOA驱动电路的第二栅极信号输出端(图中O[N+1]点)耦接在第N+2级GOA驱动单元的信号传入单元100的输入端，以根据第N级GOA驱动单元输出的第二栅极信号G[N+1]启动第N+2级GOA驱动单元。
以下结合图2所示的信号时序图详细说明第N级GOA驱动单元的工作原理。在图2中，时段t0至t3构成一个时钟周期，时段t0至t3分别为25％时钟周期。
在时段t0期间，传入信号G[N-1]从高电位跳变至低电位，T1导通，T1输出的下拉控制信号KD[N]为低电位，即将Q[N]的电位下拉至第一低电位。由于Q[N]为低电位，T2、T3和T5导通。T2导通，因为CK1为高电位进而使输出的第一栅极信号G[N]保持高电位。T3导通，因为CK2为高电位进而使T3输出的第二栅极信号G[N+1]保持高电位。
由于CK3为高电位，T4截止。T5导通，使得T6和T7栅极电位保持在高电位VGH，从而T6和T7截止。这样T6和T7可以保持在稳定的截止状态，防止产生从高电位直流 电源VGH到Q[N]点的漏电流，有利于保持GOA驱动单元的稳定性。
在时段t1期间，传入信号G[N-1]从低电位跳变至高电位，T1截止。Q[N]点为低电位，T2、T3和T5导通。T3导通，因为CK2保持高电位，使得T3输出的第二栅极信号G[N+1]保持高电位。T2导通，CK1由高电位跳变至低电位，使得T2输出的第一栅极信号G[N]跳变为低电位。在时段t1的初始时刻，由于电容C1第二端(图中O[N]点)由高电位跳变为低电位，因此电容C1第一端(图中Q[N]点)由第一低电位变化为更低的第二低电位。在本实施例中，T2的栅极耦接在Q[N]点，T2的第一端为源极以接收第一时钟信号CK1。由于T2为P型晶体管且栅极电位为更低的第二低电位，可保证在CK1跳变为低电位的情况下，T2的栅极和源极之间保持负压差，使得T2仍然处于打开状态，保证T2能够正常输出第一栅极信号G[N]。
在时段t2期间，传入信号G[N-1]保持高电位，使得T1截止。Q[N]点为低电位，T2、T3和T5导通。在t2时段的初始时刻，Q[N]点为第二低电位，T2和T3均导通。T3导通，CK2由高电位跳变至低电位，进而使输出的第二栅极信号G[N+2]为低电位。T2导通，CK1由低电位跳变至高电位，进而使输出的第一栅极信号G[N]为高电位。由于电容C1第二端的电位从低电位跳变为高电位，使得Q[N]的电位由第二低电位推高至第一低电位。
在时段t3期间，传入信号G[N-1]保持高电位，使得T1和T5截止。由于CK3由高电位跳变至低电位，T4导通，从而T6和T7导通。T6导通，直流电源VGH向电容C1充电，将Q[N]点上拉至高电位，进而使得T2和T3截止。需要说明的是，由于在时段t2内Q[N]的电位由第二低电位推高至第一低电位，直流电源VGH仅需较短的充电时间即可将Q[N]点上拉至高电位，以使得T2和T3迅速截止。
T2截止，使第一栅极信号G[N]仍然保持前一时段的高电位。T7导通，使得直流电源VGH将第二栅极信号G[N+1]的电位上拉至高电位。这样以来，直流电源VGH将Q[N]点和第二栅极信号G[N+1]的电位持续上拉，直到下一个帧周期中传入信号G[N-1]低电位脉冲到来。
以下说明第N+2级GOA驱动单元的工作过程。
如上文所述，第N+2级GOA驱动单元的结构与第N级类似，不同之处在于传入信号和时钟信号。其中，第N+2级GOA驱动单元接收的传入信号为G[N+1]，第一时钟信号为CK3，第二时钟信号为CK4。并且，第N+2级GOA驱动单元接收的上拉信号为时钟信号CK1。
如图2所示，与第N级GOA驱动单元相比，第N+2级GOA驱动单元接收的传入信 号和时钟信号均延迟两个时钟脉冲。因此，Q[N+2]点电位的波形图比Q[N]点电位的波形图延迟两个时钟脉冲，第N+2级GOA驱动单元输出的第一栅极信号G[N+2]比G[N]延迟两个时钟脉冲，同样的，第N+2级GOA驱动单元输出的第二栅极信号G[N+3]比G[N+1]延迟两个时钟脉冲。
从以上信号时序分析可以看出，本实施例提供的栅极驱动电路可根据CK1、CK2、CK3和CK4的周期性变化完成连续四行栅线的驱动扫描。本实施例通过设计单级控制双行栅线扫描驱动，能够减少TFT使用数目，实现栅极驱动电路的简化设计，并能降低电路功耗。并可使显示装置实现更窄边框的设计。
实施例二
图3是本实施例第N级GOA驱动单元的结构示意图。本实施例的第N+2级GOA驱动单元的结构与图3类似，不同之处在于传入信号和时钟信号。
与图1a相比，本实施例中降压单元400的结构不同。具体而言，降压单元400包括第二降压电容C2。第二降压电容C2的第一端耦接在输出单元200的控制端(图中Q[N]点)，第二端耦接在第二输出晶体管T3的第二端(图中O[N]点)，以根据第二时钟信号CK2下拉Q[N]的电位。
以下结合图4所示的信号时序图详细说明本实施例中第N级GOA驱动单元的工作原理。
在时段t0期间，传入信号G[N-1]从高电位跳变至低电位，T1导通，T1输出的下拉控制信号KD[N]为低电位，即将Q[N]的电位下拉至第一低电位。由于Q[N]为低电位，T2、T3和T5导通。T2导通，因为CK1为高电位进而使输出的第一栅极信号G[N]保持高电位。T3导通，因为CK2为高电位进而使T3输出的第二栅极信号G[N+1]保持高电位。
由于CK3为高电位，T4截止。T5导通，使得T6和T7栅极电位保持在高电位VGH，从而T6和T7处于稳定的截止状态，防止产生漏电流。
在时段t1期间，传入信号G[N-1]从低电位跳变至高电位，T1截止。Q[N]点为低电位，T2、T3和T5导通。T3导通，由于CK2保持高电位，使得T3输出的第二栅极信号G[N+1]保持高电位。由于电容C1第二端保持在高电位，且与t0时段电位相同，因此在时段t1内电容C1并未发生充电或者放电，因此Q[N]点的电位保持在第一低电位。T2导通，CK1由高电位跳变至低电位，使得输出的第一栅极信号G[N]跳变为低电位。
在时段t2期间，传入信号G[N-1]保持高电位，使得T1截止。Q[N]点为低电位，T2、 T3和T5导通。在t2时段的初始时刻，Q[N]点为第一低电位，T2和T3均导通。T3导通，由于CK2由高电位跳变至低电位，进而使输出的第二栅极信号G[N+2]为低电位。由于电容C2第二端(图中O[N+1]点)由高电位跳变为低电位，电容C2第一端(图中Q[N]点)由第一低电位变化为更低的第二低电位。在本实施例中，T3的栅极耦接在Q[N]点，T3的第一端为源极以接收第二时钟信号CK2。由于T3为P型晶体管且栅极电位为更低的第二低电位，可保证在CK2跳变为低电位的情况下，T3的栅极和源极之间保持负压差，使得T3仍然处于打开状态，保证T3能够正常输出第二栅极信号G[N+1]。T2导通，由于CK1由低电位跳变至高电位，进而使输出的第一栅极信号G[N]为高电位。
在时段t3期间，传入信号G[N-1]保持高电位，使得T1和T5截止。由于CK3由高电位跳变至低电位，T4导通，从而T6和T7导通。T6导通，直流电源VGH向电容C1充电，将Q[N]点上拉至高电位，进而使得T2和T3截止。T2截至，使第一栅极信号G[N]仍然保持前一时段的高电位。T7导通，使得直流电源VGH将第二栅极信号G[N+1]上拉至高电位。
第N+2级GOA驱动单元的工作过程与第N级GOA驱动单元类似。如图4所示，Q[N+2]点电位的波形图比Q[N]点电位的波形图延迟两个时钟脉冲，第N+2级GOA驱动单元输出的第一栅极信号G[N+2]比G[N]延迟两个时钟脉冲，同样的，第N+2级GOA驱动单元输出的第二栅极信号G[N+3]比G[N+1]延迟两个时钟脉冲。
实施例三
图5显示了本实施例的GOA驱动单元的电路结构示意图。该电路是图1a和图2所示的两种GOA驱动单元的整合。
以下结合图6所示的信号时序图详细说明本实施例中第N级GOA驱动单元的工作原理。
在时段t0期间，传入信号G[N-1]从高电位跳变至低电位，T1导通，T1输出的下拉控制信号KD[N]为低电位，即将Q[N]的电位下拉至第一低电位。由于Q[N]为低电位，T2、T3和T5导通。T2导通，因为CK1为高电位进而使输出的第一栅极信号G[N]保持高电位。T3导通，因为CK2为高电位进而使T3输出的第二栅极信号G[N+1]保持高电位。
在时段t1期间，传入信号G[N-1]从低电位跳变至高电位，T1截止。Q[N]点为低电位，T2、T3和T5导通。T3导通，由于CK2保持高电位，使得T3输出的第二栅极信号G[N+1]保持高电位。T2导通，CK1由高电位跳变至低电位，使得输出的第一栅极信号G[N]跳变 为低电位。在时段t1的初始时刻，由于电容C1第二端(图中O[N]点)由高电位跳变为低电位，电容C1第一端(图中Q[N]点)由第一低电位变化为更低的第二低电位。在本实施例中，T2的栅极耦接在Q[N]点，T2的第一端为源极以接收第一时钟信号CK1。由于T2为P型晶体管且栅极电位为更低的第二低电位，可保证在CK1跳变为低电位的情况下，T2的栅极和源极之间保持负压差，使得T2仍然处于打开状态，保证T2能够正常输出第一栅极信号G[N]。
在时段t2期间，传入信号G[N-1]保持高电位，使得T1截止。Q[N]点为低电位，T2、T3和T5导通。在t2时段的初始时刻，Q[N]点为第二低电位，T2和T3均导通。
T3导通，CK2由高电位跳变至低电位，进而使输出的第二栅极信号G[N+2]为低电位。电容C2的第二端(图中O[N+1]点)由高电位跳变为低电位，对Q[N]点电位具有下拉的作用。T2导通，CK1由低电位跳变至高电位，进而使输出的第一栅极信号G[N]为高电位。电容C1的第二端(图中O[N]点)由低电位跳变为高电位，对Q[N]点电位具有推高的作用。在本实施例中，晶体管T2和T3电性能相同，优选地将电容C1和C2配置为容量相等。对Q[N]点的电位来说，时钟信号CK1的推高作用与CK2的下拉作用抵消，使得Q[N]点的电位保持在第二低电位。
这样既可以在CK2跳变为低电位的情况下，T3的栅极和源极之间保持负压差，使得T3仍然处于打开状态，保证T3能够正常输出第二栅极信号G[N+1]；又可避免CK2的下拉作用将Q[N]点下拉至更低的电位，从而防止在时段t3期间中直流电源VGH对C1和C2的充电时间过长。
在时段t3期间，传入信号G[N-1]保持高电位，使得T1和T5截止。由于CK3由高电位跳变至低电位，T4导通，从而T6和T7导通。T6导通，直流电源VGH向电容C1和C2充电，将Q[N]点上拉至高电位，进而使得T2和T3截止。T2截止，使第一栅极信号G[N]仍然保持前一时段的高电位。T7导通，使得直流电源VGH将第二栅极信号G[N+1]的电位上拉至高电位。需要说明的是，由于在时段t2内Q[N]的电位保持在第二低电位，直流电源VGH仅需较短的充电时间即可将Q[N]点上拉至高电位，以使得T2和T3迅速截止。
因此，电容C1和C2对Q[N]点的电位具有调节的作用。既能在第N行和第N+1行栅线作用期间下拉Q[N]点电位，使得T2和T3正常输出，又能使得第N+1行栅线由作用状态切换至非作用状态时第二输出晶体管T3迅速关闭。
此外，直流电源VGH为恒压的DC高电位，结合四个时钟源和降压单元的配合作用， 可以解决现有技术中LTPS GOA电路中下拉维持部分在非作用期间冗长的下拉维持电路架构，完成下拉维持功能。
实施例四
图7显示了本实施例的第N级GOA驱动单元的电路结构示意图。该电路是在图1a的电路基础上对其中的上拉控制单元500做出了进一步改进。需要说明的是，第N+2级驱动单元(图中未示出)也做出相应的改进。
具体而言，上拉控制单元500接收的上拉信号为第N+2级GOA驱动单元输出的第一栅极信号G[N+2]。具体信号时序及对其的分析过程参考附图2，不再赘述。
本实施例在实施例一的基础上将下一级输出Gate[N+2]信号输入到T4的栅极，可保持上拉控制单元500和上拉维持单元600在非作用期间的稳定性。
需要说明的是，实施例二和实施例三也可以适用于实施例四中。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种栅极驱动电路，包括多级GOA驱动单元，每级GOA驱动单元包括：
    信号传入单元，其用于根据传入信号输出下拉控制信号；
    输出单元，其控制端耦接在信号传入单元的输出端，以根据下拉控制信号和第一时钟脉冲信号下拉第一栅极信号输出端的电位，以及根据下拉控制信号和第二时钟脉冲信号下拉第二栅极信号输出端的电位，使本级GOA驱动单元输出第一和第二栅极信号，所述第一和第二栅极信号为相邻两行栅线的扫描信号；
    上拉控制单元，其根据上拉信号输出上拉控制信号；
    上拉维持单元，其耦接在上拉控制单元的输出端、输出单元的控制端、第二栅极信号输出端和直流电源之间，以根据上拉控制信号将输出单元控制端的电位上拉至直流电源电位，从而使第一栅极信号和第二栅极信号维持在高电位。
  2. 根据权利要求1所述的栅极驱动电路，其中，每级GOA驱动单元的第二栅极信号输出端耦接在下一级GOA驱动单元的信号传入单元的输入端，以根据当前级GOA驱动单元输出的第二栅极信号启动下一级GOA驱动单元。
  3. 根据权利要求1所述的栅极驱动电路，其中，每级GOA驱动单元的第一和第二时钟脉冲信号与其下一级GOA驱动单元的第一和第二时钟脉冲信号构成一个时钟周期，在时序上互相错开并且顺次衔接。
  4. 根据权利要求1所述的栅极驱动电路，其中，所述输出单元包括：
    第一输出晶体管，其栅极耦接在信号传入单元的输出端，其第一端接收第一时钟信号，其第二端输出第一栅极信号；
    第二输出晶体管，其栅极耦接在信号传入单元的输出端，其第一端接收第二时钟信号，其第二端输出第二栅极信号。
  5. 根据权利要求4所述的栅极驱动电路，其中，还包括降压单元，所述降压单元包括第一降压电容和/或第二降压电容，
    第一降压电容的第一端耦接在所述输出单元控制端，第二端耦接在所述第一输出晶体管的第二端，以根据第一时钟信号下拉或者抬升所述输出单元控制端的电位；
    第二降压电容的第一端耦接在所述输出单元控制端，第二端耦接在所述第二输出晶体管的第二端，以根据第二时钟信号下拉所述输出单元控制端的电位。
  6. 根据权利要求3所述的栅极驱动电路，其中，每级GOA驱动单元的上拉信号为 下一级GOA驱动单元的第一时钟信号，或者为下一级GOA驱动单元输出的第一栅极信号。
  7. 根据权利要求3所述的栅极驱动电路，其中，所述上拉维持单元包括：
    第一上拉晶体管，其栅极耦接在所述上拉控制单元的输出端，其第一端耦接直流电源，其第二端耦接在输出单元的控制端；
    第二上拉晶体管，其栅极耦接在所述上拉控制单元的输出端，其第一端耦接直流电源，其第二端耦接在输出单元的第二栅极信号输出端；
    其中，在上拉控制信号有效时第一和第二上拉晶体管导通，将输出单元控制端的电位上拉至直流电源电位，并将第二栅极信号上拉至直流电源电位。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述上拉维持单元进一步包括：
    防漏电晶体管，其栅极耦接在输出单元的控制端，其第一端耦接直流电源，其第二端耦接在第一上拉晶体管和第二上拉晶体管的栅极；
    其中，在输出单元控制端为低电位的情况下所述防漏电晶体管导通，使第一和第二上拉晶体管的栅极保持在高电位，从而防止产生从直流电源到输出单元控制端的漏电流。
  9. 根据权利要求7所述的栅极驱动电路，其中，所述上拉控制单元包括一上拉控制晶体管，其栅极短接第一端，以接收上拉信号，其第二端耦接在所述第一和第二上拉晶体管的栅极。
  10. 根据权利要求2所述的栅极驱动电路，其中，所述信号传入单元包括一信号传入晶体管，其栅极短接第一端，以接收传入信号，其第二端耦接在所述输出单元的控制端。
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