WO2017096658A1 - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents

基于ltps半导体薄膜晶体管的goa电路 Download PDF

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Publication number
WO2017096658A1
WO2017096658A1 PCT/CN2015/099594 CN2015099594W WO2017096658A1 WO 2017096658 A1 WO2017096658 A1 WO 2017096658A1 CN 2015099594 W CN2015099594 W CN 2015099594W WO 2017096658 A1 WO2017096658 A1 WO 2017096658A1
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electrically connected
thin film
film transistor
node
source
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PCT/CN2015/099594
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English (en)
French (fr)
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李亚锋
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武汉华星光电技术有限公司
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Priority to US14/907,817 priority Critical patent/US9841620B2/en
Publication of WO2017096658A1 publication Critical patent/WO2017096658A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit based on an LTPS semiconductor thin film transistor.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • GOA technology (Gate Driver on Array) is an array substrate row driving technology.
  • the original array process of the liquid crystal display panel is used to fabricate a horizontal scanning line driving circuit on a substrate around the display area, so that it can replace the external integrated circuit board ( (Integrated Circuit, IC) to complete the horizontal scanning line drive.
  • IC integrated circuit board
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase productivity and reduce product cost, and can make LCD panels more suitable for making narrow borders or no borders. Display product.
  • LTPS-TFT liquid crystal displays have attracted more and more attention.
  • LTPS-TFT liquid crystal displays have high resolution, fast response, high brightness and high opening. Rate and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved.
  • a-Si amorphous silicon
  • a conventional LTPS semiconductor thin film transistor based GOA circuit includes a plurality of cascaded GOA units, wherein n is a positive integer, and the nth stage GOA unit includes: a first thin film transistor T1, the first The gate of a thin film transistor T1 is electrically connected to the Mth clock signal CK(M), and the source is electrically connected to the output terminal G(n-1) of the upper n-1th GOA unit, and the drain is electrically Connected to the third node K(n); the second thin film transistor T2, the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), and the source is electrically connected to the M+1th The clock signal CK(M+1), the drain is electrically connected to the output terminal G(n); the third thin film transistor T3, the gate of the third thin film transistor T3 is electrically connected to the M+2 clock signal CK (M+2), the drain is electrically connected to the third node K(n), and the source
  • the drain is electrically connected to the second node P(n), the source is electrically connected to the constant voltage low potential VGL; the ninth thin film transistor T9, the gate and the source of the ninth thin film transistor T9 Uniform electricity Connected to the M+1th clock signal CK(M+1), the drain is electrically connected to the second node P(n); the bootstrap capacitor C1, one end of the bootstrap capacitor C1 is electrically connected to the first node Q(n), the other end is electrically connected to the output terminal G(n); the second capacitor C2, one end of the second capacitor C2 is electrically connected to the second node P(n), and the other end is electrically connected to the constant Press down the potential VGL.
  • the GOA circuit shown in Figure 1 can be scanned either in the forward direction or in the reverse direction.
  • the working processes of the forward and reverse scans are similar. Please refer to FIG. 1 and FIG. 2, taking forward scanning as an example.
  • the working process is: first, the Mth clock signal CK(M) and the output end G of the n-1th stage GOA unit ( N-1) provides a high potential, the first and fifth thin film transistors T1, T5 are turned on, the first node Q(n) is precharged to a high potential; then, the Mth clock signal CK(M) and the nth-
  • the output terminal G(n-1) of the level 1 GOA unit becomes low, the M+1th clock signal CK(M+1) provides a high potential, and the first node Q(n) is kept by the storage of the bootstrap capacitor C1.
  • the second thin film transistor T2 is turned on, and the output terminal G(n) outputs the high potential of the M+1th clock signal CK(M+1), and causes the first node Q(n) to be raised to a higher potential.
  • the eighth thin film transistor T8 is turned on, the second node P(n) is pulled down to the constant voltage low potential VGL, and the sixth and seventh thin film transistors T6, T7 are turned off; next, the M+2 clock signal CK (M+2) and the output terminal G(n+1) of the n+1th GOA unit both provide a high potential, the first node Q(n) is still at a high potential, and the M+1th clock signal CK (M+ 1) decreasing to a low potential, the output terminal G(n) outputs a low potential of the M+1th clock signal CK(M+1); Then, the Mth clock signal CK(M) again provides a high potential, the output terminal G(n-1) of the n-1th stage GOA unit remains
  • the eighth thin film transistor T8 is turned off; subsequently, the M+1th clock signal CK(M+1) provides a high potential, the ninth thin film transistor T9 is turned on, and the second node P(n) is charged to The high potential of the M+1th clock signal CK(M+1), the sixth and seventh thin film transistors T6, T7 are turned on, respectively, and continue to pull down the first node Q(n) and the output terminal G(n) to be constant Depressing the potential VGL at the second capacitor C2 Under the storage action, the second node P(n) continues to maintain a high potential, and the sixth and seventh thin film transistors T6, T7 are turned on to maintain the low potential of the first node Q(n) and the output terminal G(n).
  • the potential of the second node P(n) and the output signal of the output terminal G(n) pass through the M+1th clock.
  • the signal CK(M+1) is controlled, and the first node Q(n) is charged and discharged by the Mth clock signal CK(M) and the M+2th clock signal CK(M+2).
  • the load of the clock signal is increased, and the GOA circuit often adopts a multi-level connection, which causes the load of the clock signal to be further amplified, which may cause a serious output delay (Delay), thereby causing the GOA circuit to fail.
  • the object of the invention is a GOA circuit based on LTPS semiconductor thin film transistor, wherein the clock signal is only responsible for the output of the corresponding level GOA unit, which can effectively reduce the load of the clock signal and ensure the overall load reduction of the clock signal after the multi-stage GOA unit is connected. Improve the output stability of the GOA circuit.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: cascaded multi-level GOA units, each stage of which includes: a scan control unit, a forward scan pull-down unit, and a reverse Scanning the pull-down unit and the output unit;
  • n be a positive integer, in addition to the first, second, penultimate, and last-level GOA units, in the n-th GOA unit:
  • the scan control unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to an output end of the upper two-stage n-2th GOA unit, and the source is electrically connected to the forward scan DC control
  • the signal is electrically connected to the source of the fourth thin film transistor;
  • the third thin film transistor is electrically connected to the output of the n+2th GOA unit of the next two stages of the GOA unit.
  • the drain is electrically connected to the source of the fourth thin film transistor, the source is electrically connected to the reverse scan DC control signal, and the fourth thin film transistor is electrically connected to the constant voltage high potential The drain is electrically connected to the first node;
  • the forward scan pull-down unit includes: a fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the forward scan DC control signal, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected a second node; a sixth thin film transistor, the gate of the sixth thin film transistor is electrically connected to the reverse scan DC control signal, the drain is electrically connected to the second node, and the source is electrically connected to the constant voltage low potential a thirteenth thin film transistor, the gate of the thirteenth thin film transistor is electrically connected to the first node, the drain is electrically connected to the second node, and the source is electrically connected to the constant voltage low potential; the ninth thin film transistor The gate of the ninth thin film transistor is electrically connected to the second node, The source is electrically connected to the constant voltage low potential, the drain is electrically connected to the first node, and the tenth thin film transistor, the gate of the tenth thin film transistor is electrically connected to the second node, and the source is electrically connected Constant voltage
  • the reverse scan pull-down unit includes: an eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to the forward scan DC control signal, the source is electrically connected to the constant voltage low potential, and the drain is electrically connected a third node; a seventh thin film transistor, the gate of the seventh thin film transistor is electrically connected to the reverse scan DC control signal, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the third node a fourteenth thin film transistor, the gate of the fourteenth thin film transistor is electrically connected to the first node, the drain is electrically connected to the third node, and the source is electrically connected to the constant voltage low potential; the eleventh film a transistor, the gate of the eleventh thin film transistor is electrically connected to the third node, the source is electrically connected to the constant voltage low potential, the drain is electrically connected to the first node; and the twelfth thin film transistor is The gate of the twelfth thin film transistor is electrically connected to the third node, the source is
  • the output unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first node, a source is electrically connected to the Mth clock signal, and a drain is electrically connected to the output end; a bootstrap capacitor, one end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the forward scan DC control signal is opposite to the potential of the reverse scan DC control signal.
  • the potentials of the first node, the second node, and the third node are both controlled by a forward scan DC control signal and a reverse scan DC control signal.
  • the gates of the first thin film transistors are electrically connected to the circuit start signal.
  • the gates of the third thin film transistors are electrically connected to the circuit start signal.
  • the GOA circuit based on the LTPS semiconductor thin film transistor performs forward scanning when the forward scanning DC control signal is high and the reverse scanning DC control signal is low.
  • the GOA circuit based on the LTPS semiconductor thin film transistor performs reverse scanning when the forward scanning DC control signal is low and the reverse scanning DC control signal is high.
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal.
  • the thin film transistors are all N-type low temperature polysilicon thin film transistors.
  • the present invention also provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a cascaded multi-level GOA unit, each stage GOA unit comprising: a scan control unit, a forward scan pull-down unit, a reverse scan pull-down unit, and Output unit
  • n be a positive integer, in addition to the first, second, penultimate, and last-level GOA units, in the n-th GOA unit:
  • the scan control unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to an output end of the upper two-stage n-2th GOA unit, and the source is electrically connected to the forward scan DC control a signal, a drain electrically connected to the source of the fourth thin film transistor; a third thin film transistor, the gate of the third thin film transistor is electrically connected to the output end of the next two stages of the n+2th GOA unit, and the drain Electrically connected to the source of the fourth thin film transistor, the source is electrically connected to the reverse scan DC control signal; and the fourth thin film transistor, the gate of the fourth thin film transistor is electrically connected to the constant voltage high potential, and the drain Very electrically connected to the first node;
  • the forward scan pull-down unit includes: a fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the forward scan DC control signal, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected a second node; a sixth thin film transistor, the gate of the sixth thin film transistor is electrically connected to the reverse scan DC control signal, the drain is electrically connected to the second node, and the source is electrically connected to the constant voltage low potential a thirteenth thin film transistor, the gate of the thirteenth thin film transistor is electrically connected to the first node, the drain is electrically connected to the second node, and the source is electrically connected to the constant voltage low potential; the ninth thin film transistor The gate of the ninth thin film transistor is electrically connected to the second node, the source is electrically connected to the constant voltage low potential, the drain is electrically connected to the first node, and the tenth thin film transistor, the tenth thin film The gate of the transistor is electrically connected to the second node, the source is electrically connected to the constant
  • the reverse scan pull-down unit includes: an eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to the forward scan DC control signal, the source is electrically connected to the constant voltage low potential, and the drain is electrically connected a third node; a seventh thin film transistor, the gate of the seventh thin film transistor is electrically connected to the reverse scan DC control signal, the source is electrically connected to the constant voltage high potential, and the drain is electrically connected to the third node a fourteenth thin film transistor, the gate of the fourteenth thin film transistor is electrically connected to the first node, the drain is electrically connected to the third node, and the source is electrically connected to the constant voltage low potential; the eleventh film a transistor, the gate of the eleventh thin film transistor is electrically connected to the third node, the source is electrically connected to the constant voltage low potential, the drain is electrically connected to the first node; and the twelfth thin film transistor is The gate of the twelfth thin film transistor is electrically connected to the third node, the source is
  • the output unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first node, a source is electrically connected to the Mth clock signal, and a drain is electrically connected to the output end; a bootstrap capacitor, one end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the forward scan DC control signal is opposite to the potential of the reverse scan DC control signal
  • the potentials of the first node, the second node, and the third node are all controlled by a forward scanning DC control signal and a reverse scanning DC control signal;
  • the gates of the first thin film transistors are electrically connected to the circuit start signal
  • the gates of the third thin film transistors are electrically connected to the circuit start signal.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, which controls the potentials of the first, second, and third nodes by a forward-scanning DC control signal and a reverse-scan DC control signal.
  • the signal is only responsible for the output of the corresponding level GOA unit, which can effectively reduce the load of the clock signal, ensure the overall load of the clock signal after the multi-level GOA unit is connected, improve the output stability of the GOA circuit, and can also realize the forward and reverse of the GOA circuit. scanning.
  • FIG. 1 is a circuit diagram of a conventional GOA circuit based on an LTPS semiconductor thin film transistor
  • FIG. 2 is a timing chart corresponding to a forward scan of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 4 is a timing diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention in forward scanning;
  • FIG. 5 is a timing diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention in reverse scanning;
  • FIG. 6 is a circuit diagram of a first stage GOA unit of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 7 is a circuit diagram of a second stage GOA unit of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention.
  • FIG. 8 is a circuit diagram of a penultimate stage GOA unit of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • Figure 9 is a circuit diagram of the final stage GOA unit of the LTPS semiconductor thin film transistor based GOA circuit of the present invention.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a cascaded multi-level GOA unit, each stage GOA unit includes: a scan control unit 100, a forward scan pull-down unit 200, and a reverse The pull-down unit 300 and the output unit 400 are scanned.
  • n be a positive integer, in addition to the first, second, penultimate, and last-level GOA units, in the n-th GOA unit:
  • the scan control unit 100 includes a first thin film transistor T1 whose gate is electrically connected to the output terminal G(n-2) of the upper two-stage n-2th GOA unit, the source Electrically connected to the forward-scanning DC control signal U2D, the drain is electrically connected to the source of the fourth thin film transistor T4; the third thin film transistor T3, the gate of the third thin film transistor T3 is electrically connected to the next two stages An output terminal G(n+2) of the n+2th GOA unit, the drain is electrically connected to the source of the fourth thin film transistor T4, the source is electrically connected to the reverse scan DC control signal D2U; and the fourth film The transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the constant voltage high potential VGH, and the drain is electrically connected to the first node Q(n);
  • the forward scan pull-down unit 200 includes a fifth thin film transistor T5, the gate of the fifth thin film transistor T5 is electrically connected to the forward scan DC control signal U2D, and the source is electrically connected to the constant voltage high potential VGH.
  • the drain is electrically connected to the second node P1(n);
  • the sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is electrically connected to the reverse scan DC control signal D2U, and the drain is electrically connected to the second a node P1(n), the source is electrically connected to the constant voltage low potential VGL;
  • the thirteenth thin film transistor T13, the gate of the thirteenth thin film transistor T13 is electrically connected to the first node Q(n), and the drain Electrically connected to the second node P1(n), the source is electrically connected to the constant voltage low potential VGL;
  • the ninth thin film transistor T9, the gate of the ninth thin film transistor T9 is electrically connected to the second node P1 (n)
  • the source is electrically connected to the
  • the reverse scan pull-down unit 300 includes an eighth thin film transistor T8.
  • the gate of the eighth thin film transistor T8 is electrically connected to the forward scan DC control signal U2D, and the source is electrically connected to the constant voltage low potential VGL.
  • the drain is electrically connected to the third node P2(n); the seventh thin film transistor T9, the gate of the seventh thin film transistor T7 is electrically connected to the reverse scan DC control signal D2U, and the source is electrically connected to the constant voltage High potential VGH, the drain is electrically connected to the third node P2(n); the fourteenth thin a film transistor T14, the gate of the fourteenth thin film transistor T14 is electrically connected to the first node Q(n), the drain is electrically connected to the third node P2(n), and the source is electrically connected to the constant voltage a potential VGL; an eleventh thin film transistor T11, the gate of the eleventh thin film transistor T11 is electrically connected to the third node P2(n), the source is electrically connected to the constant
  • the output unit 400 includes a second thin film transistor T2.
  • the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), and the source is electrically connected to the Mth clock signal CK(M).
  • the drain is electrically connected to the output terminal G(n); and the bootstrap capacitor C1, one end of the bootstrap capacitor C1 is electrically connected to the first node Q(n), and the other end is electrically connected to the output terminal G ( n).
  • each of the thin film transistors is an N-type low temperature polysilicon thin film transistor.
  • the gates of the first thin film transistors T1 are electrically connected to the circuit start signal STV; in the final stage GOA unit And in the penultimate stage GOA unit, the gate of the third thin film transistor T3 is electrically connected to the circuit start signal STV.
  • the GOA circuit based on the LTPS semiconductor thin film transistor of the present invention has a forward-backward scanning function.
  • the forward scan DC control signal U2D is opposite to the potential of the reverse scan DC control signal D2U.
  • the GOA circuit performs Forward scanning; when the forward scanning DC control signal U2D is low and the reverse scanning DC control signal D2U is high, the GOA circuit performs reverse scanning.
  • the LTPS semiconductor thin film transistor-based GOA circuit includes four clock signals: a first clock signal CK(1), a second clock signal CK(2), and a third clock signal CK(3).
  • the fourth clock signal CK(4) each clock signal corresponding to the first-level GOA unit, for example, the first clock signal CK(1) is connected to the first-level GOA unit, and the second clock signal CK(2)
  • the second level GOA unit is accessed, the third clock signal CK(3) is connected to the third level GOA unit, and the fourth clock signal CK(4) is connected to the fourth level GOA unit.
  • This clock signal is only used for the output of the corresponding GOA unit.
  • the LTPS semiconductor thin film transistor GOA circuit of the present invention performs the forward scanning or the reverse scanning, and the clock signal CK(M) is only responsible for the output G(n) output of the corresponding level GOA unit, and
  • the potentials of the first node Q(n), the second node P1(n), and the third node P2(n) are both controlled by the forward scan DC control signal U2D and the reverse scan DC control signal D2U, which can effectively reduce
  • the load of the clock signal CK(M) ensures that the multi-level GOA unit is connected The overall load of the clock signal is reduced, improving the output stability of the GOA circuit.
  • the forward-scanning DC control signal U2D is at a high potential
  • the reverse-scan DC control signal D2U is at a low potential
  • the GOA circuit is forward-scanning.
  • Phase 1 pre-charging phase: the output terminal G(n-2) of the n-2th GOA unit and the forward-scanning DC control signal U2D are both at a high potential, the first thin film transistor T1 is turned on, and the fourth thin film transistor T4 is subjected to The control of the constant voltage high potential VGH is always in a conducting state, and the first node Q(n) is precharged to a high potential by the high potential forward scanning DC control signal U2D, and is thirteenth controlled by the first node Q(n). And the fourteenth thin film transistors T13, T14 are in an on state, the potential of the second node P1 (n), the third node P2 (n) is pulled down to a constant voltage low potential VGL;
  • Phase 2, high-potential output stage the output terminal G(n-2) of the n-2th GOA unit is lowered to a low potential, the Mth clock signal CK(M) provides a high potential, and the first thin film transistor T1 is turned off, A node Q(n) continues to maintain a high potential under the storage of the bootstrap capacitor C1, the second thin film transistor T2 is turned on, and the high potential of the Mth clock signal CK(M) is output via the output terminal G(n), and Causing the first node Q(n) to be raised to a higher potential;
  • Phase 3 low potential output phase the Mth clock signal CK(M) provides a low potential, the first node Q(n) continues to maintain a high potential, the second thin film transistor T2 is turned on, and the Mth clock signal CK(M) The low potential is output via the output terminal G(n);
  • Phase 4 the first node pull-down phase: the output terminal G(n+2) of the n+2th GOA unit provides a high potential, the reverse scan DC control signal D2U is at a low potential, and the third thin film transistor T3 is turned on, the first node Q(n) is pulled low to a low potential by the low potential reverse scan DC control signal D2U;
  • Phase 5 the first node and the output terminal are pulled down to maintain the phase: after the first node Q(n) becomes low, the forward scan DC control signal U2D is high, and the reverse scan DC control signal D2U is low,
  • the fifth thin film transistor T5 is turned on
  • the sixth thin film transistor T6 is turned off
  • the second node P1(n) is charged to a high potential by the constant voltage high potential VGH
  • T10 is turned on, the first node Q(n) and the output terminal G(n) are maintained to the constant voltage low potential VGL.
  • the eighth thin film transistor T8 is turned on, the seventh thin film transistor T7 is turned off, and the third node P2(n) is charged to a low potential by the constant voltage low potential VGL, and is eleventh controlled by the third node P2(n). And the twelfth thin film transistors T11, T12 are both turned off.
  • the forward-scanning DC control signal U2D is at a low potential
  • the reverse-scan DC control signal D2U is at a high potential
  • the GOA circuit is reverse-scanned.
  • Phase 1 pre-charging phase: the output terminal G(n+2) of the n+2th GOA unit and the reverse-scanning DC control signal D2U are both at a high potential, the third thin film transistor T3 is turned on, and the fourth thin film transistor T4 is subjected to The control of the constant voltage high potential VGH is always in a conducting state, and the first node Q(n) is precharged to a high potential by the high potential reverse scanning DC control signal D2U, which is controlled by the first node. 13.
  • the fourteenth thin film transistors T13, T14 are in an on state, and the potentials of the second node P1(n) and the third node P2(n) are pulled down to a constant voltage low potential VGL;
  • Phase 2, high-potential output stage the output terminal G(n+2) of the n+2th GOA unit is lowered to a low potential, the Mth clock signal CK(M) provides a high potential, and the third thin film transistor T3 is turned off, A node Q(n) continues to maintain a high potential under the storage of the bootstrap capacitor C1, the second thin film transistor T2 is turned on, and the high potential of the Mth clock signal CK(M) is output via the output terminal G(n), and Causing the first node Q(n) to be raised to a higher potential;
  • Phase 3 low potential output phase the Mth clock signal CK(M) provides a low potential, the first node Q(n) continues to maintain a high potential, the second thin film transistor T2 is turned on, and the Mth clock signal CK(M) The low potential is output via the output terminal G(n);
  • Phase 4 the first node pull-down phase: the output terminal G(n-2) of the n-2th GOA unit provides a high potential, the forward scanning DC control signal U2D is at a low potential, and the first thin film transistor T1 is turned on, the first node Q(n) is pulled low to a low potential by the low-potential forward-scanning DC control signal U2D;
  • Phase 5 the first node and the output terminal are pulled down to maintain the phase: after the first node Q(n) becomes low, the forward-scanning DC control signal U2D is low, and the forward-scanning DC control signal U2D is low,
  • the eight thin film transistor T8 is turned off, the seventh thin film transistor T7 is turned on, and the third node P2(n) is charged to a high potential by the constant voltage high potential VGH, and is eleventh and twelfth controlled by the third node P2(n).
  • the thin film transistors T11 and T12 are turned on, and the first node Q(n) and the output terminal G(n) are maintained to the constant voltage low potential VGL.
  • the fifth thin film transistor T5 is turned off, the sixth thin film transistor T6 is turned on, and the second node P1(n) is charged to a low potential by the constant voltage low potential VGL, and is ninth controlled by the second node P1(n).
  • the tenth thin film transistors T9, T10 are turned off.
  • the GOA circuit based on the LTPS semiconductor thin film transistor of the present invention controls the potentials of the first, second, and third nodes by the forward scanning DC control signal and the reverse scanning DC control signal, and the clock signal is only responsible for the corresponding
  • the output of the level GOA unit can effectively reduce the load of the clock signal, ensure the overall load of the clock signal after the multi-stage GOA unit is connected, improve the output stability of the GOA circuit, and can also realize the forward and reverse scanning of the GOA circuit.

Abstract

一种基于LTPS半导体薄膜晶体管的GOA电路，通过正向扫描直流控制信号(U2D)和反向扫描直流控制信号(D2U)控制第一、第二、及第三节点(Q(n)、P1(n)、P2(n))的电位，时钟信号(CK(M))仅负责对应级GOA单元的输出，能够有效的降低时钟信号的负载，保证多级GOA单元连接后时钟信号的整体负载降低，提升GOA电路的输出稳定性，还可以实现GOA电路的正反向扫描。

Description

基于LTPS半导体薄膜晶体管的GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种基于LTPS半导体薄膜晶体管的GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板((Integrated Circuit，IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序，低温多晶硅半导体本身具有超高的电子迁移率，比非晶硅半导体相对高100倍以上，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。
请参阅图1，现有的一种基于LTPS半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于第M条时钟信号CK(M)，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点K(n)；第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第M+1条时钟信号CK(M+1)，漏极电性连接于输出端G(n)；第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于第M+2条时钟信号CK(M+2)，漏极电性连接于第三节点K(n)，源极电性连接于下一级第n+1级GOA单元的输出端 G(n+1)；第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第M+3条时钟信号CK(M+3)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于恒压高电位VGH，源极电性连接于第三节点K(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第二节点P(n)，漏极电性连接于第三节点K(n)，源极电性连接于恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第三节点K(n)，漏极电性连接于第二节点P(n)，源极电性连接于恒压低电位VGL；第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极与源极均电性连接于第M+1条时钟信号CK(M+1)，漏极电性连接于第二节点P(n)；自举电容C1，所述自举电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；第二电容C2，所述第二电容C2的一端电性连接于第二节点P(n)，另一端电性连接于恒压低电位VGL。
图1所示的GOA电路既可以正向扫描也可以反向扫描，正、反向扫描的工作过程类似。请结合图1与图2，以正向扫描为例，在正向扫描时，其工作过程为：首先，第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1)均提供高电位，第一、及第五薄膜晶体管T1、T5打开，第一节点Q(n)被预充电至高电位；然后，第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1)变为低电位，第M+1条时钟信号CK(M+1)提供高电位，第一节点Q(n)因自举电容C1的存储保持高电位，第二薄膜晶体管T2打开，输出端G(n)输出第M+1条时钟信号CK(M+1)的高电位，并使得第一节点Q(n)被抬升至更高的电位，同时第八薄膜晶体管T8打开，第二节点P(n)被拉低至恒压低电位VGL，第六、及第七薄膜晶体管T6、T7关闭；接下来，第M+2条时钟信号CK(M+2)与第n+1级GOA单元的输出端G(n+1)均提供高电位，第一节点Q(n)仍为高电位，第M+1条时钟信号CK(M+1)降低为低电位，输出端G(n)输出第M+1条时钟信号CK(M+1)的低电位；再接下来，第M条时钟信号CK(M)再次提供高电位，第n-1级GOA单元的输出端G(n-1)保持低电位，第一薄膜晶体管T1打开拉低第一节点Q(n)至低电位，第八薄膜晶体管T8关闭；随后，第M+1条时钟信号CK(M+1)提供高电位，第九薄膜晶体管T9打开，第二节点P(n)被充电至第M+1条时钟信号CK(M+1)的高电位，第六、及第七薄膜晶体管T6、T7打开，分别继续拉低第一节点Q(n)与输出端G(n)至恒压低电位VGL，在第二电容C2的 存储作用下，第二节点P(n)持续保持高电位，第六、及第七薄膜晶体管T6、T7打开，保持第一节点Q(n)与输出端G(n)的低电位。
在上述现有的基于LTPS半导体薄膜晶体管的GOA电路中，对于任一级GOA单元，第二节点P(n)的电位和输出端G(n)的输出信号均是通过第M+1条时钟信号CK(M+1)控制的，而第一节点Q(n)通过第M条时钟信号CK(M)和第M+2条时钟信号CK(M+2)来实现充放电，这种方式会增加时钟信号的负载(Loading)，且GOA电路往往采用多级连接，导致时钟信号的负载被进一步放大，会导致严重的输出延迟(Delay)，进而造成GOA电路功能失效。
发明内容
本发明的目的在于一种基于LTPS半导体薄膜晶体管的GOA电路，其时钟信号仅负责对应级GOA单元的输出，能够有效的降低时钟信号的负载，保证多级GOA单元连接后时钟信号的整体负载降低，提升GOA电路的输出稳定性。
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：扫描控制单元、正向扫描下拉单元、反向扫描下拉单元、及输出单元；
设n为正整数，除第一级、第二级、倒数第二级、及最后一级GOA单元外，在第n级GOA单元中：
所述扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于上两级第n-2级GOA单元的输出端，源极电性连接于正向扫描直流控制信号，漏极电性连接于第四薄膜晶体管的源极；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于下两级GOA单元第n+2级GOA单元的输出端，漏极电性连接于第四薄膜晶体管的源极，源极电性连接于反向扫描直流控制信号；以及第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于恒压高电位，漏极电性连接于第一节点；
所述正向扫描下拉单元包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第二节点；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于反向扫描直流控制信号，漏极电性连接于第二节点，源极电性连接于恒压低电位；第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第二节点， 源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电位，漏极电性连接于输出端；
所述反向扫描下拉单元包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压低电位，漏极电性连接于第三节点；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第三节点；第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压低电位，漏极电性连接于输出端；
所述输出单元包括：第二薄膜晶体，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及自举电容，所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述正向扫描直流控制信号与反向扫描直流控制信号的电位相反。
第一节点、第二节点、及第三节点的电位均受正向扫描直流控制信号与反向扫描直流控制信号的控制。
在第一级GOA单元和第二级GOA单元中，第一薄膜晶体管的栅极均电性连接于电路起始信号。
在最后一级GOA单元和倒数第二级GOA单元中，第三薄膜晶体管的栅极均电性连接于电路起始信号。
所述基于LTPS半导体薄膜晶体管的GOA电路在所述正向扫描直流控制信号为高电位、反向扫描直流控制信号为低电位时进行正向扫描。
所述基于LTPS半导体薄膜晶体管的GOA电路在所述正向扫描直流控制信号为低电位、反向扫描直流控制信号为高电位时，进行反向扫描。
所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号。
所述薄膜晶体管均为N型低温多晶硅薄膜晶体管。
本发明还提供一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：扫描控制单元、正向扫描下拉单元、反向扫描下拉单元、及输出单元；
设n为正整数，除第一级、第二级、倒数第二级、及最后一级GOA单元外，在第n级GOA单元中：
所述扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于上两级第n-2级GOA单元的输出端，源极电性连接于正向扫描直流控制信号，漏极电性连接于第四薄膜晶体管的源极；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于下两级第n+2级GOA单元的输出端，漏极电性连接于第四薄膜晶体管的源极，源极电性连接于反向扫描直流控制信号；以及第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于恒压高电位，漏极电性连接于第一节点；
所述正向扫描下拉单元包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第二节点；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于反向扫描直流控制信号，漏极电性连接于第二节点，源极电性连接于恒压低电位；第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电位，漏极电性连接于输出端；
所述反向扫描下拉单元包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压低电位，漏极电性连接于第三节点；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第三节点；第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压低电位，漏极电性连接于输出端；
所述输出单元包括：第二薄膜晶体，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及自举电容，所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述正向扫描直流控制信号与反向扫描直流控制信号的电位相反；
其中，第一节点、第二节点、及第三节点的电位均受正向扫描直流控制信号与反向扫描直流控制信号的控制；
其中，在第一级GOA单元和第二级GOA单元中，第一薄膜晶体管的栅极均电性连接于电路起始信号；
其中，在最后一级GOA单元和倒数第二级GOA单元中，第三薄膜晶体管的栅极均电性连接于电路起始信号。
本发明的有益效果：本发明提供的一种基于LTPS半导体薄膜晶体管的GOA电路，通过正向扫描直流控制信号和反向扫描直流控制信号控制第一、第二、及第三节点的电位，时钟信号仅负责对应级GOA单元的输出，能够有效的降低时钟信号的负载，保证多级GOA单元连接后时钟信号的整体负载降低，提升GOA电路的输出稳定性，还可以实现GOA电路的正反向扫描。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的电路图；
图2为对应与图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时的时序图；
图3为本发明的基于LTPS半导体薄膜晶体管的GOA电路的电路图；
图4为本发明的基于LTPS半导体薄膜晶体管的GOA电路在正向扫描时的时序图；
图5为本发明的基于LTPS半导体薄膜晶体管的GOA电路在反向扫描时的时序图；
图6为本发明的基于LTPS半导体薄膜晶体管的GOA电路的第一级GOA单元的电路图；
图7为本发明的基于LTPS半导体薄膜晶体管的GOA电路的第二级GOA单元的电路图；
图8为本发明的基于LTPS半导体薄膜晶体管的GOA电路的倒数第二级GOA单元的电路图；
图9为本发明的基于LTPS半导体薄膜晶体管的GOA电路的最后一级GOA单元的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明提供一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：扫描控制单元100、正向扫描下拉单元200、反向扫描下拉单元300、及输出单元400。
设n为正整数，除第一级、第二级、倒数第二级、及最后一级GOA单元外，在第n级GOA单元中：
所述扫描控制单元100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于上两级第n-2级GOA单元的输出端G(n-2)，源极电性连接于正向扫描直流控制信号U2D，漏极电性连接于第四薄膜晶体管T4的源极；第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于下两级第n+2级GOA单元的输出端G(n+2)，漏极电性连接于第四薄膜晶体管T4的源极，源极电性连接于反向扫描直流控制信号D2U；以及第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于恒压高电位VGH，漏极电性连接于第一节点Q(n)；
所述正向扫描下拉单元200包括：第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于正向扫描直流控制信号U2D，源极电性连接于恒压高电位VGH，漏极电性连接于第二节点P1(n)；第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于反向扫描直流控制信号D2U，漏极电性连接于第二节点P1(n)，源极电性连接于恒压低电位VGL；第十三薄膜晶体管T13，所述第十三薄膜晶体管T13的栅极电性连接于第一节点Q(n)，漏极电性连接于第二节点P1(n)，源极电性连接于恒压低电位VGL；第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于第二节点P1(n)，源极电性连接于恒压低电位VGL，漏极电性连接于第一节点Q(n)；以及第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极电性连接于第二节点P1(n)，源极电性连接于恒压低电位VGL，漏极电性连接于输出端G(n)；
所述反向扫描下拉单元300包括：第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于正向扫描直流控制信号U2D，源极电性连接于恒压低电位VGL，漏极电性连接于第三节点P2(n)；第七薄膜晶体管T9，所述第七薄膜晶体管T7的栅极电性连接于反向扫描直流控制信号D2U，源极电性连接于恒压高电位VGH，漏极电性连接于第三节点P2(n)；第十四薄 膜晶体管T14，所述第十四薄膜晶体管T14的栅极电性连接于第一节点Q(n)，漏极电性连接于第三节点P2(n)，源极电性连接于恒压低电位VGL；第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极电性连接于第三节点P2(n)，源极电性连接于恒压低电位VGL，漏极电性连接于第一节点Q(n)；以及第十二薄膜晶体管T12，所述第十二薄膜晶体管T12的栅极电性连接于第三节点P2(n)，源极电性连接于恒压低电位VGL，漏极电性连接于输出端G(n)；
所述输出单元400包括：第二薄膜晶体T2，所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第M条时钟信号CK(M)，漏极电性连接于输出端G(n)；以及自举电容C1，所述自举电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)。
具体地，各个薄膜晶体管均为N型低温多晶硅薄膜晶体管。
特别地，请参阅图6-图9，在第一级GOA单元和第二级GOA单元中，第一薄膜晶体管T1的栅极均电性连接于电路起始信号STV；在最后一级GOA单元和倒数第二级GOA单元中，第三薄膜晶体管T3的栅极均电性连接于电路起始信号STV。
本发明的基于LTPS半导体薄膜晶体管的GOA电路具备正反向扫描功能。所述正向扫描直流控制信号U2D与反向扫描直流控制信号D2U的电位相反，当所述正向扫描直流控制信号U2D为高电位、反向扫描直流控制信号D2U为低电位时，GOA电路进行正向扫描；当所述正向扫描直流控制信号U2D为低电位、反向扫描直流控制信号D2U为高电位时，GOA电路进行反向扫描。
结合图4与图5，所述基于LTPS半导体薄膜晶体管的GOA电路包括四条时钟信号：第一条时钟信号CK(1)、第二条时钟信号CK(2)、第三条时钟信号CK(3)、及第四条时钟信号CK(4)，每一条时钟信号对应一级GOA单元，例如：第一条时钟信号CK(1)接入第一级GOA单元、第二条时钟信号CK(2)接入第二级GOA单元、第三条时钟信号CK(3)接入第三级GOA单元、第四条时钟信号CK(4)接入第四级GOA单元。该时钟信号仅用于对应的GOA单元的输出端输出。
值得一提的是，本发明的基于LTPS半导体薄膜晶体管GOA电路不论进行正向扫描还是反向扫描，所述时钟信号CK(M)仅负责对应级GOA单元的输出端G(n)输出，而第一节点Q(n)、第二节点P1(n)、及第三节点P2(n)的电位均受正向扫描直流控制信号U2D与反向扫描直流控制信号D2U的控制，能够有效的降低时钟信号CK(M)的负载，保证多级GOA单元连接后时 钟信号的整体负载降低，提升GOA电路的输出稳定性。
请结合图3与图4，所述正向扫描直流控制信号U2D为高电位，反向扫描直流控制信号D2U为低电位，GOA电路正向扫描，具体工作过程为：
阶段1、预充电阶段：第n-2级GOA单元的输出端G(n-2)与正向扫描直流控制信号U2D均为高电位，第一薄膜晶体管T1导通，第四薄膜晶体管T4受恒压高电位VGH的控制一直处于导通的状态，第一节点Q(n)被高电位的正向扫描直流控制信号U2D预充电至高电位，受第一节点Q(n)控制的第十三、和第十四薄膜晶体管T13、T14处于导通状态，第二节点P1(n)、第三节点P2(n)的电位被拉低至恒压低电位VGL；
阶段2、高电位输出阶段：第n-2级GOA单元的输出端G(n-2)降为低电位，第M条时钟信号CK(M)提供高电位，第一薄膜晶体管T1关闭，第一节点Q(n)在自举电容C1的存储作用下继续保持高电位，第二薄膜晶体管T2导通，第M条时钟信号CK(M)的高电位经由输出端G(n)输出，并使得第一节点Q(n)被抬升至更高的电位；
阶段3、低电位输出阶段：第M条时钟信号CK(M)提供低电位，第一节点Q(n)继续保持高电位，第二薄膜晶体管T2导通，第M条时钟信号CK(M)的低电位经由输出端G(n)输出；
阶段4、第一节点下拉阶段：第n+2级GOA单元的输出端G(n+2)提供高电位，反向扫描直流控制信号D2U为低电位，第三薄膜晶体管T3打开，第一节点Q(n)被低电位的反向扫描直流控制信号D2U拉低至低电位；
阶段5、第一节点与输出端下拉维持阶段：第一节点Q(n)变为低电位后，由于正向扫描直流控制信号U2D为高电位，反向扫描直流控制信号D2U为低电位，第五薄膜晶体管T5导通，第六薄膜晶体管T6关闭，第二节点P1(n)被恒压高电位VGH充电至高电位，受第二节点P1(n)控制的第九、和第十薄膜晶体管T9、T10导通，第一节点Q(n)与输出端G(n)被维持到恒压低电位VGL。与此同时，第八薄膜晶体管T8导通，第七薄膜晶体管T7关闭，第三节点P2(n)被恒压低电位VGL充电到低电位，受第三节点P2(n)控制的第十一、和第十二薄膜晶体管T11、T12均关闭。
请结合图3和图5，所述正向扫描直流控制信号U2D为低电位，反向扫描直流控制信号D2U为高电位，GOA电路反向扫描，具体工作过程为：
阶段1，预充电阶段：第n+2级GOA单元的输出端G(n+2)与反向扫描直流控制信号D2U均为高电位，第三薄膜晶体管T3导通，第四薄膜晶体管T4受恒压高电位VGH的控制一直处于导通的状态，第一节点Q(n)被高电位的反向扫描直流控制信号D2U预充电至高电位，受第一节点控制的第 十三、和第十四薄膜晶体管T13、T14处于导通状态，第二节点P1(n)、第三节点P2(n)的电位被拉低至恒压低电位VGL；
阶段2、高电位输出阶段：第n+2级GOA单元的输出端G(n+2)降为低电位，第M条时钟信号CK(M)提供高电位，第三薄膜晶体管T3关闭，第一节点Q(n)在自举电容C1的存储作用下继续保持高电位，第二薄膜晶体管T2导通，第M条时钟信号CK(M)的高电位经由输出端G(n)输出，并使得第一节点Q(n)被抬升至更高的电位；
阶段3、低电位输出阶段：第M条时钟信号CK(M)提供低电位，第一节点Q(n)继续保持高电位，第二薄膜晶体管T2导通，第M条时钟信号CK(M)的低电位经由输出端G(n)输出；
阶段4、第一节点下拉阶段：第n-2级GOA单元的输出端G(n-2)提供高电位，正向扫描直流控制信号U2D为低电位，第一薄膜晶体管T1打开，第一节点Q(n)被低电位的正向扫描直流控制信号U2D拉低至低电位；
阶段5、第一节点与输出端下拉维持阶段：第一节点Q(n)变为低电位后，由于反向扫描直流控制信号D2U为高电位，正向扫描直流控制信号U2D为低电位，第八薄膜晶体管T8关闭，第七薄膜晶体管T7导通，第三节点P2(n)被恒压高电位VGH充电到高电位，受第三节点P2(n)控制的第十一、和第十二薄膜晶体管T11、T12打开，第一节点Q(n)与输出端G(n)被维持到恒压低电位VGL。与此同时，第五薄膜晶体管T5关闭，第六薄膜晶体管T6导通，第二节点P1(n)被恒压低电位VGL充电至低电位，受第二节点P1(n)控制的第九、和第十薄膜晶体管T9、T10关闭。
综上所述，本发明的基于LTPS半导体薄膜晶体管的GOA电路，通过正向扫描直流控制信号和反向扫描直流控制信号控制第一、第二、及第三节点的电位，时钟信号仅负责对应级GOA单元的输出，能够有效的降低时钟信号的负载，保证多级GOA单元连接后时钟信号的整体负载降低，提升GOA电路的输出稳定性，还可以实现GOA电路的正反向扫描。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：扫描控制单元、正向扫描下拉单元、反向扫描下拉单元、及输出单元；
    设n为正整数，除第一级、第二级、倒数第二级、及最后一级GOA单元外，在第n级GOA单元中：
    所述扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于上两级第n-2级GOA单元的输出端，源极电性连接于正向扫描直流控制信号，漏极电性连接于第四薄膜晶体管的源极；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于下两级第n+2级GOA单元的输出端，漏极电性连接于第四薄膜晶体管的源极，源极电性连接于反向扫描直流控制信号；以及第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于恒压高电位，漏极电性连接于第一节点；
    所述正向扫描下拉单元包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第二节点；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于反向扫描直流控制信号，漏极电性连接于第二节点，源极电性连接于恒压低电位；第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电位，漏极电性连接于输出端；
    所述反向扫描下拉单元包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压低电位，漏极电性连接于第三节点；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第三节点；第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于第三节点，源极电 性连接于恒压低电位，漏极电性连接于输出端；
    所述输出单元包括：第二薄膜晶体，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及自举电容，所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述正向扫描直流控制信号与反向扫描直流控制信号的电位相反。
  2. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，第一节点、第二节点、及第三节点的电位均受正向扫描直流控制信号与反向扫描直流控制信号的控制。
  3. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元和第二级GOA单元中，第一薄膜晶体管的栅极均电性连接于电路起始信号。
  4. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在最后一级GOA单元和倒数第二级GOA单元中，第三薄膜晶体管的栅极均电性连接于电路起始信号。
  5. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为高电位、反向扫描直流控制信号为低电位时，进行正向扫描。
  6. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为低电位、反向扫描直流控制信号为高电位时，进行反向扫描。
  7. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述时钟信号包括四条时钟信号：第一条时钟信号(CK(1))、第二条时钟信号、第三条时钟信号、及第四条时钟信号。
  8. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述薄膜晶体管均为N型低温多晶硅薄膜晶体管。
  9. 一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：扫描控制单元、正向扫描下拉单元、反向扫描下拉单元、及输出单元；
    设n为正整数，除第一级、第二级、倒数第二级、及最后一级GOA单元外，在第n级GOA单元中：
    所述扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于上两级第n-2级GOA单元的输出端，源极电性连接于正向扫描直流控制信号，漏极电性连接于第四薄膜晶体管的源极；第三薄膜晶体 管，所述第三薄膜晶体管的栅极电性连接于下两级第n+2级GOA单元的输出端，漏极电性连接于第四薄膜晶体管的源极，源极电性连接于反向扫描直流控制信号；以及第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于恒压高电位，漏极电性连接于第一节点；
    所述正向扫描下拉单元包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第二节点；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于反向扫描直流控制信号，漏极电性连接于第二节点，源极电性连接于恒压低电位；第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电位，漏极电性连接于输出端；
    所述反向扫描下拉单元包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于正向扫描直流控制信号，源极电性连接于恒压低电位，漏极电性连接于第三节点；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于恒压高电位，漏极电性连接于第三节点；第十四薄膜晶体管，所述第十四薄膜晶体管的栅极电性连接于第一节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压低电位，漏极电性连接于第一节点；以及第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于第三节点，源极电性连接于恒压低电位，漏极电性连接于输出端；
    所述输出单元包括：第二薄膜晶体，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及自举电容，所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述正向扫描直流控制信号与反向扫描直流控制信号的电位相反；
    其中，第一节点、第二节点、及第三节点的电位均受正向扫描直流控制信号与反向扫描直流控制信号的控制；
    其中，在第一级GOA单元和第二级GOA单元中，第一薄膜晶体管的栅极均电性连接于电路起始信号；
    其中，在最后一级GOA单元和倒数第二级GOA单元中，第三薄膜晶 体管的栅极均电性连接于电路起始信号。
  10. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为高电位、反向扫描直流控制信号为低电位时，进行正向扫描。
  11. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为低电位、反向扫描直流控制信号为高电位时，进行反向扫描。
  12. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述时钟信号包括四条时钟信号：第一条时钟信号(CK(1))、第二条时钟信号、第三条时钟信号、及第四条时钟信号。
  13. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述薄膜晶体管均为N型低温多晶硅薄膜晶体管。
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