CN105976775B - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents
基于ltps半导体薄膜晶体管的goa电路 Download PDFInfo
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Abstract
本发明提供的基于LTPS半导体薄膜晶体管的GOA电路,引入了电阻与一时序信号调整第二节点对应的电压的高低电平和频率。采用电阻与第十薄膜晶体管取代现有技术中的第二电容,将电阻的一端接恒压高电位,另一端接第九薄膜晶体管的栅极,第九薄膜晶体管的源极电性连接于时序信号;能够在输出端保持低电平的阶段,使第二节点的电平随着时序信号在高、低电平之间跳变而发生同样的高、低电平跳变,即按一定频率拉低第二节点的电平,有效避免了第二节点长时间处于高电平,防止因第六与第七薄膜晶体管长时间工作引起的阈值电压偏移问题,提升GOA电路的稳定性。
Description
技术领域
本发明涉及液晶显示领域,尤其是涉及一种可以提升GOA电路稳定性的基于LTPS半导体薄膜晶体管的GOA电路。
背景技术
GOA(Gate Driver on Array,集成在阵列基板上的行扫描)技术,是利用现有TFT-LCD(Thin Film Transistor-Liquid Crystal Display,薄膜晶体管液晶显示器)阵列制程将Gate行扫描驱动电路制作在阵列基板上,实现对Gate逐行扫描的驱动方式的一项技术。GOA技术能减少外接IC(Integrated Circuit,集成电路板)的焊接(bonding)工序,有机会提升产能并跳变产品成本,而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(Low Temperature Poly-silicon,LTPS)半导体薄膜晶体管的发展,LTPS-TFT液晶显示器也越来越受关注,LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。而且由于LTPS半导体本身具有超高载流子迁移率的特性,可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上,达到系统整合的目标、节省空间及驱动IC的成本。为了保证输出端G(n)点的稳定,都会引入Q(n)、P(n)两节点,Q(n)点为用于控制栅极驱动信号输出的点;P(n)点为用于维持Q(n)点及输出端G(n)点低电平的稳定点,而Q(n)、P(n)两节点之间多为相互牵制的关系。
参考图1,现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括级联的多个GOA单元,设n为正整数,第n级GOA单元包括:第一薄膜晶体管T1,其栅极电性连接于第一时钟信号CK1,源极电性连接于上一级第n-1级GOA单元的输出端G(n-1),漏极电性连接于第三节点K(n);第二薄膜晶体管T2,其栅极电性连接于第一节点Q(n),源极电性连接于第二时钟信号CK2,漏极电性连接于输出端G(n);第三薄膜晶体管T3,其栅极电性连接于第三时钟信号CK3,源极电性连接于下一级第n+1级GOA单元的输出端G(n+1),漏极电性连接于第三节点K(n);第四薄膜晶体管T4,其栅极电性连接于第四时钟信号CK4,源极电性连接于恒压低电平VGL,漏极电性连接于输出端G(n);第五薄膜晶体管T5,其栅极电性连接于恒压高电平VGH,源极电性连接于第三节点K(n),漏极电性连接于第一节点Q(n);第六薄膜晶体管T6,其栅极电性连接于第二节点P(n),源极电性连接于恒压低电平VGL,漏极电性连接于第三节点K(n);第七薄膜晶体管T7,其栅极电性连接于第二节点P(n),源极电性连接于恒压低电平VGL,漏极电性连接于输出端G(n);第八薄膜晶体管T8,其栅极电性连接于第三节点K(n),源极电性连接于恒压低电平VGL,漏极电性连接于第二节点P(n);第九薄膜晶体管T9,其栅极与源极均电性连接于第二时钟信号CK2,漏极电性连接于第二节点P(n);自举电容C1,其一端电性连接于第一节点Q(n),另一端电性连接于输出端G(n);第二电容C2,其一端电性连接于第二节点P(n),另一端电性连接于恒压低电平VGL。
图1所示的GOA电路既可以正向扫描也可以反向扫描,正、反向扫描的工作过程类似。结合图1与图2,以正向扫描为例进行说明,其中,图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时,其工作过程为:阶段1,预充电:G(n-1)与CK1同时为高电平,T1导通,T5栅极接恒压高电平VGH因此T5一直处于导通的状态,第一节点Q(n)被预充电至高电平。阶段2,输出端G(n)输出高电平:G(n-1)与CK1跳变为低电平,CK2提供高电平,第一节点Q(n)因自举电容C1的存储作用保持高电平,T2导通,CK2的高电平输出到输出端G(n),从而输出端G(n)输出高电平,并使得第一节点Q(n)被抬升至更高的电平,同时T8导通,第二节点P(n)被拉低,T6、T7截止。阶段3,输出端G(n)输出低电平:CK3与G(n+1)均提供高电平,第一节点Q(n)仍为高电平,CK2跳变为低电平,CK2的低电平输出到输出端G(n),从而输出端G(n)输出低电平。阶段4,第一节点Q(n)拉低到恒压低电平VGL:CK1再次提供高电平,G(n-1)保持低电平,T1导通拉低第一节点Q(n)至恒压低电平VGL,T8截止。阶段5,第一节点Q(n)及输出端G(n)低电平维持阶段:CK2提供高电平,T9导通,第二节点P(n)被充电至高电平,T6、T7导通,分别继续拉低第一节点Q(n)及输出端G(n)至恒压低电平VGL,在第二电容C2的存储作用下,第二节点P(n)持续保持高电平,T6、T7在一帧时间内一直导通,保持第一节点Q(n)及输出端G(n)的低电平。
从图2中不难看出,第二节点P(n)对应的高电平接近恒压高电平VGH(第二节点P(n)的高电平一定程度上可以通过T9的大小来调整),低电平为恒压低电平VGL(没有办法做改动)。在上述现有的GOA电路中,由于第二节点P(n)一直处于高电平的状态,也就是T6、T7一直处于导通的状态。T6、T7长时间工作,会造成T6、T7这两个关键薄膜晶体管阈值电压发生偏移(Vth Shift),造成电路的稳定能力下降,从而引起GOA电路输出异常。
因此,亟需提供一种新的GOA电路,以提升GOA电路的稳定性。
发明内容
本发明的目的在于,提供一种基于LTPS半导体薄膜晶体管的GOA电路,与现有的基于LTPS半导体薄膜晶体管的GOA电路相比,可以避免第二节点P(n)长时间处于高电平,防止因第六与第七薄膜晶体管长T6、T7时间工作引起的阈值电压偏移问题,提升GOA电路的稳定性,提高液晶面板显示品质。
为实现上述目的,本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路,包括:级联的多个GOA单元,每一级GOA单元均包括扫描控制模块、输出模块、自举电容以及下拉模块;设n为正整数,除第一级与最后一级GOA单元以外,在第n级GOA单元中:所述扫描控制模块包括:第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管;所述第一薄膜晶体管的栅极电性连接于第一时钟信号,源极电性连接于上一级第n-1级GOA单元的输出端G(n-1),漏极电性连接于第三节点;所述第三薄膜晶体管的栅极电性连接于第三时钟信号,源极电性连接于下一级第n+1级GOA单元的输出端G(n+1),漏极电性连接于所述第三节点;所述第五薄膜晶体管的栅极电性连接于恒压高电平,源极电性连接于所述第三节点,漏极电性连接于第一节点;所述输出模块包括:第二薄膜晶体管,所述第二薄膜晶体管的栅极电性连接于所述第一节点,源极电性连接于第二时钟信号,漏极电性连接于输出端G(n);所述自举电容的一端电性连接于所述第一节点,另一端电性连接于所述输出端G(n);以及所述下拉模块包括:第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及电阻;所述第四薄膜晶体管的栅极电性连接于第四时钟信号,源极电性连接于恒压低电平,漏极电性连接于所述输出端G(n);所述第六薄膜晶体管的栅极电性连接于第二节点,源极电性连接于所述恒压低电平,漏极电性连接于所述第三节点;所述第七薄膜晶体管的栅极电性连接于所述第二节点,源极电性连接于所述恒压低电平,漏极电性连接于所述输出端G(n);所述第八薄膜晶体管的栅极电性连接于所述第三节点,源极电性连接于所述恒压低电平,漏极电性连接于所述第二节点;所述第九薄膜晶体管的栅极电性连接于第四节点,源极电性连接于时序信号,漏极电性连接于所述第二节点;所述第十薄膜晶体管的栅极电性连接于所述第三节点,源极电性连接于所述恒压低电平,漏极电性连接于所述第四节点;所述电阻的一端电性连接于所述恒压高电平,另一端电性连接于所述第四节点。
本发明的优点在于,本发明提供的基于LTPS半导体薄膜晶体管的GOA电路,引入了电阻与一时序信号调整第二节点P(n)对应的电压的高低电平和频率。采用电阻与第十薄膜晶体管取代现有技术中的第二电容,并改变现有技术中第九薄膜晶体管的二极体接法;将电阻的一端接恒压高电位,另一端接第九薄膜晶体管的栅极,第九薄膜晶体管的源极电性连接于时序信号;能够在输出端G(n)保持低电平的阶段,使第二节点P(n)的电平随着时序信号在高、低电平之间跳变而发生同样的高、低电平跳变,即按一定频率拉低第二节点P(n)的电平,有效避免了第二节点P(n)长时间处于高电平,防止因第六与第七薄膜晶体管长T6、T7时间工作引起的阈值电压偏移问题,提升GOA电路的稳定性,以适用高解析度的液晶面板设计。本发明所提供的GOA电路可应用于手机,显示器,电视的栅极驱动领域。
附图说明
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图;
图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图;
图3,本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图;
图4为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图;
图5为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图。
具体实施方式
下面结合附图对本发明提供的基于LTPS半导体薄膜晶体管的GOA电路做详细说明。
参考图3,本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括:级联的多个GOA单元,每一级GOA单元均包括扫描控制模块32、输出模块34、自举电容C1以及下拉模块36。
设n为正整数,除第一级与最后一级GOA单元以外,在第n级GOA单元中:所述扫描控制模块32包括:第一薄膜晶体管T1、第三薄膜晶体管T3以及第五薄膜晶体管T5;所述输出模块34包括:第二薄膜晶体管T2;所述下拉模块36包括:第四薄膜晶体管T4、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及电阻R1。
在所述扫描控制模块32中:第一薄膜晶体管T1的栅极电性连接于第一时钟信号CK1,源极电性连接于上一级第n-1级GOA单元的输出端G(n-1),漏极电性连接于第三节点K(n);第三薄膜晶体管T3的栅极电性连接于第三时钟信号CK3,源极电性连接于下一级第n+1级GOA单元的输出端G(n+1),漏极电性连接于第三节点K(n);第五薄膜晶体管T5的栅极电性连接于恒压高电平VGH,源极电性连接于第三节点K(n),漏极电性连接于第一节点Q(n)。
在所述输出模块34中:第二薄膜晶体管T2的栅极电性连接于第一节点Q(n),源极电性连接于第二时钟信号CK2,漏极电性连接于输出端G(n)。
所述自举电容C1的一端电性连接于第一节点Q(n),另一端电性连接于输出端G(n)。
在所述下拉模块36中:第四薄膜晶体管T4的栅极电性连接于第四时钟信号CK4,源极电性连接于恒压低电平VGL,漏极电性连接于输出端G(n);第六薄膜晶体管T6的栅极电性连接于第二节点P(n),源极电性连接于恒压低电平VGL,漏极电性连接于第三节点K(n);第七薄膜晶体管T7的栅极电性连接于第二节点P(n),源极电性连接于恒压低电平VGL,漏极电性连接于输出端G(n);第八薄膜晶体管T8的栅极电性连接于第三节点K(n),源极电性连接于恒压低电平VGL,漏极电性连接于第二节点P(n);第九薄膜晶体管T9的栅极电性连接于第四节点M(n),源极电性连接于时序信号Reset,漏极电性连接于第二节点P(n);第十薄膜晶体管T10的栅极电性连接于第三节点K(n),源极电性连接于恒压低电平VGL,漏极电性连接于第四节点M(n);电阻R1的一端电性连接于恒压高电平VGH,另一端电性连接于第四节点M(n)。
具体的,本发明所述的各个薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
具体的,所述的GOA电路的四条时钟信号:所述第一时钟信号CK1、所述第二时钟信号CK2、所述第三时钟信号CK3和所述第四时钟信号CK4的脉冲是依序轮流输出,且互不重叠。
特别地,在第一级GOA单元中,第一薄膜晶体管T1的源极电性连接于电路起始信号STV;在最后一级GOA单元中,第三薄膜晶体管T3的源极电性连接于电路起始信号STV。本发明所述的基于LTPS半导体薄膜晶体管的GOA电路既可以从第一级向最后一级逐级进行正向扫描,也可以从最后一级向第一级逐级进行反向扫描。其中,在正向扫描时,首先向第一级GOA单元中的第一薄膜晶体管T1提供第一条时钟信号(即CK1为高电平)和电路起始信号STV;也即正向扫描时,与所述第一薄膜晶体管T1电性连接的第一时钟信号CK1和上一级第n-1级GOA单元的输出端G(n-1)同时提供高电平。反向扫描时,首先向最后一级GOA单元中的第三薄膜晶体管T3提供第一条时钟信号(即CK3为高电平)和电路起始信号STV;也即反向扫描时,与所述第三薄膜晶体管电性连接的第三时钟信号CK3和下一级第n+1级GOA单元的输出端G(n+1)同时提供高电平。
本发明所述的基于LTPS半导体薄膜晶体管的GOA电路,无论是在正向扫描时还是反向扫描时,均能够按一定频率拉低所述第二节点P(n)的电平。
参考图4,其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时,其工作过程为:
阶段1、预充电:时钟信号CK1与输出端G(n-1)均提供高电平,时钟信号CK2、CK3、CK4均提供低电平,输出端G(n+1)也提供低电平;第一薄膜晶体管T1受时钟信号CK1的控制导通,第三节点K(n)被预充电至高电平,受第三节点K(n)控制的第八、第十薄膜晶体管T8、T10导通;第五薄膜晶体管T5受恒压高电平VGH的控制始终导通,故第三节点K(n)与第一节点Q(n)的电平始终相同,第一节点Q(n)被预充电至高电平;第二、第四节点P(n)、M(n)被拉低至恒压低电平VGL,受第二节点P(n)控制的第六、第七薄膜晶体管T6、T7截止,受第四节点M(n)控制的第九薄膜晶体管T9截止。
阶段2、输出端G(n)输出高电平:时钟信号CK1与输出端G(n-1)均跳变为低电平,时钟信号CK2提供高电平,时钟信号CK3、CK4和输出端G(n+1)仍提供低电平;第一节点Q(n)因自举电容C1的存储作用保持高电平;第二薄膜晶体管T2导通,时钟信号CK2的高电平输出到输出端G(n),从而输出端G(n)输出高电平,并使得第一节点Q(n)被抬升至更高的电平,第八、第十薄膜晶体管T8、T10仍导通;第二、第四节点P(n)、M(n)保持恒压低电平VGL,受第二节点P(n)控制的第六、第七薄膜晶体管T6、T7仍截止,受第四节点M(n)控制的第九薄膜晶体管T9仍截止。
阶段3、输出端G(n)输出低电平:时钟信号CK2跳变为低电平,时钟信号CK3与输出端G(n+1)均提供高电平,时钟信号CK1、CK4及输出端G(n-1)仍提供低电平;受时钟信号CK3控制的第三薄膜晶体管T3导通;第一节点Q(n)仍为高电平,受第一节点Q(n)控制的第二、第八、第十薄膜晶体管T2、T8、T10仍导通;第二、第四节点P(n)、M(n)仍保持恒压低电平VGL,受第二节点P(n)控制的第六、第七薄膜晶体管T6、T7仍截止,受第四节点M(n)控制的第九薄膜晶体管T9仍截止;由于第二薄膜晶体管T2仍导通,时钟信号CK2的低电平输出到输出端G(n),从而输出端G(n)输出低电平。
阶段4,第一节点Q(n)拉低到恒压低电平VGL:时钟信号CK1再次提供高电平,时钟信号CK2、CK3、CK4和输出端G(n-1)提供低电平;受时钟信号CK1控制的第一薄膜晶体管T1导通,拉低第一节点Q(n)至恒压低电平VGL;受第一节点Q(n)控制的第二、第八、第十薄膜晶体管T2、T8、T10截止。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段:第四节点M(n)由于电阻R1的分压始终处于高电平,第九薄膜晶体管T9始终导通,时序信号Reset会被传输到第二节点P(n);随着时序信号Reset交替提供高、低电平,第二节点P(n)的电平随着发生同样的高、低电平跳变,即第二节点P(n)的高低电平跳变频率与时序信号Reset一致。当时序信号Reset为高电平时,第二节点P(n)会被充电到高电平,第六、第七薄膜晶体管T6、T7导通;当时序信号Reset为低电平时,第二节点P(n)会被拉低到低电平,第六、第七薄膜晶体管T6、T7截止;第一节点Q(n)及输出端G(n)保持低电平。即在输出端G(n)保持低电平的阶段,第二节点P(n)的电平随着时序信号Reset在高、低电平之间跳变而发生同样的高、低电平跳变。
具体地:时序信号Reset的高电平V2低于或等于恒压高电平VGH且高于第六、第七薄膜晶体管T6、T7的阈值电压VTH(即VTH<V2≤VGH);时序信号Reset的低电平V1低于0且高于或等于恒压低电平VGL(即VGL≤V1<0)。时序信号Reset对应的占空比可以为25%、33%、50%等等,只要在某一占空比下,高电平V2造成阈值电压偏移(Vth shift向右)和低压V1造成的阈值电压偏移(Vth shift向左)一定程度上可以抵消即可。
相比于现有技术中第二节点P(n)长时间保持高电平,第六、第七薄膜晶体管T6、T7在一帧时间内一直导通,本发明提供的基于LTPS薄膜晶体管的GOA电路在阶段5中第二节点P(n)按一定频率被拉低,有效避免了第二节点P(n)长时间处于高电平,防止因第六与第七薄膜晶体管T6、T7长时间工作引起的阈值电压偏移问题,提升GOA电路的稳定性。
参考图5,其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图;由于正、反向扫描的工作过程类似,以下简述反向扫描的工作过程。在反向扫描时,其工作过程为:
阶段1、预充电:时钟信号CK3与输出端G(n+1)均提供高电平,第三薄膜晶体管T3受时钟信号CK3的控制导通,第三节点K(n)被预充电至高电平,受第三节点K(n)控制的第八、第十薄膜晶体管T8、T10导通;第五薄膜晶体管T5受恒压高电平VGH的控制始终导通,故第三节点K(n)与第一节点Q(n)的电平始终相同,第一节点Q(n)被预充电至高电平;第二、第四节点P(n)、M(n)被拉低至恒压低电平VGL,第六、第七、第九薄膜晶体管T6、T7、T9截止。
阶段2、输出端G(n)输出高电平:时钟信号CK2提供高电平;第一节点Q(n)因自举电容C1的存储作用保持高电平,第二薄膜晶体管T2导通,时钟信号CK2的高电平输出到输出端G(n),从而输出端G(n)输出高电平,并使得第一节点Q(n)被抬升至更高的电平。
阶段3、输出端G(n)输出低电平:时钟信号CK2跳变为低电平,时钟信号CK1与输出端G(n-1)均提供高电平,第一节点Q(n)仍为高电平,第二薄膜晶体管T2仍导通,时钟信号CK2的低电平输出到输出端G(n),从而输出端G(n)输出低电平。
阶段4,第一节点Q(n)拉低到恒压低电平VGL:时钟信号CK3再次提供高电平,输出端G(n+1)提供低电平;第三薄膜晶体管T3导通,拉低第一节点Q(n)至恒压低电平VGL。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段:当第一节点Q(n)被拉低至恒压低电平VGL后,第二、第八、第十薄膜晶体管T2、T8、T10截止,第一节点Q(n)及输出端G(n)保持低电平;第四节点M(n)由于电阻R1的分压始终处于高电平,第九薄膜晶体管T9始终导通,时序信号Reset会被传输到第二节点P(n);随着时序信号Reset交替提供高、低电平,第二节点P(n)的电平随着发生同样的高、低电平跳变,即第二节点P(n)的高低电平跳变频率与时序信号Reset一致。当时序信号Reset为高电平时,第二节点P(n)会被充电到高电平,第六、第七薄膜晶体管T6、T7导通;当时序信号Reset为低电平时,第二节点P(n)会被拉低到低电平,第六、第七薄膜晶体管T6、T7截止。即在输出端G(n)保持低电平的阶段,第二节点P(n)的电平随着时序信号Reset在高、低电平之间跳变而发生同样的高、低电平跳变。
具体地:时序信号Reset的高电平V2低于或等于恒压高电平VGH且高于第六、第七薄膜晶体管T6、T7的阈值电压VTH(即VTH<V2≤VGH);时序信号Reset的低电平V1低于0且高于或等于恒压低电平VGL(即VGL≤V1<0)。时序信号Reset对应的占空比可以为25%、33%、50%等等,只要在某一占空比下,高电平V2造成阈值电压偏移(Vth shift向右)和低压V1造成的阈值电压偏移(Vth shift向左)一定程度上可以抵消即可。
相比于现有技术中第二节点P(n)长时间保持高电平,第六、第七薄膜晶体管T6、T7在一帧时间内一直导通,本发明提供的基于LTPS薄膜晶体管的GOA电路在阶段5中第二节点P(n)按一定频率被拉低,有效避免了第二节点P(n)长时间处于高电平,防止因第六与第七薄膜晶体管T6、T7长时间工作引起的阈值电压偏移问题,提升GOA电路的稳定性。
综上所述,本发明提供的基于LTPS半导体薄膜晶体管的GOA电路,引入了电阻与一时序信号,通过调整第二节点P(n)对应的电压的高低电平和频率,能够在输出端G(n)保持低电平的阶段,使第二节点P(n)的电平随着时序信号在高、低电平之间跳变而发生同样的高、低电平跳变,即按一定频率拉低第二节点P(n)的电平,有效避免了第二节点P(n)长时间处于高电平,防止因第六与第七薄膜晶体管长T6、T7时间工作引起的阈值电压偏移问题,提升GOA电路的稳定性,以适用高解析度的液晶面板设计。本发明所提供的电路可应用于手机,显示器,电视的栅极驱动领域。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (4)
1.一种基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,包括:级联的多个GOA单元,每一级GOA单元均包括扫描控制模块、输出模块、自举电容以及下拉模块;
设n为正整数,除第一级与最后一级GOA单元以外,在第n级GOA单元中:
所述扫描控制模块包括:第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管;所述第一薄膜晶体管的栅极电性连接于第一时钟信号,源极电性连接于上一级第n-1级GOA单元的输出端G(n-1),漏极电性连接于第三节点;所述第三薄膜晶体管的栅极电性连接于第三时钟信号,源极电性连接于下一级第n+1级GOA单元的输出端G(n+1),漏极电性连接于所述第三节点;所述第五薄膜晶体管的栅极电性连接于恒压高电平,源极电性连接于所述第三节点,漏极电性连接于第一节点;
所述输出模块包括:第二薄膜晶体管,所述第二薄膜晶体管的栅极电性连接于所述第一节点,源极电性连接于第二时钟信号,漏极电性连接于输出端G(n);
所述自举电容的一端电性连接于所述第一节点,另一端电性连接于所述输出端G(n);以及
所述下拉模块包括:第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及电阻;所述第四薄膜晶体管的栅极电性连接于第四时钟信号,源极电性连接于恒压低电平,漏极电性连接于所述输出端G(n);所述第六薄膜晶体管的栅极电性连接于第二节点,源极电性连接于所述恒压低电平,漏极电性连接于所述第三节点;所述第七薄膜晶体管的栅极电性连接于所述第二节点,源极电性连接于所述恒压低电平,漏极电性连接于所述输出端G(n);所述第八薄膜晶体管的栅极电性连接于所述第三节点,源极电性连接于所述恒压低电平,漏极电性连接于所述第二节点;所述第九薄膜晶体管的栅极电性连接于第四节点,源极电性连接于时序信号,漏极电性连接于所述第二节点;所述第十薄膜晶体管的栅极电性连接于所述第三节点,源极电性连接于所述恒压低电平,漏极电性连接于所述第四节点;所述电阻的一端电性连接于所述恒压高电平,另一端电性连接于所述第四节点;
其中,在所述输出端G(n)保持低电平的阶段,所述第二节点的电平随着所述时序信号在高、低电平之间跳变而发生同样的高、低电平跳变;所述时序信号对应的占空比为33%或50%的其中之一;
所述时序信号的高电平低于或等于所述恒压高电平且高于所述第六薄膜晶体管与所述第七薄膜晶体管的阈值电压;所述时序信号的低电平低于0且高于或等于所述恒压低电平。
2.如权利要求1所述的GOA电路,其特征在于,所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出,且互不重叠。
3.如权利要求1所述的GOA电路,其特征在于,正向扫描时,与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1)同时提供高电平;反向扫描时,与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
4.如权利要求1所述的GOA电路,其特征在于,所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
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