CN105788553B - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents

基于ltps半导体薄膜晶体管的goa电路 Download PDF

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CN105788553B
CN105788553B CN201610331196.1A CN201610331196A CN105788553B CN 105788553 B CN105788553 B CN 105788553B CN 201610331196 A CN201610331196 A CN 201610331196A CN 105788553 B CN105788553 B CN 105788553B
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李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to KR1020187025654A priority patent/KR102033165B1/ko
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Abstract

本发明提供的基于LTPS半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及输出调节模块。引入了第九、第十、第十一、第十二薄膜晶体管组成的输出调节模块，无论是在正向扫描时还是反向扫描时，第四节点M(n)的电平随着第二时钟信号CK2在高、低电平之间跳变而发生同样的高、低电平跳变。相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管来实现，本发明提供的基于LTPS薄膜晶体管的GOA电路，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。

Description

基于LTPS半导体薄膜晶体管的GOA电路
技术领域
本发明涉及液晶显示领域，尤其是涉及一种可以提升GOA电路输出点的输出能力的基于LTPS半导体薄膜晶体管的GOA电路。
背景技术
GOA(Gate Driver on Array，集成在阵列基板上的行扫描)技术，是利用现有TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器)阵列制程将Gate行扫描驱动电路制作在阵列基板上，实现对Gate逐行扫描的驱动方式的一项技术。GOA技术能减少外接IC(Integrated Circuit，集成电路板)的焊接(bonding)工序，有机会提升产能并跳变产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。而且由于LTPS半导体本身具有超高载流子迁移率的特性，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。
参考图1，现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括级联的多个GOA单元，设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，其栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点H(n)；第二薄膜晶体管T2，其栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)；第三薄膜晶体管T3，其栅极电性连接于第三时钟信号CK3，漏极电性连接于第三节点H(n)，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)；第四薄膜晶体管T4，其栅极电性连接于第二节点P(n)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电平VGL；第五薄膜晶体管T5，其栅极电性连接于恒压高电平VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，其栅极电性连接于第三节点H(n)，漏极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL；第七薄膜晶体管T7，其栅极电性连接于第二节点P(n)，漏极电性连接于第一节点Q(n)，源极电性连接于恒压低电平VGL；第八薄膜晶体管T8，其栅极电性连接于第二时钟信号CK2，源极电性连接于输出端G(n)，漏极电性连接于恒压低电平VGL；第一电容C1，其一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；第二电容C2，其一端电性连接于第二节点P(n)，另一端电性连接于第二时钟信号CK2。
图1所示的GOA电路既可以正向扫描也可以反向扫描，正、反向扫描的工作过程类似。结合图1与图2，以正向扫描为例进行说明，其中，图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：阶段1，预充电：G(n-1)与CK1同时提供高电平，T1导通，T5栅极接恒压高电平VGH因此T5一直处于导通的状态，第三节点H(n)被预充电至高电平，T6导通；第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平，第二节点P(n)被拉低，T4、T7截止。阶段2，输出端G(n)输出高电平：G(n-1)与CK1跳变为低电平，CK2提供高电平；第一节点Q(n)因第一电容C1的存储作用保持高电平，T2导通，CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平。阶段3，输出端G(n)输出低电平：CK3与G(n+1)同时提供高电平，第一节点Q(n)被保持在高电平；CK2跳变为低电平，CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。阶段4，第一节点Q(n)拉低到恒压低电平VGL：CK1再次提供高电平，G(n-1)保持低电平，T1导通拉低第一节点Q(n)至恒压低电平VGL，T6截止。阶段5，第一节点Q(n)及输出端G(n)低电平维持阶段：CK2跳变为高电平，由于第二电容C2的自举作用，第二节点P(n)被充电至高电平，T4、T7导通，可以保持第一节点Q(n)及输出端G(n)的低电平。
在上述现有的GOA电路中，输出端G(n)的高低电平主要是靠薄膜晶体管T2来实现。即当第一节点Q(n)被预充电以后，时钟信号CK2为高时，通过薄膜晶体管T2将输出端G(n)拉高；时钟信号CK2为低时，通过薄膜晶体管T2将输出端G(n)拉低。而在一定的时间内，薄膜晶体管T2对应的充电能力有限，尤其当在图像中每英寸所表达的像素数目(Pixel Per Inch，PPI)越高时，充电时间急剧缩短，输出端G(n)可能无法达到预先要求的电位，或者对应的RCDelay(RC延迟)时间过长，这两种情况都会影响到面内像素(Pixel)的充电结果，进而影响液晶面板的显示效果。
因此，亟需提供一种新的GOA电路，以提升GOA电路输出点的输出能力。
发明内容
本发明的目的在于，提供一种基于LTPS半导体薄膜晶体管的GOA电路，与现有的基于LTPS半导体薄膜晶体管的GOA电路相比，在相同的时间内可以提高输出点G(n)的输出能力，提高面内像素的充电率，提高负载能力，进而改善液晶面板的显示效果。
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及输出调节模块；设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述第二时钟信号；以及所述输出调节模块包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管；所述第九薄膜晶体管的栅极电性连接于所述第二时钟信号，源极电性连接于所述恒压高电平，漏极电性连接于第四节点；所述第十薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于所述第四节点，漏极电性连接于所述输出端G(n)；所述第十一薄膜晶体管的栅极电性连接于所述输出端G(n-1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述第十二薄膜晶体管的栅极电性连接于所述输出端G(n+1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点。
本发明的优点在于，本发明提供的基于LTPS半导体薄膜晶体管的GOA电路，引入了第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，无论是在正向扫描时还是反向扫描时，第四节点M(n)的电平随着第二时钟信号CK2在高、低电平之间跳变而发生同样的高、低电平跳变。相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，本发明提供的基于LTPS薄膜晶体管的GOA电路，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。本发明所提供的GOA电路可应用于手机，显示器，电视的栅极驱动领域。
附图说明
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图；
图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图；
图4为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图5为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图。
具体实施方式
下面结合附图对本发明提供的基于LTPS半导体薄膜晶体管的GOA电路做详细说明。
参考图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块32、输出模块34、下拉模块36以及输出调节模块38。
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块32包括：第一薄膜晶体管T1、第三薄膜晶体管T3以及第五薄膜晶体管T5；所述输出模块34包括：第二薄膜晶体管T2以及第一自举电容C1；所述下拉模块36包括：第四薄膜晶体管T4、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8以及第二自举电容C2；所述输出调节模块38包括：第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11以及第十二薄膜晶体管T12。
在所述扫描控制模块32中：第一薄膜晶体管T1的栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点H(n)；第三薄膜晶体管T3的栅极电性连接于第三时钟信号CK3，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第三节点H(n)；第五薄膜晶体管T5的栅极电性连接于恒压高电平VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)。
在所述输出模块34中：第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)；第一自举电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)。
在所述下拉模块36中：第四薄膜晶体管T4的栅极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第六薄膜晶体管T6的栅极电性连接于第三节点H(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第二节点P(n)；第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第一节点Q(n)；第八薄膜晶体管T8的栅极电性连接于第四时钟信号CK4，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第二自举电容C2的一端电性连接于第二节点P(n)，另一端电性连接于第二时钟信号CK2。
在所述输出调节模块38中：第九薄膜晶体管T9的栅极电性连接于第二时钟信号CK2，源极电性连接于恒压高电平VGH，漏极电性连接于第四节点M(n)；第十薄膜晶体管T10的栅极电性连接于第一节点Q(n)，源极电性连接于第四节点M(n)，漏极电性连接于输出端G(n)；第十一薄膜晶体管T11的栅极电性连接于输出端G(n-1)，源极电性连接于恒压低电平VGL，漏极电性连接于第四节点M(n)；第十二薄膜晶体管T12的栅极电性连接于输出端G(n+1)，源极电性连接于恒压低电平VGL，漏极电性连接于第四节点M(n)。
具体的，本发明所述的各个薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
具体的，所述的GOA电路的四条时钟信号：所述第一时钟信号CK1、所述第二时钟信号CK2、所述第三时钟信号CK3和所述第四时钟信号CK4的脉冲是依序轮流输出，且互不重叠。
特别地，在第一级GOA单元中，第一薄膜晶体管T1的源极电性连接于电路起始信号STV；在最后一级GOA单元中，第三薄膜晶体管T3的源极电性连接于电路起始信号STV。本发明所述的基于LTPS半导体薄膜晶体管的GOA电路既可以从第一级向最后一级逐级进行正向扫描，也可以从最后一级向第一级逐级进行反向扫描。其中，在正向扫描时，首先向第一级GOA单元中的第一薄膜晶体管T1提供第一条时钟信号(即CK1为高电平)和电路起始信号STV；也即正向扫描时，与所述第一薄膜晶体管T1电性连接的第一时钟信号CK1和上一级第n-1级GOA单元的输出端G(n-1)同时提供高电平。反向扫描时，首先向最后一级GOA单元中的第三薄膜晶体管T3提供第一条时钟信号(即CK3为高电平)和电路起始信号STV；也即反向扫描时，与所述第三薄膜晶体管电性连接的第三时钟信号CK3和下一级第n+1级GOA单元的输出端G(n+1)同时提供高电平。
本发明所述的基于LTPS半导体薄膜晶体管的GOA电路，无论是在正向扫描时还是反向扫描时，第四节点M(n)的电平随着第二时钟信号CK2在高、低电平之间跳变而发生同样的高、低电平跳变。与现有技术相比，能够在相同的时间内，一定程度上提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。
参考图4，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK1与输出端G(n-1)均提供高电平，时钟信号CK2、CK3、CK4均提供低电平，输出端G(n+1)也提供低电平；第一薄膜晶体管T1受时钟信号CK1的控制导通，第三节点H(n)被预充电至高电平，受第三节点H(n)控制的第六薄膜晶体管T6导通；第五薄膜晶体管T5受恒压高电平VGH的控制始终导通，故第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二节点P(n)被拉低至恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7截止；同时，由于输出端G(n-1)提供高电平，第十一薄膜晶体管T11导通，第四节点M(n)被拉低。
阶段2、输出端G(n)输出高电平：时钟信号CK1与输出端G(n-1)均跳变为低电平，时钟信号CK2提供高电平，时钟信号CK3、CK4和输出端G(n+1)仍提供低电平；第一节点Q(n)因第一自举电容C1的存储作用保持高电平；第二薄膜晶体管T2导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平，第六薄膜晶体管T6仍导通；第二节点P(n)保持恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7仍截止；同时，由于时钟信号CK2提供高电平，第九薄膜晶体管T9导通，恒压高电平VGH将第四节点M(n)预充电至恒压高电平VGH；第十薄膜晶体管T10导通，第四节点M(n)的高电平会对输出端G(n)进行充电。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK3与输出端G(n+1)均提供高电平，时钟信号CK1、CK4及输出端G(n-1)仍提供低电平；受时钟信号CK3控制的第三薄膜晶体管T3导通；第一节点Q(n)保持高电平，第二、第六薄膜晶体管T2、T6仍导通；第二节点P(n)仍保持恒压低电平VGL，受第二节点P(n)控制的第四、第七薄膜晶体管T4、T7仍截止；由于第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而拉低输出端G(n)；同时，由于时钟信号CK2提供低电平，第九薄膜晶体管T9截止；由于输出端G(n+1)提供高电平，第十二薄膜晶体管T12导通，恒压低电平VGL将第四节点M(n)预充电至恒压低电平VGL；第十薄膜晶体管T10仍处于导通的状态，第四节点M(n)的低电平也会起到拉低输出端G(n)的作用。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK1再次提供高电平，时钟信号CK2、CK3、CK4和输出端G(n-1)提供低电平；受时钟信号CK1控制的第一薄膜晶体管T1导通，拉低第一节点Q(n)至恒压低电平VGL，使得第二、第六薄膜晶体管T2、T6截止。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：时钟信号CK2再次提供高电平，时钟信号CK1跳变为低电平，时钟信号CK3、CK4和输出端G(n-1)、G(n+1)提供低电平；由于第二自举电容C2的自举，第二节点P(n)被充电至高电平，第四、第七薄膜晶体管T4、T7导通，使得第一节点Q(n)及输出端G(n)保持低电平。
相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，而在一定的时间内第二薄膜晶体管T2对应的充电能力有限，本发明提供的基于LTPS薄膜晶体管的GOA电路，在第一节点Q(n)预充电阶段，通过第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。
参考图5，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图，由于正、反向扫描的工作过程类似，以下简述反向扫描的工作过程。在反向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK3与输出端G(n+1)均提供高电平，第三薄膜晶体管T3受时钟信号CK3的控制导通，第三节点H(n)被预充电至高电平，受第三节点H(n)控制的第六薄膜晶体管T6导通；第五薄膜晶体管T5受恒压高电平VGH的控制始终导通，故第三节点H(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二节点P(n)被拉低至恒压低电平VGL，第四、第七薄膜晶体管T4、T7截止；同时，由于输出端G(n+1)提供高电平，第十二薄膜晶体管T12导通，第四节点M(n)被拉低。
阶段2、输出端G(n)输出高电平：时钟信号CK2提供高电平，第一节点Q(n)因第一自举电容C1的存储作用保持高电平，第二薄膜晶体管T2导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平；同时，由于时钟信号CK2提供高电平，第九薄膜晶体管T9导通，恒压高电平VGH将第四节点M(n)预充电至恒压高电平VGH；第十薄膜晶体管T10导通，第四节点M(n)的高电平会对输出端G(n)进行充电。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK1与输出端G(n-1)均提供高电平，第一节点Q(n)仍为高电平，第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平；同时，由于时钟信号CK2提供低电平，第九薄膜晶体管T9截止；由于输出端G(n-1)提供高电平，第十一薄膜晶体管T11导通，恒压低电平VGL将第四节点M(n)预充电至恒压低电平VGL；第十薄膜晶体管T10仍处于导通的状态，第四节点M(n)的低电平也会起到拉低输出端G(n)的作用。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK3再次提供高电平，输出端G(n+1)提供低电平；第三薄膜晶体管T3导通，拉低第一节点Q(n)至恒压低电平VGL。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：时钟信号CK2再次提供高电平，时钟信号CK3跳变为低电平；由于第二自举电容C2的自举，第二节点P(n)被充电至高电平，第四、第七薄膜晶体管T4、T7导通，使得第一节点Q(n)及输出端G(n)保持低电平。
相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，而在一定的时间内第二薄膜晶体管T2对应的充电能力有限，本发明提供的基于LTPS薄膜晶体管的GOA电路，在第一节点Q(n)预充电阶段，通过第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。
综上所述，本发明提供的基于LTPS半导体薄膜晶体管的GOA电路，引入了第九、第十、第十一、第十二薄膜晶体管T9、T10、T11、T12组成的输出调节模块，无论是在正向扫描时还是反向扫描时，第四节点M(n)的电平随着第二时钟信号CK2在高、低电平之间跳变而发生同样的高、低电平跳变。相比于现有技术中输出端G(n)的高低电平主要是靠第二薄膜晶体管T2来实现，本发明提供的基于LTPS薄膜晶体管的GOA电路，在相同的时间内，一定程度上可以提高输出端G(n)的输出能力，提高面内Pixel的充电率，进而改善液晶面板的显示效果。本发明所提供的GOA电路可应用于手机，显示器，电视的栅极驱动领域。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (5)

1.一种基于LTPS半导体薄膜晶体管的GOA电路，其特征在于，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、下拉模块以及输出调节模块；
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；
所述输出模块包括：第二薄膜晶体管以及第一自举电容；所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于第n级GOA单元的输出端G(n)；所述第一自举电容的一端电性连接于所述第一节点，另一端电性连接于所述第n级GOA单元的输出端G(n)；
所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第二自举电容；所述第四薄膜晶体管的栅极电性连接于第二节点，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；
所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第一节点；所述第八薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第二自举电容的一端电性连接于所述第二节点，另一端电性连接于所述第二时钟信号；以及
所述输出调节模块包括：第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管；所述第九薄膜晶体管的栅极电性连接于所述第二时钟信号，源极电性连接于所述恒压高电平，漏极电性连接于第四节点；所述第十薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于所述第四节点，漏极电性连接于所述输出端G(n)；
所述第十一薄膜晶体管的栅极电性连接于所述输出端G(n-1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述第十二薄膜晶体管的栅极电性连接于所述输出端G(n+1)，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点。
2.如权利要求1所述的GOA电路，其特征在于，所述第四节点的电平随着所述第二时钟信号在高、低电平之间跳变而发生同样的高、低电平跳变。
3.如权利要求1所述的GOA电路，其特征在于，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠。
4.如权利要求1所述的GOA电路，其特征在于，正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1)同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
5.如权利要求1所述的GOA电路，其特征在于，所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
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WO2017197684A1 (zh) 2017-11-23
KR102033165B1 (ko) 2019-11-08
CN105788553A (zh) 2016-07-20
GB201814452D0 (en) 2018-10-17
EA201891566A1 (ru) 2018-12-28
US10403219B2 (en) 2019-09-03
JP2019512715A (ja) 2019-05-16
JP6799069B2 (ja) 2020-12-09
EA035508B1 (ru) 2020-06-26

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