CN105469756A - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents
基于ltps半导体薄膜晶体管的goa电路 Download PDFInfo
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
本发明提供一种基于LTPS半导体薄膜晶体管的GOA电路,通过正向扫描直流控制信号(U2D)和反向扫描直流控制信号(D2U)控制第一节点(Q(n))和第二节点(P(n))的电位,时钟信号(CK(M))仅负责对应级GOA单元的输出,能够有效的降低时钟信号的负载,保证多级GOA单元连接后时钟信号的整体负载降低,提升GOA电路的输出稳定性,还可以实现GOA电路的正反向扫描,且每级GOA单元仅包括十个薄膜晶体管,有利于减少GOA电路的布局空间,实现显示装置的窄边框设计。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种基于LTPS半导体薄膜晶体管的GOA电路。
背景技术
液晶显示器(LiquidCrystalDisplay,LCD)具有机身薄、省电、无辐射等众多优点,得到了广泛的应用。如:液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等,在平板显示领域中占主导地位。
GOA技术(GateDriveronArray)即阵列基板行驱动技术,是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上,使之能替代外接集成电路板((IntegratedCircuit,IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序,有机会提升产能并降低产品成本,而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(LowTemperaturePoly-silicon,LTPS)半导体薄膜晶体管的发展,LTPS-TFT液晶显示器也越来越受关注,LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序,低温多晶硅半导体本身具有超高的电子迁移率,比非晶硅半导体相对高100倍以上,可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上,达到系统整合的目标、节省空间及驱动IC的成本。
请参阅图1,现有的一种基于LTPS半导体薄膜晶体管的GOA电路,包括级联的多个GOA单元,设n为正整数,第n级GOA单元包括:第一薄膜晶体管T1,所述第一薄膜晶体管T1的栅极电性连接于第M条时钟信号CK(M),源极电性连接于上一级第n-1级GOA单元的输出端G(n-1),漏极电性连接于第三节点K(n);第二薄膜晶体管T2,所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n),源极电性连接于第M+1条时钟信号CK(M+1),漏极电性连接于输出端G(n);第三薄膜晶体管T3,所述第三薄膜晶体管T3的栅极电性连接于第M+2条时钟信号CK(M+2),漏极电性连接于第三节点K(n),源极电性连接于下一级第n+1级GOA单元的输出端G(n+1);第四薄膜晶体管T4,所述第四薄膜晶体管T4的栅极电性连接于第M+3条时钟信号CK(M+3),漏极电性连接于输出端G(n),源极电性连接于恒压低电位VGL;第五薄膜晶体管T5,所述第五薄膜晶体管T5的栅极电性连接于恒压高电位VGH,源极电性连接于第三节点K(n),漏极电性连接于第一节点Q(n);第六薄膜晶体管T6,所述第六薄膜晶体管T6的栅极电性连接于第二节点P(n),漏极电性连接于第三节点K(n),源极电性连接于恒压低电位VGL;第七薄膜晶体管T7,所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n),漏极电性连接于输出端G(n),源极电性连接于恒压低电位VGL;第八薄膜晶体管T8,所述第八薄膜晶体管T8的栅极电性连接于第三节点K(n),漏极电性连接于第二节点P(n),源极电性连接于恒压低电位VGL;第九薄膜晶体管T9,所述第九薄膜晶体管T9的栅极与源极均电性连接于第M+1条时钟信号CK(M+1),漏极电性连接于第二节点P(n);第一电容C1,所述第一电容C1的一端电性连接于第一节点Q(n),另一端电性连接于输出端G(n);第二电容C2,所述第二电容C2的一端电性连接于第二节点P(n),另一端电性连接于恒压低电位VGL。
图1所示的GOA电路既可以正向扫描也可以反向扫描,正、反向扫描的工作过程类似。请结合图1与图2,以正向扫描为例,在正向扫描时,其工作过程为:首先,第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1)均提供高电位,第一、及第五薄膜晶体管T1、T5打开,第一节点Q(n)被预充电至高电位;然后,第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1)变为低电位,第M+1条时钟信号CK(M+1)提供高电位,第一节点Q(n)因第一电容C1的存储作用保持高电位,第二薄膜晶体管T2打开,输出端G(n)输出第M+1条时钟信号CK(M+1)的高电位,并使得第一节点Q(n)被抬升至更高的电位,同时第八薄膜晶体管T8打开,第二节点P(n)被拉低至恒压低电位VGL,第六、及第七薄膜晶体管T6、T7关闭,;接下来,第M+2条时钟信号CK(M+2)与第n+1级GOA单元的输出端G(n+1)均提供高电位,第一节点Q(n)仍为高电位,第M+1条时钟信号CK(M+1)降低为低电位,输出端G(n)输出第M+1条时钟信号CK(M+1)的低电位;再接下来,第M条时钟信号CK(M)再次提供高电位,第n-1级GOA单元的输出端G(n-1)保持低电位,第一薄膜晶体管T1打开拉低第一节点Q(n)至低电位,第八薄膜晶体管T8关闭;随后,第M+1条时钟信号CK(M+1)提供高电位,第九薄膜晶体管T9打开,第二节点P(n)被充电至第M+1条时钟信号CK(M+1)的高电位,第六、及第七薄膜晶体管T6、T7打开,分别继续拉低第一节点Q(n)与输出端G(n)至恒压低电位VGL,在第二电容C2的存储作用下,第二节点P(n)持续保持高电位,第六、及第七薄膜晶体管T6、T7打开,保持第一节点Q(n)与输出端G(n)的低电位。
在上述现有的基于LTPS半导体薄膜晶体管的GOA电路中,对于任一级GOA单元,第二节点P(n)的电位和输出端G(n)的输出信号均是通过第M+1条时钟信号CK(M+1)控制的,而第一节点Q(n)通过第M条时钟信号CK(M)和第M+2条时钟信号CK(M+2)来实现充放电,这种方式会增加时钟信号的负载(Loading),且GOA电路往往采用多级连接,导致时钟信号的负载被进一步放大,会导致严重的输出延迟(Delay),进而造成GOA电路功能失效。
随着液晶显示装置的发展与普及,市场越来越要求尽量使液晶显示面板的外框窄边框化,所以为了实现窄边框设计,GOA电路在设计时也不希望有过多的薄膜晶体管。
发明内容
本发明的目的在于提供一种基于LTPS半导体薄膜晶体管的GOA电路,其时钟信号仅负责对应级GOA单元的输出,能够有效的降低时钟信号的负载,保证多级GOA单元连接后时钟信号的整体负载降低,在提升GOA电路的输出稳定性的同时兼顾窄边框设计。
为实现上述目的,本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路,包括:级联的多级GOA单元,每一级GOA单元均包括:扫描控制单元、输出单元、及节点控制单元;
设n为正整数,除第一级、第二级、倒数第二级、及最后一级GOA单元外,在第n级GOA单元中:
所述扫描控制单元包括:第一薄膜晶体管,所述第一薄膜晶体管的栅极电性连接于上两级第n-2级GOA单元的输出端,源极电性连接于正向扫描直流控制信号,漏极电性连接于第三节点;以及第三薄膜晶体管,所述第三薄膜晶体管的栅极电性连接于下两级第n+2级GOA单元的输出端,源极电性连接于反向扫描直流控制信号,漏极电性连接于第三节点;
所述输出单元包括:第二薄膜晶体管,所述第二薄膜晶体管的栅极电性连接于第一节点,源极电性连接于第M条时钟信号,漏极电性连接于输出端;以及自举电容,所述自举电容的一端电性连接于第一节点,另一端电性连接于输出端;
所述节点控制单元包括:第四薄膜晶体管,所述第四薄膜晶体管的栅极电性连接于恒压高电位,源极电性连接于第三节点,漏极电性连接于第一节点;第五薄膜晶体管,所述第五薄膜晶体管的栅极电性连接于第二节点,漏极电性连接于第三节点,源极电性连接于恒压低电位;第六薄膜晶体管,所述第六薄膜晶体管的栅极电性连接于第二节点,漏极电性连接于输出端,源极电性连接于恒压低电位;第七薄膜晶体管,所述第七薄膜晶体管的栅极电性连接于恒压高电位,源极电性连接于第四节点,漏极电性连接于第二节点;第八薄膜晶体管,所述第八薄膜晶体管的栅极电性连接于第三节点,漏极电性连接于第四节点,源极电性连接于恒压低电位;第九薄膜晶体管,所述第九薄膜晶体管的栅极与源极均电性连接于正向扫描直流控制信号,漏极电性连接于第四节点;以及第十薄膜晶体管,所述第十薄膜晶体管的栅极与源极均电性连接于反向扫描直流控制信号,漏极电性连接于第四节点;
所述正向扫描直流控制信号与反向扫描直流控制信号的电位相反。
第一节点和第二节点的电位均受正向扫描直流控制信号与反向扫描直流控制信号的控制。
在第一级GOA单元和第二级GOA单元中,所述第一薄膜晶体管的栅极均电性连接于电路起始信号。
在倒数第二级GOA单元和最后一级GOA单元中,所述第三薄膜晶体管的栅极均电性连接于电路起始信号。
所述正向扫描直流控制信号为高电位,反向扫描直流控制信号为低电位时,进行正向扫描。
所述正向扫描直流控制信号为低电位,反向扫描直流控制信号为高电位时,进行反向扫描。
所述时钟信号包括四条时钟信号:第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号。
所述薄膜晶体管均为N型低温多晶硅薄膜晶体管。
本发明的有益效果:本发明提供的一种基于LTPS半导体薄膜晶体管的GOA电路,通过正向扫描直流控制信号和反向扫描直流控制信号控制第一节点和第二节点的电位,时钟信号仅负责对应级GOA单元的输出,能够有效的降低时钟信号的负载,保证多级GOA单元连接后时钟信号的整体负载降低,提升GOA电路的输出稳定性,还可以实现GOA电路的正反向扫描,且每级GOA单元仅包括十个薄膜晶体管,有利于减少GOA电路的布局空间,实现显示装置的窄边框设计。
附图说明
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图中,
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的电路图;
图2为对应于图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时的时序图;
图3为本发明的基于LTPS半导体薄膜晶体管的GOA电路的电路图;
图4为本发明的基于LTPS半导体薄膜晶体管的GOA电路在正向扫描时的时序图;
图5为本发明的基于LTPS半导体薄膜晶体管的GOA电路在反向扫描时的时序图;
图6为本发明的基于LTPS半导体薄膜晶体管的GOA电路的第一级GOA单元的电路图;
图7为本发明的基于LTPS半导体薄膜晶体管的GOA电路的第二级GOA单元的电路图;
图8为本发明的基于LTPS半导体薄膜晶体管的GOA电路的倒数第二级GOA单元的电路图;
图9为本发明的基于LTPS半导体薄膜晶体管的GOA电路的最后一级GOA单元的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3,本发明提供一种基于LTPS半导体薄膜晶体管的GOA电路,包括:级联的多级GOA单元,每一级GOA单元均包括:扫描控制单元100、输出单元200、及节点控制单元300。
设n为正整数,除第一级、第二级、倒数第二级、及最后一级GOA单元外,在第n级GOA单元中:
所述扫描控制单元100包括:第一薄膜晶体管T1,所述第一薄膜晶体管T1的栅极电性连接于上两级第n-2级GOA单元的输出端G(n-2),源极电性连接于正向扫描直流控制信号U2D,漏极电性连接于第三节点K(n);以及第三薄膜晶体管T3,所述第三薄膜晶体管T3的栅极电性连接于下两级第n+2级GOA单元的输出端G(n+2),源极电性连接于反向扫描直流控制信号D2U,漏极电性连接于第三节点K(n);
所述输出单元200包括:第二薄膜晶体管T2,所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n),源极电性连接于第M条时钟信号CK(M),漏极电性连接于输出端G(n);以及自举电容C1,所述自举电容C1的一端电性连接于第一节点Q(n),另一端电性连接于输出端G(n);
所述节点控制单元300包括:第四薄膜晶体管T4,所述第四薄膜晶体管T4的栅极电性连接于恒压高电位VGH,源极电性连接于第三节点K(n),漏极电性连接于第一节点Q(n);第五薄膜晶体管T5,所述第五薄膜晶体管T5的栅极电性连接于第二节点P(n),漏极电性连接于第三节点K(n),源极电性连接于恒压低电位VGL;第六薄膜晶体管T6,所述第六薄膜晶体管T6的栅极电性连接于第二节点P(n),漏极电性连接于输出端G(n),源极电性连接于恒压低电位VGL;第七薄膜晶体管T7,所述第七薄膜晶体管T7的栅极电性连接于恒压高电位VGH,源极电性连接于第四节点H(n),漏极电性连接于第二节点P(n);第八薄膜晶体管T8,所述第八薄膜晶体管T8的栅极电性连接于第三节点K(n),漏极电性连接于第四节点H(n),源极电性连接于恒压低电位VGL;第九薄膜晶体管T9,所述第九薄膜晶体管T9的栅极与源极均电性连接于正向扫描直流控制信号U2D,漏极电性连接于第四节点H(n);以及第十薄膜晶体管T10,所述第十薄膜晶体管T10的栅极与源极均电性连接于反向扫描直流控制信号D2U,漏极电性连接于第四节点H(n)。
具体地,各个薄膜晶体管均为N型低温多晶硅薄膜晶体管。
特别地,请参阅图6和图7,在第一级GOA单元和第二级GOA单元中,所述第一薄膜晶体管T1的栅极均电性连接于电路起始信号STV;请参阅图8和图9,在倒数第二级GOA单元和最后一级GOA单元中,所述第三薄膜晶体管T3的栅极均电性连接于电路起始信号STV。
本发明的基于LTPS半导体薄膜晶体管的GOA电路具备正反向扫描功能。所述正向扫描直流控制信号U2D与反向扫描直流控制信号D2U的电位相反,当所述正向扫描直流控制信号U2D为高电位、反向扫描直流控制信号D2U为低电位时,GOA电路进行正向扫描;当所述正向扫描直流控制信号U2D为低电位、反向扫描直流控制信号D2U为高电位时,GOA电路进行反向扫描。
请参阅图4或图5,所述基于LTPS半导体薄膜晶体管的GOA电路包括四条时钟信号:第一条时钟信号CK(1)、第二条时钟信号CK(2)、第三条时钟信号CK(3)、及第四条时钟信号CK(4),每一条时钟信号对应一级GOA单元,例如:第一条时钟信号CK(1)接入第一级GOA单元、第二条时钟信号CK(2)接入第二级GOA单元、第三条时钟信号CK(3)接入第三级GOA单元、第四条时钟信号CK(4)接入第四级GOA单元,依次类推。该时钟信号仅用于对应的GOA单元的输出端输出。
值得一提的是,本发明的基于LTPS半导体薄膜晶体管GOA电路不论进行正向扫描还是反向扫描,所述时钟信号CK(M)仅负责对应级GOA单元的输出端G(n)输出,而第一节点Q(n)和第二节点P(n)这两个关键节点的电位均受正向扫描直流控制信号U2D与反向扫描直流控制信号D2U的控制,能够有效的降低时钟信号CK(M)的负载,保证多级GOA单元连接后时钟信号的整体负载降低,提升GOA电路的输出稳定性。
请结合图3与图4,所述正向扫描直流控制信号U2D为高电位,反向扫描直流控制信号D2U为低电位,GOA电路正向扫描,具体工作过程为:
阶段1、预充电阶段:第n-2级GOA单元的输出端G(n-2)与正向扫描直流控制信号U2D均为高电位,第一薄膜晶体管T1导通,第四薄膜晶体管T4受恒压高电位VGH控制始终处于导通状态,第一节点Q(n)被高电位的正向扫描直流控制信号U2D预充电至高电位。
阶段2、高电位输出阶段:第n-2级GOA单元的输出端G(n-2)降为低电位,第M条时钟信号CK(M)提供高电位,第一薄膜晶体管T1关闭,第一节点Q(n)在自举电容C1的存储作用下继续保持高电位,第二薄膜晶体管T2导通,第M条时钟信号CK(M)提供的高电位经由输出端G(n)输出,并使得第一节点Q(n)被抬升至更高的电位;受第一节点Q(n)控制的第八薄膜晶体管T8导通,拉低第四节点H(n)的电位至恒压低电位VGL,第七薄膜晶体管T7受恒压高电位VGH控制始终处于导通状态,拉低第二节点P(n)的电位至恒压低电位VGL,第五和第六薄膜晶体管T5、T6关闭。
阶段3、低电位输出阶段:第M条时钟信号CK(M)提供低电位,第一节点Q(n)继续保持高电位,第二薄膜晶体管T2仍导通,第M条时钟信号CK(M)提供的低电位经由输出端G(n)输出。
阶段4、第一节点下拉阶段:第n+2级GOA单元的输出端G(n+2)提供高电位,反向扫描直流控制信号D2U为低电位,第三薄膜晶体管T3导通,第四薄膜晶体管T4导通,第三节点K(n)和第一节点Q(n)的电位被低电位的反向扫描直流控制信号D2U拉低至低电位。
阶段5、第一节点与输出端下拉维持阶段:第三节点K(n)和第一节点Q(n)变为低电位后,第八薄膜晶体管T8关闭,由于正向扫描直流控制信号U2D为高电位,反向扫描直流控制信号D2U为低电位,第九薄膜晶体管T9导通,第十薄膜晶体管T10关闭,第四节点H(n)被高电位的正向扫描直流控制信号U2D充电到高电位,第七薄膜晶体管T7始终打开,第二节点P(n)被高电位的正向扫描直流控制信号U2D充电到高电位,第五和第六薄膜晶体管T5、T6导通,第一节点Q(n)及输出端G(n)均被拉低并维持在恒压低电位VGL。
请结合图3与图5,所述正向扫描直流控制信号U2D为低电位,反向扫描直流控制信号D2U为高电位,GOA电路反向扫描,具体工作过程为:
阶段1、预充电阶段:第n+2级GOA单元的输出端G(n+2)与反向扫描直流控制信号D2U均为高电位,第三薄膜晶体管T3导通,第四薄膜晶体管T4受恒压高电位VGH控制始终处于导通状态,第一节点Q(n)被高电位的反向扫描直流控制信号D2U预充电至高电位。
阶段2、高电位输出阶段:第n+2级GOA单元的输出端G(n+2)降为低电位,第M条时钟信号CK(M)提供高电位,第三薄膜晶体管T3关闭,第一节点Q(n)在自举电容C1的存储作用下保持高电位,第二薄膜晶体管T2导通,第M条时钟信号CK(M)提供的高电位经由输出端G(n)输出,并使得第一节点Q(n)被抬升至更高的电位;受第一节点Q(n)控制的第八薄膜晶体管T8导通,拉低第四节点H(n)的电位至恒压低电位VGL,第七薄膜晶体管T7受恒压高电位VGH控制始终处于导通状态,拉低第二节点P(n)的电位至恒压低电位VGL,第五和第六薄膜晶体管T5、T6关闭。
阶段3、低电位输出阶段:第M条时钟信号CK(M)提供低电位,第一节点Q(n)继续保持高电位,第二薄膜晶体管T2仍导通,第M条时钟信号CK(M)提供的低电位经由输出端G(n)输出。
阶段4、第一节点下拉阶段:第n-2级GOA单元的输出端G(n-2)提供高电位,正向扫描直流控制信号U2D为低电位,第一薄膜晶体管T1导通,第四薄膜晶体管T4导通,第三节点K(n)和第一节点Q(n)的电位被低电位的正向扫描直流控制信号U2D拉低至低电位。
阶段5、第一节点与输出端下拉维持阶段:第三节点K(n)和第一节点Q(n)变为低电位后,第八薄膜晶体管T8关闭,由于正向扫描直流控制信号U2D为低电位,反向扫描直流控制信号D2U为高电位,第九薄膜晶体管T9关闭,第十薄膜晶体管T10导通,第四节点H(n)被高电位的反向扫描直流控制信号D2U充电到高电位,第七薄膜晶体管T7始终打开,第二节点P(n)被高电位的反向扫描直流控制信号D2U充电到高电位,第五和第六薄膜晶体管T5、T6导通,第一节点Q(n)及输出端G(n)均被拉并维持在恒压低电位VGL。
值得一提的是,本发明的基于LTPS半导体薄膜晶体管的GOA电路除了能够实现正、反向扫描,有效降低时钟信号的负载外,每级GOA单元仅包含十个薄膜晶体管,有利于减少GOA电路的布局空间,实现显示装置的窄边框设计。
综上所述,本发明的基于LTPS半导体薄膜晶体管的GOA电路,通过正向扫描直流控制信号和反向扫描直流控制信号控制第一节点和第二节点的电位,时钟信号仅负责对应级GOA单元的输出,能够有效的降低时钟信号的负载,保证多级GOA单元连接后时钟信号的整体负载降低,提升GOA电路的输出稳定性,还可以实现GOA电路的正反向扫描,且每级GOA单元仅包括十个薄膜晶体管,有利于减少GOA电路的布局空间,实现显示装置的窄边框设计。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。
Claims (8)
1.一种基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,包括:级联的多级GOA单元,每一级GOA单元均包括:扫描控制单元(100)、输出单元(200)、及节点控制单元(300);
设n为正整数,除第一级、第二级、倒数第二级、及最后一级GOA单元外,在第n级GOA单元中:
所述扫描控制单元(100)包括:第一薄膜晶体管(T1),所述第一薄膜晶体管(T1)的栅极电性连接于上两级第n-2级GOA单元的输出端(G(n-2)),源极电性连接于正向扫描直流控制信号(U2D),漏极电性连接于第三节点(K(n));以及第三薄膜晶体管(T3),所述第三薄膜晶体管(T3)的栅极电性连接于下两级第n+2级GOA单元的输出端(G(n+2)),源极电性连接于反向扫描直流控制信号(D2U),漏极电性连接于第三节点(K(n));
所述输出单元(200)包括:第二薄膜晶体管(T2),所述第二薄膜晶体管(T2)的栅极电性连接于第一节点(Q(n)),源极电性连接于第M条时钟信号(CK(M)),漏极电性连接于输出端(G(n));以及自举电容(C1),所述自举电容(C1)的一端电性连接于第一节点(Q(n)),另一端电性连接于输出端(G(n));
所述节点控制单元(300)包括:第四薄膜晶体管(T4),所述第四薄膜晶体管(T4)的栅极电性连接于恒压高电位(VGH),源极电性连接于第三节点(K(n)),漏极电性连接于第一节点(Q(n));第五薄膜晶体管(T5),所述第五薄膜晶体管(T5)的栅极电性连接于第二节点(P(n)),漏极电性连接于第三节点(K(n)),源极电性连接于恒压低电位(VGL);第六薄膜晶体管(T6),所述第六薄膜晶体管(T6)的栅极电性连接于第二节点(P(n)),漏极电性连接于输出端(G(n)),源极电性连接于恒压低电位(VGL);第七薄膜晶体管(T7),所述第七薄膜晶体管(T7)的栅极电性连接于恒压高电位(VGH),源极电性连接于第四节点(H(n)),漏极电性连接于第二节点(P(n));第八薄膜晶体管(T8),所述第八薄膜晶体管(T8)的栅极电性连接于第三节点(K(n)),漏极电性连接于第四节点(H(n)),源极电性连接于恒压低电位(VGL);第九薄膜晶体管(T9),所述第九薄膜晶体管(T9)的栅极与源极均电性连接于正向扫描直流控制信号(U2D),漏极电性连接于第四节点(H(n));以及第十薄膜晶体管(T10),所述第十薄膜晶体管(T10)的栅极与源极均电性连接于反向扫描直流控制信号(D2U),漏极电性连接于第四节点(H(n));
所述正向扫描直流控制信号(U2D)与反向扫描直流控制信号(D2U)的电位相反。
2.如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,第一节点(Q(n))和第二节点(P(n))的电位均受正向扫描直流控制信号(U2D)与反向扫描直流控制信号(D2U)的控制。
3.如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,在第一级GOA单元和第二级GOA单元中,所述第一薄膜晶体管(T1)的栅极均电性连接于电路起始信号(STV)。
4.如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,在倒数第二级GOA单元和最后一级GOA单元中,所述第三薄膜晶体管(T3)的栅极均电性连接于电路起始信号(STV)。
5.如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,所述正向扫描直流控制信号(U2D)为高电位,反向扫描直流控制信号(D2U)为低电位时,进行正向扫描。
6.如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,所述正向扫描直流控制信号(U2D)为低电位,反向扫描直流控制信号(D2U)为高电位时,进行反向扫描。
7.如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,所述时钟信号包括四条时钟信号:第一条时钟信号(CK(1))、第二条时钟信号(CK(2))、第三条时钟信号(CK(3))、及第四条时钟信号(CK(4))。
8.如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路,其特征在于,所述薄膜晶体管均为N型低温多晶硅薄膜晶体管。
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