WO2017092116A1 - 降低馈通电压的goa电路 - Google Patents

降低馈通电压的goa电路 Download PDF

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Publication number
WO2017092116A1
WO2017092116A1 PCT/CN2015/099280 CN2015099280W WO2017092116A1 WO 2017092116 A1 WO2017092116 A1 WO 2017092116A1 CN 2015099280 W CN2015099280 W CN 2015099280W WO 2017092116 A1 WO2017092116 A1 WO 2017092116A1
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Prior art keywords
thin film
electrically connected
film transistor
clock signal
drain
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PCT/CN2015/099280
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English (en)
French (fr)
Inventor
龚强
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武汉华星光电技术有限公司
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Priority to US14/908,128 priority Critical patent/US9875706B1/en
Publication of WO2017092116A1 publication Critical patent/WO2017092116A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit that reduces a feedthrough voltage.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • GOA technology (Gate Driver on Array) is an array substrate row driving technology.
  • the original array process of the liquid crystal display panel is used to fabricate a horizontal scanning line driving circuit on a substrate around the display area, so that it can replace the external integrated circuit board (Integrated Circuit, IC) to complete the horizontal scan line drive.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • Figure 1 shows a conventional GOA circuit, including a cascade of multiple GOA units.
  • n be a positive integer
  • the nth stage GOA unit includes: a first thin film transistor T1, the gate of the first thin film transistor T1 is electrically connected to the forward scan control signal U2D, and the source is electrically connected to the upper level
  • the output terminal G(n-1) of the n-1 stage GOA unit is electrically connected to the source of the third thin film transistor T3; the second thin film transistor T2 is electrically connected to the gate of the second thin film transistor T2.
  • the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage, and the drain is electrically connected to the source of the third thin film transistor T3;
  • the third thin film transistor T3 has a gate electrically connected to the first clock signal CK(1), a drain electrically connected to the gate of the fourth thin film transistor T4, and a fourth thin film transistor T4.
  • the gate of the fourth thin film transistor T4 is electrically connected to the source of the seventh thin film transistor T7, the drain is electrically connected to the second node P(n), and the source is electrically connected to the first clock signal CK ( 1); a fifth thin film transistor T5, the gate of the fifth thin film transistor T5 is electrically connected to the first clock signal CK(1), and the drain is electrically connected In the second node P(n), the source is electrically connected to the constant voltage high potential VGH; the sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is electrically connected to the second node P(n), the source The gate of the seventh thin film transistor T7 is electrically connected to the drain of the seventh thin film transistor T7, the drain is electrically connected to the constant voltage low potential VGL, and the gate of the seventh thin film transistor T7 is electrically connected to the second clock.
  • the source is electrically connected to the source of the eighth thin film transistor T8;
  • the eighth thin film transistor T8 the gate of the eighth thin film transistor T8 is electrically connected to the constant voltage high potential VGH, the drain is electrically connected to the first node Q(n); the ninth thin film transistor T9, the ninth thin film
  • the gate of the transistor T9 is electrically connected to the first node Q(n)
  • the source is electrically connected to the second clock signal CK(2)
  • the drain is electrically connected to the output terminal G(n)
  • the tenth thin film transistor is electrically connected.
  • the gate of the tenth thin film transistor T10 is electrically connected to the second node P(n), the drain is electrically connected to the output terminal G(n), and the source is electrically connected to the constant voltage low potential VGL; a capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q(n), the other end is electrically connected to the output terminal G(n), and the second capacitor C2 is at one end of the second capacitor C2. It is electrically connected to the second node P(n), and the other end is electrically connected to the constant voltage low potential VGL.
  • the first thin film transistor T1 and the second thin film transistor T2 constitute a forward and reverse scan control unit 100 of the GOA circuit;
  • the ninth thin film transistor T9 and the first capacitor C1 constitute a pull-up output unit 200 of the GOA circuit, and are used for Outputting the high potential of the second clock signal CK(2) to the output terminal G(n), the high potential of the second clock signal CK(2) is equal to the constant voltage high potential VGH;
  • sixth, seventh, And the eighth thin film transistors T6, T7, T8 constitute a first node pull-down unit 300 of the GOA circuit;
  • the fourth thin film transistor T4, the fifth thin film transistor T5, the tenth thin film transistor T10, and the second capacitor C2 form a pull-down output of the GOA circuit
  • the unit 400 is configured to output the output terminal G(n) to a low potential equal to the constant voltage low potential VGL.
  • the signal outputted by the output terminal G(n) of the GOA circuit (shown as G(1)-G(4) in FIG. 2) is a pulse signal having only one falling edge, that is, from a constant voltage high potential VGH. Directly reduce to constant voltage low potential VGL.
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) Then connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • Applying sufficient voltage on the horizontal scanning line will cause all TFTs electrically connected to the horizontal scanning line to be turned on, so that the signal voltage on the data line can be written into the pixel, and the transmittance of different liquid crystals can be controlled to achieve control color. With the effect of brightness.
  • the gate of the TFT is turned off.
  • some external integrated circuits for gate driving are capable of outputting an output signal waveform having two falling edges to reduce the feedthrough voltage, but are not applicable to the GOA circuit.
  • the above conventional GOA circuit shown in FIG. 1 can only output an output signal having a falling edge, and the gate of the TFT is directly reduced to a constant voltage low potential by a constant voltage high potential VGH before and after the gate is closed.
  • VGL cannot reduce the feedthrough voltage when the pixel is charged, which is not conducive to improving the display uniformity of the liquid crystal panel.
  • the output of the GOA circuit is capable of outputting a waveform signal having two falling edges, thereby reducing the feedthrough voltage and improving the display uniformity of the liquid crystal panel.
  • the present invention provides a GOA circuit for reducing a feedthrough voltage, comprising a plurality of cascaded GOA units, each stage of the GOA unit comprising: a forward and reverse scan control unit, a pull-up output unit, and a first a node pull-down unit, a pull-down output unit, and a third thin film transistor;
  • n be a positive integer, in addition to the first and last level of the GOA unit, in the nth level GOA unit:
  • the forward and reverse scan control unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to a forward scan control signal, and a source is electrically connected to the upper n-1th GOA unit An output of the drain is electrically connected to the source of the third thin film transistor; and a second thin film transistor, the gate of the second thin film transistor is electrically connected to the reverse scan control signal, and the source is electrically connected to the lower The output of the first n+1th GOA unit;
  • the gate of the third thin film transistor is electrically connected to the Mth clock signal, the source is electrically connected to the drain of the first thin film transistor and the drain of the second thin film transistor, and the drain is electrically connected to the fourth thin film.
  • the gate of the transistor is electrically connected to the Mth clock signal, the source is electrically connected to the drain of the first thin film transistor and the drain of the second thin film transistor, and the drain is electrically connected to the fourth thin film.
  • the pull-up output unit includes: a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the first node, the source is electrically connected to the M+1th clock signal, and the drain is electrically connected to the drain An output end; and a first capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the pull-down output unit includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to a drain of the third thin film transistor, a drain is electrically connected to the second node, and a source is electrically connected to the first a clock signal of the fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the Mth clock signal, the drain is electrically connected to the second node, and the source is electrically connected to the constant voltage high potential; a tenth thin film transistor, the gate of the tenth thin film transistor is electrically connected to the second node, the drain is electrically connected to the output end, the source is electrically connected to the constant voltage low potential; and the eleventh thin film transistor is The gate of the eleventh thin film transistor is electrically connected to the output control signal, the drain is electrically connected to the output end, the source is electrically connected to one end of the first resistor, and the first resistor is electrically connected to the other end of the first resistor. Connected to the constant voltage low potential;
  • the first node pull-down unit includes: a sixth thin film transistor, a gate of the sixth thin film transistor is electrically connected to the second node, and a source is electrically connected to a drain of the seventh thin film transistor, and the drain is electrically connected a constant voltage low potential; a seventh thin film transistor, the gate of the seventh thin film transistor is electrically connected to the M+1th clock signal, and the source is electrically connected to the drain of the third thin film transistor, and the drain is electrically a gate connected to the sixth thin film transistor; and an eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to a constant voltage high potential, and the source is electrically connected to the drain and drain of the third thin film transistor Electrically connected to the first node;
  • the output control signal is a pulse signal, and its period is 1/2 of a clock signal period;
  • the signal waveform output by the output has two falling edges.
  • the source of the first thin film transistor is electrically connected to the circuit start signal.
  • the source of the second thin film transistor is electrically connected to the circuit start signal.
  • the GOA circuit When the forward scan control signal provides a high potential, the reverse scan control signal provides a low potential, the GOA circuit performs a forward scan; when the forward scan control signal provides a low potential, and the reverse scan control signal provides a high potential, The GOA circuit performs a reverse scan.
  • the clock signal includes two clock signals: a first clock signal and a second clock signal; when the Mth clock signal is the first clock signal, the M+1th clock signal is the second a clock signal; when the Mth clock signal is the second clock signal, the M+1th clock signal is the first clock signal.
  • a rising edge of the output control signal is generated in a high potential phase of the M+1th clock signal, and a falling edge is generated simultaneously with a falling edge of the M+1th clock signal.
  • the high potential of the M+1th clock signal is the same as the potential of the constant voltage high potential.
  • the potential of the first falling edge of the signal waveform outputted by the output terminal falls between a constant voltage high potential and a constant voltage low potential.
  • the thin film transistors are all N-type low temperature polysilicon semiconductor thin film transistors.
  • the present invention also provides a GOA circuit for reducing a feedthrough voltage, comprising a plurality of cascaded GOA units, each stage GOA unit comprising: a forward and reverse scan control unit, a pull-up output unit, a first node pull-down unit, and a pull-down An output unit, and a third thin film transistor;
  • n be a positive integer, in addition to the first and last level of the GOA unit, in the nth level GOA unit:
  • the forward and reverse scan control unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to a forward scan control signal, and a source is electrically connected to the upper n-1th GOA unit An output of the drain is electrically connected to the source of the third thin film transistor; and a second thin film transistor, the gate of the second thin film transistor is electrically connected to the reverse scan control signal, and the source is electrically connected to the lower An output end of the first n+1th GOA unit, the drain is electrically connected to the source of the third thin film transistor;
  • the gate of the third thin film transistor is electrically connected to the Mth clock signal, the source is electrically connected to the drain of the first thin film transistor and the drain of the second thin film transistor, and the drain is electrically connected to the fourth thin film.
  • the gate of the transistor is electrically connected to the Mth clock signal, the source is electrically connected to the drain of the first thin film transistor and the drain of the second thin film transistor, and the drain is electrically connected to the fourth thin film.
  • the pull-up output unit includes: a ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected to the first node, the source is electrically connected to the M+1th clock signal, and the drain is electrically connected to the drain An output end; and a first capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the pull-down output unit includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to a drain of the third thin film transistor, a drain is electrically connected to the second node, and a source is electrically connected to the first a clock signal of the fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the Mth clock signal, the drain is electrically connected to the second node, and the source is electrically connected to the constant voltage high potential; a tenth thin film transistor, the gate of the tenth thin film transistor is electrically connected to the second node, the drain is electrically connected to the output end, the source is electrically connected to the constant voltage low potential; and the eleventh thin film transistor is The gate of the eleventh thin film transistor is electrically connected to the output control signal, the drain is electrically connected to the output end, the source is electrically connected to one end of the first resistor, and the first resistor is electrically connected to the other end of the first resistor. Connected to the constant voltage low potential;
  • the first node pull-down unit includes: a sixth thin film transistor, a gate of the sixth thin film transistor is electrically connected to the second node, and a source is electrically connected to a drain of the seventh thin film transistor, and the drain is electrically connected a constant voltage low potential; a seventh thin film transistor, the gate of the seventh thin film transistor is electrically connected to the M+1th clock signal, and the source is electrically connected to the drain of the third thin film transistor, and the drain is electrically Connected to the source of the sixth thin film transistor; and the eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to the constant voltage high potential source electrically connected to the drain of the third thin film transistor, and the drain is electrically Sexually connected to the first node;
  • the output control signal is a pulse signal, and its period is 1/2 of a clock signal period;
  • the signal waveform outputted by the output has two falling edges
  • the source of the first thin film transistor is electrically connected to the circuit start signal
  • the source of the second thin film transistor is electrically connected to the circuit start signal
  • the GOA circuit when the forward scan control signal provides a high potential and the reverse scan control signal provides a low potential, the GOA circuit performs a forward scan; when the forward scan control signal provides a low potential, the reverse scan control signal provides a high potential The GOA circuit performs a reverse scan.
  • the invention provides a GOA circuit for reducing the feedthrough voltage, and adding an eleventh thin film transistor and a first resistor connected in series with the eleventh thin film transistor in the pull-down output unit, in the output process of the GOA circuit
  • the eleventh thin film transistor is turned on by the added output control signal, and the voltage division effect of the first resistor is used to generate a falling edge of the signal waveform outputted by the output terminal, that is, the signal waveform outputted by the output terminal has two falling edges.
  • the voltage difference before and after the gate of the TFT in the pixel is turned off can be reduced, thereby reducing the feedthrough voltage and improving the display uniformity of the liquid crystal panel.
  • Figure 1 shows a conventional GOA circuit
  • FIG. 2 is a timing diagram of the GOA circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of a GOA circuit for reducing a feedthrough voltage according to the present invention.
  • FIG. 4 is a circuit diagram of a first stage GOA unit of a GOA circuit for reducing a feedthrough voltage according to the present invention
  • FIG. 5 is a circuit diagram of a final stage GOA unit of a GOA circuit for reducing a feedthrough voltage according to the present invention
  • FIG. 6 is a timing chart of forward scanning of the GOA circuit for reducing the feedthrough voltage of the present invention.
  • the present invention first provides a GOA circuit for reducing a feedthrough voltage, including a plurality of cascaded GOA units, each of which includes: a forward and reverse scan control unit 100, and a pull-up output.
  • n be a positive integer, in addition to the first and last level of the GOA unit, in the nth level GOA unit:
  • the forward-reverse scan control unit 100 includes a first thin film transistor T1.
  • the gate of the first thin film transistor T1 is electrically connected to the forward scan control signal U2D, and the source is electrically connected to the first n-th.
  • the output terminal G(n-1) of the first-stage GOA unit is electrically connected to the source of the third thin film transistor T3; and the second thin film transistor T2 is electrically connected to the gate of the second thin film transistor T2.
  • the reverse scan control signal D2U the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage, and the drain is electrically connected to the source of the third thin film transistor T3;
  • the pull-up output unit 200 includes a ninth thin film transistor T9.
  • the gate of the ninth thin film transistor T9 is electrically connected to the first node Q(n), and the source is electrically connected to the M+1th clock signal.
  • CK(M+1) the drain is electrically connected to the output terminal G(n); and the first capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q(n), and the other end is electrically Connected to the output terminal G(n);
  • the pull-down output unit 400 includes a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the drain of the third thin film transistor T3, and the drain is electrically connected to the second node P(n).
  • the source is electrically connected to the Mth clock signal CK(M); the fifth thin film transistor T5, the gate of the fifth thin film transistor T5 is electrically connected to the Mth clock signal CK(M), and the drain is electrically Connected to the second node P(n), the source is electrically connected to the constant voltage high potential (VGH);
  • the tenth thin film transistor T10, the gate of the tenth thin film transistor T10 is electrically connected to the second node P ( n), the drain is electrically connected to the output terminal G(n), the source is electrically connected to the constant voltage low potential VGL; the eleventh thin film transistor T11, the gate of the eleventh thin film transistor T11 is electrically connected to The output control signal CKF is electrically connected to the output terminal G(n), the
  • the first node pull-down unit 300 includes a sixth thin film transistor T6.
  • the gate of the sixth thin film transistor T6 is electrically connected to the second node P(n), and the source is electrically connected to the seventh thin film transistor T7.
  • the drain and the drain are electrically connected to the constant voltage low potential VGL; the seventh thin film transistor T7, the gate of the seventh thin film transistor T7 is electrically connected to the M+1th clock signal CK(M+1), the source
  • the gate is electrically connected to the source of the third thin film transistor T3, the drain is electrically connected to the source of the sixth thin film transistor T6, and the eighth thin film transistor T8 is electrically connected to the gate of the eighth thin film transistor T8.
  • the constant voltage high potential VGH is electrically connected to the drain of the third thin film transistor T3, and the drain is electrically connected to the first node Q(n).
  • the GOA circuit of the present invention enables the signal waveform output from the output terminal G(n) to have two falling edges.
  • the source of the first thin film transistor T1 is electrically connected to the circuit start signal STV; in the last stage GOA unit, The source of the second thin film transistor T2 is electrically connected to the circuit start signal STV.
  • each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor.
  • the clock signal includes two clock signals: a first clock signal CK(1) and a second clock signal CK(2); when the Mth clock signal CK(M) is the first clock signal CK ( 1), the M+1th clock signal CK(M+1) is the second clock signal CK(2); when the Mth clock signal CK(M) is the second clock signal CK ( 2), the M+1th clock signal CK(M+1) is the first clock signal CK(1).
  • the output control signal CKF is a pulse signal whose period is 1/2 of the period of the clock signal. In one cycle of the output control signal CKF, a rising edge of the output control signal CKF is generated in a high potential phase of the M+1th clock signal CK(M+1), a falling edge and the M+1th clock The falling edge of the signal CK(M+1) is generated simultaneously.
  • the high potential of the M+1th clock signal CK(M+1) is the same as the potential of the constant voltage high potential VGH.
  • the potential of the first falling edge of the signal waveform outputted by the output terminal G(n) drops to between the constant voltage high potential VGH and the constant voltage bit VGL, and the potential of the second falling edge falls to the constant voltage bit VGL In this way, the voltage difference before and after the gate of the TFT in the pixel is turned off can be reduced, thereby reducing the feedthrough voltage and improving the display uniformity of the liquid crystal panel.
  • the potential dropped to the first falling edge of the signal waveform outputted from the output terminal G(n) by adjusting the channel width to length ratio (W/L) of the eleventh thin film transistor T11 and the resistance of the first resistor R1.
  • the GOA circuit of the present invention for reducing the feedthrough voltage can realize both forward scanning and reverse scanning.
  • the forward scan control signal U2D provides a high potential
  • the reverse scan control signal D2U provides a low potential
  • the forward scan control signal U2D provides a low potential
  • the reverse scan control signal D2U provides a high potential.
  • the reverse scan process is similar to the forward scan, except that the scan direction is different.
  • the forward scan is sequentially scanned from the first-level GOA unit to the last-level GOA unit, and the reverse scan is sequentially scanned from the last-level GOA unit. To the first level GOA unit.
  • the output terminal G(n-1) and the Mth clock signal CK(M) of the first stage, the n-1th stage GOA unit provide a high potential, and the output control signal CKF and the M+1th clock signal CK (M) +1) providing a low potential, the first, third, and fifth thin film transistors T1, T3, and T5 are turned on, and the eighth thin film transistor T8 is always turned on by the constant voltage high potential VGH, the second, seventh, and The eleven thin film transistors T2, T7, T11 are turned off, the first node Q(n) is charged to a high potential, and is controlled by the first node Q(n).
  • the fourth thin film transistor T4 is turned on, the second node P(n) is charged to a high potential, the tenth thin film transistor T10 is turned on, and the output terminal G(n) outputs a constant voltage low potential VGL.
  • the output terminal G(n-1) and the Mth clock signal CK(M) of the second stage, the n-1th stage GOA unit are turned into a low potential, and the M+1th clock signal CK(M+1) is provided high.
  • the potential, the output control signal CKF provides a low potential
  • the third and fifth thin film transistors T3, T5 are turned off
  • the seventh thin film transistor T7 is turned on
  • the first node Q(n) is kept high by the action of the first capacitor C1
  • the four thin film transistors T4 are still turned on, pulling down the potential of the second node P(n) to a low potential
  • the sixth and tenth thin film transistors T6 and T10 are turned off, and the ninth thin film transistor T9 is still turned on, and the output terminal G(n) Outputting a high potential of the M+1th clock signal CK(M+1), that is, a high potential equal to the constant voltage high potential VGH;
  • the waveform outputted by the output terminal G(n) drops for the first time to form a first falling edge, and the falling edge
  • the potential drops between the constant voltage high potential VGH and the constant voltage low potential VGL, and can be controlled by adjusting the channel width to length ratio of the eleventh thin film transistor T11 and the resistance of the first resistor R1.
  • the fourth stage and the Mth clock signal CK(M) again provide a high potential
  • the output terminal G(n-1) of the n-1th stage GOA unit, the output control signal CKF, and the M+1th clock signal CK ( M+1) provides a low potential
  • the third and fifth thin film transistors T3, T5 are turned on
  • the second node P(n) is charged to a high potential
  • the first node Q(n) is lowered to a low potential
  • ninth, tenth A thin film transistor T9, T11 is turned off
  • the tenth thin film transistor T10 is turned on
  • the output terminal G(n) outputs a constant voltage low potential VGL to form a second falling edge.
  • the action remains high, and the sixth, seventh, and tenth thin film transistors T6, T7, and T10 are both turned on to maintain the low potential of the first node Q(n) and the output terminal G(n).
  • V is the feedthrough voltage
  • Vgd is the capacitance between the gate and the drain of the thin film transistor in the pixel
  • Clc is the liquid crystal capacitance of the pixel
  • Cst is the storage capacitance of the pixel
  • Vg1 is the gate before the gate of the thin film transistor in the pixel is turned off
  • the gate voltage that is, the voltage at the output of the GOA circuit, is a constant voltage high potential VGH for the conventional GOA circuit shown in FIG. 1, and the signal waveform of the output (G(n)) output for the GOA circuit of the present invention.
  • the first falling edge of the falling edge is at the constant voltage high potential
  • VGH the constant voltage low potential
  • VGL the potential between VGH and the constant voltage low potential VGL
  • Vg2 is the gate voltage after the gate of the thin film transistor in the pixel is turned off
  • the conventional GOA circuit shown in FIG. 1 and the GOA circuit of the present invention are both constant voltage and low potential VGL.
  • the GOA circuit of the present invention reduces the difference between Vg1 and Vg2. According to the above formula (1), the difference between Vg1 and Vg2 is lowered, and the feedthrough voltage is also lowered.
  • the GOA circuit for reducing the feedthrough voltage of the present invention adds an eleventh thin film transistor and a first resistor in series with the eleventh thin film transistor in the pull-down output unit, and is added in the output process of the GOA circuit.
  • the output control signal turns on the eleventh thin film transistor, and the voltage division effect of the first resistor is used to generate a falling edge of the signal waveform outputted from the output end, that is, the signal waveform outputted by the output terminal has two falling edges, which can be reduced.
  • the voltage difference before and after the gate of the TFT in the pixel is turned off, thereby reducing the feedthrough voltage and improving the display uniformity of the liquid crystal panel.

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Abstract

一种降低馈通电压的GOA电路，在下拉输出单元(400)中增设第十一薄膜晶体管(T11)及与第十一薄膜晶体管(T11)串联的第一电阻(R1)，在GOA电路的输出过程中，通过增设的输出控制信号(CKF)导通第十一薄膜晶体管(T11)，利用第一电阻(R1)的分压作用，使得输出端(G(n))输出的信号波形多产生一个下降沿，即输出端(G(n))输出的信号波形具有两个下降沿，能够减小像素内TFT的栅极关闭前后的电压差，从而降低馈通电压，提升液晶面板的显示均一性。

Description

降低馈通电压的GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种降低馈通电压的GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板(Integrated Circuit，IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
图1所示为现有的一种常见的GOA电路，包括级联的多个GOA单元。设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于正向扫描控制信号U2D，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三薄膜晶体管T3的源极；第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于反向扫描控制信号D2U，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第三薄膜晶体管T3的源极；第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于第1条时钟信号CK(1)，漏极电性连接于第四薄膜晶体管T4的栅极；第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第七薄膜晶体管T7的源极，漏极电性连接于第二节点P(n)，源极电性连接于第1条时钟信号CK(1)；第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于第1条时钟信号CK(1)，漏极电性连接于第二节点P(n)，源极电性连接于恒压高电位VGH；第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第二节点P(n)，源极电性连接于第七薄膜晶体管T7的漏极，漏极电性连接于恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第2条时钟信号CK(2)，源极电性连接于第八薄膜晶体管T8的源极；第 八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于恒压高电位VGH，漏极电性连接于第一节点Q(n)；第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于第一节点Q(n)，源极电性连接于第2条时钟信号CK(2)，漏极电性连接于输出端G(n)；第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极电性连接于第二节点P(n)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第一电容C1，所述第一电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；第二电容C2，所述第二电容C2的一端电性连接于第二节点P(n)，另一端电性连接于恒压低电位VGL。
进一步地，所述第一薄膜晶体管T1与第二薄膜晶体管T2组成GOA电路的正反向扫描控制单元100；第九薄膜晶体管T9与第一电容C1组成GOA电路的上拉输出单元200，用于将第二条时钟信号CK(2)的高电位输出至输出端G(n)，所述第二条时钟信号CK(2)的高电位与恒压高电位VGH相等；第六、第七、及第八薄膜晶体管T6、T7、T8组成GOA电路的第一节点下拉单元300；第四薄膜晶体管T4、第五薄膜晶体管T5、第十薄膜晶体管T10、及第二电容C2组成GOA电路的下拉输出单元400，用于使输出端G(n)输出与恒压低电位VGL相等的低电位。结合图2，上述GOA电路的输出端G(n)输出的信号(如图2中G(1)-G(4)所示)为只有一个下降沿的脉冲信号，即从恒压高电位VGH直接降低至恒压低电位VGL。
通常液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度从而达到控制色彩与亮度的效果。在给像素充电后，TFT的栅极关闭，在TFT的栅极关闭的瞬间会因为栅极与漏极的电容耦合发生馈通(Feed through)现象，导致像素中充入的电压与数据线上的电压有差异，TFT的栅极关闭前后的电压差越大引发的馈通电压越大，虽然可以调整公共电极电压来补偿这个差异，但是在制程出现偏差时，馈通电压越大，制程偏差导致的公共电压不均就会越明显，所以降低像素充电时的馈通电压对提升液晶面板的显示均一性有很大意义。目前，部分用于栅极驱动的外接集成电路(Gate IC)能够输出具有两个下降沿的输出信号波形，以降低馈通电压，但对于GOA电路并不适用。上述如图1所示的现有的GOA电路，只能输出具有一个下降沿的输出信号，TFT的栅极关闭前后由恒压高电位VGH直接降低至恒压低电位 VGL，不能降低像素充电时的馈通电压，不利于提升液晶面板的显示均一性。
发明内容
本发明的目的在于提供一种降低馈通电压的GOA电路，该GOA电路的输出端能够输出具有两个下降沿的波形信号，从而降低馈通电压，提升液晶面板的显示均一性。
为实现上述目的，本发明提供了一种降低馈通电压的GOA电路，包括级联的多个GOA单元，每一级GOA单元均包括：正反向扫描控制单元、上拉输出单元、第一节点下拉单元、下拉输出单元、及第三薄膜晶体管；
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描控制信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三薄膜晶体管的源极；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于反向扫描控制信号，源极电性连接于下一级第n+1级GOA单元的输出端；
所述第三薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于第一薄膜晶体管的漏极与第二薄膜晶体管的漏极，漏极电性连接于第四薄膜晶体管的栅极；
所述上拉输出单元包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述下拉输出单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第二节点，源极电性连接于第M条时钟信号；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第M条时钟信号，漏极电性连接于第二节点，源极电性连接于恒压高电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于输出控制信号，漏极电性连接于输出端，源极电性连接于第一电阻的一端；第一电阻，所述第一电阻的另一端电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
所述第一节点下拉单元包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第七薄膜晶体管的漏极，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第六薄膜晶体管的源极；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第一节点；
所述输出控制信号为脉冲信号，其周期是时钟信号周期的1/2；
所述输出端输出的信号波形具有两个下降沿。
在第一级GOA单元中，所述第一薄膜晶体管的源极电性连接于电路起始信号。
在最后一级GOA单元中，所述第二薄膜晶体管的源极电性连接于电路起始信号。
当正向扫描控制信号提供高电位，反向扫描控制信号提供低电位时，所述GOA电路进行正向扫描；当正向扫描控制信号提供低电位，反向扫描控制信号提供高电位时，所述GOA电路进行反向扫描。
所述时钟信号包括两条时钟信号：第一条时钟信号和第二条时钟信号；当所述第M条时钟信号为第一条时钟信号时，所述第M+1条时钟信号为第二条时钟信号；当所述第M条时钟信号为第二条时钟信号时，所述第M+1条时钟信号为第一条时钟信号。
在所述输出控制信号的一个周期内，输出控制信号的上升沿产生于第M+1条时钟信号的高电位阶段，下降沿与所述第M+1条时钟信号的下降沿同时产生。
所述第M+1条时钟信号的高电位与恒压高电位的电位相同。
所述输出端输出的信号波形的第一个下降沿的电位下降至介于恒压高电位与恒压低电位之间。
通过调节第十一薄膜晶体管的沟道宽长比和第一电阻的阻值控制输出端输出的信号波形的第一个下降沿下降至的电位。
所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
本发明还提供一种降低馈通电压的GOA电路，包括级联的多个GOA单元，每一级GOA单元均包括：正反向扫描控制单元、上拉输出单元、第一节点下拉单元、下拉输出单元、及第三薄膜晶体管；
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描控制信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三薄膜晶体管的源极；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于反向扫描控制信号，源极电性连接于下一级第n+1级GOA单元的输出端，漏极电性连接于第三薄膜晶体管的源极；
所述第三薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于第一薄膜晶体管的漏极与第二薄膜晶体管的漏极，漏极电性连接于第四薄膜晶体管的栅极；
所述上拉输出单元包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述下拉输出单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第二节点，源极电性连接于第M条时钟信号；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第M条时钟信号，漏极电性连接于第二节点，源极电性连接于恒压高电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于输出控制信号，漏极电性连接于输出端，源极电性连接于第一电阻的一端；第一电阻，所述第一电阻的另一端电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
所述第一节点下拉单元包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第七薄膜晶体管的漏极，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第六薄膜晶体管的源极；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于恒压高电位源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第一节点；
所述输出控制信号为脉冲信号，其周期是时钟信号周期的1/2；
所述输出端输出的信号波形具有两个下降沿；
其中，在第一级GOA单元中，所述第一薄膜晶体管的源极电性连接于电路起始信号；
其中，在最后一级GOA单元中，所述第二薄膜晶体管的源极电性连接于电路起始信号；
其中，当正向扫描控制信号提供高电位，反向扫描控制信号提供低电位时，所述GOA电路进行正向扫描；当正向扫描控制信号提供低电位，反向扫描控制信号提供高电位时，所述GOA电路进行反向扫描。
本发明的有益效果：本发明提供的一种降低馈通电压的GOA电路，在下拉输出单元中增设第十一薄膜晶体管及与第十一薄膜晶体管串联的第一电阻，在GOA电路的输出过程中，通过增设的输出控制信号导通第十一薄膜晶体管，利用第一电阻的分压作用，使得输出端输出的信号波形多产生一个下降沿，即输出端输出的信号波形具有两个下降沿，能够减小像素内TFT的栅极关闭前后的电压差，从而降低馈通电压，提升液晶面板的显示均一性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种常见的GOA电路；
图2为图1所示GOA电路的时序图；
图3为本发明的降低馈通电压的GOA电路的电路图；
图4为本发明的降低馈通电压的GOA电路的第一级GOA单元的电路图；
图5为本发明的降低馈通电压的GOA电路的最后一级GOA单元的电路图；
图6为本发明的降低馈通电压的GOA电路的正向扫描时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图3与图6，本发明首先提供一种降低馈通电压的GOA电路，包括级联的多个GOA单元，每一GOA单元均包括：正反向扫描控制单元100、上拉输出单元200、第一节点下拉单元300、下拉输出单元400、及第三薄膜晶体管T3。
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
所述正反向扫描控制单元100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于正向扫描控制信号U2D，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三薄膜晶体管T3的源极；以及第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于反向扫描控制信号D2U，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第三薄膜晶体管T3的源极；
所述上拉输出单元200包括：第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于第一节点Q(n)，源极电性连接于第M+1条时钟信号CK(M+1)，漏极电性连接于输出端G(n)；以及第一电容C1，所述第一电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；
所述下拉输出单元400包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第三薄膜晶体管T3的漏极，漏极电性连接于第二节点P(n)，源极电性连接于第M条时钟信号CK(M)；第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于第M条时钟信号CK(M)，漏极电性连接于第二节点P(n)，源极电性连接于恒压高电位(VGH)；第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极电性连接于第二节点P(n)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极电性连接于输出控制信号CKF，漏极电性连接于输出端G(n)，源极电性连接于第一电阻R1的一端；第一电阻R1，所述第一电阻R1的另一端电性连接于恒压低电位VGL；以及第二电容C2，所述第二电容C2的一端电性连接于第二节点P(n)，另一端电性连接于恒压低电位VGL；
所述第一节点下拉单元300包括：第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第二节点P(n)，源极电性连接于第七薄膜晶体管T7的漏极，漏极电性连接于恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第M+1条时钟信号CK(M+1)，源极电性连接于第三薄膜晶体管T3的源极，漏极电性连接于第六薄膜晶体管T6的源极；以及第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于恒压高电位VGH，源极电性连接于第三薄膜晶体管T3的漏极，漏极电性连接于第一节点Q(n)。
如图6所示，本发明的GOA电路能够使输出端G(n)输出的信号波形具有两个下降沿。
特别地，请分别参阅图4和图5，在第一级GOA单元中，所述第一薄膜晶体管T1的源极电性连接于电路起始信号STV；在最后一级GOA单元中，所述第二薄膜晶体管T2的源极电性连接于电路起始信号STV。
具体地，各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
所述时钟信号包括两条时钟信号：第一条时钟信号CK(1)和第二条时钟信号CK(2)；当所述第M条时钟信号CK(M)为第一条时钟信号CK(1)时，所述第M+1条时钟信号CK(M+1)为第二条时钟信号CK(2)；当所述第M条时钟信号CK(M)为第二条时钟信号CK(2)时，所述第M+1条时钟信号CK(M+1)为第一条时钟信号CK(1)。
所述输出控制信号CKF为脉冲信号，其周期是时钟信号周期的1/2。在所述输出控制信号CKF的一个周期内，输出控制信号CKF的上升沿产生于第M+1条时钟信号CK(M+1)的高电位阶段，下降沿与所述第M+1条时钟信号CK(M+1)的下降沿同时产生。
进一步地，所述第M+1条时钟信号CK(M+1)的高电位与恒压高电位VGH的电位相同。所述输出端G(n)输出的信号波形的第一个下降沿的电位下降至介于恒压高电位VGH与恒压电位VGL之间，第二个下降沿的电位下降至恒压电位VGL，这样能够减小像素内TFT的栅极关闭前后的电压差，从而降低馈通电压，提升液晶面板的显示均一性。可通过调节第十一薄膜晶体管T11的沟道宽长比(W/L)和第一电阻R1的阻值控制输出端G(n)输出的信号波形的第一个下降沿下降至的电位。
值得一提的是，本发明的降低馈通电压的GOA电路既可以实现正向扫描，也可以实现反向扫描。正向扫描时，正向扫描控制信号U2D提供高电位，反向扫描控制信号D2U提供低电位；反向扫描时，正向扫描控制信号U2D提供低电位，反向扫描控制信号D2U提供高电位。反向扫描的过程与正向扫描类似，只是扫描方向不同，正向扫描是从第一级GOA单元开始依次扫描至最后一级GOA单元，而反向扫描是从最后一级GOA单元开始依次扫描至第一级GOA单元。
下面以正向扫描为例，说明本发明的降低馈通电压的GOA电路工作过程：
第一阶段、第n-1级GOA单元的输出端G(n-1)及第M条时钟信号CK(M)提供高电位，输出控制信号CKF、及第M+1条时钟信号CK(M+1)提供低电位，第一、第三、及第五薄膜晶体管T1、T3、T5导通，第八薄膜晶体管T8受恒压高电位VGH控制始终导通，第二、第七、及第十一薄膜晶体管T2、T7、T11截止，第一节点Q(n)充电至高电位，受第一节点Q(n)控制的 第四薄膜晶体管T4导通，第二节点P(n)充电至高电位，第十薄膜晶体管T10导通，输出端G(n)输出恒压低电位VGL。
第二阶段、第n-1级GOA单元的输出端G(n-1)及第M条时钟信号CK(M)转变为低电位，第M+1条时钟信号CK(M+1)提供高电位，输出控制信号CKF、提供低电位，第三、第五薄膜晶体管T3、T5截止，第七薄膜晶体管T7导通，第一节点Q(n)受第一电容C1的作用保持高电位，第四薄膜晶体管T4仍导通，拉低第二节点P(n)的电位至低电位，第六、及第十薄膜晶体管T6、T10截止，第九薄膜晶体管T9仍导通，输出端G(n)输出第M+1条时钟信号CK(M+1)的高电位，即等于恒压高电位VGH的高电位；
第三阶段、第M+1条时钟信号CK(M+1)及输出控制信号CKF均提供高电位，第n-1级GOA及第M条时钟信号CK(M)均提供低电位，第十一薄膜晶体管T11受输出控制信号CKF的控制导通，在第一电阻R1的分压作用下，输出端G(n)输出的波形第一次下降，形成第一个下降沿，该下降沿的电位下降至介于恒压高电位VGH与恒压低电位VGL之间，可通过调节第十一薄膜晶体管T11的沟道宽长比和第一电阻R1的阻值来控制。
第四阶段、第M条时钟信号CK(M)再次提供高电位，第n-1级GOA单元的输出端G(n-1)、输出控制信号CKF、及第M+1条时钟信号CK(M+1)提供低电位，第三、及第五薄膜晶体管T3、T5导通，第二节点P(n)充电至高电位，第一节点Q(n)降低为低电位，第九、第十一薄膜晶体管T9、T11均截止、第十薄膜晶体管T10导通，输出端G(n)输出恒压低电位VGL，形成第二个下降沿。
第五阶段、第M+1条时钟信号CK(M+1)再次提供高电位，第n-1级GOA单元的输出端G(n-1)、输出控制信号CKF、及第M条时钟信号CK(M)提供低电位，第三、第四、第五、第九、第十一薄膜晶体管T3、T4、T5、T9、T11均截止，第二节点P(n)受第二电容C2的作用保持高电位，第六、第七、第十薄膜晶体管T6、T7、T10均导通，维持第一节点Q(n)、及输出端G(n)的低电位。
已知馈通电压的计算公式为：V＝Cgd×(Vg1-Vg2)/(Cgs+Clc+Cst)(1)
其中，V为馈通电压，Vgd是像素中薄膜晶体管的栅极与漏极间的电容，Clc是像素的液晶电容，Cst是像素的存储电容；Vg1是像素中薄膜晶体管的栅极关闭之前的栅极电压，即GOA电路输出端的电压，针对于图1所示的现有GOA电路为恒压高电位VGH，而针对于本发明的GOA电路为输出端(G(n))输出的信号波形的第一个下降沿所下降至的界于恒压高电位 VGH与恒压低电位VGL之间的电位；Vg2是像素中薄膜晶体管的栅极关闭之后的栅极电压，针对图1所示的现有GOA电路及本发明的GOA电路均为恒压低电位VGL。与现有技术相比，本发明的GOA电路使得Vg1与Vg2之间的差值降低，根据上述公式(1)可知，Vg1与Vg2之间的差值降低，馈通电压也随之降低。
综上所述，本发明的降低馈通电压的GOA电路，在下拉输出单元中增设第十一薄膜晶体管及与第十一薄膜晶体管串联的第一电阻，在GOA电路的输出过程中，通过增设的输出控制信号导通第十一薄膜晶体管，利用第一电阻的分压作用，使得输出端输出的信号波形多产生一个下降沿，即输出端输出的信号波形具有两个下降沿，能够减小像素内TFT的栅极关闭前后的电压差，从而降低馈通电压，提升液晶面板的显示均一性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (17)

  1. 一种降低馈通电压的GOA电路，包括级联的多个GOA单元，每一级GOA单元均包括：正反向扫描控制单元、上拉输出单元、第一节点下拉单元、下拉输出单元、及第三薄膜晶体管；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描控制信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三薄膜晶体管的源极；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于反向扫描控制信号，源极电性连接于下一级第n+1级GOA单元的输出端，漏极电性连接于第三薄膜晶体管的源极；
    所述第三薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于第一薄膜晶体管的漏极与第二薄膜晶体管的漏极，漏极电性连接于第四薄膜晶体管的栅极；
    所述上拉输出单元包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述下拉输出单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第二节点，源极电性连接于第M条时钟信号；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第M条时钟信号，漏极电性连接于第二节点，源极电性连接于恒压高电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于输出控制信号，漏极电性连接于输出端，源极电性连接于第一电阻的一端；第一电阻，所述第一电阻的另一端电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
    所述第一节点下拉单元包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第七薄膜晶体管的漏极，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极 电性连接于第M+1条时钟信号，源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第六薄膜晶体管的源极；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于恒压高电位源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第一节点；
    所述输出控制信号为脉冲信号，其周期是时钟信号周期的1/2；
    所述输出端输出的信号波形具有两个下降沿。
  2. 如权利要求1所述的降低馈通电压的GOA电路，其中，在第一级GOA单元中，所述第一薄膜晶体管的源极电性连接于电路起始信号。
  3. 如权利要求1所述的降低馈通电压的GOA电路，其中，在最后一级GOA单元中，所述第二薄膜晶体管的源极电性连接于电路起始信号。
  4. 如权利要求1所述的降低馈通电压的GOA电路，其中，当正向扫描控制信号提供高电位，反向扫描控制信号提供低电位时，所述GOA电路进行正向扫描；当正向扫描控制信号提供低电位，反向扫描控制信号提供高电位时，所述GOA电路进行反向扫描。
  5. 如权利要求1所述的降低馈通电压的GOA电路，其中，所述时钟信号包括两条时钟信号：第一条时钟信号和第二条时钟信号；当所述第M条时钟信号为第一条时钟信号时，所述第M+1条时钟信号为第二条时钟信号；当所述第M条时钟信号为第二条时钟信号时，所述第M+1条时钟信号为第一条时钟信号。
  6. 如权利要求1所述的降低馈通电压的GOA电路，其中，在所述输出控制信号的一个周期内，输出控制信号的上升沿产生于第M+1条时钟信号的高电位阶段，下降沿与所述第M+1条时钟信号的下降沿同时产生。
  7. 如权利要求1所述的降低馈通电压的GOA电路，其中，所述第M+1条时钟信号的高电位与恒压高电位的电位相同。
  8. 如权利要求7所述的降低馈通电压的GOA电路，其中，所述输出端输出的信号波形的第一个下降沿的电位下降至介于恒压高电位与恒压低电位之间。
  9. 如权利要求8所述的降低馈通电压的GOA电路，其中，通过调节第十一薄膜晶体管的沟道宽长比和第一电阻的阻值控制输出端输出的信号波形的第一个下降沿下降至的电位。
  10. 如权利要求1所述的降低馈通电压的GOA电路，其中，所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
  11. 一种降低馈通电压的GOA电路，包括级联的多个GOA单元，每一级GOA单元均包括：正反向扫描控制单元、上拉输出单元、第一节点下 拉单元、下拉输出单元、及第三薄膜晶体管；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描控制信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三薄膜晶体管的源极；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于反向扫描控制信号，源极电性连接于下一级第n+1级GOA单元的输出端，漏极电性连接于第三薄膜晶体管的源极；
    所述第三薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于第一薄膜晶体管的漏极与第二薄膜晶体管的漏极，漏极电性连接于第四薄膜晶体管的栅极；
    所述上拉输出单元包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述下拉输出单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第二节点，源极电性连接于第M条时钟信号；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第M条时钟信号，漏极电性连接于第二节点，源极电性连接于恒压高电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于输出控制信号，漏极电性连接于输出端，源极电性连接于第一电阻的一端；第一电阻，所述第一电阻的另一端电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
    所述第一节点下拉单元包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第七薄膜晶体管的漏极，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第六薄膜晶体管的源极；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于恒压高电位源极电性连接于第三薄膜晶体管的漏极，漏极电性连接于第一节点；
    所述输出控制信号为脉冲信号，其周期是时钟信号周期的1/2；
    所述输出端输出的信号波形具有两个下降沿；
    其中，在第一级GOA单元中，所述第一薄膜晶体管的源极电性连接于电路起始信号；
    其中，在最后一级GOA单元中，所述第二薄膜晶体管的源极电性连接于电路起始信号；
    其中，当正向扫描控制信号提供高电位，反向扫描控制信号提供低电位时，所述GOA电路进行正向扫描；当正向扫描控制信号提供低电位，反向扫描控制信号提供高电位时，所述GOA电路进行反向扫描。
  12. 如权利要求11所述的降低馈通电压的GOA电路，其中，所述时钟信号包括两条时钟信号：第一条时钟信号和第二条时钟信号；当所述第M条时钟信号为第一条时钟信号时，所述第M+1条时钟信号为第二条时钟信号；当所述第M条时钟信号为第二条时钟信号时，所述第M+1条时钟信号为第一条时钟信号。
  13. 如权利要求11所述的降低馈通电压的GOA电路，其中，在所述输出控制信号的一个周期内，输出控制信号的上升沿产生于第M+1条时钟信号的高电位阶段，下降沿与所述第M+1条时钟信号的下降沿同时产生。
  14. 如权利要求11所述的降低馈通电压的GOA电路，其中，所述第M+1条时钟信号的高电位与恒压高电位的电位相同。
  15. 如权利要求14所述的降低馈通电压的GOA电路，其中，所述输出端输出的信号波形的第一个下降沿的电位下降至介于恒压高电位与恒压低电位之间。
  16. 如权利要求15所述的降低馈通电压的GOA电路，其中，通过调节第十一薄膜晶体管的沟道宽长比和第一电阻的阻值控制输出端输出的信号波形的第一个下降沿下降至的电位。
  17. 如权利要求11所述的降低馈通电压的GOA电路，其中，所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
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US20110157124A1 (en) * 2009-12-30 2011-06-30 Sanghoon Jung Shift register and display device using the same
CN103137061A (zh) * 2013-02-18 2013-06-05 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104103244A (zh) * 2013-04-03 2014-10-15 瀚宇彩晶股份有限公司 液晶显示器及其双向移位暂存装置
CN103714792A (zh) * 2013-12-20 2014-04-09 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路

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