WO2016161727A1 - 移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板 - Google Patents

移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板 Download PDF

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Publication number
WO2016161727A1
WO2016161727A1 PCT/CN2015/085996 CN2015085996W WO2016161727A1 WO 2016161727 A1 WO2016161727 A1 WO 2016161727A1 CN 2015085996 W CN2015085996 W CN 2015085996W WO 2016161727 A1 WO2016161727 A1 WO 2016161727A1
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Prior art keywords
pull
node
module
square wave
output
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PCT/CN2015/085996
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English (en)
French (fr)
Inventor
王峥
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US14/913,315 priority Critical patent/US10037741B2/en
Publication of WO2016161727A1 publication Critical patent/WO2016161727A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of liquid crystal display driving technologies, and in particular, to a shift register unit and a driving method thereof, an array substrate gate driving device, and a display panel.
  • VDD is a DC high voltage
  • the eighth thin film transistor M8 is always in an on state due to the high voltage of VDD, so that the PD point of the pull-down node is high.
  • Level Therefore, when the PD is in the high level state, the sixth thin film transistor M6 and the fourth thin film transistor M4 are in an on state. Only when the pull-up node PU point is at a high level, the ninth thin film transistor M9 is turned on, causing the PD point to be low, so that the sixth thin film transistor M6 and the fourth thin film transistor M4 connected to the pull-down node are turned off. .
  • the gates of the sixth thin film transistor M6 and the fourth thin film transistor M4 connected to the pull-down node are at a high level for a long time, that is, It is a state of high duty cycle, which affects the service life of the thin film transistor.
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, an array substrate gate driving device, and a display panel for reducing a duty ratio of a thin film transistor connected to a pull-down node, thereby preventing aging of a thin film transistor Increase the service life of thin film transistors.
  • An embodiment of the present disclosure provides a shift register unit, including: an input module, an output module, a reset module, a function module, a first pull-down module, and a second pull-down module; wherein the control end of the first pull-down module a pull-down node is connected, the first input end is connected to the first square wave signal, the second input end is connected to the second square wave signal, the first output end is connected to the pull-up node, and the second output end is connected to the output terminal;
  • the control terminal and the second of the two pull-down modules The pull-down node is connected, the first input end is connected to the second square wave signal, the second input end is connected to the first square wave signal, the first output end is connected to the pull-up node, and the second output end is connected to the output terminal
  • the first pull-down node is a first output node of the function module
  • the second pull-down node is a second output node of the function module
  • the pull-up node is an output node of the
  • the first pull-down module is configured to: provide a low level of the second square wave signal to the pull-up node and the output terminal in response to the high level of the first square wave signal and the high level signal of the first pull-down node;
  • the second pull-down module is configured to: provide a low level of the first square wave signal to the pull-up node and the output terminal in response to the high level of the second square wave signal and the high level signal of the second pull-down node;
  • the second square wave signal when the first square wave signal is at a high level, the second square wave signal is at a low level, and when the first square wave signal is at a low level, the second square wave signal is at a high level.
  • An advantage of the shift register unit provided by the embodiment of the present disclosure is that when the first pull-down module is responsive to a high level of the first square wave signal and a high level signal of the first pull-down node, the first pull-down is connected The thin film transistor of the node is turned on, thereby reducing the duty ratio of the thin film transistor connected to the second pull-down node; when the second pull-down module is responsive to the high level of the second square wave signal and the high level signal of the second pull-down node The thin film transistor connected to the second pull-down node is turned on, thereby reducing the duty ratio of the thin film transistor connected at the first pull-down node.
  • the input end and the control end of the input module are connected to an input signal, and the output end is a pull-up node.
  • the input module is configured to provide an input signal to the pull up node in response to the input signal.
  • control end of the output module is connected to the output end of the input module, the input end thereof is connected to the clock signal, and the output end thereof is connected to the output terminal.
  • the output module is configured to provide a clock signal voltage to the output terminal in response to the pull-up node voltage signal.
  • control end of the reset module is connected to the reset signal, and the input end thereof is connected to the negative pole of the power source, the first output end thereof is connected to the pull-up node, and the second output end thereof is connected to the output terminal.
  • the reset module is configured to: respond to the reset signal, The source negative voltage is supplied to the pull-up node and the output terminal.
  • control end of the function module is connected to the pull-up node, and the input end thereof is connected to the negative pole of the power source, the first output end is connected to the first pull-down node, and the second output end thereof is connected to the second output terminal.
  • the drop-down nodes are connected.
  • the functional module is configured to provide a negative supply voltage to the first pulldown node and the second pulldown node in response to the pull up node voltage signal.
  • the input module comprises: a first thin film transistor having a gate and a source connected to the input signal end, and a drain serving as an output node of the input module, ie, a pull-up node.
  • the output module comprises: a second thin film transistor having a gate connected to the pull-up node, a source connected to the clock signal input end, and a drain connected to the output terminal; and a first capacitor connected to the pull-up node and the output terminal between.
  • the reset module includes: a third thin film transistor having a gate connected to the reset signal input end, a source connected to the negative voltage terminal of the power supply, and a drain connected to the pull-up node; and a fourth thin film transistor having a gate connected to the reset signal At the input end, the source is connected to the negative voltage terminal of the power supply, and the drain is connected to the output terminal.
  • the functional module includes: a fifth thin film transistor having a gate connected to the pull-up node, a source connected to the negative voltage terminal of the power supply, and a drain serving as a first output node of the functional module, ie, a first pull-down node;
  • the sixth thin film transistor has a gate connected to the pull-up node, a source connected to the first pull-down node, and a drain as a second output node of the function module, that is, a second pull-down node.
  • the first pull-down module includes: a seventh thin film transistor having a gate and a source connected to the first square wave signal input end, a drain connected to the first pull-down node, and an eighth thin film transistor having a gate Connecting the first pull-down node, the source is connected to the second square wave signal input end, and the drain is connected to the output terminal; the ninth thin film transistor has a gate connected to the first pull-down node, and a source connected to the second square wave signal input end, The drain is connected to the pull-up node; the second capacitor is connected between the first pull-down node and the second square wave signal input terminal; and the third capacitor is connected in parallel with the second capacitor.
  • the second pull-down module includes: a tenth thin film transistor having a gate and a source connected to the second square wave signal input end, a drain connected to the second pull-down node, and an eleventh thin film transistor having a gate connection a second pull-down node, the source is connected to the first square wave signal input end, the drain is connected to the output terminal; the twelfth thin film transistor has a gate connected to the second pull-down node, the source is connected to the first square wave signal input end, and the drain is connected Connecting a pull-up node; a fourth capacitor connected between the second pull-down node and the first square wave signal input end; a fifth capacitor, wherein Four capacitors are connected in parallel.
  • the first pull-down module and the second pull-down module provided in the embodiments of the present disclosure enable the first pull-down module to work and the second pull-down module to stop working at the same time, thereby reducing the connection in the second pull-down module in the second Pulling down the duty cycle of the thin film transistor of the node, or the second pull-down module is working and the first pull-down module is stopped, thereby reducing the duty ratio of the thin film transistor connected to the first pull-down node in the first pull-down module.
  • the thin film transistor connected at the first pull-down node and the thin film transistor connected to the second pull-down node are alternately turned on, thereby reducing connection at the first pull-down node
  • the duty ratio of the thin film transistor and the thin film transistor connected to the second pull-down node prevents aging of the thin film transistor and increases the life of the thin film transistor.
  • An embodiment of the present disclosure further provides a driving method of a shift register unit, the method comprising:
  • the input module provides the input signal voltage to the pull-up node when receiving the input signal
  • the output module After receiving the voltage signal of the pull-up node, the output module supplies the clock signal voltage to the output terminal;
  • the reset module supplies the negative voltage of the power supply to the pull-up node and the output terminal when receiving the reset signal
  • the function module After receiving the voltage signal of the pull-up node, the function module provides the negative voltage of the power supply to the first pull-down node and the second pull-down node;
  • the first pull-down module After receiving the high level of the first square wave signal and the high level signal of the first pull-down node, the first pull-down module supplies the low level of the second square wave signal to the pull-up node and the output terminal;
  • the second pull-down module After receiving the high level of the second square wave signal and the high level signal of the second pull-down node, the second pull-down module supplies the low level of the first square wave signal to the pull-up node and the output terminal;
  • the first pull-down node is a first output node of the function module
  • the second pull-down node is a second output node of the function module
  • the pull-up node is an output node of the input module
  • the second square wave signal when the first square wave signal is at a high level, the second square wave signal is at a low level, and when the first square wave signal is at a low level, the second square wave signal is at a high level.
  • the first pull-down module and the second pull-down module provided in the embodiments of the present disclosure enable the first pull-down module to work and the second pull-down module to stop working at the same time, thereby reducing the connection in the second pull-down module in the second Dropping the duty cycle of the thin film transistor of the node, or the second pull-down module works and the first pull-down module stops working, thereby lowering the first pull-down module The duty cycle of the thin film transistor connected in the first pull-down node.
  • the thin film transistor connected at the first pull-down node and the thin film transistor connected to the second pull-down node are alternately turned on, thereby reducing connection at the first pull-down node
  • the duty ratio of the thin film transistor and the thin film transistor connected to the second pull-down node prevents aging of the thin film transistor and increases the life of the thin film transistor.
  • Embodiments of the present disclosure provide an array substrate gate driving apparatus including a cascade of any of the shift register units as provided by embodiments of the present disclosure.
  • Embodiments of the present disclosure provide a display panel including an array substrate gate driving device provided by an embodiment of the present disclosure.
  • 1 is a schematic structural diagram of a shift register unit provided by the prior art
  • FIG. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of a square wave signal according to an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of a control signal of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of another control signal of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of an array substrate gate driving device according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register unit and a driving method, an array substrate gate driving device, and a display panel for reducing a duty ratio of a thin film transistor connected to a pull-down node, thereby preventing aging of the thin film transistor. Increase the life of thin film transistors.
  • the clock signal provided in the embodiment of the present disclosure includes the prior art.
  • Clock signals CLK and CLKB are composed of a plurality of cascaded shift register units, and the array substrate gate driver structure includes a plurality of rows of shift register units, each row including a shift register unit.
  • the clock signal input to the shift register unit corresponding to each odd row is CLK
  • the clock signal input to the shift register unit corresponding to each even row is CLKB.
  • the voltage VSS provided by the negative electrode of the power supply is a low level
  • the thin film transistor TFTs in the embodiments of the present disclosure may both be N-type TFTs, or may be P-type TFTs, or the thin film transistor TFTs in the embodiment. It is a combination of an N-type TFT and a P-type TFT.
  • the thin film transistor TFTs are all N-type TFTs as an example, and the TFTs are turned on when the gate voltages of all the TFTs are at a high level, and the TFTs are turned off at a low level.
  • the shift register unit in the embodiment of the present disclosure is an improvement over the shift register unit under the amorphous silicon process provided in the prior art.
  • An embodiment of the present disclosure provides a square wave signal for providing to a pull-down unit, wherein the square wave signal includes a first square wave signal and a second square wave signal, and the first square wave signal and the second square wave signal are A square wave with a frequency of 1HZ to 3HZ repeatedly switching between high and low levels.
  • an embodiment of the present disclosure provides a shift register unit, including: an input module 201, an output module 202, a reset module 203, a function module 204, a first pull-down module 205, and a second pull-down module 206.
  • the input end and the control end of the input module 201 are connected to the input signal INPUT, and the output end thereof is connected to the PU point of the pull-up node; the control end of the output module 202 is connected to the output end of the input module 201, and the input end thereof is connected to the clock signal CLK.
  • the output end is connected to the output terminal OUTPUT; the control end of the reset module 203 is connected to the reset signal RESET, the input end thereof is connected to the power supply negative pole VSS, the first output end is connected to the pull-up node PU point, and the second output end and the output thereof are connected.
  • the terminal OUTPUT is connected; the control end of the function module 204 is connected to the PU point of the pull-up node, the input end thereof is connected to the power supply negative pole VSS, the first output end is connected to the first pull-down node PD1, and the second output end is connected to the second pull-down node.
  • the node PD2 is connected to the first pull-down node PD1, and the first input end is connected to the first square wave signal VLL1, and the second input end is connected to the second square wave signal VLL2.
  • the first output end is connected to the pull-up node PU point, the second output end is connected to the output terminal OUTPUT;
  • the control end of the second pull-down module 206 is connected to the second pull-down node PD2 point, and the first input end thereof is VLL2
  • two square wave signal is connected to a second input terminal connected to the first party VLL1 wave signal, a first output terminal coupled to pull-up node PU point, a second input and output terminal
  • the terminal OUTPUT is connected.
  • control terminal of each module is connected to the gate of the thin film transistor, the input end is connected to the source of the thin film transistor, and the output end is connected to the drain of the thin film transistor.
  • control terminal of each module is connected to the gate of the thin film transistor, the input end is connected to the drain of the thin film transistor, and the output end is connected to the source of the thin film transistor, which is not limited in the embodiment of the present disclosure.
  • the input module 201 is configured to provide an input signal INPUT to the pull-up node PU point in response to the input signal INPUT, wherein the pull-up node PU point is an output node of the input module 201.
  • the input module may include a first thin film transistor M1 having a gate and a source connected to the input signal terminal INPUT and a drain serving as an output node of the input module, that is, as a pull-up node PU point.
  • the output module 202 is configured to provide a clock signal voltage CLK to the output terminal OUTPUT in response to a voltage signal of the pull-up node PU point.
  • the output module includes: a second thin film transistor M2 having a gate connected to the pull-up node PU point, a source connected to the clock signal input terminal CLK, and a drain connected to the output terminal OUTPUT; and a first capacitor C1 connected to the pull-up node PU Between the point and the output terminal OUTPUT.
  • the reset module 203 is configured to provide the power supply negative voltage VSS to the pull-up node PU point and the output terminal OUTPUT in response to the reset signal RESET.
  • the reset module includes: a third thin film transistor M3 having a gate connected to the reset signal input terminal RESET, a source connected to the power supply negative voltage terminal VSS, a drain connected to the pull-up node PU point, and a drain of the third thin film transistor M3 as a drain a first output terminal of the reset module 203; a fourth thin film transistor M4 having a gate connected to the reset signal input terminal RESET, a source connected to the power supply negative voltage terminal VSS, a drain connected to the output terminal OUTPUT, and a drain of the fourth thin film transistor M4 As the second output of the reset module 203.
  • the function module 204 is configured to provide the power supply negative voltage VSS to the first pull-down node PD1 and the second pull-down node PD2 in response to the pull-up node PU point voltage signal, wherein the first pull-down node PD1 is the function module 204 The first output node, the second pull-down node PD2 is the second output node of the function module 204.
  • the function module includes: a fifth thin film transistor MS, the gate is connected to the pull-up node PU point, the source is connected to the power supply negative voltage terminal VSS, and the drain is the first output node of the function module, that is, the first pull-down node PD1;
  • the sixth thin film transistor M6 has a gate connected to the pull-up node PU point, a source connected to the first pull-down node PD1, and a drain as a second output node of the function module, that is, the second pull-down node PD2.
  • the first pull-down module 205 is configured to: provide a low level of the second square wave signal VLL2 to the pull-up node in response to the high level of the first square wave signal VLL1 and the PD1 high level signal of the first pull-down node PU point and output terminal OUTPUT.
  • the first pull-down module includes: a seventh thin film transistor M7 having a gate and a source connected to the first square wave signal input terminal VLL1, a drain connected to the first pull-down node PD1, and a source of the seventh thin film transistor M7 being the first a first input end of the pull-down module 205; an eighth thin film transistor M8 having a gate connected to the first pull-down node PD1, a source connected to the second square wave signal input terminal VLL2, a drain connected to the output terminal OUTPUT, and an eighth film
  • the drain of the transistor M8 is the second output end of the first pull-down module 205;
  • the ninth thin film transistor M9 has a gate connected to the first pull-down node PD1, a source connected to the second square wave signal input terminal VLL2, and a drain connection Pulling the node PU point, and the source of the ninth thin film transistor M9 is the second input end of the first pull-down module 205, the drain is the first output end of the first pull-down module
  • the second pull-down module 206 is configured to: provide a low level of the first square wave signal VLL1 to the pull-up node PU and in response to the high level of the second pull-down node voltage signal PD2 and the second square wave signal VLL2 high level Output terminal OUTPUT.
  • the second pull-down module includes: a tenth thin film transistor M10, whose gate and source are connected to the second square wave signal input terminal VLL2, the drain is connected to the second pull-down node PD2, and the source of the tenth thin film transistor M10 is the second pull-down module.
  • the first input end of the eleventh thin film transistor M11 has a gate connected to the second pull-down node PD2, a source connected to the first square wave signal input terminal VLL1, a drain connected to the output terminal OUTPUT, and an eleventh thin film transistor M11
  • the drain is the second output of the second pull-down module 206
  • the twelfth thin film transistor M12 has a gate connected to the second pull-down node PD2, a source connected to the first square wave signal input terminal VLL1, and a drain connected to the pull-up node PU Point
  • the source of the twelfth thin film transistor M12 is the second input end of the second pull-down module 206
  • the drain is the first output end of the second pull-down module 206
  • the fourth capacitor C4 is connected to the second pull-down node PD2 and the The first wave signal is input between the terminals VLL1;
  • the fifth capacitor C5 is connected in parallel with the fourth capacitor C4.
  • the first pull-down module and the second pull-down module provided in the embodiment of the present disclosure enable the first pull-down module to work at the same time, and the second pull-down module stops working, thereby reducing the connection in the second pull-down module in the second
  • the alternate operation of the second pull-down module causes the thin film transistor connected to the first pull-down node and the thin film transistor connected to the second pull-down node to be alternately turned on, thereby reducing the thin film transistor connected to the first pull-down node and connecting the second
  • the duty cycle of the thin film transistor of the pull-down node prevents the aging of the thin film transistor, thereby increasing the service life of the thin film transistor.
  • the first square wave signal when the first square wave signal is at a high level, the first pull-down module operates, the first pull-down node is at a high level, and the thin film transistor connected to the first pull-down node is turned on, and the second party is The low level of the wave signal is introduced to the pull-up node and the output terminal, because the second pull-down node is low, the second pull-down module stops working, and the thin film transistor connected at the second pull-down node is turned off, thereby reducing the connection at the The duty ratio of the thin film transistor of the second pull-down node; when the second square wave signal is high level, the second pull-down module operates, the second pull-down module is high level, and the thin film transistor connected to the second pull-down node is turned on, The low level of the first square wave signal is introduced to the pull-up node and the output terminal.
  • the first pull-down node is at a low level, the first pull-down module stops working, and the thin film transistor connected at the first pull-down node is turned off. Thereby, the duty ratio of the thin film transistor connected to the first pull-down node is lowered.
  • the first pull-down module and the second pull-down module alternately work, the thin film transistor connected to the first pull-down node and the thin film transistor connected to the second pull-down node are alternately turned on, thereby reducing the connection.
  • the duty ratio of the thin film transistor of the first pull-down node and the thin film transistor connected to the second pull-down node prevents the aging of the thin film transistor and improves the service life of the thin film transistor.
  • the square wave signal provided by the embodiment of the present disclosure includes a first square wave signal VLL1 and a second square wave signal VLL2, and the high and low level switching periods of VLL1 and VLL2 may be about 0.3 s to 1 s.
  • the switching direction of the first square wave signal VLL1 and the second square wave signal VLL2 in the same period of time is opposite, and the low level of the square wave signal is higher than the power source negative voltage VSS and lower than the thin film transistor turn-on voltage.
  • the switching period of the clock signal CLK or CLKB in the shift register unit is about 16 ⁇ s. Obviously, the switching frequency of the square wave signal is much smaller than the switching frequency of the clock signal.
  • FIG. 3 is a waveform diagram of a first square wave signal VLL1 and a second square wave signal VLL2 waveform, and clock signals CLK and CLKB in the embodiment of the present disclosure. Obviously, in the plurality of periods of the clock signals CLK and CLKB, neither the first square wave signal nor the second square wave signal changes in high and low levels.
  • the high and low level switching periods of the first square wave signal VLL1 and the second square wave signal VLL2 provided in the embodiments of the present disclosure may be different from the level of the clock signal CLK.
  • the level switching period is the same or different.
  • the embodiment of the present disclosure does not specifically limit the first square wave signal VLL1 and the second square wave signal VLL2.
  • the first pull-down module and the second pull-down module provided according to an embodiment of the present disclosure can be lowered in the first Pulling the thin film transistor of the node and the duty ratio of the thin film transistor connected to the second pull-down node, thereby preventing aging of the thin film transistor, thereby increasing the service life of the thin film transistor.
  • the first pull-down module when the first square wave signal is at a high level, the first pull-down module operates, and when the second square wave signal is at a high level, the second pull-down module operates, so that the first pull-down module and the second pull-down module alternate Working, thereby reducing the duty ratio of the thin film transistor connected to the first pull-down node and the thin film transistor connected to the second pull-down node, thereby preventing aging of the thin film transistor and increasing the service life of the thin film transistor.
  • the input module provides the input signal voltage to the pull-up node when receiving the input signal
  • the output module After receiving the voltage signal of the pull-up node, the output module supplies the clock signal voltage to the output terminal;
  • the reset module supplies the negative voltage of the power supply to the pull-up node and the output terminal when receiving the reset signal
  • the function module After receiving the voltage signal of the pull-up node, the function module provides the negative voltage of the power supply to the first pull-down node and the second pull-down node;
  • the first pull-down module After receiving the high level of the first square wave signal and the high level signal of the first pull-down node, the first pull-down module supplies the low level of the second square wave signal to the pull-up node and the output terminal;
  • the second pull-down module After receiving the high level of the second square wave signal and the high level signal of the second pull-down node, the second pull-down module supplies the low level of the first square wave signal to the pull-up node and the output terminal;
  • the first pull-down node is a first output node of the function module
  • the second pull-down node is a second output node of the function module
  • the pull-up node is an output node of the input module
  • the second square wave signal when the first square wave signal is at a high level, the second square wave signal is at a low level, and when the first square wave signal is at a low level, the second square wave signal is at a high level.
  • the shift register provided by the embodiment of the present disclosure is described in detail by taking the clock input signal of the shift register unit as CLK, the first square wave signal VLL1 as a high level, and the second square wave signal VLL2 as a low level.
  • CLK clock input signal of the shift register unit
  • VLL1 first square wave signal
  • VLL2 second square wave signal
  • the input signal INPUT is at a high level
  • the clock signal CLK is at a low level
  • the reset signal RESET is at a low level.
  • the first thin film transistor M1 is turned on, and the PU node of the pull-up node is at a high level.
  • the first capacitor C1 is charged;
  • the fifth thin film transistor M5 is turned on, the power supply negative voltage VSS is introduced to the first pull-down node PD1, the first pull-down node PD1 is at a low level;
  • the sixth thin film transistor M6 is turned on, and the power supply negative is introduced.
  • the voltage VSS is given to the second pull-down node PD2, and the second pull-down node PD2 is at a low level; because the first square wave signal VLL1 is at a high level, the second square wave signal VLL2 is at a low level, and the seventh thin film transistor M7 is turned on,
  • the high level of the first square wave signal VLL1 is introduced to the first pull-down node PD1, but since the voltage of the power source negative voltage VSS is lower than the low level of the square wave signal, and the low level of the power source negative voltage VSS is pulled low
  • the effect is greater than the high level pulling action of the first square wave signal VLL1, so even if the high level of the first square wave signal VLL1 is introduced to the first pull-down node PD1, since the fifth thin film transistor M5 is turned on, the power is introduced.
  • the negative voltage VSS is given to the first pull-down node PD1, such that The first pull-down node PD1 continues to be low level; at the same time, the high level of the first square wave signal VLL1 in the second pull-down module charges the fourth capacitor C4 and the fifth capacitor C5, so that the first square wave signal VLL1
  • the high level cannot be introduced to the second pull-down node PD2, so that the eleventh thin film transistor M11 and the twelfth thin film transistor M12 connected to the second pull-down node PD2 are turned off, and the thin film transistor connected to the second pull-down node PD2 is reduced.
  • the duty ratio of the second thin film transistor M2 is turned on, the low level of the clock signal CLK is introduced to the output terminal OUTPUT, and the output terminal OUTPUT is outputted to the low level.
  • the input signal INPUT is low level
  • the clock signal CLK is high level
  • the reset signal RESET is low level.
  • the first thin film transistor M1 is turned off, because the first capacitor C1 is discharged, and the PU point continues.
  • the second thin film transistor is continuously turned on, and the high level of the clock signal CLK is introduced to the output terminal OUTPUT, and the output terminal OUTPUT is outputted to the high level.
  • the input signal INPUT is low level
  • the clock signal CLK is low level
  • the reset signal RESET is high level.
  • the third thin film transistor M3 is turned on, and the power supply negative voltage VSS is introduced to the pull-up node PU point.
  • the PU point is low level; the fourth thin film transistor M4 is turned on, the power supply negative voltage VSS is introduced to the output terminal OUTPUT, and the output terminal OUTPUT is low level; because the PU point is low level, the fifth thin film transistor M5 is turned off; Since the first square wave signal VLL1 is at a high level, the seventh thin film transistor M7 is continuously turned on because the fifth thin film transistor M5 is turned off, so that the voltage of the first pull-down node PD1 is only affected by the first square wave signal VLL1.
  • the first pull-down node PD1 is at a high level
  • the eighth thin film transistor M8 is turned on
  • the low level of the second square wave signal VLL2 is introduced to the output terminal OUTPUT
  • the ninth thin film transistor M9 is turned on, introducing the second party
  • the low level of the wave signal VLL2 is given to the pull-up node PU point; since the PU point is low, the sixth thin film transistor M6 is turned off, and the second pull-down node PD2 is kept low.
  • the input signal INPUT is low level
  • the clock signal CLK is high level
  • the reset signal RESET is low level.
  • the third thin film transistor M3 and the fourth thin film transistor M4 are turned off, in order to make the pull-up
  • the node PU point and the output terminal OUTPUT are at a low level, and are implemented only by the action of the first pull-down module and the second pull-down module. Because the first square wave signal VLL1 is at a high level, the seventh thin film transistor M7 is continuously turned on, the first pull-down node PD1 continues to be at a high level, and the eighth thin film transistor M8 is turned on to introduce a second square wave signal VLL2.
  • the low level is given to the output terminal OUTPUT, and the ninth thin film transistor M9 is turned on, and the low level of the second square wave signal VLL2 is introduced to the PU point of the pull-up node. Therefore, in the fourth stage t4, the output terminal OUTPUT outputs a low level.
  • the input signal INPUT is low level
  • the clock signal CLK is low level
  • the reset signal RESET is low level.
  • the seventh thin film transistor M7 is continuously turned on, and the first pull-down node PD1 continues to be high.
  • the eighth thin film transistor M8 is turned on, introducing a low level of the second square wave signal VLL2 to the output terminal OUTPUT
  • the ninth thin film transistor M9 is turned on, introducing a low level of the second square wave signal VLL2 to the pull-up node
  • the PU point is low. Therefore, in the fourth stage t4, the output terminal OUTPUT outputs a low level.
  • the operations of the fourth phase t4 and the fifth phase t5 are repeated until the timings of the first phase t1, the second phase t2, and the third phase t3 appear again in sequence, and the first phase t1 is executed again.
  • the second phase t2 and the third phase t3 are: causing the third thin film transistor M3 and the fourth thin film transistor M4 and the eighth thin film transistor M8 and the ninth thin film transistor M9 to alternately discharge the PU point and the OUTPUT point, so that the shift register The unit always remains low at the OUTPUT point and the PU point during the remaining time periods except for the period in which the high level is output.
  • the shift register provided by the embodiment of the present disclosure is described in detail by taking the clock input signal of the shift register unit as CLK, the first square wave signal VLL1 as a low level, and the second square wave signal VLL2 as a high level as an example.
  • the driving method of the unit is described in detail by taking the clock input signal of the shift register unit as CLK, the first square wave signal VLL1 as a low level, and the second square wave signal VLL2 as a high level as an example.
  • the input signal INPUT is at a high level
  • the clock signal CLK is at a low level
  • the reset signal RESET is at a low level
  • the first thin film transistor M1 is turned on
  • the pull-up node PU is at a high level
  • the first capacitor C1 is charged
  • the fifth thin film transistor M5 is turned on, and the power supply negative voltage VSS is introduced to the first pull-down node PD1, so that the first pull-down node PD1 is at a low level
  • the sixth thin film transistor M6 is turned on, and a negative power supply is introduced.
  • the voltage VSS is given to the second pull-down node PD2, so that the second pull-down node PD2 is at a low level; because the second square wave signal VLL2 is at a high level, the first square wave signal VLL1 is at a low level, so the tenth thin film transistor M10 leads Passing, the high level of the second square wave signal VLL2 is introduced to the second pull-down node PD2, but since the voltage of the power source negative voltage VSS is lower than the low level of the square wave signal, and the low voltage of the power source negative voltage VSS is pulled The low effect is greater than the high level of the second square wave signal VLL2, so even if the high level of the second square wave signal VLL2 is introduced to the second pull-down node PD2, since the tenth thin film transistor M10 is turned on, the power is introduced.
  • the input signal INPUT is at a low level
  • the clock signal CLK is at a high level
  • the reset signal RESET is at a low level.
  • the first thin film transistor M1 is turned off, because the first capacitor C1 is discharged, so the PU point
  • the high level is continued; the second thin film transistor is continuously turned on, and the high level of the clock signal CLK is introduced to the output terminal OUTPUT, so that the output terminal OUTPUT outputs a high level.
  • the input signal INPUT is low level
  • the clock signal CLK is low level
  • the reset signal RESET is high level.
  • the third thin film transistor M3 is turned on, and the power supply negative voltage VSS is introduced to the pull-up node PU point.
  • the PU point is low; the fourth thin film transistor M4 is turned on, the power supply negative voltage VSS is applied to the output terminal OUTPUT, and the output terminal OUTPUT is low; because the PU point is low, the sixth thin film transistor M6 is turned off.
  • the tenth thin film transistor M10 is turned on, and a high level is introduced to the second pull-down node PD2; because the sixth thin film transistor M6 is turned off, the voltage of the second pull-down node PD2 is only affected by the second square wave signal VLL2, so The second pull-down node PD2 is at a high level, the eleventh thin film transistor M11 is turned on, and the low level of the first square wave signal VLL1 is introduced to the output terminal OUTPUT; and the twelfth thin film transistor M12 is turned on to introduce the first square wave signal.
  • the low level of VLL1 is for the pull-up node, and the PU point is low; because the PU point is low, the fifth thin film transistor M5 is turned off, and the first pull-down node PD1 continues to be low.
  • the input signal INPUT is low level
  • the clock signal CLK is high level
  • the reset signal RESET is low level.
  • the third thin film transistor M3 and the fourth thin film transistor M4 are turned off, in order to make the pull-up
  • the node PU point and the output terminal OUTPUT are at a low level, and are implemented only by the action of the first pull-down module and the second pull-down module. Because the second square wave signal VLL2 is at a high level, the tenth thin film transistor M10 is continuously turned on, and the second pull-down node PD2 continues to be at a high level, whereby the eleventh thin film transistor M11 is turned on, and the first square wave signal is introduced.
  • the low level of VLL1 is output terminal OUTPUT, and the twelfth thin film transistor M12 is turned on, and the low level of the first square wave signal VLL1 is introduced to the PU point of the pull-up node to be low level. Therefore, in the fourth stage t4, the output terminal OUTPUT outputs a low level.
  • the input signal INPUT is low level
  • the clock signal CLK is low level
  • the reset signal RESET is low level.
  • the tenth thin film transistor M10 is continuously turned on, and the second pull-down node PD2 continues to be high level.
  • the eleventh thin film transistor M11 is turned on, and the low level of the first square wave signal VLL1 is introduced to the output terminal OUTPUT, and the twelfth thin film transistor M12 is turned on, and the low level of the first square wave signal VLL1 is introduced to pull up. Node, PU point is low. Therefore, in the fourth stage t4, the output terminal OUTPUT outputs a low level.
  • the operations of the fourth phase t4 and the fifth phase t5 are repeated until the timings of the first phase t1, the second phase t2, and the third phase t3 appear again in sequence, and the first phase t1 is executed again.
  • the second phase t2 and the third phase t3 are: causing the third thin film transistor M3 and the fourth thin film transistor M4 and the eleventh thin film transistor M11 and the twelfth thin film transistor M12 to alternately discharge the PU point and the OUTPUT point, so that the shift The bit register unit always remains low for the rest of the time period except for the period in which the high level is output.
  • the first pull-down module when the first square wave signal VLL1 is at a high level and the second square wave signal VLL2 is at a low level, the first pull-down module operates to be connected to the eighth thin film transistor M8 of the first pull-down node PD1 and The gate of the ninth thin film transistor M9 is at a high level; when the first square wave signal VLL1 is at a low level, the second square wave signal VLL2 is at a high level, the second pull-down module operates, and the gates of the eleventh thin film transistor M11 and the twelfth thin film transistor M12 connected to the second pull-down node PD2 are at a high level. .
  • the first square wave signal VLL1 and the second square wave signal VLL2 are square wave signals of high and low level switching, in the present disclosure, at the same time, or the thin film transistor connected to the first pull-down node is turned on, or connected The thin film transistor of the second pull-down node is turned on, so that the first pull-down module and the second pull-down module work alternately. Thereby, the duty ratio of the thin film transistor connected to the first pull-down node and the thin film transistor connected to the second pull-down node is lowered, thereby preventing aging of the thin film transistor and increasing the life of the thin film transistor.
  • FIG. 6 it is a structural diagram of an array substrate gate driving device provided by an embodiment of the present disclosure, wherein the structure includes one or more cascaded shift register units described above.
  • N is the number of gate lines
  • the first stage of the INPUT is provided by a vertical turn-on signal (Start Vertical, STV)
  • the INPUT of the Nth stage is provided by the OUTPUT of the N-1th (if any) stage
  • the RESET signal of the Nth stage is provided by the RESET unit.
  • the input signal INPUT of the nth stage (1 ⁇ n ⁇ N, if any) is supplied by the output OUTPUT of the n-1 stage, and the reset signal RESET of the nth stage is supplied by the output OUTPUT of the n+1 stage.
  • Embodiments of the present disclosure provide a display panel including the array substrate gate driving device described above.
  • an embodiment of the present disclosure provides a shift register unit, where the shift register unit includes an input module, an output module, a reset module, a function module, a first pull-down module, and a second pull-down module.
  • the shift register unit can reduce the duty ratio of the thin film transistor connected to the first pull-down node and the thin film transistor connected to the second pull-down node, thereby preventing aging of the thin film transistor and increasing the service life of the thin film transistor.

Abstract

提供了一种移位寄存器单元及驱动方法、阵列基板栅极驱动装置、以及显示面板，用以降低连接在下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。该移位寄存器单元包括：输入模块(201)、输出模块(202)、复位模块(203)、功能模块(204)、第一下拉模块(205)和第二下拉模块(206)；其中，第一下拉模块(205)被配置成：响应于第一方波信号(VLL1)的高电平和第一下拉节点(PD1)的高电平信号，将第二方波信号(VLL2)的低电平提供给上拉节点(PU)和输出端子(OUTPUT)；第二下拉模块(206)被配置成：响应于第二方波信号(VLL2)的高电平和第二下拉节点(PD2)的高电平信号，将第一方波信号(VLL1)的低电平提供给上拉节点(PU)和输出端子(OUTPUT)。

Description

移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板 技术领域
本公开涉及液晶显示驱动技术领域，尤其涉及一种移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板。
背景技术
近年来，移位寄存器(Gate on Array，GOA)技术被广泛应用于液晶显示面板中，所以人们对GOA的使用寿命、GOA工作消耗以及GOA工作的稳定性的要求越来越高。
现有技术中，一个GOA单元的电路结构参见图1所示，VDD是直流高压电，所以因为VDD的高电压使得第八薄膜晶体管M8一直处于导通状态，从而使得下拉节点PD点处于高电平。因此，当PD处于高电平状态时，第六薄膜晶体管M6和第四薄膜晶体管M4处于导通状态。只有当上拉结点PU点处于高电平时，使得第九薄膜晶体管M9的导通，导致PD点为低电平，从而使得连接在下拉节点的第六薄膜晶体管M6和第四薄膜晶体管M4关闭。然而，由于PD节点处于高电平的时间远远大于PD节点为低电平的时间，使得连接在下拉节点的第六薄膜晶体管M6和第四薄膜晶体管M4的栅极长期处于高电平，即为高占空比的状态，从而影响薄膜晶体管的使用寿命。
发明内容
本公开的实施例提供了一种移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板，用以降低连接在下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
本公开的实施例提供了一种移位寄存器单元，包括：输入模块、输出模块、复位模块、功能模块、第一下拉模块和第二下拉模块；其中第一下拉模块的控制端与第一下拉节点相连，第一输入端与第一方波信号相连，第二输入端与第二方波信号相连，第一输出端与上拉节点相连，第二输出端与输出端子相连；第二下拉模块的控制端与第二 下拉节点相连，第一输入端与第二方波信号相连，第二输入端与第一方波信号相连，第一输出端与所述上拉节点相连，第二输出端与所述输出端子相连；其中，第一下拉节点为功能模块的第一输出节点，第二下拉节点为功能模块的第二输出节点，上拉节点为输入模块的输出节点；
第一下拉模块被配置成：响应于第一方波信号的高电平和第一下拉节点的高电平信号，将第二方波信号的低电平提供给上拉节点和输出端子；
第二下拉模块被配置成：响应于第二方波信号的高电平和第二下拉节点的高电平信号，将第一方波信号的低电平提供给上拉节点和输出端子；
以及其中，当第一方波信号为高电平时，则第二方波信号为低电平，当第一方波信号为低电平时，则第二方波信号为高电平。
本公开的实施例提供的移位寄存器单元的优点在于：当第一下拉模块响应于第一方波信号的高电平和第一下拉节点的高电平信号时，连接在第一下拉节点的薄膜晶体管导通，从而降低了连接在第二下拉节点的薄膜晶体管的占空比；当第二下拉模块响应于第二方波信号的高电平和第二下拉节点的高电平信号时，连接在第二下拉节点的薄膜晶体管导通，从而降低了连接在第一下拉节点的薄膜晶体管的占空比。通过连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管交替工作，降低了连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
可选地，所述输入模块的输入端和控制端与输入信号相连，输出端为上拉节点。输入模块被配置成：响应于输入信号，将输入信号提供给上拉节点。
可选地，所述输出模块的控制端与所述输入模块的输出端相连，其输入端与时钟信号相连，其输出端与输出端子相连。输出模块被配置成：响应于上拉节点电压信号，将时钟信号电压提供给输出端子。
可选地，所述复位模块的控制端与复位信号相连，其输入端与电源负极相连，其第一输出端与所述上拉节点相连，其第二输出端与所述输出端子相连。并且，复位模块被配置成：响应于复位信号，将电 源负极电压提供给上拉节点和输出端子。
可选地，所述功能模块的控制端与所述上拉节点相连，其输入端与所述电源负极相连，其第一输出端与第一下拉节点相连，其第二输出端与第二下拉节点相连。功能模块被配置成：响应于上拉节点电压信号，将电源负极电压提供给第一下拉节点和第二下拉节点。
可选地，所述输入模块包括：第一薄膜晶体管，其栅极和源极连接输入信号端，漏极作为输入模块的输出节点，即上拉节点。
可选地，所述输出模块包括：第二薄膜晶体管，其栅极连接上拉节点，源极连接时钟信号输入端，漏极连接输出端子；第一电容，其连接于上拉节点和输出端子之间。
可选地，所述复位模块包括：第三薄膜晶体管，其栅极连接复位信号输入端，源极连接电源负极电压端，漏极连接上拉节点；第四薄膜晶体管，其栅极连接复位信号输入端，源极连接电源负极电压端，漏极连接输出端子。
可选地，所述功能模块包括：第五薄膜晶体管，其栅极连接上拉节点，源极连接电源负极电压端，漏极作为功能模块的第一输出节点，即第一下拉节点；以及第六薄膜晶体管，其栅极连接上拉节点，源极连接第一下拉节点，漏极作为功能模块的第二输出节点，即第二下拉节点。
可选地，所述第一下拉模块包括：第七薄膜晶体管，其栅极和源极连接第一方波信号输入端，漏极连接第一下拉节点；第八薄膜晶体管，其栅极连接第一下拉节点，源极连接第二方波信号输入端，漏极连接输出端子；第九薄膜晶体管，其栅极连接第一下拉节点，源极连接第二方波信号输入端，漏极连接上拉节点；第二电容，其连接于第一下拉节点与第二方波信号输入端之间；第三电容，其与所述第二电容并联。
可选地，所述第二下拉模块包括：第十薄膜晶体管，其栅极和源极连接第二方波信号输入端，漏极连接第二下拉节点；第十一薄膜晶体管，其栅极连接第二下拉节点，源极连接第一方波信号输入端，漏极连接输出端子；第十二薄膜晶体管，其栅极连接第二下拉节点，源极连接第一方波信号输入端，漏极连接上拉节点；第四电容，其连接于第二下拉节点与第一方波信号输入端之间；第五电容，其与所述第 四电容并联。
通过本公开的实施例中提供的第一下拉模块和第二下拉模块，使得在同一时刻，第一下拉模块工作而第二下拉模块停止工作，从而降低第二下拉模块中连接在第二下拉节点的薄膜晶体管的占空比，或者第二下拉模块工作而第一下拉模块停止工作，从而降低第一下拉模块中连接在第一下拉节点的薄膜晶体管的占空比。因为第一下拉模块和第二下拉模块的交替工作，使得连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管交替导通，从而降低了连接在第一下拉节点的薄膜晶体管和连接第二下拉节点的薄膜晶体管的占空比，防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
本公开的实施例还提供的一种移位寄存器单元的驱动方法，该方法包括：
输入模块在接收到输入信号时，将所述输入信号电压提供给上拉节点；
输出模块在接收到上拉节点的电压信号后，将时钟信号电压提供给输出端子；
复位模块在接收到复位信号时，将电源负极电压提供给上拉节点和输出端子；
功能模块在接收到上拉节点的电压信号后，将电源负极电压提供给第一下拉节点和第二下拉节点；
第一下拉模块在接收到第一方波信号的高电平和第一下拉节点的高电平信号后，将第二方波信号的低电平提供给上拉节点和输出端子；
第二下拉模块在接收到第二方波信号的高电平和第二下拉节点的高电平信号后，将第一方波信号的低电平提供给上拉节点和输出端子；
其中，第一下拉节点为功能模块的第一输出节点，第二下拉节点为功能模块的第二输出节点，上拉节点为输入模块的输出节点；
其中，当第一方波信号为高电平时，则第二方波信号为低电平，当第一方波信号为低电平时，则第二方波信号为高电平。
通过本公开的实施例中提供的第一下拉模块和第二下拉模块，使得在同一时刻，第一下拉模块工作而第二下拉模块停止工作，从而降低第二下拉模块中连接在第二下拉节点的薄膜晶体管的占空比，或者，第二下拉模块工作而第一下拉模块停止工作，从而降低第一下拉模块 中连接在第一下拉节点的薄膜晶体管的占空比。因为第一下拉模块和第二下拉模块的交替工作，使得连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管交替导通，从而降低了连接在第一下拉节点的薄膜晶体管和连接第二下拉节点的薄膜晶体管的占空比，防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
本公开的实施例提供了一种阵列基板栅极驱动装置，包括级联的如本公开的实施例提供的任一移位寄存器单元。
本公开的实施例提供了一种显示面板，包括本公开的实施例提供的阵列基板栅极驱动装置。
附图说明
图1为现有技术提供的一种移位寄存器单元的结构示意图；
图2为本公开的实施例提供的一种移位寄存器单元的结构示意图；
图3为本公开的实施例提供的一种方波信号的时序图；
图4为本公开的实施例提供的移位寄存器单元的一种控制信号时序图；
图5为本公开的实施例提供的移位寄存器单元的另一种控制信号时序图；
图6为本公开的实施例提供的一种阵列基板栅极驱动装置结构示意图。
具体实施方式
下面将结合本公开的实施例中的附图，对本公开的实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本公开一部分实施例，并不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开的实施例提供了一种移位寄存器单元及驱动方法、阵列基板栅极驱动装置、以及显示面板，用以降低连接在下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
需要说明的是，本公开的实施例中提供的时钟信号包括现有技术 中的时钟信号CLK和CLKB。一般地，阵列基板栅极驱动装置结构是由多个级联的移位寄存器单元组成，阵列基板栅极驱动装置结构包括多行移位寄存器单元，每行包括一个移位寄存器单元。每一奇数行对应的移位寄存器单元输入的时钟信号为CLK，每一偶数行对应的移位寄存器单元输入的时钟信号为CLKB。本公开的实施例中电源负极提供的电压VSS为低电平，本公开的实施例中的薄膜晶体管TFT可以均为N型TFT，也可以均为P型TFT，或者实施例中的薄膜晶体管TFT为N型TFT和P型TFT的组合。具体地，本公开的实施例中以薄膜晶体管TFT均为N型TFT为例进行详细描述，且所有TFT的栅极电压为高电平时TFT导通，低电平时TFT断开。
本公开的实施例中的移位寄存器单元是针对现有技术中提供的非晶硅工艺下的移位寄存器单元的改进。本公开的实施例提供了一种方波信号，用以提供给下拉单元，其中方波信号包括第一方波信号和第二方波信号，且第一方波信号与第二方波信号为频率为1HZ到3HZ的高低电平反复切换的方波。
参见图2，本公开的实施例提供了一种移位寄存器单元，包括：输入模块201、输出模块202、复位模块203、功能模块204、第一下拉模块205和第二下拉模块206。
输入模块201的输入端和控制端与输入信号INPUT相连，其输出端与上拉节点PU点相连；输出模块202的控制端与输入模块201的输出端相连，其输入端与时钟信号CLK相连，其输出端与输出端子OUTPUT相连；复位模块203的控制端与复位信号RESET相连，其输入端与电源负极VSS相连，其第一输出端与上拉节点PU点相连，其第二输出端与输出端子OUTPUT相连；功能模块204的控制端与上拉节点PU点相连，其输入端与电源负极VSS相连，其第一输出端与第一下拉节点PD1相连，其第二输出端与第二下拉节点PD2相连；第一下拉模块205的控制端与第一下拉节点PD1相连，其第一输入端与第一方波信号VLL1相连，其第二输入端与第二方波信号VLL2相连，其第一输出端与上拉节点PU点相连，其第二输出端与输出端子OUTPUT相连；第二下拉模块206的控制端与第二下拉节点PD2点相连，其第一输入端与第二方波信号VLL2相连，其第二输入端与第一方波信号VLL1相连，其第一输出端与上拉节点PU点相连，其第二输出端与输 出端子OUTPUT相连。
本公开的实施例中每个模块中的控制端连接薄膜晶体管的栅极，输入端连接薄膜晶体管的源极，输出端连接薄膜晶体管的漏极。当然，也可以每个模块的控制端连接薄膜晶体管的栅极，输入端连接薄膜晶体管的漏极，输出端连接薄膜晶体管的源极，本公开的实施例对此不做限定。
输入模块201被配置成：响应于输入信号INPUT，将输入信号INPUT提供给上拉节点PU点，其中，上拉节点PU点为输入模块201的输出节点。所述输入模块可以包括第一薄膜晶体管M1，其栅极和源极连接输入信号端INPUT，漏极作为输入模块的输出节点，即作为上拉节点PU点。
输出模块202被配置成：响应于上拉节点PU点的电压信号，将时钟信号电压CLK提供给输出端子OUTPUT。所述输出模块包括：第二薄膜晶体管M2，其栅极连接上拉节点PU点，源极连接时钟信号输入端CLK，漏极连接输出端子OUTPUT；第一电容C1，其连接于上拉节点PU点和输出端子OUTPUT之间。
复位模块203被配置成：响应于复位信号RESET，将电源负极电压VSS提供给上拉节点PU点和输出端子OUTPUT。所述复位模块包括：第三薄膜晶体管M3，其栅极连接复位信号输入端RESET，源极连接电源负极电压端VSS，漏极连接上拉节点PU点，且第三薄膜晶体管M3的漏极作为复位模块203的第一输出端；第四薄膜晶体管M4，其栅极连接复位信号输入端RESET，源极连接电源负极电压端VSS，漏极连接输出端子OUTPUT，且第四薄膜晶体管M4的漏极作为复位模块203的第二输出端。
功能模块204被配置成：响应于上拉节点PU点电压信号，将电源负极电压VSS提供给第一下拉节点PD1和第二下拉节点PD2，其中，第一下拉节点PD1为功能模块204的第一输出节点，第二下拉节点PD2为功能模块204的第二输出节点。所述功能模块包括：第五薄膜晶体管MS，其栅极连接上拉节点PU点，源极连接电源负极电压端VSS，漏极作为功能模块的第一输出节点，即第一下拉节点PD1；第六薄膜晶体管M6，其栅极连接上拉节点PU点，源极连接第一下拉节点PD1，漏极作为功能模块的第二输出节点，即第二下拉节点PD2。
第一下拉模块205被配置成：响应于第一方波信号VLL1的高电平和第一下拉节点的PD1高电平信号，将第二方波信号VLL2的低电平提供给上拉节点PU点和输出端子OUTPUT。第一下拉模块包括：第七薄膜晶体管M7，其栅极和源极连接第一方波信号输入端VLL1，漏极连接第一下拉节点PD1，且第七薄膜晶体管M7的源极为第一下拉模块205的第一输入端；第八薄膜晶体管M8，其栅极连接第一下拉节点PD1，源极连接第二方波信号输入端VLL2，漏极连接输出端子OUTPUT，且第八薄膜晶体管M8的漏极为第一下拉模块205的第二输出端；第九薄膜晶体管M9，其栅极连接第一下拉节点PD1，源极连接第二方波信号输入端VLL2，漏极连接上拉节点PU点，且第九薄膜晶体管M9的源极为第一下拉模块205的第二输入端，漏极为第一下拉模块205的第一输出端；第二电容C2，连接于第一下拉节点PD1与第二方波信号输入端VLL2之间；第三电容C3，其与第二电容C2并联。
第二下拉模块206被配置成：响应于第二下拉节点电压信号PD2的高电平和第二方波信号VLL2高电平，将第一方波信号VLL1的低电平提供给上拉节点PU和输出端子OUTPUT。第二下拉模块包括：第十薄膜晶体管M10，其栅极和源极连接第二方波信号输入端VLL2，漏极连接第二下拉节点PD2，且第十薄膜晶体管M10的源极为第二下拉模块206的第一输入端；第十一薄膜晶体管M11，其栅极连接第二下拉节点PD2，源极连接第一方波信号输入端VLL1，漏极连接输出端子OUTPUT，且第十一薄膜晶体管M11的漏极为第二下拉模块206的第二输出端；第十二薄膜晶体管M12，其栅极连接第二下拉节点PD2，源极连接第一方波信号输入端VLL1，漏极连接上拉节点PU点，且第十二薄膜晶体管M12的源极为第二下拉模块206的第二输入端，漏极为第二下拉模块206的第一输出端；第四电容C4，连接于第二下拉节点PD2与第一方波信号输入端VLL1之间；第五电容C5，其与第四电容C4并联。
通过本公开的实施例中提供的第一下拉模块和第二下拉模块，使得在同一时刻，第一下拉模块工作，第二下拉模块停止工作，从而降低第二下拉模块中连接在第二下拉节点的薄膜晶体管的占空比，或者，第二下拉模块工作，第一下拉模块停止工作，从而降低第一下拉模块中连接在第一下拉节点的薄膜晶体管的占空比。因为第一下拉模块和 第二下拉模块的交替工作，使得连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管交替导通，从而降低了连接在第一下拉节点的薄膜晶体管和连接第二下拉节点的薄膜晶体管的占空比，防止薄膜晶体管的老化，进而增加薄膜晶体管的使用寿命。
需要说明的是，当第一方波信号为高电平时，第一下拉模块工作，第一下拉节点为高电平，连接在第一下拉节点的薄膜晶体管导通，将第二方波信号的低电平引入到上拉节点和输出端子，因为第二下拉节点为低电平，第二下拉模块停止工作，连接在第二下拉节点的薄膜晶体管关断，从而降低了连接在第二下拉节点的薄膜晶体管的占空比；当第二方波信号为高电平时，第二下拉模块工作，第二下拉模块为高电平，连接在第二下拉节点的薄膜晶体管导通，将第一方波信号的低电平引入到上拉节点和输出端子，因为第一下拉节点为低电平，第一下拉模块停止工作，连接在第一下拉节点的薄膜晶体管关断，从而降低了连接在第一下拉节点的薄膜晶体管的占空比。综上所述，因为第一下拉模块和第二下拉模块的交替工作，使得连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管交替导通，从而降低了连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管的占空比，从而防止该薄膜晶体管的老化，提高该薄膜晶体管的使用寿命。
本公开的实施例提供的方波信号包括第一方波信号VLL1和第二方波信号VLL2，VLL1和VLL2的高低电平切换周期可以约为0.3s至1s。第一方波信号VLL1和第二方波信号VLL2在同一时间段内高低电平的切换方向正好相反，且方波信号的低电平高于电源负极电压VSS，且低于薄膜晶体管导通电压。一般地，移位寄存器单元中时钟信号CLK或者CLKB的切换周期约为16μs。显然，该方波信号的切换频率远远小于时钟信号的切换频率。
图3为本公开的实施例中第一方波信号VLL1和第二方波信号VLL2波形，以及时钟信号CLK和CLKB的波形图。显然，在时钟信号CLK和CLKB的多个周期内，第一方波信号和第二方波信号都不发生高低电平的变化。
需要说明的是，本公开的实施例中提供的第一方波信号VLL1和第二方波信号VLL2的高低电平切换周期可以与时钟信号CLK的高低 电平切换周期相同，也可以不同。本公开的实施例对第一方波信号VLL1和第二方波信号VLL2不做具体限定。无论第一方波信号VLL1和第二方波信号VLL2的高低电平切换周期为多少，根据本公开的实施例提供的第一下拉模块和第二下拉模块，都可以降低连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，进而增加薄膜晶体管的使用寿命。具体地，当第一方波信号为高电平时，第一下拉模块工作，当第二方波信号为高电平时，第二下拉模块工作，使得第一下拉模块和第二下拉模块交替工作，从而降低连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
接下来详细描述上面提供的移位寄存器单元的驱动方法，该方法包括：
输入模块在接收到输入信号时，将所述输入信号电压提供给上拉节点；
输出模块在接收到上拉节点的电压信号后，将时钟信号电压提供给输出端子；
复位模块在接收到复位信号时，将电源负极电压提供给上拉节点和输出端子；
功能模块在接收到上拉节点的电压信号后，将电源负极电压提供给第一下拉节点和第二下拉节点；
第一下拉模块在接收到第一方波信号的高电平和第一下拉节点的高电平信号后，将第二方波信号的低电平提供给上拉节点和输出端子；
第二下拉模块在接收到第二方波信号的高电平和第二下拉节点的高电平信号后，将第一方波信号的低电平提供给上拉节点和输出端子；
其中，第一下拉节点为功能模块的第一输出节点，第二下拉节点为功能模块的第二输出节点，上拉节点为输入模块的输出节点；
其中，当第一方波信号为高电平时，则第二方波信号为低电平，当第一方波信号为低电平时，则第二方波信号为高电平。
下面，以移位寄存器单元的时钟输入信号为CLK，第一方波信号VLL1为高电平，第二方波信号VLL2为低电平为例，详细描述本公开的实施例提供的移位寄存器单元的驱动方法和工作原理。
参见图4的控制信号时序图描述本公开的实施例提供的移位寄存器单元的驱动方法，包括：
第一阶段t1，输入信号INPUT为高电平，时钟信号CLK为低电平，复位信号RESET为低电平，此时第一薄膜晶体管M1导通，上拉节点PU点为高电平，同时给第一电容C1充电；第五薄膜晶体管M5导通，引入电源负极电压VSS给第一下拉节点PD1，第一下拉节点PD1为低电平；第六薄膜晶体管M6导通，引入电源负极电压VSS给第二下拉节点PD2，第二下拉节点PD2为低电平；因为第一方波信号VLL1为高电平，第二方波信号VLL2为低电平，第七薄膜晶体管M7导通，会引入第一方波信号VLL1的高电平到第一下拉节点PD1，但由于电源负极电压VSS的电压低于方波信号的低电平，且电源负极电压VSS的低电平的拉低作用大于第一方波信号VLL1的高电平的拉高作用，所以即使第一方波信号VLL1的高电平引入到第一下拉节点PD1，但因为第五薄膜晶体管M5导通，引入电源负极电压VSS给第一下拉节点PD1，使得第一下拉节点PD1持续为低电平；同时，第二下拉模块中第一方波信号VLL1的高电平对第四电容C4和第五电容C5进行充电，使得第一方波信号VLL1的高电平不能引入到第二下拉节点PD2，从而使得连接在第二下拉节点PD2的第十一薄膜晶体管M11和第十二薄膜晶体管M12关断，减小连接在第二下拉节点PD2的薄膜晶体管的占空比；因为PU点为高电平，第二薄膜晶体管M2导通，引入时钟信号CLK的低电平给输出端子OUTPUT，输出端子OUTPUT输出低电平。
第二阶段t2，输入信号INPUT为低电平、时钟信号CLK为高电平、复位信号RESET为低电平，此时第一薄膜晶体管M1关断，因为第一电容C1放电作用，PU点持续高电平；第二薄膜晶体管持续导通，引入时钟信号CLK的高电平给输出端子OUTPUT，输出端子OUTPUT输出高电平。
第三阶段t3，输入信号INPUT为低电平、时钟信号CLK为低电平、复位信号RESET为高电平，此时第三薄膜晶体管M3导通，引入电源负极电压VSS给上拉节点PU点，PU点为低电平；第四薄膜晶体管M4导通，引入电源负极电压VSS给输出端子OUTPUT，输出端子OUTPUT为低电平；因为PU点为低电平，第五薄膜晶体管M5关断； 由于第一方波信号VLL1为高电平，则第七薄膜晶体管M7持续导通，因为第五薄膜晶体管M5关断，使得第一下拉节点PD1的电压只受第一方波信号VLL1的影响，所以第一下拉节点PD1为高电平，第八薄膜晶体管M8导通，引入第二方波信号VLL2的低电平给输出端子OUTPUT，同时第九薄膜晶体管M9导通，引入第二方波信号VLL2的低电平给上拉节点PU点；因为PU点为低电平，第六薄膜晶体管M6关断，第二下拉节点PD2持续为低电平。
第四阶段t4，输入信号INPUT为低电平、时钟信号CLK为高电平、复位信号RESET为低电平，此时第三薄膜晶体管M3和第四薄膜晶体管M4关断，要想使得上拉节点PU点和输出端子OUTPUT为低电平，只有通过第一下拉模块和第二下拉模块的作用来实现。因为第一方波信号VLL1为高电平，所以第七薄膜晶体管M7持续导通，第一下拉节点PD1持续为高电平，第八薄膜晶体管M8导通，引入第二方波信号VLL2的低电平给输出端子OUTPUT，同时第九薄膜晶体管M9导通，引入第二方波信号VLL2的低电平给上拉节点PU点。所以第四阶段t4中，输出端子OUTPUT输出低电平。
第五阶段t5，输入信号INPUT为低电平、时钟信号CLK为低电平、复位信号RESET为低电平，此时第七薄膜晶体管M7持续导通，第一下拉节点PD1持续为高电平，第八薄膜晶体管M8导通，引入第二方波信号VLL2的低电平给输出端子OUTPUT，同时第九薄膜晶体管M9导通，引入第二方波信号VLL2的低电平给上拉节点PU点为低电平。所以第四阶段t4中，输出端子OUTPUT输出低电平。
在第五阶段t5之后，重复进行第四阶段t4和第五阶段t5的操作，直到再次依次出现第一阶段t1、第二阶段t2和第三阶段t3的时序，并再次执行第一阶段t1、第二阶段t2和第三阶段t3，即为：使第三薄膜晶体管M3和第四薄膜晶体管M4以及第八薄膜晶体管M8和第九薄膜晶体管M9轮流对PU点和OUTPUT点放电，使得移位寄存器单元在除了输出高电平的时间段的其余时间段中OUTPUT点和PU点始终保持低电平。
此外，以移位寄存器单元的时钟输入信号为CLK，第一方波信号VLL1为低电平，第二方波信号VLL2为高电平为例，详细描述本公开的实施例提供的移位寄存器单元的驱动方法。
参见图5的控制信号时序图，描述了本公开的实施例提供的移位寄存器单元的驱动方法，包括：
第一阶段t1，输入信号INPUT为高电平，时钟信号CLK为低电平，复位信号RESET为低电平，使得第一薄膜晶体管M1导通，上拉节点PU点为高电平，同时给第一电容C1充电；第五薄膜晶体管M5导通，引入电源负极电压VSS给第一下拉节点PD1，使得第一下拉节点PD1为低电平；第六薄膜晶体管M6导通，引入电源负极电压VSS给第二下拉节点PD2，使得第二下拉节点PD2为低电平；因为第二方波信号VLL2为高电平，第一方波信号VLL1为低电平，所以第十薄膜晶体管M10导通，引入第二方波信号VLL2的高电平到第二下拉节点PD2，但是，由于电源负极电压VSS的电压低于方波信号的低电平，且电源负极电压VSS的低电平的拉低作用大于第二方波信号VLL2的高电平的拉高作用，所以即使第二方波信号VLL2的高电平引入到第二下拉节点PD2，但由于第十薄膜晶体管M10导通，引入电源负极电压VSS给第二下拉节点PD2，使得第二下拉节点PD2持续为低电平；同时，第一下拉模块中第二方波信号VLL2的高电平对第二电容C2和第三电容C3进行充电，使得第二方波信号VLL2的高电平不能引入到第一下拉节点PD1，从而使连接在第一下拉节点PD1的第八薄膜晶体管M8和第九薄膜晶体管M9关断，减小连接在第一下拉节点PD1的薄膜晶体管的占空比；因为PU点为高电平，第二薄膜晶体管M2导通，引入时钟信号CLK的低电平给输出端子OUTPUT，输出端子OUTPUT输出低电平。
第二阶段t2，输入信号INPUT为低电平、时钟信号CLK为高电平、复位信号RESET为低电平，此时第一薄膜晶体管M1关断，因为第一电容C1放电作用，所以PU点持续高电平；第二薄膜晶体管持续导通，引入时钟信号CLK的高电平给输出端子OUTPUT，使得输出端子OUTPUT输出高电平。
第三阶段t3，输入信号INPUT为低电平、时钟信号CLK为低电平、复位信号RESET为高电平，此时第三薄膜晶体管M3导通，引入电源负极电压VSS给上拉节点PU点，PU点为低电平；第四薄膜晶体管M4导通，引入电源负极电压VSS给输出端子OUTPUT，输出端子OUTPUT为低电平；因为PU点为低电平，第六薄膜晶体管M6关断， 同时第十薄膜晶体管M10导通，引入高电平给第二下拉节点PD2；因为第六薄膜晶体管M6关断，使得第二下拉节点PD2的电压只受第二方波信号VLL2的影响，所以第二下拉节点PD2为高电平，第十一薄膜晶体管M11导通，引入第一方波信号VLL1的低电平给输出端子OUTPUT；同时第十二薄膜晶体管M12导通，引入第一方波信号VLL1的低电平给上拉节点，PU点为低电平；因为PU点为低电平，第五薄膜晶体管M5关断，第一下拉节点PD1持续为低电平。
第四阶段t4，输入信号INPUT为低电平、时钟信号CLK为高电平、复位信号RESET为低电平，此时第三薄膜晶体管M3和第四薄膜晶体管M4关断，要想使得上拉节点PU点和输出端子OUTPUT为低电平，只有通过第一下拉模块和第二下拉模块的作用来实现。因为第二方波信号VLL2为高电平，所以第十薄膜晶体管M10持续导通，第二下拉节点PD2持续为高电平，由此第十一薄膜晶体管M11导通，引入第一方波信号VLL1的低电平给输出端子OUTPUT，同时第十二薄膜晶体管M12导通，引入第一方波信号VLL1的低电平给上拉节点PU点为低电平。所以第四阶段t4中，输出端子OUTPUT输出低电平。
第五阶段t5，输入信号INPUT为低电平、时钟信号CLK为低电平、复位信号RESET为低电平，此时第十薄膜晶体管M10持续导通，第二下拉节点PD2持续为高电平，第十一薄膜晶体管M11导通，引入第一方波信号VLL1的低电平给输出端子OUTPUT，同时第十二薄膜晶体管M12导通，引入第一方波信号VLL1的低电平给上拉节点，PU点为低电平。所以第四阶段t4中，输出端子OUTPUT输出低电平。
在第五阶段t5之后，重复进行第四阶段t4和第五阶段t5的操作，直到再次依次出现第一阶段t1、第二阶段t2和第三阶段t3的时序，并再次执行第一阶段t1、第二阶段t2和第三阶段t3，即为：使第三薄膜晶体管M3和第四薄膜晶体管M4以及第十一薄膜晶体管M11和第十二薄膜晶体管M12轮流对PU点和OUTPUT点放电，使得移位寄存器单元除了输出高电平的时间段的其余时间段中OUTPUT点和PU点始终保持低电平。
综上所述，当第一方波信号VLL1为高电平且第二方波信号VLL2为低电平，第一下拉模块工作，连接于第一下拉节点PD1的第八薄膜晶体管M8和第九薄膜晶体管M9的栅极为高电平；当第一方波信号 VLL1为低电平，第二方波信号VLL2为高电平，第二下拉模块工作，连接于第二下拉节点PD2的第十一薄膜晶体管M11和第十二薄膜晶体管M12的栅极为高电平。因为第一方波信号VLL1和第二方波信号VLL2为高低电平切换的方波信号，所以本公开中在同一时刻，或者连接在第一下拉节点的薄膜晶体管的导通，或者连接在第二下拉节点的薄膜晶体管的导通，从而使得第一下拉模块和第二下拉模块交替工作。由此，降低了连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
参见图6，其是本公开的实施例提供的一种阵列基板栅极驱动装置的结构图，其中该结构包括级联的一个或多个上面描述的移位寄存器单元。
如果整个栅极驱动电路总共有N级移位寄存器单元(GOA unit)，N为栅线数量，其中的第一级的INPUT由垂直开启信号(Start Vertical，STV)提供，第一级的RESET信号由第二级(若有的话)的OUTPUT提供，第N级的INPUT由第N-1(若有的话)级的OUTPUT提供，第N级的RESET信号由RESET单元提供。第n级(1＜n＜N，若有的话)的输入信号INPUT由n-1级的输出OUTPUT提供，第n级的复位信号RESET由n+1级的输出OUTPUT提供。
本公开的实施例提供了一种显示面板，包括上面所描述的阵列基板栅极驱动装置。
综上所述，本公开的实施例提供的一种移位寄存器单元，该移位寄存器单元包括输入模块、输出模块、复位模块、功能模块、第一下拉模块和第二下拉模块。该移位寄存器单元可以降低连接在第一下拉节点的薄膜晶体管和连接在第二下拉节点的薄膜晶体管的占空比，从而防止薄膜晶体管的老化，增加薄膜晶体管的使用寿命。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种移位寄存器单元，包括：输入模块、输出模块、复位模块、功能模块、第一下拉模块和第二下拉模块；其中，第一下拉模块的控制端与第一下拉节点相连，第一输入端与第一方波信号相连，第二输入端与第二方波信号相连，第一输出端与上拉节点相连，第二输出端与输出端子相连；第二下拉模块的控制端与第二下拉节点相连，第一输入端与第二方波信号相连，第二输入端与第一方波信号相连，第一输出端与所述上拉节点相连，第二输出端与所述输出端子相连；其中，第一下拉节点为功能模块的第一输出节点，第二下拉节点为功能模块的第二输出节点，上拉节点为输入模块的输出节点；并且
    第一下拉模块被配置成：响应于第一方波信号的高电平和第一下拉节点的高电平信号，将第二方波信号的低电平提供给上拉节点和输出端子；
    第二下拉模块被配置成：响应于第二方波信号的高电平和第二下拉节点的高电平信号，将第一方波信号的低电平提供给上拉节点和输出端子；
    其中，当第一方波信号为高电平时，第二方波信号为低电平，以及当第一方波信号为低电平时，第二方波信号为高电平。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入模块的输入端和控制端与输入信号相连，输出端为上拉节点；并且输入模块被配置成：响应于输入信号，将输入信号提供给上拉节点。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述输出模块的控制端与所述输入模块的输出端相连，输入端与时钟信号相连，输出端与输出端子相连；并且所述输出模块被配置成：响应于上拉节点电压信号，将时钟信号电压提供给输出端子。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述复位模块的控制端与复位信号相连，输入端与电源负极相连，第一输出端与所述上拉节点相连，第二输出端与所述输出端子相连；并且所述复位模块被配置成：响应于复位信号，将电源负极电压提供给上拉节点和输出端子。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述功能模块 的控制端与所述上拉节点相连，输入端与所述电源负极相连，第一输出端与第一下拉节点相连，第二输出端与第二下拉节点相连；并且功能模块被配置成：响应于上拉节点电压信号，将电源负极电压提供给第一下拉节点和第二下拉节点。
  6. 根据权利要求2所述的移位寄存器单元，其中，所述输入模块包括：
    第一薄膜晶体管，其控制端和第一端连接输入信号端，第二端作为输入模块的输出节点，所述输出节点为上拉节点。
  7. 根据权利要求3所述的移位寄存器单元，其中，所述输出模块包括：
    第二薄膜晶体管，其控制端连接上拉节点，第一端连接时钟信号输入端，第二端连接输出端子；
    第一电容，其连接于上拉节点和输出端子之间。
  8. 根据权利要求4所述的移位寄存器单元，其中，所述复位模块包括：
    第三薄膜晶体管，其控制端连接复位信号输入端，第一端连接电源负极电压端，第二端连接上拉节点；
    第四薄膜晶体管，其控制端连接复位信号输入端，第一端连接电源负极电压端，第二端连接输出端子。
  9. 根据权利要求5所述的移位寄存器单元，其中，所述功能模块包括：
    第五薄膜晶体管，其控制端连接上拉节点，第一端连接电源负极电压端，第二端作为功能模块的第一输出节点，该第一输出节点为第一下拉节点；
    第六薄膜晶体管，其控制端连接上拉节点，第一端连接第一下拉节点，第二端作为功能模块的第二输出节点，该第二输出节点为第二下拉节点。
  10. 根据权利要求1所述的移位寄存器单元，其中，所述第一下拉模块包括：
    第七薄膜晶体管，其控制端和第一端连接第一方波信号输入端，第二端连接第一下拉节点；
    第八薄膜晶体管，其控制端连接第一下拉节点，第一端连接第二 方波信号输入端，第二端连接输出端子；
    第九薄膜晶体管，其控制端连接第一下拉节点，第一端连接第二方波信号输入端，第二端连接上拉节点；
    第二电容，其连接于第一下拉节点与第二方波信号输入端之间；
    第三电容，其与所述第二电容并联。
  11. 根据权利要求1所示的移位寄存器单元，其中，所述第二下拉模块包括：
    第十薄膜晶体管，其控制端和第一端连接第二方波信号输入端，第二端连接第二下拉节点；
    第十一薄膜晶体管，其控制端连接第二下拉节点，第一端连接第一方波信号输入端，第二端连接输出端子；
    第十二薄膜晶体管，其控制端连接第二下拉节点，第一端连接第一方波信号输入端，第二端连接上拉节点；
    第四电容，其连接于第二下拉节点与第一方波信号输入端之间；
    第五电容，其与所述第四电容并联。
  12. 一种移位寄存器单元的驱动方法，该方法包括：
    输入模块在接收到输入信号时，将所述输入信号电压提供给上拉节点；
    输出模块在接收到上拉节点的电压信号后，将时钟信号电压提供给输出端子；
    复位模块在接收到复位信号时，将电源负极电压提供给上拉节点和输出端子；
    功能模块在接收到上拉节点的电压信号后，将电源负极电压提供给第一下拉节点和第二下拉节点；
    第一下拉模块在接收到第一方波信号的高电平和第一下拉节点的高电平信号后，将第二方波信号的低电平提供给上拉节点和输出端子；
    第二下拉模块在接收到第二方波信号的高电平和第二下拉节点的高电平信号后，将第一方波信号的低电平提供给上拉节点和输出端子；
    其中，第一下拉节点为功能模块的第一输出节点，第二下拉节点为功能模块的第二输出节点，上拉节点为输入模块的输出节点；
    其中，当第一方波信号为高电平时，则第二方波信号为低电平，当第一方波信号为低电平时，则第二方波信号为高电平。
  13. 一种阵列基板栅极驱动装置，包括级联的如权利要求1～11的任一权项所述的移位寄存器单元。
  14. 一种显示面板，包括如权利要求13所述阵列基板栅极驱动装置。
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