WO2016037381A1 - 基于igzo制程的栅极驱动电路 - Google Patents

基于igzo制程的栅极驱动电路 Download PDF

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Publication number
WO2016037381A1
WO2016037381A1 PCT/CN2014/086889 CN2014086889W WO2016037381A1 WO 2016037381 A1 WO2016037381 A1 WO 2016037381A1 CN 2014086889 W CN2014086889 W CN 2014086889W WO 2016037381 A1 WO2016037381 A1 WO 2016037381A1
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Prior art keywords
electrically connected
gate
transistor
node
pull
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PCT/CN2014/086889
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English (en)
French (fr)
Inventor
肖军城
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深圳市华星光电技术有限公司
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Priority to GB1702185.8A priority Critical patent/GB2543235B/en
Priority to US14/426,368 priority patent/US9489907B2/en
Priority to KR1020177004330A priority patent/KR101944641B1/ko
Priority to JP2017513129A priority patent/JP6423957B2/ja
Priority to DE112014006943.4T priority patent/DE112014006943T5/de
Publication of WO2016037381A1 publication Critical patent/WO2016037381A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a gate driving circuit based on an IGZO process.
  • GOA Gate Drive On Array
  • a gate driver is fabricated on a thin film transistor array substrate by a thin film transistor liquid crystal display Array process to realize progressive scanning.
  • the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down hold circuit (Pull-down). Holding part), and a boost part that is responsible for the potential rise.
  • the pull-up circuit is mainly responsible for outputting the input clock signal (Clock) to the gate of a thin film transistor (TFT) as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down holding circuit is responsible for keeping the scan signal and the signal of the pull-up circuit (that is, the signal applied to the Q point) in the off state (ie, the set negative potential), usually two The pull-down hold circuits alternate.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • IGZO indium gallium zinc oxide
  • the carrier mobility is 20 to 30 times that of amorphous silicon, which can greatly increase the charge and discharge rate of the TFT electrode and improve the pixel.
  • the response speed enables faster refresh rates, while the faster response also greatly increases the pixel scan rate, making ultra-high resolution possible in TFT-LCDs.
  • IGZO displays have higher energy efficiency levels and are more efficient due to the reduced number of transistors and improved light transmission per pixel.
  • IGZO's GOA circuit is likely to replace a-Si TFT in the future, and the GOA development for IGZO in the prior art is rare, especially for large-size GOA circuits, which need to overcome many problems caused by IGZO materials themselves and need to be overcome.
  • the main problems are: (1) the problem of Vth drifting to the negative direction; (2) the SS region is too steep, and a small voltage change will cause a change in the magnitude of the current, which will directly lead to the leakage of the key TFT of the GOA circuit, resulting in IGZO
  • the GOA function is invalid.
  • FIG. 1 and FIG. 2 are timing diagrams of a classic module of a common GOA circuit and a corresponding signal thereof.
  • the common GOA circuit includes a first transistor T1 whose gate is electrically connected to the input signal end.
  • the source is also electrically connected to the input signal terminal Input, the drain electrical Connected to the node Q;
  • the second transistor T2 has a gate electrically connected to the node Q, a source electrically connected to the clock signal Clock, a drain electrically connected to the output terminal Output, and a third transistor T3 having a gate electrical property Connected to the reset signal terminal Reset, the source is electrically connected to the output terminal Output, and the drain is electrically connected to a negative potential VSS;
  • the fourth transistor T4 has a gate electrically connected to the reset signal terminal Reset, and the source is electrically connected.
  • FIG. 1 further includes a pull-down & compensation module including four leads and nodes respectively Q, the clock signal Clock, the output terminal Output, the negative potential VSS is connected; the first transistor T1 is used to turn on the second transistor T2 according to the signal input by the input signal terminal Input; the second transistor T2 is used according to the clock signal, Outputting a signal pulse from the output terminal; the third transistor T3 and the fourth transistor T4 are configured to pull down the potentials of the node Q and the output terminal respectively during the inactive period; the capacitor Cb is used for the secondary rise of the node Q potential to ensure the output Output signals of the normal output.
  • the purpose of the invention is to reduce the cost of the liquid crystal display by using the GOA technology and save the packaging time on the module process; develop the pull-down and compensation module in the GOA circuit of the IGZO to curb the leakage of the special TFT of the circuit; effectively save the number of TFTs, The parasitic capacitance of the TFT is reasonably reduced, and the power consumption of the circuit is saved.
  • the present invention provides a gate driving circuit based on an IGZO process, comprising: a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth-level GOA unit includes:
  • a pull-up circuit includes a first transistor, a gate of the first transistor is electrically connected to the first node, a source is electrically connected to the first clock signal, and a drain is electrically connected to the output end, and is configured to be based on the first clock The signal outputs a signal pulse at the output;
  • the gate of the second transistor is electrically connected to the first node, the source is electrically connected to the first clock signal, and the drain is electrically connected to the driving signal end, and is used according to the first a clock signal, wherein the driving signal is output by the driving signal terminal;
  • a pull-up control circuit includes a third transistor, the gate of the third transistor is electrically connected to a driving signal end of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the source is electrically connected to the The output stage of the N-1th GOA unit of the first stage of the Nth stage GOA unit, the drain is electrically connected to the first node, and is configured to turn on the pull-up circuit according to the driving signal sent by the driving signal end;
  • a pull-down holding circuit includes a first pull-down holding circuit and a second pull-down holding circuit;
  • the first pull-down holding circuit includes: a fourth transistor whose gate is electrically connected to the first clock signal, and the source is also electrically Connected to the first clock signal, the drain is electrically connected to the second node;
  • the fifth transistor has a gate electrically connected to the driving signal end, the source is electrically connected to the second node, and the drain is electrically connected to the second node a negative potential for pulling down the potential of the second node when the driving signal terminal is at a high potential;
  • the seventh transistor has a gate electrically connected to the second clock signal,
  • the pull-down circuit includes: a thirteenth transistor whose gate is electrically connected to a driving signal end of the N+1th GOA unit of the next-stage GOA unit, and the source is electrically connected to the driving signal end, and the drain Electropolarly connected to the third negative potential for pulling down the potential of the driving signal terminal during the inactive period, preventing the fifth transistor and the sixth transistor from generating leakage during the non-active period; the fifteenth crystal
  • the gate is electrically connected to the driving signal end of the N+1th GOA unit of the next-stage GOA unit, the source is electrically connected to the first node, and the drain is electrically connected to the second negative a potential for rapidly pulling down the potential of the first node at the beginning of the next adjacent phase after the output is completed;
  • the rising circuit includes a capacitor electrically connected to the first node and the output end respectively for respectively raising the potential of the first node to ensure a normal output of the output terminal of the pull-up circuit;
  • the conduction channel in the TFT switching device in the gate driving circuit based on the IGZO process is an oxide semiconductor conduction channel.
  • the gate and the source of the third transistor T3 are electrically connected to the startup signal of the circuit.
  • the gate of the thirteenth transistor and the gate of the fifteenth transistor are electrically connected to the start signal of the circuit; the gate of the eleventh transistor and the twelfth The gates of the transistors are electrically connected to the driving signal terminals of the second stage GOA unit.
  • the pull-down circuit further includes: a fourteenth transistor, the gate of which is electrically connected to the driving signal end of the N+1th GOA unit of the next stage of the Nth stage GOA unit, and the source is electrically connected to the output end, The drain is electrically connected to the first negative potential.
  • the gate of the fourteenth transistor is electrically connected to the startup signal of the circuit.
  • the relationship between the first negative potential, the second negative potential, and the third negative potential is: a third negative potential ⁇ a second negative potential ⁇ a first negative potential.
  • the first negative potential is mainly responsible for the potential of the pull-down output terminal
  • the second negative potential is mainly responsible for pulling down the potentials of the first node and the second node
  • the third negative potential is mainly responsible for pulling down the potential of the output terminal.
  • the first clock signal and the second clock signal are two high frequency clock signal sources whose phases are completely opposite.
  • a gate driving circuit based on the IGZO process of the present invention adopts three gradually decreasing negative potentials to respectively perform pull-down processing on the potentials of the output terminal, the first node, the second node, and the driving signal end,
  • the problem of critical TFT leakage of the gate drive circuit based on the IGZO process can be overcome.
  • the driving signal is used to process the potential of the second node, the load of the first node is weakened, and the first node is better stabilized, which is beneficial to the stable output of the output end of the circuit; the fifteenth transistor and the second negative potential of the pull-down circuit
  • the connection can quickly pull down the potential of the first node, reducing the delay of the first node.
  • the present invention cuts off the TFT for the characteristics of the IGZO material, effectively saves the number of TFTs, and rationally reduces the parasitic capacitance of the TFT, thereby effectively saving power consumption of the circuit.
  • Figure 1 is a circuit diagram of a common GOA
  • Figure 2 is a timing diagram corresponding to each signal in the circuit of Figure 1;
  • FIG. 3 is a circuit diagram of a first embodiment of a gate driving circuit based on an IGZO process of the present invention
  • FIG. 4 is a timing diagram of respective signals and nodes in a gate driving circuit based on the IGZO process of the present invention
  • FIG. 5 is a circuit diagram of a second embodiment of a gate driving circuit based on an IGZO process of the present invention
  • FIG. 6 is a circuit diagram of a first stage GOA unit in a first embodiment of a gate driving circuit based on an IGZO process of the present invention
  • FIG. 7 is a circuit diagram of a final stage GOA unit in a first embodiment of a gate driving circuit based on an IGZO process of the present invention
  • FIG. 8 is a circuit diagram of a final stage GOA unit in a second embodiment of a gate driving circuit based on an IGZO process of the present invention
  • FIG. 9 is a simulation experiment result diagram of a gate driving circuit based on the IGZO process of the present invention.
  • FIG. 3, FIG. 6, and FIG. 7, are the first embodiment of the gate driving circuit based on the IGZO process of the present invention.
  • the gate driving circuit based on the IGZO process comprises a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit comprises a pull-up control circuit 100, a pull-up circuit 200, a sub-transmission circuit 300, and a pull-down The circuit 400, the pull-and-hold circuit 500, and a rising circuit 600.
  • composition of each of the above circuits and the specific connection method are as follows:
  • the pull-up circuit 200 includes a first transistor T1.
  • the gate of the first transistor T1 is electrically connected to the first node Q(N), the source is electrically connected to the first clock signal CK, and the drain is electrically connected to the drain.
  • the first transistor T1 is configured to output a signal pulse at the output terminal G(N) according to the first clock signal CK.
  • the lower pass circuit 300 includes a second transistor T2.
  • the gate of the second transistor T2 is electrically connected to the first node Q(N), the source is electrically connected to the first clock signal CK, and the drain is electrically connected to the drain.
  • the second transistor T2 is configured to output a driving signal from the driving signal terminal ST(N) according to the first clock signal CK.
  • the pull-up control circuit 100 includes a third transistor T3, and the gate of the third transistor T3 is electrically connected to the driving signal terminal ST of the N-1th GOA unit of the previous stage of the Nth stage GOA unit (N- 1)
  • the source is electrically connected to the output stage G(N-1) of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the drain is electrically connected to the first node Q(N).
  • the third transistor T3 is configured to turn on the pull-up circuit 200 according to a pulse signal sent from the driving signal terminal ST(N-1).
  • the pull-down holding circuit 500 includes a first pull-down holding circuit 510 and a second pull-down holding circuit 520.
  • the first pull-down holding circuit 510 includes a fourth transistor T4 whose gate is electrically connected to the first clock signal CK, the source is also electrically connected to the first clock signal CK, and the drain is electrically connected to the second a node P(N); a fifth transistor T5 having a gate electrically connected to the driving signal terminal ST(N), a source electrically connected to the second node P(N), and a drain electrically connected to the second negative potential VSS2, the fifth transistor T5 is used to pull down the potential of the second node P(N) when the driving signal terminal ST(N) is at a high potential; the sixth transistor T6 whose gate is electrically connected to the Nth-level GOA unit a drive signal terminal ST(N-1) of the N-1th GOA unit of the previous stage, the source is electrically connected to the second node P(N), and the drain is electrically connected to the second
  • the six-transistor T6 is used to pull down the potential of the second node P(N) when the driving signal terminal ST(N-1) is at a high potential; the seventh transistor T7 whose gate is electrically connected to the second clock signal XCK, the source Electrically connected to the first clock signal CK, the drain is electrically connected to the second node P (N); the eighth transistor T8, the gate of which is electrically connected to the second node P (N), the source Electrically connected to the output terminal G(N), the drain is electrically connected to the first negative potential VSS1; the ninth transistor T9 has a gate electrically connected to the second node P(N), and the source is electrically connected to the first a node Q(N), the drain is electrically connected to the second negative potential VSS2; the tenth transistor T10 has a gate electrically connected to the second node P(N), and the source is electrically connected to the driving signal terminal ST ( N), the drain is electrically connected to the third negative potential VSS3.
  • the second pull-down holding circuit 520 includes: an eleventh transistor T11 whose gate is electrically connected to the driving signal terminal ST(N+2) of the lower second-stage N+2-level GOA unit of the N-th stage GOA unit.
  • the source is electrically connected to the first node Q(N)
  • the drain is electrically connected to the second negative potential VSS2
  • the twelfth transistor T12 is electrically connected to the lower second of the Nth stage GOA unit.
  • the driving signal terminal ST(N+2) of the N+2th GOA unit is electrically connected to the output terminal G(N), and the drain is electrically connected to the first negative potential VSS1.
  • the pull-down circuit 400 includes a thirteenth transistor T13 whose gate is electrically connected to the driving signal terminal ST(N+1) of the next-stage N+1th GOA unit of the Nth stage GOA unit, the source The pole is electrically connected to the driving signal terminal ST(N), and the drain is electrically connected to the third negative potential VSS3.
  • the thirteenth transistor T13 is used to pull down the potential of the driving signal terminal ST(N) during the inactive period to prevent the first
  • the five transistors T5 and the sixth transistor T6 generate leakage during the inactive period;
  • the fifteenth transistor T15 has a gate electrically connected to the driving signal terminal ST of the next-stage N+1th GOA unit of the Nth stage GOA unit.
  • the source is electrically connected to the first node Q(N), and the drain is electrically connected to the second negative The potential VSS2, the fifteenth transistor T15 is used to quickly pull down the potential of the first node Q(N) at the beginning of the next adjacent stage after the output G(N) output is completed.
  • the rising circuit 600 includes a capacitor Cb.
  • the two ends of the capacitor Cb are electrically connected to the first node Q(N) and the output terminal G(N), respectively, for raising the potential of the first node Q(N) twice.
  • the normal output of the output terminal G(N) of the pull-up circuit 200 is ensured.
  • the three negative potential first negative potential VSS1, the second negative potential VSS2, and the third negative potential VSS3 are different in voltage, and the relationship between the three is: the third negative potential VSS3 ⁇ second negative potential VSS2 ⁇ first negative potential VSS1.
  • the first negative potential VSS1 is mainly responsible for the potential of the pull-down output terminal G(N)
  • the second negative potential VSS2 is mainly responsible for pulling down the potential of the first node Q(N) and the second node P(N)
  • the third negative potential VSS3 Mainly responsible for the potential of the pull-down drive output ST (N).
  • the gate and the source of the third transistor T3 are electrically connected to the start signal STV of the circuit.
  • the gate of the thirteenth transistor T13 and the gate of the fifteenth transistor T15 are electrically connected to the start signal of the circuit.
  • the gate of the eleventh transistor T11 and the gate of the twelfth transistor T12 are electrically connected to the driving signal terminal ST(2) of the second-stage GOA unit.
  • the conduction channel in each of the TFT switching devices in the gate driving circuit based on the IGZO process of the present invention is an oxide semiconductor conduction channel.
  • the first clock signal CK and the second clock signal XCK are two sources of high frequency clock signals whose phases are completely opposite.
  • FIG. 4 is a timing diagram of each signal and node in the gate driving circuit based on the IGZO process of the present invention.
  • the eighth transistor T8 is used to maintain the output terminal G(N) at a low level. Level; the ninth transistor T9 is used to maintain the first node Q(N) at a low level; and the fifth transistor T5 is used to set the second node P(N) when the driving signal terminal ST(N) is at a high level.
  • the potential of the second transistor T6 is used to pull down the potential of the second node P(N) when the driving signal terminal ST(N-1) is at a high level, thereby turning off the pull-down holding circuit 500 during the action, The effect on the output of the first node Q(N) and the output terminal G(N) is prevented.
  • the potential of the second negative potential VSS2 is lower than the first negative potential VSS1, and the potential of the second node P(N) is effectively reduced by the two-stage voltage division principle, and the second node P(N) is The lower the pull, the better the three transistors T8, T9 and T10 connected to it are connected, which prevents the discharge of the output terminal G(N) from causing an output abnormality and also lowers the first node Q(N). Potential to better turn off both T1 and T2 transistors.
  • the tenth transistor T10 and the thirteenth transistor T13 are responsible for the pull-down processing of the driving signal terminal ST(N), and the potential of the third negative potential VSS3 is mainly used to pull down
  • the potential of the driving signal terminal ST(N) prevents the two transistors of the fifth transistor T5 and the sixth transistor T6 from generating leakage during the inactive period.
  • the fifteenth transistor T15 is responsible for performing pull-down processing on the first node Q(N) immediately after the output G(N) is outputted, and ensuring that the first node Q(N) is fast from a high potential. Lowering to a lower potential, and the drain of the fifteenth transistor T15 is connected to the second negative potential VSS2, the first node Q(N) can be quickly pulled down to a low potential after the output is completed.
  • FIG. 5 and FIG. 8 is a second embodiment of the gate driving circuit based on the IGZO process of the present invention.
  • the components, the connection relationship, the function and the operation principle of the same reference numerals in FIG. 5 and FIG. 3 are the same, and are not described herein again.
  • the difference between the second embodiment and the first embodiment is that the fourteenth transistor T14 is added to the pull-down circuit 400, and the gate thereof is electrically connected to the next-stage N+1th GOA of the Nth-level GOA unit.
  • the driving signal terminal ST(N+1) of the cell is electrically connected to the output terminal G(N), and the drain is electrically connected to the first negative potential VSS1.
  • the fourteenth transistor T14 is used to pull down the potential of the output terminal G(N) during inactive periods. Since the present invention is based on the GOA circuit of the IGZO process, the corresponding W will be small, the parasitic capacitance will be small, the ripple current of the corresponding circuit is also small, and the influence on the output of the output terminal G(N) is not a-Si. serious. Therefore, the fourteenth transistor T14 can also be omitted in the actual circuit design, which saves wiring space and reduces power consumption. In addition, as shown in FIG. 8, in the second embodiment, in the last stage connection relationship of the gate driving circuit of the IGZO process, the gate of the fourteenth transistor T14 is electrically connected to the circuit. Kai Motion signal STV.
  • the second embodiment is the same as the first embodiment, and details are not described herein again.
  • FIG. 9 is a simulation effect diagram of a gate driving circuit based on the IGZO process in a 60-level circuit according to the present invention. It can be seen from the figure that the output is good and the expected effect can be achieved.
  • the gate driving circuit based on the IGZO process of the present invention uses three gradually decreasing negative potentials to respectively perform pull-down processing on the potentials of the output terminals, the first node, the second node, and the driving signal terminals. Overcome the problem of critical TFT leakage in gate drive circuits based on IGZO processes.
  • the driving signal is used to process the potential of the second node, the load of the first node is weakened, and the first node is better stabilized, which is beneficial to the stable output of the output end of the circuit; the fifteenth transistor and the second negative potential of the pull-down circuit
  • the VSS2 connection quickly pulls down the first node potential, reducing the delay of the first node.
  • the present invention cuts off the TFT for the characteristics of the IGZO material, effectively saves the number of TFTs, and rationally reduces the parasitic capacitance of the TFT, thereby effectively saving power consumption of the circuit.

Abstract

一种基于IGZO制程的栅极驱动电路，包括级联的多个GOA单元，第N级GOA单元包括一上拉控制电路（100）、一上拉电路（200）、一下传电路（300）、一下拉电路（400）、一下拉保持电路（500）、一上升电路（600），并引入了第一负电位（VSS1）、第二负电位（VSS2）与第三负电位（VSS3），该三个负电位依次降低，分别对输出端（G（N）），第一节点（Q（N））、第二节点（P（N）），驱动信号端（ST（N））做下拉处理；有效防止了电路特殊TFT漏电的问题。该基于IGZO制程的栅极驱动电路中的TFT开关的导通沟道为氧化物半导体导通沟道。

Description

基于IGZO制程的栅极驱动电路 技术领域
本发明涉及液晶显示领域，尤其涉及一种基于IGZO制程的栅极驱动电路。
背景技术
GOA(Gate Drive On Array)，是利用薄膜晶体管液晶显示器Array制程将栅极驱动器制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。
GOA电路主要由上拉电路(Pull-up part)、上拉控制电路(Pull-up control part)、下传电路(Transfer part)、下拉电路(Pull-down part)、下拉保持电路(Pull-down Holding part)、以及负责电位抬升的上升电路(Boost part)组成。
上拉电路主要负责将输入的时钟信号(Clock)输出至薄膜晶体管(thin film transistor，TFT)的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉保持电路则负责将扫描信号和上拉电路的信号(亦即施加于Q点的信号)保持在关闭状态(即设定的负电位)，通常有两 个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
IGZO(indium gallium zinc oxide)是一种含有铟、镓和锌的非晶氧化物，载流子迁移率是非晶硅的20～30倍，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在TFT-LCD中成为可能。另外，由于晶体管数量减少和提高了每个像素的透光率，IGZO显示器具有更高的能效水平，而且效率更高。
IGZO的GOA电路未来有可能取代a-Si的TFT，而现有技术中针对IGZO的GOA开发很少，尤其是针对大尺寸的GOA电路，需要克服很多由于IGZO材料本身带来的问题，需要克服的主要问题为：(1)Vth向负向漂移的问题；(2)SS区太陡峭，微小的电压变化将会引起电流数量级的变化，将会直接导致GOA电路的关键TFT漏电，造成IGZO的GOA功能失效。
请参阅图1以及图2，图1、图2为常见GOA电路的经典模块及其对应各个信号的时序图，该常见GOA电路的包括第一晶体管T1，其栅极电性连接于输入信号端Input，源极也电性连接于输入信号端Input，漏极电性 连接于节点Q；第二晶体管T2，其栅极电性连接于节点Q，源极电性连接于时钟信号Clock，漏极电性连接于输出端Output；第三晶体管T3，其栅极电性连接于复位信号端Reset，源极电性连接于输出端Output，漏极电性连接于一负电位VSS；第四晶体管T4，其栅极电性连接于复位信号端Reset，源极电性连接于节点Q，漏极电性连接于一负电位VSS；电容Cb，其一端连接于节点Q，另一端与输出端Output相连；图1中还包括下拉&补偿模块，其包括四条引线分别与节点Q，时钟信号Clock，输出端Output，负电位VSS相连；所述第一晶体管T1用于依据输入信号端Input输入的信号导通第二晶体管T2；所述第二晶体管T2用来依据时钟信号，由输出端输出信号脉冲；所述第三晶体管T3与第四晶体管T4用于在非作用期间分别下拉节点Q与输出端Output的电位；电容Cb用于节点Q电位的二次抬升，确保输出端Output信号的正常输出。
发明内容
本发明的目的为：利用GOA技术降低液晶显示器的成本，节省模组制程上的封装时间；开发IGZO的GOA电路中的下拉与补偿模块，遏制电路特殊TFT的漏电；有效的节省TFT的数量，合理的减少了TFT的寄生电容，节约电路的功耗。
为实现上述目的，本发明提供了一种基于IGZO制程的栅极驱动电路，包括：级联的多个GOA单元，设N为正整数，第N级GOA单元包括：
上拉电路，包括第一晶体管，该第一晶体管的栅极电性连接于第一节点，源极电性连接于第一时钟信号，漏极电性连接于输出端，用来依据第一时钟信号在输出端输出信号脉冲；
下传电路，包括第二晶体管，该第二晶体管的栅极电性连接于第一节点，源极电性连接于第一时钟信号，漏极电性连接于驱动信号端，用来依据第一时钟信号，由驱动信号端输出驱动信号；
上拉控制电路，包括第三晶体管，该第三晶体管的栅极电性连接于该第N级GOA单元的前一级第N-1级GOA单元的驱动信号端，源极电性连接于该第N级GOA单元的前一级第N-1级GOA单元输出端，漏极电性连接于第一节点，用来依据驱动信号端发出的驱动信号，导通上拉电路；
下拉保持电路，包括第一下拉保持电路与第二下拉保持电路；所述第一下拉保持电路，包括：第四晶体管，其栅极电性连接于第一时钟信号，源极也电性连接于第一时钟信号，漏极电性连接于第二节点；第五晶体管，其栅极电性连接于驱动信号端，源极电性连接于第二节点，漏极电性连接于第二负电位，用于在驱动信号端处于高电位时下拉第二节点的电位；第 六晶体管，其栅极电性连接于该第N级GOA单元的前一级第N-1级GOA单元的驱动信号端，源极电性连接于第二节点，漏极电性连接于第二负电位，用于在驱动信号端处于高电位时下拉第二节点的电位；第七晶体管，其栅极电性连接于第二时钟信号，源极电性连接于第一时钟信号，漏极电性连接于第二节点；第八晶体管，其栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一负电位；第九晶体管，其栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二负电位；第十晶体管，其栅极电性连接于第二节点，源极电性连接于驱动信号端，漏极电性连接于第三负电位；所述第二下拉保持电路，包括：第十一晶体管，其栅极电性连接于该第N级GOA单元的下二级第N+2级GOA单元的驱动信号端，源极电性连接于第一节点，漏极电性连接于第二负电位；第十二晶体管，其栅极电性连接于该第N级GOA单元的下二级第N+2级GOA单元的驱动信号端，源极电性连接于输出端，漏极电性连接于第一负电位；
下拉电路，包括：第十三晶体管，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端，源极电性连接于驱动信号端，漏极电性连接于第三负电位，用于在非作用期间下拉驱动信号端的电位，防止第五晶体管与第六晶体管在非作用期间产生漏电；第十五晶体 管，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端，源极电性连接于第一节点，漏极电性连接于第二负电位，用于在输出端输出完成后相邻的下一阶段开始时迅速下拉第一节点的电位；
上升电路，包括一电容，该电容两端分别电性连接于第一节点与输出端，用来二次抬升第一节点的电位，确保上拉电路输出端的正常输出；
该基于IGZO制程的栅极驱动电路中的TFT开关器件中的导通沟道为氧化物半导体导通沟道。
所述栅极驱动电路的第一级连接关系中，第三晶体管T3的栅极与源极均电性连接于电路的启动信号。
所述栅极驱动电路的最后一级连接关系中，第十三晶体管的栅极与第十五晶体管的栅极均电性连接于电路的启动信号；第十一晶体管的栅极与第十二晶体管的栅极均电性连接于第二级GOA单元的驱动信号端。
所述下拉电路还包括：第十四晶体管，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端，源极电性连接于输出端，漏极电性连接于第一负电位。
所述栅极驱动电路的最后一级连接关系中，第十四晶体管的栅极电性连接于电路的启动信号。
所述第一负电位、第二负电位与第三负电位的关系为：第三负电位<第二负电位<第一负电位。
所述第一负电位主要负责下拉输出端的电位，第二负电位主要负责下拉第一节点和第二节点的电位，第三负电位主要负责下拉驱动输出端的电位。
所述第一时钟信号与第二时钟信号是两个相位完全相反的高频时钟信号源。
本发明的有益效果：本发明的一种基于IGZO制程的栅极驱动电路，采用了三个逐渐递减的负电位分别对输出端，第一节点、第二节点，驱动信号端的电位做下拉处理，可以克服基于IGZO制程的栅极驱动电路的关键TFT漏电的问题。此外，采用驱动信号来处理第二节点的电位，减弱第一节点的负载作用，较好的稳定第一节点，有利于电路的输出端的稳定输出；下拉电路的第十五晶体管与第二负电位相连可以迅速下拉第一节点的电位，减小第一节点的延迟。最后，本发明针对IGZO材料的特点对TFT做了删减，有效的节省TFT的数量，合理的减小了TFT的寄生电容，可以有效的节约电路的功耗。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为常见GOA的电路图；
图2为对应于图1电路中各个信号的时序图；
图3为本发明基于IGZO制程的栅极驱动电路的第一实施例的电路图；
图4为本发明基于IGZO制程的栅极驱动电路中各个信号和节点的时序图；
图5为本发明基于IGZO制程的栅极驱动电路的第二实施例的电路图；
图6为本发明基于IGZO制程的栅极驱动电路第一实施例中第一级GOA单元的电路图；
图7为本发明基于IGZO制程的栅极驱动电路第一实施例中最后一级GOA单元的电路图；
图8为本发明基于IGZO制程的栅极驱动电路第二实施例中最后一级GOA单元的电路图；
图9为本发明基于IGZO制程的栅极驱动电路的仿真实验效果图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图3、图6、图7，为本发明基于IGZO制程的栅极驱动电路的第一实施例。该基于IGZO制程的栅极驱动电路包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制电路100、一上拉电路200、一下传电路300、一下拉电路400、一下拉保持电路500、一上升电路600。
上述各电路的组成以及具体的连接方式如下：
所述上拉电路200包含第一晶体管T1，该第一晶体管T1的栅极电性连接于第一节点Q(N)，源极电性连接于第一时钟信号CK，漏极电性连接于输出端G(N)。该第一晶体管T1用来依据第一时钟信号CK在输出端G(N)输出信号脉冲。
所述下传电路300包括第二晶体管T2，该第二晶体管T2的栅极电性连接于第一节点Q(N)，源极电性连接于第一时钟信号CK，漏极电性连接于驱动信号端ST(N)。该第二晶体管T2用来依据第一时钟信号CK，由驱动信号端ST(N)输出驱动信号。
所述上拉控制电路100包括第三晶体管T3，该第三晶体管T3的栅极电性连接于该第N级GOA单元的前一级第N-1级GOA单元的驱动信号端ST(N-1)，源极电性连接于该第N级GOA单元的前一级第N-1级GOA单元输出端G(N-1)，漏极电性连接于第一节点Q(N)。该第三晶体管T3用来依据驱动信号端ST(N-1)发出的脉冲信号，导通所述上拉电路200。
所述下拉保持电路500，包括第一下拉保持电路510与第二下拉保持电路520。所述第一下拉保持电路510包括：第四晶体管T4，其栅极电性连接于第一时钟信号CK，源极也电性连接于第一时钟信号CK，漏极电性连接于第二节点P(N)；第五晶体管T5，其栅极电性连接于驱动信号端ST(N)，源极电性连接于第二节点P(N)，漏极电性连接于第二负电位VSS2，该第五晶体管T5用于在驱动信号端ST(N)处于高电位时下拉第二节点P(N)的电位；第六晶体管T6，其栅极电性连接于该第N级GOA单元的前一级第N-1级GOA单元的驱动信号端ST(N-1)，源极电性连接于第二节点P(N)，漏极电性连接于第二负电位VSS2，该第六晶体管T6用于在驱动信号端ST(N-1)处于高电位时下拉第二节点P(N)的电位；第七晶体管T7，其栅极电性连接于第二时钟信号XCK，源极电性连接于第一时钟信号CK，漏极电性连接于第二节点P(N)；第八晶体管T8，其栅极电性连接于第二节点P(N)，源极 电性连接于输出端G(N)，漏极电性连接于第一负电位VSS1；第九晶体管T9，其栅极电性连接于第二节点P(N)，源极电性连接于第一节点Q(N)，漏极电性连接于第二负电位VSS2；第十晶体管T10，其栅极电性连接于第二节点P(N)，源极电性连接于驱动信号端ST(N)，漏极电性连接于第三负电位VSS3。所述第二下拉保持电路520包括：第十一晶体管T11，其栅极电性连接于该第N级GOA单元的下二级第N+2级GOA单元的驱动信号端ST(N+2)，源极电性连接于第一节点Q(N)，漏极电性连接于第二负电位VSS2；第十二晶体管T12，其栅极电性连接于该第N级GOA单元的下二级第N+2级GOA单元的驱动信号端ST(N+2)，源极电性连接于输出端G(N)，漏极电性连接于第一负电位VSS1。
所述下拉电路400，包括：第十三晶体管T13，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端ST(N+1)，源极电性连接于驱动信号端ST(N)，漏极电性连接于第三负电位VSS3，该第十三晶体管T13用于在非作用期间下拉驱动信号端ST(N)的电位，防止第五晶体管T5与第六晶体管T6在非作用期间产生漏电；第十五晶体管T15，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端ST(N+1)，源极电性连接于第一节点Q(N)，漏极电性连接于第二负 电位VSS2，该第十五晶体管T15用于在输出端G(N)输出完成后相邻的下一阶段开始时迅速下拉第一节点Q(N)的电位。
所述上升电路600包括一电容Cb，该电容Cb两端分别电性连接于第一节点Q(N)与输出端G(N)，用来二次抬升第一节点Q(N)的电位，确保上拉电路200输出端G(N)的正常输出。
特别需要说明的是，上述电路中引入的三个负电位第一负电位VSS1、第二负电位VSS2与第三负电位VSS3的电压高低各不相同，且三者的关系为：第三负电位VSS3<第二负电位VSS2<第一负电位VSS1。所述第一负电位VSS1主要负责下拉输出端G(N)的电位，第二负电位VSS2主要负责下拉第一节点Q(N)和第二节点P(N)的电位，第三负电位VSS3主要负责下拉驱动输出端ST(N)的电位。
如图6所示，本发明基于IGZO制程的栅极驱动电路的第一级连接关系中，第三晶体管T3的栅极与源极均电性连接于电路的启动信号STV。
如图7所示，本发明基于IGZO制程的栅极驱动电路的最后一级连接关系中，第十三晶体管T13的栅极与第十五晶体管T15的栅极均电性连接于电路的启动信号STV；第十一晶体管T11的栅极与第十二晶体管T12的栅极均电性连接于第二级GOA单元的驱动信号端ST(2)。
此外，本发明基于IGZO制程的栅极驱动电路中各TFT开关器件中的导通沟道均为氧化物半导体导通沟道。
所述第一时钟信号CK与第二时钟信号XCK是两个相位完全相反的高频时钟信号源。
请进一步的，请参阅图4，为本发明基于IGZO制程的栅极驱动电路中各个信号和节点的时序图，结合图3可知：第八晶体管T8用来将输出端G(N)维持在低电平；第九晶体管T9用来将第一节点Q(N)维持在低电平；第五晶体管T5用来当驱动信号端ST(N)处于高电平的时候将第二节点P(N)的电位下拉；第六晶体管T6用来当驱动信号端ST(N-1)处于高电平的时候将第二节点P(N)的电位下拉，从而关闭作用期间的下拉保持电路500，以防止对第一节点Q(N)和输出端G(N)输出的影响。
所述第二负电位VSS2的电位低于第一负电位VSS1，利用了两段分压原理有效的降低了第二节点P(N)的电位，而第二节点P(N)在作用期间被拉得越低，与其连接的三个晶体管T8、T9和T10就关得越好，可防止对输出端G(N)的放电导致输出异常，同时也拉低了第一节点Q(N)的电位，以更好的关闭T1和T2两个晶体管。第十晶体管T10和第十三晶体管T13负责对驱动信号端ST(N)的下拉处理，第三负电位VSS3的电位主要是用来拉低 驱动信号端ST(N)的电位，防止第五晶体管T5和第六晶体管T6两个晶体管在非作用期间产生漏电。第十五晶体管T15负责在输出端G(N)输出完后紧接着于相邻的下一阶段对第一节点Q(N)做下拉处理，保证第一节点Q(N)从高电位快速的降低到低电位，并且第十五晶体管T15的漏极接第二负电位VSS2，能够将第一节点Q(N)在输出完之后迅速下拉到低电位。
请同时参阅图5、图8，为本发明基于IGZO制程的栅极驱动电路的第二实施例。图5与图3中具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。该第二实施例与第一实施例的区别在于，所述下拉电路400中增加第十四晶体管T14，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端ST(N+1)，源极电性连接于输出端G(N)，漏极电性连接于第一负电位VSS1。所述第十四晶体管T14用于在非作用期间下拉输出端G(N)的电位。由于本发明是基于IGZO制程的GOA电路，对应的W会很小，寄生电容也会较小，相应电路的波纹电流也很小，对输出端G(N)的输出的影响没有a-Si那么严重。因此在实际电路设计中也可以省掉该第十四晶体管T14，节约布线空间，减小功耗。此外，如图8所示，在该第二实施例中，本发明基于IGZO制程的栅极驱动电路的最后一级连接关系中，所述第十四晶体管T14的栅极电性连接于电路的启 动信号STV。
在其它方面，第二实施例均与第一实施例相同，此处不再赘述。
请参阅图9，为本发明基于IGZO制程的栅极驱动电路在60级电路中实施的仿真效果图，从图中可以看出，输出良好，可以达到预期的效果。
综上所述，本发明的一种基于IGZO制程的栅极驱动电路，采用了三个逐渐递减的负电位分别对输出端，第一节点、第二节点，驱动信号端的电位做下拉处理，可以克服基于IGZO制程的栅极驱动电路的关键TFT漏电的问题。此外，采用驱动信号来处理第二节点的电位，减弱第一节点的负载作用，较好的稳定第一节点，有利于电路的输出端的稳定输出；下拉电路的第十五晶体管与第二负电位VSS2相连迅速下拉第一节点电位，减小第一节点的延迟。最后，本发明针对IGZO材料的特点对TFT做了删减，有效的节省TFT的数量，合理的减小了TFT的寄生电容，可以有效的节约电路的功耗。
虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (8)

  1. 一种基于IGZO制程的栅极驱动电路，包括：级联的多个GOA单元，设N为正整数，第N级GOA单元包括：
    上拉电路，包括第一晶体管，该第一晶体管的栅极电性连接于第一节点，源极电性连接于第一时钟信号，漏极电性连接于输出端，用来依据第一时钟信号在输出端输出信号脉冲；
    下传电路，包括第二晶体管，该第二晶体管的栅极电性连接于第一节点，源极电性连接于第一时钟信号，漏极电性连接于驱动信号端，用来依据第一时钟信号，由驱动信号端输出驱动信号；
    上拉控制电路，包括第三晶体管，该第三晶体管的栅极电性连接于该第N级GOA单元的前一级第N-1级GOA单元的驱动信号端，源极电性连接于该第N级GOA单元的前一级第N-1级GOA单元输出端，漏极电性连接于第一节点，用来依据驱动信号端发出的驱动信号，导通上拉电路；
    下拉保持电路，包括第一下拉保持电路与第二下拉保持电路；所述第一下拉保持电路，包括：第四晶体管，其栅极电性连接于第一时钟信号，源极也电性连接于第一时钟信号，漏极电性连接于第二节点；第五晶体管，其栅极电性连接于驱动信号端，源极电性连接于第二节点，漏极电性连接 于第二负电位，用于在驱动信号端处于高电位时下拉第二节点的电位；第六晶体管，其栅极电性连接于该第N级GOA单元的前一级第N-1级GOA单元的驱动信号端，源极电性连接于第二节点，漏极电性连接于第二负电位，用于在驱动信号端处于高电位时下拉第二节点的电位；第七晶体管，其栅极电性连接于第二时钟信号，源极电性连接于第一时钟信号，漏极电性连接于第二节点；第八晶体管，其栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一负电位；第九晶体管，其栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二负电位；第十晶体管，其栅极电性连接于第二节点，源极电性连接于驱动信号端，漏极电性连接于第三负电位；
    所述第二下拉保持电路，包括：第十一晶体管，其栅极电性连接于该第N级GOA单元的下二级第N+2级GOA单元的驱动信号端，源极电性连接于第一节点，漏极电性连接于第二负电位；第十二晶体管，其栅极电性连接于该第N级GOA单元的下二级第N+2级GOA单元的驱动信号端，源极电性连接于输出端，漏极电性连接于第一负电位；
    下拉电路，包括：第十三晶体管，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端，源极电性连接于驱动信 号端，漏极电性连接于第三负电位，用于在非作用期间下拉驱动信号端的电位，防止第五晶体管与第六晶体管在非作用期间产生漏电；第十五晶体管，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端，源极电性连接于第一节点，漏极电性连接于第二负电位，用于在输出端输出完成后相邻的下一阶段开始时迅速下拉第一节点的电位；
    上升电路，包括一电容，该电容两端分别电性连接于第一节点与输出端，用来二次抬升第一节点的电位，确保上拉电路输出端的正常输出；
    该基于IGZO制程的栅极驱动电路中的TFT开关器件中的导通沟道为氧化物半导体导通沟道。
  2. 如权利要求1所述的基于IGZO制程的栅极驱动电路，其中，所述栅极驱动电路的第一级连接关系中，第三晶体管的栅极与源极均电性连接于电路的启动信号。
  3. 如权利要求1所述的基于IGZO制程的栅极驱动电路，其中，所述栅极驱动电路的最后一级连接关系中，第十三晶体管的栅极与第十五晶体管的栅极均电性连接于电路的启动信号；第十一晶体管的栅极与第十二晶体管的栅极均电性连接于第二级GOA单元的驱动信号端。
  4. 如权利要求1所述的基于IGZO制程的栅极驱动电路，其中，所述 下拉电路还包括：第十四晶体管，其栅极电性连接于该第N级GOA单元的下一级第N+1级GOA单元的驱动信号端，源极电性连接于输出端，漏极电性连接于第一负电位。
  5. 如权利要求4所述的基于IGZO制程的栅极驱动电路，其中，所述栅极驱动电路的最后一级连接关系中，第十四晶体管的栅极电性连接于电路的启动信号。
  6. 如权利要求1所述的基于IGZO制程的栅极驱动电路，其中，所述第一负电位、第二负电位与第三负电位的关系为：第三负电位<第二负电位<第一负电位。
  7. 如权利要求6所述的基于IGZO制程的栅极驱动电路，其中，所述第一负电位主要负责下拉输出端的电位，第二负电位主要负责下拉第一节点和第二节点的电位，第三负电位主要负责下拉驱动输出端的电位。
  8. 如权利要求1所述的基于IGZO制程的栅极驱动电路，其中，所述第一时钟信号与第二时钟信号是两个相位完全相反的高频时钟信号源。
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CN103700705A (zh) * 2013-12-09 2014-04-02 深圳市华星光电技术有限公司 一种igzo电晶体结构及其制造方法、显示面板
CN103680453A (zh) * 2013-12-20 2014-03-26 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN103928008A (zh) * 2014-04-24 2014-07-16 深圳市华星光电技术有限公司 一种用于液晶显示的goa电路及液晶显示装置
CN103928009A (zh) * 2014-04-29 2014-07-16 深圳市华星光电技术有限公司 用于窄边框液晶显示器的栅极驱动器
CN104157260A (zh) * 2014-09-10 2014-11-19 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路

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KR20170035973A (ko) 2017-03-31
DE112014006943T5 (de) 2017-06-22
JP2017535105A (ja) 2017-11-24
GB2543235A (en) 2017-04-12
US20160267864A1 (en) 2016-09-15
US9489907B2 (en) 2016-11-08
JP6423957B2 (ja) 2018-11-14
GB201702185D0 (en) 2017-03-29
KR101944641B1 (ko) 2019-01-31
GB2543235B (en) 2020-07-15
CN104157259A (zh) 2014-11-19

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