WO2016061851A1 - 用于氧化物半导体薄膜晶体管的行驱动电路 - Google Patents

用于氧化物半导体薄膜晶体管的行驱动电路 Download PDF

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WO2016061851A1
WO2016061851A1 PCT/CN2014/090286 CN2014090286W WO2016061851A1 WO 2016061851 A1 WO2016061851 A1 WO 2016061851A1 CN 2014090286 W CN2014090286 W CN 2014090286W WO 2016061851 A1 WO2016061851 A1 WO 2016061851A1
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electrically connected
transistor
source
node
gate
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PCT/CN2014/090286
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English (en)
French (fr)
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戴超
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深圳市华星光电技术有限公司
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Priority to GB1702109.8A priority Critical patent/GB2543700B/en
Priority to KR1020177003727A priority patent/KR101940933B1/ko
Priority to JP2017520956A priority patent/JP6440224B2/ja
Priority to US14/424,147 priority patent/US9461627B2/en
Publication of WO2016061851A1 publication Critical patent/WO2016061851A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a row driving circuit for an oxide semiconductor thin film transistor.
  • GOA Gate Drive On Array
  • a gate scan driving signal circuit is fabricated on a thin film transistor array substrate by using a thin film transistor liquid crystal display Array process to realize Gate progressive scanning.
  • the threshold voltage Vth of the amorphous silicon thin film transistor is generally greater than 0 V, and the voltage of the subthreshold region is relatively large with respect to the current swing, even some transistors in the circuit design
  • the leakage current generated by the voltage Vgs between the gate and the source of the transistor at a frequency equal to 0V during operation is also small.
  • the threshold voltage Vth of the thin film transistor is sometimes less than 0V, and the voltage of the subthreshold region is relative to the current.
  • the row driver circuit for the oxide semiconductor thin film transistor needs to adopt some special design schemes to avoid some important thin film transistor operations in the vicinity of Vgs equal to 0V.
  • FIG. 1 it is a conventional row driving circuit applied to an amorphous silicon thin film transistor, wherein the main structure of the circuit includes: a pull-up control portion 100, a pull-up portion 200, a downlink portion 300, and a first pull-down. Portion 400, bootstrap capacitor 500 and pull-down sustain portion 600.
  • the control signal source applied to the row driving circuit of the amorphous silicon thin film transistor mainly includes a high frequency clock signal CK(n), a constant voltage low potential source VSS, and a low frequency clock signal LC1 and LC2, wherein LC1 and LC2 are two phases completely.
  • the opposite source of low frequency signals In general, the low potential of CK(n), LC1, and LC2 will be less than VSS, but the critical nodes Q(N) and G(N) in the circuit will be pulled down to VSS during the inactive period.
  • the off-state operating voltage Vgs ⁇ 0V, and Q(N) also has high and low fluctuations, That is to say, if there is a case where Vgs>0V, if the circuit is directly applied to the driving circuit design of the oxide semiconductor thin film transistor, there is a large leakage current, and it is impossible to ensure that the output terminal G(N) is maintained during the inactive period. At low potentials, this can result in poor output at the output G(N) and poor functionality of the GOA circuit.
  • T31 and T41 of the first pull-down portion 400 there is a problem with the thirty-first transistor T31 and the forty-first transistor T41 of the first pull-down portion 400, that during the action of Q(N) and G(N) being at a high potential, T31 and T41 Leakage can cause distortion of the output waveforms of Q(N) and G(N), resulting in poor functionality of the GOA circuit under severe conditions (eg, high temperature operation).
  • the circuit design uses the low potential of LC1 or LC2 to control the pull-down of P(N) or K(N) during the action, it is ensured that during the action period P(N) and K( The low potential of N) is less than VSS, ensuring that the Vgs ⁇ 0V of the thirty-second, thirty-three, forty-two, and forty-three transistors T32, T33, T42, and T43 are in a good off state, thereby reducing the pull-down sustain circuit portion.
  • the bridge TFT T55 of the pull-down sustaining circuit portion has Vgs>0V during the inactive period, which causes the high potential of P(N) or K(N) during the inactive period to be unacceptably high, thereby It will affect the pull-down maintenance effect of T32, T33, T42 and T43 on Q(N) and G(N).
  • this can be improved in the design by adjusting the size of the element, there is also a problem of an increase in leakage current due to an increase in size.
  • the present invention provides a row driving circuit for an oxide semiconductor thin film transistor, comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth-level GOA unit comprises: a pull-up control portion, a a pull-up portion, a next-pass portion, a first pull-down portion, a bootstrap capacitor portion, and a pull-down sustain circuit portion;
  • the pull-up control portion includes an eleventh transistor, and a gate of the eleventh transistor is electrically connected to a driving signal end of the N-2th GOA unit of the first two stages of the GOA unit of the Nth stage GOA unit, and a source
  • the output terminal of the Nth-level GOA unit of the first two stages of the GOA unit of the Nth stage GOA unit is electrically connected to the first node.
  • the pull-up portion includes a twenty-first transistor, the gate of the twenty-first transistor is electrically connected to the first node, the source is electrically connected to the high-frequency clock signal, and the drain is electrically connected to the output end;
  • the lower pass portion includes a twenty-second transistor, the gate of the second twelve transistor is electrically connected to the first node, the source is electrically connected to the high frequency clock signal, and the drain is electrically connected to the driving output end;
  • the first pull-down portion includes a forty-first transistor, and the gate of the forty-first transistor is electrically The output is connected to the output terminal of the N+3th GOA unit of the lower third-stage GOA unit of the Nth-level GOA unit, the drain is electrically connected to the first node, and the source is electrically connected to the output end.
  • the bootstrap capacitor portion includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the output end.
  • the pull-down sustaining portion includes: a forty-second transistor, the gate of the forty-second transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the second constant voltage Negative potential source;
  • the gate of the thirty-second transistor is electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected to the first constant voltage negative potential source;
  • the gate and the source of the fifty-first transistor are electrically connected to the first low frequency signal source, and the drain is electrically connected to the fourth node;
  • the gate of the fifty-second transistor is electrically connected to the first node, the source is electrically connected to the fourth node, and the drain is electrically connected to the first constant voltage negative potential source;
  • the gate of the fifty-third transistor is electrically connected to the fourth node, the source is electrically connected to the first low-frequency signal source, and the drain is electrically connected to the second node;
  • the gate of the fifty-fourth transistor is electrically connected to the second low-frequency signal source, the source is electrically connected to the first low-frequency signal source, and the drain is electrically connected to the second node;
  • the gate of the fifty-fifth transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the third node;
  • the gate of the 64th transistor is electrically connected to the first low frequency signal source, the source is electrically connected to the second low frequency signal source, and the drain is electrically connected to the third node;
  • the gate of the 63rd transistor is electrically connected to the fifth node, the source is electrically connected to the second low frequency signal source, and the drain is electrically connected to the third node;
  • the gate of the sixty-second transistor is electrically connected to the first node, the source is electrically connected to the fifth node, and the drain is electrically connected to the first constant voltage negative potential source;
  • the gate and the source of the sixty-first transistor are electrically connected to the second low frequency signal source, and the drain is electrically connected to the fifth node;
  • the gate of the thirty-third transistor is electrically connected to the third node, the source is electrically connected to the output end, and the drain is electrically connected to the first constant voltage negative potential source;
  • the gate of the forty-third transistor is electrically connected to the third node, the source is electrically connected to the first node, and the drain is electrically connected to the second constant voltage negative potential source;
  • the first constant voltage negative potential source is higher than the second constant voltage negative potential source.
  • the gate of the eleventh transistor is electrically connected to the start signal end, and the source is electrically connected to the start signal end.
  • the gate and the source of the eleventh transistor are electrically connected to the startup signal end of the circuit.
  • the gate of the forty-first transistor is electrically connected to the startup signal terminal.
  • the source of the forty-first transistor in the first pull-down portion may also be electrically connected to the second constant voltage negative potential source.
  • a gate of the fifty-fifth transistor in the pull-down maintaining portion is electrically connected to the driving output end, and the pull-down maintaining portion further includes a fifty-seventh transistor, wherein a gate of the fifty-seventh transistor is electrically connected to the first The driving output end of the N-th GOA unit of the first two stages of the GOA unit of the N-stage GOA unit, the source is electrically connected to the second node, and the drain is electrically connected to the third node.
  • the pull-down maintaining portion further includes a seventy-second transistor, the gate of the seventy-second transistor is electrically connected to the second node, the source is electrically connected to the driving output end, and the drain is electrically connected to the second constant voltage a negative potential source; a seventy-third transistor, the gate of the seventy-third transistor is electrically connected to the third node, the source is electrically connected to the driving output end, and the drain is electrically connected to the second constant voltage negative potential source .
  • the first low frequency signal source and the second low frequency signal source are two low frequency clock signal sources whose phases are completely opposite.
  • the low frequency signals of the high frequency clock signal, the first low frequency signal source and the second low frequency signal source are both lower than the second constant voltage negative potential source.
  • the row driving circuit for the oxide semiconductor thin film transistor is a row driving circuit of the IGZO thin film transistor.
  • the row driving circuit for an oxide semiconductor thin film transistor of the present invention ensures the non-active period by setting two successively decreasing constant voltage negative potential sources and a high frequency clock signal and a low potential of a low frequency clock signal
  • the pull-up circuit portion can be in a good off state, not affected by the high frequency clock signal, thereby ensuring the normal operation of the circuit; further, by redesigning the first pull-down circuit portion to avoid its operation to the first node and during operation
  • the effect of the output of the output ensures that the first node and the output can output normally without signal distortion.
  • 1 is a conventional row driving circuit applied to an amorphous silicon thin film transistor
  • FIG. 2 is a first implementation of a row driving circuit for an oxide semiconductor thin film transistor of the present invention Circuit diagram of an example
  • FIG. 3 is a circuit diagram of a first stage GOA unit of the first embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a second stage GOA unit of the first embodiment of the present invention.
  • Figure 5 is a circuit diagram of a third-order third-stage GOA unit of the first embodiment of the present invention.
  • Figure 6 is a circuit diagram of a penultimate stage GOA unit of the first embodiment of the present invention.
  • Figure 7 is a circuit diagram of a final stage GOA unit of the first embodiment of the present invention.
  • Figure 8 is a circuit diagram of a second embodiment of a row driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • Figure 9 is a circuit diagram of a third embodiment of a row driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • Figure 10 is a circuit diagram of a fourth embodiment of a row driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • Figure 11 is a schematic diagram showing the input and output waveforms of the nodes of the circuit shown in Figure 2 or Figure 8.
  • the row driving circuit for the oxide semiconductor thin film transistor is a row driving circuit of an Indium Gallium Zinc Oxide (IGZO) thin film transistor, which includes a plurality of cascaded GOA units, and N is a positive integer,
  • the N-stage GOA unit includes a pull-up control portion 100, a pull-up portion 200, a next-pass portion 300, a first pull-down portion 400, a bootstrap capacitor portion 500, and a pull-down sustain circuit portion 600.
  • the pull-up control portion 100 includes an eleventh transistor T11.
  • the gate of the eleventh transistor T11 is electrically connected to the driving signal end of the first two-stage GOA unit of the Nth stage GOA unit.
  • ST(N-2) the source is electrically connected to the output terminal G(N-2) of the first two-stage GOA unit of the Nth stage GOA unit, and the drain is electrically connected to the first Node Q(N).
  • the pull-up portion 200 includes a twenty-first transistor T21.
  • the gate of the twenty-first transistor T21 is electrically connected to the first node Q(N), and the source is electrically connected to the high-frequency clock signal CK(n).
  • the drain is electrically connected to the output terminal G(N).
  • the downstream portion 300 includes a twenty-second transistor T22.
  • the gate of the second twelve-transistor T22 is electrically connected to the first node Q(N), and the source is electrically connected to the high-frequency clock signal CK(n).
  • the drain is electrically connected to the drive output terminal ST(N).
  • the first pull-down portion 400 includes a forty-first transistor T41, and the gate of the forty-first transistor T41 is electrically connected to the N+3th GOA unit of the lower three-level GOA unit of the Nth-stage GOA unit.
  • the output terminal G(N+3) has a drain electrically connected to the first node Q(N) and a source electrically connected to the output terminal G(N).
  • the bootstrap capacitor portion 500 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G(N).
  • the pull-down maintaining portion 600 includes a forty-second transistor T42.
  • the gate of the forty-second transistor T42 is electrically connected to the second node P(N), and the source is electrically connected to the first node Q(N).
  • the drain is electrically connected to the second constant voltage negative potential source VSS2; the thirty-second transistor T32, the gate of the thirty-second transistor T32 is electrically connected to the second node P(N), and the source is electrically connected to The output terminal G(N), the drain is electrically connected to the first constant voltage negative potential source VSS1; the fifty-first transistor T51, the gate and the source of the fifty-first transistor T51 are electrically connected to the first low frequency
  • the signal source LC1 the drain is electrically connected to the fourth node S(N); the fifty-second transistor T52, the gate of the fifty-second transistor T52 is electrically connected to the first node Q(N), and the source is electrically Connected to the fourth node S(N), the drain is electrically connected to the first constant
  • the gate of the 64th transistor T64 is electrically connected to the first low frequency signal source LC1, the source is electrically connected to the second low frequency signal source LC2, and the drain is electrically connected to the third node K(N); a transistor of the sixty-third transistor T63, the gate of the sixty-third transistor T63 is electrically connected to the fifth node T(N), the source is electrically connected to the second low-frequency signal source LC2, and the drain is electrically connected to the third node.
  • a sixty-second transistor T62 the gate of the sixty-second transistor T62 is electrically connected to the first node Q (N), the source is electrically connected to the fifth node T (N), the drain Electrically connected to the first constant voltage negative potential source VSS1; the 61st transistor T61, the gate and the source of the 61st transistor T61 are electrically connected to the second low frequency signal source LC2, and the drain is electrically Connected to the fifth node T(N); the thirty-third transistor T33, the gate of the thirty-third transistor T33 is electrically connected to the third node K(N), and the source is electrically connected to the output terminal G(N).
  • the drain is electrically connected to the first constant voltage negative potential source VSS1; the forty-third transistor T43, the gate of the forty-third transistor T43 is electrically connected to the third node K(N), and the source is electrically Connected to the first node Q(N), the drain is electrically connected to the second constant voltage negative potential source VSS2.
  • the first constant voltage negative potential source VSS1 is higher than the second constant voltage negative potential source VSS2, and the first low frequency signal source LC1 and the second low frequency signal source LC2 are two low frequency clock signal sources whose phases are completely opposite.
  • the low potentials of the high frequency clock signal CK(n), the first low frequency signal source LC1 and the second low frequency signal source LC2 are both lower than the second constant voltage negative potential source VSS2.
  • this embodiment introduces a second constant voltage negative potential source VSS2 based on the prior art, through the forty-second transistor T42, The forty-third transistor T43 pulls the potential of the first node Q(N) to the second constant voltage negative potential source VSS2, and passes the output terminal G(N) through the thirty-second transistor T32 and the thirty-third transistor T33.
  • the potential is pulled down to the first constant voltage negative potential source VSS1, and VSS1>VSS2, so that the voltage Vgs ⁇ 0V between the gate and the source of the twenty-first transistor T21 can be ensured, so that the twenty-first transistor T21 can be reduced. Leakage current during the action.
  • the source of the forty-first transistor T41 is connected to the output terminal G(N), so that during the action of the output of the output terminal G(N), since the source terminal of the forty-first transistor T41 is a high potential, then the fourth The overall leakage current of the eleven transistor T41 is significantly reduced, and can also enhance the potential of the first node Q(N).
  • the gate of the forty-first transistor T41 is connected to the N-th stage GOA.
  • the output terminal G(N+3) of the N+3th GOA unit of the lower third-stage GOA unit of the unit ensures that the first node Q(N) forms a potential of a "convex" shape, and the second eleventh transistor T21 is used. Pull the output G(N) low for a time.
  • the gate of the eleventh transistor T11 is electrically connected to the startup signal terminal STV, and the source is electrically connected to the startup signal terminal STV.
  • the gate and the source of the eleventh transistor T11 are electrically connected to the start signal terminal STV of the circuit.
  • the gate of the forty-first transistor T41 is electrically connected to the start. Signal terminal STV.
  • FIG. 8 is a circuit diagram of a second embodiment of a row driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • the second embodiment is different from the first embodiment in that the source terminal of the forty-first transistor T41 in the pull-down portion 400 is directly connected to the second constant voltage negative potential source VSS2 for pulling down the first node during the inactive period.
  • the potential of Q(N) is to the second constant voltage negative potential source VSS2 to ensure that the Vgs of the twenty-first transistor T21 is ⁇ 0V.
  • the components, the connection relationship, the function and the operation principle of the same reference numerals in FIG. 8 and FIG. 2 are the same, and are not described herein again.
  • FIG. 9 is a diagram of a row driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • the third embodiment is different from the first embodiment in that the gate of the fifty-fifth transistor in the pull-down maintaining portion 600 is electrically connected to the driving output terminal ST(N), and the pull-down maintaining portion 600 further includes The fifty-seventh transistor T57, the gate of the fifty-seventh transistor T57 is electrically connected to the driving output terminal ST(N-2) of the N-2th GOA unit of the first two stages of the GOA unit of the Nth stage GOA unit
  • the source is electrically connected to the second node P(N)
  • the drain is electrically connected to the third node K(N).
  • the components, the connection relationship, the function and the operation principle of the same reference numerals in FIG. 9 and FIG. 2 are the same, and are not described herein again.
  • This third embodiment is an improvement for the pull-down sustain circuit portion 600 based on the circuit of the first embodiment shown in Fig. 2, since the potential of the first node Q(N) during the inactive period is subjected to the twenty-first transistor.
  • the influence of the parasitic capacitance of T21 and the twenty-second transistor T22 fluctuates greatly, which causes the potentials of the second node P(N) and the third node K(N) to fluctuate accordingly.
  • the third embodiment changes the fifth transistor T55 of the bridge transistor controlled by the first node Q(N) in the first embodiment into two first GOA units of the first two stages of the N-th GOA unit.
  • FIG. 10 is a circuit diagram of a fourth embodiment of the present invention.
  • the components, the connection relationship, the function and the operation principle of the same reference numerals in FIG. 10 and FIG. 9 are the same, and are not described herein again.
  • the difference between the fourth embodiment and the third embodiment is that the pull-down maintaining portion 600 further includes a seventy-third transistor T73, and the gate of the seventy-third transistor T73 is electrically connected to the third node K(N).
  • the source is electrically connected to the driving output terminal ST(N), the drain is electrically connected to the second constant voltage negative potential source VSS2, and further includes a seventy-second transistor T72, and the gate electrical property of the seventy-second transistor Connected to the second node P(N), the source is electrically connected to the driving output terminal ST(N), and the drain is electrically connected to the second constant voltage negative potential source VSS2.
  • This fourth embodiment is an improvement made in the above-described third embodiment.
  • the fourth embodiment adds a seventy-third transistor T73 and a seventy-second transistor T72 to the third embodiment.
  • the potential of the driving output terminal ST(N) is processed by the seventy-third transistor T73 and the seventy-second transistor T72, thereby ensuring that ST(N) can be at a relatively stable low potential during the non-active period, reducing Fluctuations in P(N) and K(N).
  • FIG. 11 is a schematic diagram of input and output waveforms of respective nodes according to the first embodiment or the second embodiment of the present invention.
  • the STV signal is the start signal of the GOA circuit
  • CK1-4 is the high frequency clock signal for driving the GOA circuit
  • the low frequency clock signal sources with the opposite phases of LC1 and LC2 are opposite
  • VSS1 and VSS2 are the constant voltages of the two sets of potentials decreasing sequentially Negative potential source.
  • the pull-up circuit portion 200 is in a good off state, and the first node Q(N) and The output G(N) is output normally without signal distortion.
  • the row driving circuit for an oxide semiconductor thin film transistor of the present invention ensures the non-active period by setting two successively decreasing constant voltage negative potential sources and a high frequency clock signal and a low potential of the low frequency clock signal.
  • the pull circuit portion can be in a good off state, not affected by the high frequency clock signal, thereby ensuring the normal operation of the circuit; further, by redesigning the first pull down circuit portion to avoid its first node and output during operation The effect of the output of the terminal ensures that the first node and the output can output normally without signal distortion.

Abstract

一种用于氧化物半导体薄膜晶体管的行驱动电路通过设置两个依次递减的恒压负电位源（VSS1、VSS2）和高频时钟讯号（CK(n)）、低频时钟讯号（LC1、LC2）的低电位来确保在非作用期间上拉电路部分（200）能够处于很好的关闭状态，不受到高频时钟讯号（CK(n)）的影响，从而确保电路正常工作；进一步的，通过重新设计第一下拉电路部分（400）来避免在工作期间其对第一节点（Q(N)）和输出端（G(N)）输出的影响，确保第一节点（Q(N)）和输出端（G(N)）能够正常输出而不产生讯号失真。

Description

用于氧化物半导体薄膜晶体管的行驱动电路 技术领域
本发明涉及液晶显示领域，尤其涉及一种用于氧化物半导体薄膜晶体管的行驱动电路。
背景技术
GOA(Gate Drive On Array)，是利用薄膜晶体管液晶显示器Array制程将Gate行扫描驱动讯号电路制作在薄膜晶体管阵列基板上，以实现Gate逐行扫描的驱动方式。
对于传统的非晶硅半导体器件，由于非晶硅薄膜晶体管的电学特性中阈值电压Vth一般大于0V，而且亚阈值区域的电压相对于电流的摆幅较大，这样在电路设计中即使某些晶体管在操作时晶体管栅极与源极之间的电压Vgs在等于0V附近产生的漏电流也较小。但是，对于目前正常发展的氧化物半导体薄膜晶体管，由于半导体材料本身的特性与非晶硅有所差异，其薄膜晶体管的阈值电压Vth有时候会小于0V，而且亚阈值区域的电压相对于电流的摆幅很小，这样如果电路中某些重要的晶体管操作在Vgs等于0V附近时就会产生较大的漏电流。因此，针对氧化物半导体薄膜晶体管的行驱动电路需要采用一些特殊的设计方案来避免某些重要的薄膜晶体管操作在Vgs等于0V附近。
如图1所示，是现有的一种应用于非晶硅薄膜晶体管的行驱动电路，其中电路主要架构包括：上拉控制部分100，上拉部分200，下传部分300，第一下拉部分400，自举电容500和下拉维持部分600。
该应用于非晶硅薄膜晶体管的行驱动电路的控制讯号源主要有高频时钟讯号CK(n)，恒压低电位源VSS，低频时钟讯号LC1和LC2，其中LC1和LC2是两个相位完全相反的低频讯号源。在设定上一般CK(n)、LC1、LC2的低电位会小于VSS，但是电路中的关键节点Q(N)和G(N)在非作用期间均会被拉低到VSS。这样，对于上拉部分200的第二十一晶体管T21和下传部分300的第二十二晶体管T22，其关态的操作电压Vgs≈0V，而且Q(N)还会存在高低的波动，也就是说存在Vgs>0V的情况，那么如果将该电路直接应用到氧化物半导体薄膜晶体管的驱动电路设计中时则存在着较大的漏电流，无法确保在非作用期间输出端G(N)维持在低电位，这样会导致输出端G(N)的输出不良和GOA电路功能性不良。
同样，对于第一下拉部分400的第三十一晶体管T31和第四十一晶体管T41也存在着这样的问题，在Q(N)和G(N)处于高电位的作用期间，T31和T41的漏电会导致Q(N)和G(N)的输出波形失真，从而导致在严苛条件下(例如高温操作)GOA电路的功能性不良。
对于下拉维持电路部分600，由于该电路设计采用的是LC1或LC2的低电位来控制P(N)或K(N)在作用期间的下拉，这样可以确保在作用期间P(N)和K(N)的低电位小于VSS，确保第三十二、三十三、四十二、四十三晶体管T32、T33、T42、T43的Vgs<0V，处于良好的关闭状态，从而降低下拉维持电路部分600对Q(N)和G(N)的输出波形的影响。但是目前采用的设计方案中下拉维持电路部分的桥式TFT T55在非作用期间Vgs>0V，这样会导致非作用期间的P(N)或K(N)的高电位无法抬升得很高，从而会影响T32、T33、T42、T43对Q(N)和G(N)的下拉维持作用。虽然这一点在设计中可以通过调整元件的尺寸来改善，但是也存在因为尺寸增加而带来的漏电流增加的问题。
发明内容
本发明的目的在于提供一种用于氧化物半导体薄膜晶体管的行驱动电路，对现有的非晶硅GOA电路设计进行改进，使其可以应用到氧化物半导体GOA电路中，解决由于氧化物半导体与非晶硅本身的特性差异所引起的电路功能性不良问题。
针对上述目的，本发明提供一种用于氧化物半导体薄膜晶体管的行驱动电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括：一上拉控制部分、一上拉部分、一下传部分、一第一下拉部分、一自举电容部分和下拉维持电路部分；
所述上拉控制部分包括第十一晶体管，该第十一晶体管的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动讯号端，源极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的输出端，漏极电性连接于第一节点。
所述上拉部分包括第二十一晶体管，该第二十一晶体管的栅极电性连接于第一节点，源极电性连接于高频时钟讯号，漏极电性连接于输出端；
所述下传部分包括第二十二晶体管，该第二十二晶体管的栅极电性连接于第一节点，源极电性连接于高频时钟讯号，漏极电性连接于驱动输出端；
所述第一下拉部分包括第四十一晶体管，该第四十一晶体管的栅极电 性连接于该第N级GOA单元的下三级GOA单元第N+3级GOA单元的输出端,漏极电性连接于第一节点，源极电性连接于输出端。
所述自举电容部分包括一电容，该电容的一端电性连接于第一节点，另一端电性连接于输出端。
所述下拉维持部分包括：第四十二晶体管，该第四十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二恒压负电位源；
第三十二晶体管，该第三十二晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一恒压负电位源；
第五十一晶体管，该第五十一晶体管的栅极与源极均电性连接于第一低频讯号源，漏极电性连接于第四节点；
第五十二晶体管，该第五十二晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第一恒压负电位源；
第五十三晶体管，该第五十三晶体管的栅极电性连接于第四节点，源极电性连接于第一低频讯号源，漏极电性连接于第二节点；
第五十四晶体管，该第五十四晶体管的栅极电性连接于第二低频讯号源，源极电性连接于第一低频讯号源，漏极电性连接于第二节点；
第五十五晶体管，该第五十五晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第三节点；
第六十四晶体管，该第六十四晶体管的栅极电性连接于第一低频讯号源，源极电性连接于第二低频讯号源，漏极电性连接于第三节点；
第六十三晶体管，该第六十三晶体管的栅极电性连接于第五节点，源极电性连接于第二低频讯号源，漏极电性连接于第三节点；
第六十二晶体管，该第六十二晶体管的栅极电性连接于第一节点，源极电性连接于第五节点，漏极电性连接于第一恒压负电位源；
第六十一晶体管,该第六十一晶体管的栅极与源极均电性连接于第二低频讯号源，漏极电性连接于第五节点；
第三十三晶体管，该第三十三晶体管的栅极电性连接于第三节点，源极电性连接于输出端，漏极电性连接于第一恒压负电位源；
第四十三晶体管，该第四十三晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极电性连接于第二恒压负电位源；
所述第一恒压负电位源高于第二恒压负电位源。
所述行驱动电路的第一级GOA单元中，第十一晶体管的栅极电性连接于启动讯号端，源极电性连接于启动讯号端。
所述行驱动电路的第二级GOA单元中，第十一晶体管的栅极与源极均电性连接于电路的启动讯号端。
所述行驱动电路的倒数第三级、倒数第二级以及最后一级GOA单元中，第四十一晶体管的栅极电性均电性连接于启动讯号端。
所述第一下拉部分中第四十一晶体管的源极还可以电性连接于第二恒压负电位源。
所述下拉维持部分中的第五十五晶体管的栅极电性连接于驱动输出端，该下拉维持部分还包括第五十七晶体管，该第五十七晶体管的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动输出端，源极电性连接于第二节点，漏极电性连接于第三节点。
所述下拉维持部分还包括第七十二晶体管，该第七十二晶体管的栅极电性连接于第二节点，源极电性连接于驱动输出端，漏极电性连接于第二恒压负电位源；第七十三晶体管，该第七十三晶体管的栅极电性连接于第三节点，源极电性连接于驱动输出端，漏极电性连接于第二恒压负电位源。
所述第一低频讯号源与第二低频讯号源是两个相位完全相反的低频时钟讯号源。
所述高频时钟讯号、第一低频讯号源与第二低频讯号源的低电位均低于第二恒压负电位源。
所述用于氧化物半导体薄膜晶体管的行驱动电路为IGZO薄膜晶体管的行驱动电路。
本发明的有益效果：本发明的用于氧化物半导体薄膜晶体管的行驱动电路通过设置两个依次递减的恒压负电位源和高频时钟讯号、低频时钟讯号的低电位来确保在非作用期间上拉电路部分能够处于很好的关闭状态，不受到高频时钟讯号的影响，从而确保电路正常工作；进一步的，通过重新设计第一下拉电路部分来避免在工作期间其对第一节点和输出端输出的影响，确保第一节点和输出端能够正常输出而不产生讯号失真。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种应用于非晶硅薄膜晶体管的行驱动电路；
图2为本发明用于氧化物半导体薄膜晶体管的行驱动电路的第一实施 例的电路图；
图3为本发明的第一实施例的第一级GOA单元的电路图；
图4为本发明的第一实施例的第二级GOA单元的电路图；
图5为本发明的第一实施例的倒数第三级GOA单元的电路图；
图6为本发明的第一实施例的倒数第二级GOA单元的电路图；
图7为本发明的第一实施例的最后一级GOA单元的电路图；
图8为本发明用于氧化物半导体薄膜晶体管的行驱动电路的第二实施例的电路图；
图9为本发明用于氧化物半导体薄膜晶体管的行驱动电路的第三实施例的电路图；
图10为本发明用于氧化物半导体薄膜晶体管的行驱动电路的第四实施例的电路图；
图11为图2或图8所示电路的各节点的输入和输出波形示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图2-7，为本发明用于氧化物半导体薄膜晶体管的行驱动电路的第一实施例的电路图。该用于氧化物半导体薄膜晶体管的行驱动电路为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)薄膜晶体管的行驱动电路，其包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分100、一上拉部分200、一下传部分300、一第一下拉部分400、一自举电容部分500和下拉维持电路部分600。
上述各部分的组成以及具体的连接方式如下：
所述上拉控制部分100包括第十一晶体管T11，该第十一晶体管T11的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动讯号端ST(N-2)，源极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的输出端G(N-2)，漏极电性连接于第一节点Q(N)。
所述上拉部分200包括第二十一晶体管T21，该第二十一晶体管T21的栅极电性连接于第一节点Q(N)，源极电性连接于高频时钟讯号CK(n)，漏极电性连接于输出端G(N)。
所述下传部分300包括第二十二晶体管T22，该第二十二晶体管T22的栅极电性连接于第一节点Q(N)，源极电性连接于高频时钟讯号CK(n)， 漏极电性连接于驱动输出端ST(N)。
所述第一下拉部分400包括第四十一晶体管T41，该第四十一晶体管T41的栅极电性连接于该第N级GOA单元的下三级GOA单元第N+3级GOA单元的输出端G(N+3)，漏极电性连接于第一节点Q(N)，源极电性连接于输出端G(N)。
所述自举电容部分500包括一电容Cb，该电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)。
所述下拉维持部分600包括第四十二晶体管T42，该第四十二晶体管T42的栅极电性连接于第二节点P(N)，源极电性连接于第一节点Q(N)，漏极电性连接于第二恒压负电位源VSS2；第三十二晶体管T32，该第三十二晶体管T32的栅极电性连接于第二节点P(N)，源极电性连接于输出端G(N)，漏极电性连接于第一恒压负电位源VSS1；第五十一晶体管T51，该第五十一晶体管T51的栅极与源极均电性连接于第一低频讯号源LC1，漏极电性连接于第四节点S(N)；第五十二晶体管T52，该第五十二晶体管T52的栅极电性连接于第一节点Q(N)，源极电性连接于第四节S(N)，漏极电性连接于第一恒压负电位源VSS1；第五十三晶体管T53，该第五十三晶体管T53的栅极电性连接于第四节点S(N)，源极电性连接于第一低频讯号源LC1，漏极电性连接于第二节点P(N)；第五十四晶体管T54，该第五十四晶体管T54的栅极电性连接于第二低频讯号源LC2，源极电性连接于第一低频讯号源LC1，漏极电性连接于第二节点P(N)；第五十五晶体管T55，该第五十五晶体管T55的栅极电性连接于第一节点Q(N)，源极电性连接于第二节点P(N)，漏极电性连接于第三节点K(N)；第六十四晶体管T64，该第六十四晶体管T64的栅极电性连接于第一低频讯号源LC1，源极电性连接于第二低频讯号源LC2，漏极电性连接于第三节点K(N)；第六十三晶体管T63，该第六十三晶体管T63的栅极电性连接于第五节点T(N)，源极电性连接于第二低频讯号源LC2，漏极电性连接于第三节点K(N)；第六十二晶体管T62，该第六十二晶体管T62的栅极电性连接于第一节点Q(N)，源极电性连接于第五节点T(N)，漏极电性连接于第一恒压负电位源VSS1；第六十一晶体管T61,该第六十一晶体管T61的栅极与源极均电性连接于第二低频讯号源LC2，漏极电性连接于第五节点T(N)；第三十三晶体管T33，该第三十三晶体管T33的栅极电性连接于第三节点K(N)，源极电性连接于输出端G(N)，漏极电性连接于第一恒压负电位源VSS1；第四十三晶体管T43，该第四十三晶体管T43的栅极电性连接于第三节点K(N)，源极电性连接于第一节点Q(N)，漏极电性连接于第二恒压负电位源VSS2。
所述第一恒压负电位源VSS1高于第二恒压负电位源VSS2，所述第一低频讯号源LC1与第二低频讯号源LC2是两个相位完全相反的低频时钟讯号源。所述高频时钟讯号CK(n)、第一低频讯号源LC1与第二低频讯号源LC2的低电位均低于第二恒压负电位源VSS2。
需要特别说明的是，为了降低第二十一晶体管T21在非作用期间的漏电，该实施例在现有技术的基础上引入了第二恒压负电位源VSS2，通过第四十二晶体管T42、第四十三晶体管T43将第一节点Q(N)的电位拉低到第二恒压负电位源VSS2，通过第三十二晶体管T32和第三十三晶体管T33将输出端G(N)的电位拉低到第一恒压负电位源VSS1，而VSS1＞VSS2，因此可以确保第二十一晶体管T21的栅源极之间的电压Vgs<0V，从而能够降低第二十一晶体管T21在非作用期间的漏电流。
此外，第四十一晶体管T41的源极接输出端G(N)，这样在输出端G(N)输出的作用期间，由于第四十一晶体管T41的源极端是一个高电位，那么第四十一晶体管T41的整体漏电流会明显降低，而且还能起到增强第一节点Q(N)电位的作用。
进一步的，为了降低第一下拉部分400对输出端G(N)的影响，仅设置一颗第四十一晶体管T41，并且将第四十一晶体管T41的栅极接到该第N级GOA单元的下三级GOA单元第N+3级GOA单元的输出端G(N+3)，确保第一节点Q(N)形成“凸”字形的电位，利用该第二十一晶体管T21来第一时间拉低输出端G(N)。
如图3所示，所述行驱动电路的第一级GOA单元中，第十一晶体管T11的栅极电性连接于启动讯号端STV，源极电性连接于启动讯号端STV。
如图4所示，所述行驱动电路的第二级GOA单元中，第十一晶体管T11的栅极与源极均电性连接于电路的启动讯号端STV。
如图5、6、7所示，所述行驱动电路的倒数第三级、倒数第二级以及最后一级GOA单元中，第四十一晶体管T41的栅极电性均电性连接于启动讯号端STV。
请参阅图8，为本发明用于氧化物半导体薄膜晶体管的行驱动电路的第二实施例的电路图。该第二实施例与第一实施例的区别在于，所述下拉部分400中第四十一晶体管T41的源极端直接连接第二恒压负电位源VSS2，用于在非作用期间下拉第一节点Q(N)的电位到第二恒压负电位源VSS2，以确保第二十一晶体管T21的Vgs＜0V。除此之外，图8与图2中具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。
请参阅图9，为本发明用于氧化物半导体薄膜晶体管的行驱动电路的第 三实施例的电路图。该第三实施例与第一实施例的区别在于，所述下拉维持部分600中的第五十五晶体管的栅极电性连接于驱动输出端ST(N)，同时该下拉维持部分600还包括第五十七晶体管T57，该第五十七晶体管T57的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动输出端ST(N-2)，源极电性连接于第二节点P(N)，漏极电性连接于第三节点K(N)。除此之外，图9与图2中具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。
该第三实施例是在图2所示的第一实施例的电路基础上针对下拉维持电路部分600进行的改进，由于第一节点Q(N)在非作用期间的电位受到第二十一晶体管T21和第二十二晶体管T22寄生电容的影响波动较大，这样会导致第二节点P(N)和第三节点K(N)的电位也会随之波动。该第三实施例将第一实施例中由第一节点Q(N)控制的桥式晶体管第五十五晶体T55改成两颗分别由该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动输出端ST(N-2)和驱动输出端ST(N)来控制的桥式晶体管第五十七晶体管T57和第五十五晶体管T55，这样可以有效避免第一节点Q(N)对第二节点P(N)和第三节点K(N)电位的影响。
请参阅图10，为本发明的第四实施例的电路图。图10与图9中具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。该第四实施例与第三实施例的区别在于，所述下拉维持部分600还包括第七十三晶体管T73，该第七十三晶体管T73的栅极电性连接于第三节点K(N)，源极电性连接于驱动输出端ST(N)，漏极电性连接于第二恒压负电位源VSS2；还包括第七十二晶体管T72，该第七十二晶体管的栅极电性连接于第二节点P(N)，源极电性连接于驱动输出端ST(N)，漏极电性连接于第二恒压负电位源VSS2。
该第四实施例是在上述第三实施例上所做的改进。该第四实施例在第三实施例的基础上加入了一第七十三晶体管T73、一第七十二晶体管T72。通过所述第七十三晶体管T73和第七十二晶体管T72对驱动输出端ST(N)的电位进行处理，这样可以确保ST(N)在非作用期间能够处于一个比较稳定的低电位，降低P(N)和K(N)的波动。
请参阅图11，为本发明的第一实施例或第二实施例的各节点的输入和输出波形示意图。其中，STV讯号是GOA电路的启动讯号；CK1-4是驱动GOA电路的高频时钟讯号；LC1和LC2两个相位完全相反的低频时钟讯号源；VSS1和VSS2是两组电位依次递减的恒压负电位源。由图11可知，在非作用期间，上拉电路部分200处于很好的关闭状态，且第一节点Q(N)和 输出端G(N)正常输出而不产生讯号失真。
综上所述，本发明的用于氧化物半导体薄膜晶体管的行驱动电路通过设置两个依次递减的恒压负电位源和高频时钟讯号、低频时钟讯号的低电位来确保在非作用期间上拉电路部分能够处于很好的关闭状态，不受到高频时钟讯号的影响，从而确保电路正常工作；进一步的，通过重新设计第一下拉电路部分来避免在工作期间其对第一节点和输出端输出的影响，确保第一节点和输出端能够正常输出而不产生讯号失真。
虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种用于氧化物半导体薄膜晶体管的行驱动电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括：一上拉控制部分、一上拉部分、一下传部分、一第一下拉部分、一自举电容部分和一下拉维持电路部分；
    所述上拉控制部分包括第十一晶体管，该第十一晶体管的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动讯号端，源极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的输出端，漏极电性连接于第一节点；
    所述上拉部分包括第二十一晶体管，该第二十一晶体管的栅极电性连接于第一节点，源极电性连接于高频时钟讯号，漏极电性连接于输出端；
    所述下传部分包括第二十二晶体管，该第二十二晶体管的栅极电性连接于第一节点，源极电性连接于高频时钟讯号，漏极电性连接于驱动输出端；
    所述第一下拉部分包括第四十一晶体管，该第四十一晶体管的栅极电性连接于该第N级GOA单元的下三级GOA单元第N+3级GOA单元的输出端，漏极电性连接于第一节点，源极电性连接于输出端；
    所述自举电容部分包括一电容，该电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述下拉维持部分包括：第四十二晶体管，该第四十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二恒压负电位源；
    第三十二晶体管，该第三十二晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一恒压负电位源；
    第五十一晶体管，该第五十一晶体管的栅极与源极均电性连接于第一低频讯号源，漏极电性连接于第四节点；
    第五十二晶体管，该第五十二晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第一恒压负电位源；
    第五十三晶体管，该第五十三晶体管的栅极电性连接于第四节点，源极电性连接于第一低频讯号源，漏极电性连接于第二节点；
    第五十四晶体管，该第五十四晶体管的栅极电性连接于第二低频讯号源，源极电性连接于第一低频讯号源，漏极电性连接于第二节点；
    第五十五晶体管，该第五十五晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第三节点；
    第六十四晶体管，该第六十四晶体管的栅极电性连接于第一低频讯号源，源极电性连接于第二低频讯号源，漏极电性连接于第三节点；
    第六十三晶体管，该第六十三晶体管的栅极电性连接于第五节点，源极电性连接于第二低频讯号源，漏极电性连接于第三节点；
    第六十二晶体管，该第六十二晶体管的栅极电性连接于第一节点，源极电性连接于第五节点，漏极电性连接于第一恒压负电位源；
    第六十一晶体管，该第六十一晶体管的栅极与源极均电性连接于第二低频讯号源，漏极电性连接于第五节点；
    第三十三晶体管，该第三十三晶体管的栅极电性连接于第三节点，源极电性连接于输出端，漏极电性连接于第一恒压负电位源；
    第四十三晶体管，该第四十三晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极电性连接于第二恒压负电位源；
    所述第一恒压负电位源高于第二恒压负电位源。
  2. 如权利要求1所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述行驱动电路的第一级GOA单元中，第十一晶体管的栅极电性连接于启动讯号端，源极电性连接于启动讯号端。
  3. 如权利要求1所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述行驱动电路的第二级GOA单元中，第十一晶体管的栅极与源极均电性连接于电路的启动讯号端。
  4. 如权利要求1所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述行驱动电路的倒数第三级、倒数第二级以及最后一级GOA单元中，第四十一晶体管的栅极均电性连接于启动讯号端。
  5. 如权利要求1所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述第一下拉部分中第四十一晶体管的源极电性连接于第二恒压负电位源。
  6. 如权利要求1所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述下拉维持部分中的第五十五晶体管的栅极电性连接于驱动输出端；该下拉维持部分还包括第五十七晶体管，该第五十七晶体管的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动输出端，源极电性连接于第二节点，漏极电性连接于第三节点。
  7. 如权利要求6所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述下拉维持部分还包括第七十二晶体管，该第七十二晶体管的栅 极电性连接于第二节点，源极电性连接于驱动输出端，漏极电性连接于第二恒压负电位源；第七十三晶体管，该第七十三晶体管的栅极电性连接于第三节点，源极电性连接于驱动输出端，漏极电性连接于第二恒压负电位源。
  8. 如权利要求1所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述第一低频讯号源与第二低频讯号源是两个相位完全相反的低频时钟讯号源。
  9. 如权利要求8所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述高频时钟讯号、第一低频讯号源与第二低频讯号源的低电位均低于第二恒压负电位源。
  10. 如权利要求1所述的用于氧化物半导体薄膜晶体管的行驱动电路，其中，所述用于氧化物半导体薄膜晶体管的行驱动电路为IGZO薄膜晶体管的行驱动电路。
  11. 一种用于氧化物半导体薄膜晶体管的行驱动电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括：一上拉控制部分、一上拉部分、一下传部分、一第一下拉部分、一自举电容部分和一下拉维持电路部分；
    所述上拉控制部分包括第十一晶体管，该第十一晶体管的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动讯号端，源极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的输出端，漏极电性连接于第一节点；
    所述上拉部分包括第二十一晶体管，该第二十一晶体管的栅极电性连接于第一节点，源极电性连接于高频时钟讯号，漏极电性连接于输出端；
    所述下传部分包括第二十二晶体管，该第二十二晶体管的栅极电性连接于第一节点，源极电性连接于高频时钟讯号，漏极电性连接于驱动输出端；
    所述第一下拉部分包括第四十一晶体管，该第四十一晶体管的栅极电性连接于该第N级GOA单元的下三级GOA单元第N+3级GOA单元的输出端，漏极电性连接于第一节点，源极电性连接于输出端；
    所述自举电容部分包括一电容，该电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述下拉维持部分包括：第四十二晶体管，该第四十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二恒压负电位源；
    第三十二晶体管，该第三十二晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一恒压负电位源；
    第五十一晶体管，该第五十一晶体管的栅极与源极均电性连接于第一低频讯号源，漏极电性连接于第四节点；
    第五十二晶体管，该第五十二晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于第一恒压负电位源；
    第五十三晶体管，该第五十三晶体管的栅极电性连接于第四节点，源极电性连接于第一低频讯号源，漏极电性连接于第二节点；
    第五十四晶体管，该第五十四晶体管的栅极电性连接于第二低频讯号源，源极电性连接于第一低频讯号源，漏极电性连接于第二节点；
    第五十五晶体管，该第五十五晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第三节点；
    第六十四晶体管，该第六十四晶体管的栅极电性连接于第一低频讯号源，源极电性连接于第二低频讯号源，漏极电性连接于第三节点；
    第六十三晶体管，该第六十三晶体管的栅极电性连接于第五节点，源极电性连接于第二低频讯号源，漏极电性连接于第三节点；
    第六十二晶体管，该第六十二晶体管的栅极电性连接于第一节点，源极电性连接于第五节点，漏极电性连接于第一恒压负电位源；
    第六十一晶体管，该第六十一晶体管的栅极与源极均电性连接于第二低频讯号源，漏极电性连接于第五节点；
    第三十三晶体管，该第三十三晶体管的栅极电性连接于第三节点，源极电性连接于输出端，漏极电性连接于第一恒压负电位源；
    第四十三晶体管，该第四十三晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极电性连接于第二恒压负电位源；
    所述第一恒压负电位源高于第二恒压负电位源；
    其中，所述行驱动电路的第一级GOA单元中，第十一晶体管的栅极电性连接于启动讯号端，源极电性连接于启动讯号端；
    其中，所述行驱动电路的第二级GOA单元中，第十一晶体管的栅极与源极均电性连接于电路的启动讯号端；
    其中，所述行驱动电路的倒数第三级、倒数第二级以及最后一级GOA单元中，第四十一晶体管的栅极均电性连接于启动讯号端；
    其中，所述第一低频讯号源与第二低频讯号源是两个相位完全相反的低频时钟讯号源；
    其中，所述高频时钟讯号、第一低频讯号源与第二低频讯号源的低电 位均低于第二恒压负电位源；
    其中，所述用于氧化物半导体薄膜晶体管的行驱动电路为IGZO薄膜晶体管的行驱动电路。
PCT/CN2014/090286 2014-10-22 2014-11-05 用于氧化物半导体薄膜晶体管的行驱动电路 WO2016061851A1 (zh)

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