WO2021072948A1 - Goa器件及栅极驱动电路 - Google Patents

Goa器件及栅极驱动电路 Download PDF

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Publication number
WO2021072948A1
WO2021072948A1 PCT/CN2019/124354 CN2019124354W WO2021072948A1 WO 2021072948 A1 WO2021072948 A1 WO 2021072948A1 CN 2019124354 W CN2019124354 W CN 2019124354W WO 2021072948 A1 WO2021072948 A1 WO 2021072948A1
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Prior art keywords
stage
unit
thin film
film transistor
nth
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PCT/CN2019/124354
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English (en)
French (fr)
Inventor
朱静
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Tcl华星光电技术有限公司
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Priority to US16/626,334 priority Critical patent/US11295687B2/en
Publication of WO2021072948A1 publication Critical patent/WO2021072948A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • This application relates to the field of display panel manufacturing, in particular to a GOA device and a gate drive circuit.
  • the array substrate row drive (Gate Drive On Array, GOA) technology is to integrate the scan line drive circuit on the array substrate of the liquid crystal panel, thereby reducing product cost in terms of material cost and manufacturing process.
  • the present application provides a GOA device and a gate drive circuit to solve the technical problem of insufficient charging ability when the existing high-resolution and high-frequency display panel is working.
  • This application proposes a GOA device comprising at least two GOA units connected in cascade.
  • the nth level GOA unit is used to output gate drive signals to the nth level horizontal scan line, wherein the nth level GOA unit includes a Pull-up control unit, a bootstrap unit, a pull-up unit, a pull-down unit, and a pull-up maintenance unit;
  • the pull-up control unit receives a start signal in the first stage so that the control node (Qn) of the nth-stage GOA unit is pulled up to a first high potential;
  • the bootstrapping unit pulls up the control node (Qn) of the nth level GOA unit to a second high potential in the second stage according to a clock signal;
  • the pull-up unit outputs a pulse width as the clock according to the first high potential and the second high potential of the control node (Qn) of the nth GOA unit and the clock signal output by the bootstrap unit
  • the gate drive signal with twice the pulse width of the signal to the gate signal terminal (Gn) of the nth-stage GOA unit;
  • the pull-down unit pulls down the potentials of the control node (Qn) of the n-th GOA unit and the gate signal terminal (Gn) of the n-th GOA unit to a first DC low voltage Flat;
  • the pull-down sustaining unit maintains the control node (Qn) of the nth-stage GOA unit at the first DC low level in the fourth stage, and sets the gate signal terminal ( The potential of Gn) is maintained at a second DC low level.
  • the pull-up control unit is connected to the stage transmission signal terminal (STn-4) of the n-4th stage GOA unit, the gate signal terminal (Gn-4) of the n-4th stage and all The control node (Qn) of the nth level GOA unit;
  • the pull-up control unit receives the start signal from the stage transmission signal terminal (STn-4) of the n-4th stage GOA unit, and according to the n-4th stage
  • the gate signal of the gate signal terminal (Gn-4) makes the control node (Qn) of the nth stage GOA unit at the first high potential.
  • the pull-up control unit includes an eleventh thin film transistor (T11);
  • the gate of the eleventh thin film transistor (T11) is connected to the stage transmission signal output terminal (STn-4) of the n-4th stage GOA unit, and the source of the eleventh thin film transistor (T11) is connected to the The gate signal output terminal (Gn-4) of the n-4th stage, and the drain of the eleventh thin film transistor (T11) is connected to the control node (Qn) of the nth stage GOA unit.
  • the bootstrap unit is connected to the control node (Qn), the clock signal terminal (CK) of the nth level GOA unit, and the stage transmission signal terminal (STn) of the nth level GOA unit;
  • the clock signal terminal (CK) provides the clock signal
  • the second stage starts when the control node (Qn) of the n-th GOA unit is pulled up to the first high potential.
  • the bootstrap unit includes a bootstrap capacitor and a twenty-second thin film transistor (T22);
  • the bootstrap capacitor is connected to the control node (Qn) of the nth level GOA unit and the stage transmission signal terminal (STn) of the nth level GOA unit;
  • the gate of the twenty-second thin film transistor (T22) is connected to the control node (Qn) of the n-th GOA unit, and the source of the twenty-second thin film transistor (T22) is connected to the clock signal terminal ( CK), the drain of the twenty-second thin film transistor (T22) is connected to the stage signal terminal (STn) of the nth stage GOA unit.
  • the pull-up unit is connected to the control node (Qn) of the nth level GOA unit, the level transmission signal terminal (STn) of the nth level GOA unit, and the nth level The gate signal terminal (Gn);
  • the stage transmission signal terminal (STn) of the nth stage GOA unit is used to provide a start signal to control the opening and closing of the thin film transistor in the pull-up unit.
  • the pull-up unit includes a twenty-first thin film transistor (T21);
  • the gate of the twenty-first thin film transistor (T21) is connected to the control node (Qn) of the n-th stage GOA unit, and the source of the twenty-first thin film transistor (T21) is connected to the n-th stage GOA
  • the stage signal terminal (STn) of the unit, and the drain of the twenty-first thin film transistor (T21) is connected to the gate signal terminal (Gn) of the nth stage.
  • the pull-down unit is connected to the control node (Qn) of the nth level GOA unit, the gate signal terminal (Gn) of the nth level GOA unit, and the stage transmission signal terminal (STn+ 4), and a first DC low level terminal (VSSQ);
  • the first direct current low level terminal (VSSQ) provides the first direct current low level
  • the third stage starts when the stage transmission signal terminal (STn+4) of the n+4th stage GOA unit is at a high potential.
  • the pull-down unit includes a thirty-first thin film transistor (T31) and a forty-first thin film transistor (T41);
  • the source of the thirty-first thin film transistor (T31) is connected to the gate signal terminal (Gn) of the n-th GOA unit, and the source of the forty-first thin film transistor (T41) is connected to the n-th GOA unit.
  • the drains of the thirty-first thin film transistor (T31) and the forty-first thin film transistor (T41) are commonly connected to the first direct current low level terminal (VSSQ), and the thirty-first thin film transistor ( T31) and the gate of the forty-first thin film transistor (T41) are commonly connected to the stage transmission signal terminal (STn+4) of the n+4th GOA unit.
  • This application also proposes a gate drive circuit, wherein the gate drive circuit includes a GOA device, the GOA device includes at least two cascaded GOA units, and the nth level GOA unit is used to compare the nth level
  • the scan line outputs a gate drive signal
  • the n-th GOA unit includes a pull-up control unit, a bootstrap unit, a pull-up unit, a pull-down unit, and a pull-down sustaining unit;
  • the pull-up control unit receives a start signal in the first stage so that the control node (Qn) of the nth-stage GOA unit is pulled up to a first high potential;
  • the bootstrapping unit pulls up the control node (Qn) of the nth level GOA unit to a second high potential in the second stage according to a clock signal;
  • the pull-up unit outputs a pulse width as the clock according to the first high potential and the second high potential of the control node (Qn) of the nth GOA unit and the clock signal output by the bootstrap unit
  • the gate drive signal with twice the pulse width of the signal to the gate signal terminal (Gn) of the nth-stage GOA unit;
  • the pull-down unit pulls down the potentials of the control node (Qn) of the n-th GOA unit and the gate signal terminal (Gn) of the n-th GOA unit to a first DC low voltage Flat;
  • the pull-down sustaining unit maintains the control node (Qn) of the nth-stage GOA unit at the first DC low level in the fourth stage, and sets the gate signal terminal ( The potential of Gn) is maintained at a second DC low level.
  • the pull-up control unit is connected to the stage signal terminal (STn-4) of the n-4th stage GOA unit and the gate signal terminal (Gn-4) of the n-4th stage. And the control node (Qn) of the nth level GOA unit;
  • the pull-up control unit receives the start signal from the stage transmission signal terminal (STn-4) of the n-4th stage GOA unit, and according to the n-4th stage
  • the gate signal of the gate signal terminal (Gn-4) makes the control node (Qn) of the nth stage GOA unit at the first high potential.
  • the pull-up control unit includes an eleventh thin film transistor (T11);
  • the gate of the eleventh thin film transistor (T11) is connected to the stage transmission signal output terminal (STn-4) of the n-4th stage GOA unit, and the source of the eleventh thin film transistor (T11) is connected to the The gate signal output terminal (Gn-4) of the n-4th stage, and the drain of the eleventh thin film transistor (T11) is connected to the control node (Qn) of the nth stage GOA unit.
  • the bootstrap unit is connected to the control node (Qn), the clock signal terminal (CK) of the nth GOA unit, and the stage transmission signal terminal (STn) of the nth GOA unit. );
  • the clock signal terminal (CK) provides the clock signal
  • the second stage starts when the control node (Qn) of the n-th GOA unit is pulled up to the first high potential.
  • the bootstrap unit includes a bootstrap capacitor and a twenty-second thin film transistor (T22);
  • the bootstrap capacitor is connected to the control node (Qn) of the nth level GOA unit and the stage transmission signal terminal (STn) of the nth level GOA unit;
  • the gate of the twenty-second thin film transistor (T22) is connected to the control node (Qn) of the n-th GOA unit, and the source of the twenty-second thin film transistor (T22) is connected to the clock signal terminal ( CK), the drain of the twenty-second thin film transistor (T22) is connected to the stage signal terminal (STn) of the nth stage GOA unit.
  • the pull-up unit is connected to the control node (Qn) of the nth-stage GOA unit, the stage transmission signal terminal (STn) of the nth-stage GOA unit, and the first n-level gate signal terminal (Gn);
  • the stage transmission signal terminal (STn) of the nth stage GOA unit is used to provide a start signal to control the opening and closing of the thin film transistor in the pull-up unit.
  • the pull-up unit includes a twenty-first thin film transistor (T21);
  • the gate of the twenty-first thin film transistor (T21) is connected to the control node (Qn) of the n-th stage GOA unit, and the source of the twenty-first thin film transistor (T21) is connected to the n-th stage GOA
  • the stage signal terminal (STn) of the unit, and the drain of the twenty-first thin film transistor (T21) is connected to the gate signal terminal (Gn) of the nth stage.
  • the pull-down unit is connected to the control node (Qn) of the nth-stage GOA unit, the gate signal terminal (Gn) of the nth-stage GOA unit, and the n+4th stage
  • the first direct current low level terminal (VSSQ) provides the first direct current low level
  • the third stage starts when the stage transmission signal terminal (STn+4) of the n+4th stage GOA unit is at a high potential.
  • the pull-down unit includes a thirty-first thin film transistor (T31) and a forty-first thin film transistor (T41);
  • the source of the thirty-first thin film transistor (T31) is connected to the gate signal terminal (Gn) of the n-th GOA unit, and the source of the forty-first thin film transistor (T41) is connected to the n-th GOA unit.
  • the drains of the thirty-first thin film transistor (T31) and the forty-first thin film transistor (T41) are commonly connected to the first direct current low level terminal (VSSQ), and the thirty-first thin film transistor ( T31) and the gate of the forty-first thin film transistor (T41) are commonly connected to the stage transmission signal terminal (STn+4) of the n+4th GOA unit.
  • This application uses the pull-up control unit and the bootstrap unit to sequentially control the control nodes of the n-th GOA unit to be located at the first high potential and the second high potential.
  • the pull-up unit is based on the potential change of the control node and the second high potential.
  • the n-level transmission signal outputs the gate driving signal, which increases the pulse width of the gate driving signal, and solves the technical problem of insufficient charging capacity of the existing display panel.
  • Fig. 1 is the first circuit structure diagram of the GOA device of this application.
  • the GOA device includes at least two GOA units connected in cascade.
  • the nth level GOA unit is used to output gate drive signals to the nth level horizontal scan line, wherein the nth level GOA unit includes a Pull-up control unit 100, a bootstrap unit 200, a pull-up unit 300, a pull-down unit, and 400 a pull-down maintenance unit 500;
  • the pull-up control unit 100 receives a start signal in the first stage so that the control node (Qn) of the nth-stage GOA unit is pulled up to a first high potential;
  • the bootstrapping unit 200 pulls the control node (Qn) of the nth stage GOA unit to a second high potential in the second stage according to a clock signal;
  • the pull-up unit 300 outputs a pulse width according to the first high potential and the second high potential of the control node (Qn) of the nth GOA unit and the clock signal output by the bootstrap unit.
  • the gate drive signal with twice the pulse width of the clock signal to the gate signal terminal (Gn) of the nth-stage GOA unit;
  • the pull-down unit 400 pulls down the potentials of the control node (Qn) of the n-th GOA unit and the gate signal terminal (Gn) of the n-th GOA unit to a first DC low in the third stage Level;
  • the pull-down sustaining unit 500 maintains the control node (Qn) of the n-th stage GOA unit at the first DC low level in the fourth stage, and turns the gate signal terminal of the n-th stage GOA unit The potential of (Gn) is maintained at a second DC low level.
  • This application uses the pull-up control unit and the bootstrap unit to sequentially control the control nodes of the n-th GOA unit to be located at the first high potential and the second high potential.
  • the pull-up unit is based on the potential change of the control node and the second high potential.
  • the n-level transmission signal outputs the gate driving signal, which increases the pulse width of the gate driving signal, and solves the technical problem of insufficient charging capacity of the existing display panel.
  • the pull-up control unit 100 receives a start signal to cause the control node (Qn) of the nth-stage GOA unit to be pulled up to a first high potential.
  • the pull-up control unit 100 is connected to the stage transmission signal terminal (STn-4) of the n-4th stage GOA unit, the gate signal terminal (Gn-4) of the n-4th stage, and the nth stage. Control node (Qn) of level GOA unit.
  • the start signal is from the stage transmission signal terminal (STn-4) of the n-4th stage GOA unit.
  • the pull-up control unit 100 when the pull-up control unit 100 receives the start signal from the stage transmission signal terminal (STn-4) of the n-4th GOA unit, the pull-up control unit is based on the The gate signal of the gate signal terminal (Gn-4) of the n-4th stage causes the control node (Qn) of the nth stage GOA unit to be pulled up to a first high potential, and the control node (Qn) The waveform of is at the first high potential during the input period of the start signal of the corresponding stage transmission signal terminal (STn-4).
  • the pull-up control unit 100 specifically includes an eleventh thin film transistor (T11).
  • the gate of the eleventh thin film transistor (T11) is connected to the stage transmission signal output terminal (STn-4) of the n-4th stage GOA unit to receive the start signal to turn on the eleventh thin film transistor ( T11).
  • the source of the eleventh thin film transistor (T11) is connected to the gate signal output terminal (Gn-4) of the n-4th stage to receive the gate signal terminal (Gn-4) from the n-4th stage -4) The gate signal.
  • the drain of the eleventh thin film transistor (T11) is connected to the control node (Qn) of the nth level GOA unit, so as to turn on the nth level GOA unit when the eleventh thin film transistor (T11) is turned on.
  • the potential of the control node (Qn) is pulled up to the first high potential.
  • the bootstrapping unit 200 pulls the control node (Qn) of the nth-stage GOA unit to a second high level according to a clock signal (CK).
  • the bootstrap unit 200 is connected to the control node (Qn) of the nth level GOA unit, a clock signal terminal (CK), and the stage transmission signal terminal (STn) of the nth level GOA unit.
  • the clock signal terminal (CK) is used to provide the clock signal.
  • the second stage starts when the control node (Qn) of the nth GOA unit is pulled up to the first high potential, and the potential of the control node (Qn) is at the level of the corresponding clock signal. Under the action, it is pulled high again and is at the second high potential.
  • the second high potential is higher than the first high potential, and the second high potential may be twice the voltage level (VGH).
  • the bootstrap unit 200 includes a bootstrap capacitor Cb and a twenty-second thin film transistor (T22).
  • the bootstrap capacitor Cb is connected to the control node (Qn) of the nth-stage GOA unit and the stage transmission signal terminal (STn) of the nth-stage GOA unit, and the bootstrap capacitor Cb is used to pull up and maintain control The potential of the node (Qn).
  • the gate of the twenty-second thin film transistor (T22) is connected to the control node (Qn) of the n-th GOA unit, and the source of the twenty-second thin film transistor (T22) is connected to the clock signal terminal ( CK), the drain of the twenty-second thin film transistor (T22) is connected to the stage signal terminal (STn) of the nth stage GOA unit.
  • the twenty-second thin film transistor (T22) is mainly used to output another start signal through the stage transmission signal terminal (STn) of the nth stage GOA unit to control the opening and closing of the next stage GOA unit.
  • the pull-up unit 300 is based on the first high potential and the second high potential of the control node (Qn) of the n-th GOA unit and the stage transfer signal (STn) of an n-th GOA unit
  • a gate driving signal with a pulse width twice the pulse width of the clock signal is output to the gate signal terminal (Gn) of the GOA unit of the nth stage.
  • the pull-up unit 300 generates the gate driving signal according to the change in the potential of the control node (Qn) and the stage transfer signal (STn).
  • the waveform of the gate drive signal (Gn) is at the first high potential and the second high potential at the corresponding node (Qn), and its pulse waveform rises in two stages corresponding to the potential change of the node (Qn).
  • the width of the pulse waveform is approximately equivalent to twice the pulse width of the clock signal (CKn).
  • the pull-up unit 300 is connected to the control node (Qn) of the nth-stage GOA unit, the stage transmission signal terminal (STn) of the nth-stage GOA unit, and the gate of the nth stage.
  • Polar signal terminal (Gn) is connected to the control node (Qn) of the nth-stage GOA unit, the stage transmission signal terminal (STn) of the nth-stage GOA unit, and the gate of the nth stage.
  • the stage transmission signal terminal (STn) of the nth stage GOA unit is used to provide a high-level start signal to control the opening and closing of the thin film transistor in the pull-up unit.
  • the pull-up unit 300 includes a twenty-first thin film transistor (T21).
  • the gate of the twenty-first thin film transistor (T21) is connected to the control node (Qn) of the n-th stage GOA unit, and the source of the twenty-first thin film transistor (T21) is connected to the n-th stage GOA
  • the stage signal terminal (STn) of the unit, and the drain of the twenty-first thin film transistor (T21) is connected to the gate signal terminal (Gn) of the nth stage to output the gate drive signal to the nth stage.
  • Level scan line is provided.
  • the pull-down unit 400 pulls down the potentials of the control node (Qn) of the n-th GOA unit and the gate signal terminal (Gn) of the n-th GOA unit To a first DC low level.
  • the pull-down unit 400 is connected to the control node (Qn) of the nth level GOA unit, the gate signal terminal (Gn) of the nth level GOA unit, and the gate signal terminal (Gn) of the n+4th level GOA unit
  • the pull-down unit 400 when the pull-down unit 400 outputs a high potential at the level transmission signal terminal (STn+4) of the n+4th level GOA unit, the control node (Qn) of the nth level GOA unit The electric potential of the gate signal terminal (Gn) of the nth level GOA unit is pulled down to the first direct current low level provided by the first direct current low level terminal (VSSQ).
  • the third stage starts when the stage transmission signal terminal (STn+4) of the n+4th GOA unit is at a high potential, and the waveform of the gate drive signal (Gn) is transmitted at the corresponding stage.
  • the signal terminal (STn+4) is pulled down from the high potential to the low potential during the period when the signal terminal (STn+4) is at a high potential.
  • the pull-down unit 400 mainly includes a thirty-first thin film transistor (T31) and a forty-first thin film transistor (T41).
  • the source of the thirty-first thin film transistor (T31) is connected to the gate signal terminal (Gn) of the n-th GOA unit, and the source of the forty-first thin film transistor (T41) is connected to the n-th GOA unit.
  • the drains of the thirty-first thin film transistor (T31) and the forty-first thin film transistor (T41) are commonly connected to the first direct current low level terminal (VSSQ); the thirty-first thin film transistor (T31) The gate of the forty-first thin film transistor (T41) is commonly connected to the stage transmission signal terminal (STn+4) of the n+4th stage GOA unit.
  • the drains of the thirty-first thin film transistor (T31) and the forty-first thin film transistor (T41) are commonly connected to the first direct current low level terminal (VSSQ), and the thirty-first thin film transistor ( T31) and the gate of the forty-first thin film transistor (T41) are commonly connected to the stage transmission signal terminal (STn+4) of the n+4th GOA unit.
  • the pull-down maintaining unit 500 maintains the control node (Qn) of the nth stage GOA unit at the first DC low level, and turns the nth stage The potential of the gate signal terminal (Gn) of the GOA unit is maintained at a second DC low level.
  • the pull-down sustain unit 500 is mainly connected to the control node (Qn) of the nth stage GOA unit, the gate signal terminal (Gn) of the nth stage, the high voltage direct current signal terminal, The first direct current low level terminal (VSSQ) and the second direct current low level terminal (VSSG).
  • the pull-down sustaining unit maintains the control node (Qn) of the nth-stage GOA unit at the first DC low level, and transmits the gate signal of the nth-stage GOA unit
  • the potential of the terminal (Gn) is maintained at the second DC low level provided by the second DC low level terminal (VSSG).
  • the pull-down maintaining unit 500 may include a first pull-down maintaining sub-unit 501 and a second pull-down maintaining sub-unit 502;
  • the first pull-down sustaining subunit 501 includes a fifty-first thin film transistor (T51), a fifty-second thin film transistor (T52), a fifty-third thin film transistor (T53), and a fifty-fourth thin film transistor (T54). , Forty-second thin film transistor (T42) and thirty-second thin film transistor (T32).
  • the gate and drain of the fifty-first thin film transistor (T51) are connected to the first DC signal terminal LC1, and the source of the fifty-first thin film transistor (T51) is electrically connected to the fifty-first thin film transistor (T51).
  • the gate of the fifty-second thin film transistor (T52) is electrically connected to the output terminal of the pull-up control module, and the source of the fifty-second thin film transistor (T52) is electrically connected to the first DC low level terminal (VSSQ).
  • the drain of the fifty-third thin film transistor (T53) is connected to the first DC signal terminal LC1, and the source of the fifty-third thin film transistor (T53) is electrically connected to the fifty-fourth thin film transistor
  • the gate of the fifty-fourth thin film transistor (T54) is electrically connected to the output terminal of the pull-up control module, and the source of the fifty-fourth thin film transistor (T54) is electrically connected to the first DC low level terminal (VSSQ).
  • the source of the forty-second thin film transistor (T42) is electrically connected to the first DC low-level terminal (VSSQ), and the drain of the forty-second thin film transistor (T42) is electrically connected to the The output terminal of the pull-up control module is described.
  • the source of the thirty-second thin film transistor (T32) is electrically connected to the second DC low level terminal (VSSG), and the drain of the thirty-second thin film transistor (T32) is electrically connected to the The output terminal of the scan signal of this level.
  • the second pull-down sustaining subunit 502 includes a sixty-first thin film transistor (T61), a sixty-second thin film transistor (T62), a sixty-third thin film transistor (T63), a sixty-fourth thin film transistor (T64), The forty-third thin film transistor (T43) and the thirty-third thin film transistor (T33).
  • the gate and drain of the 61st thin film transistor (T61) are connected to the second DC signal terminal LC2, and the source of the 61st thin film transistor (T61) is electrically connected to the 62nd The drain of the thin film transistor (T62) and the gate of the 63rd thin film transistor (T63).
  • the gate of the sixty-second thin film transistor (T62) is electrically connected to the output terminal of the pull-up control module, and the source of the sixty-second thin film transistor (T62) is electrically connected to the first DC low level terminal (VSSQ).
  • the drain of the 63rd thin film transistor (T63) is connected to the second DC signal terminal LC2, and the source of the 63rd thin film transistor (T63) is electrically connected to the 64th thin film transistor ( T64) the drain, the forty-third thin film transistor (T43), and the thirty-third thin film transistor (T33).
  • the gate of the 64th thin film transistor (T64) is electrically connected to the output terminal of the pull-up control module, and the source of the 64th thin film transistor (T64) is electrically connected to the first DC low level terminal (VSSQ).
  • the source of the forty-third thin film transistor (T43) is electrically connected to the first DC low-level terminal (VSSQ), and the drain of the forty-third thin film transistor (T43) is electrically connected to the The output terminal of the pull-up control module is described.
  • the source of the thirty-third thin film transistor (T33) is electrically connected to the second DC low-level terminal (VSSG), and the drain of the thirty-third thin film transistor (T33) is electrically connected to the The output terminal of the scanning signal of this level
  • the voltage of the first direct current signal may be less than the voltage of the second direct current signal, so the drain of the thirty-first thin film transistor (T31) is connected to the first direct current low level terminal ( VSSQ), compared to connecting the second DC low-level terminal (VSSG), it can relatively reduce the falling time (FallingTime) of the waveform output from the gate signal terminal (Gn) of the n-th GOA unit, thereby solving the problem of falling The long time causes the problem of poor picture display quality.
  • This application also proposes a gate drive circuit, wherein the gate drive circuit includes the above-mentioned GOA device.
  • the working principle of the gate driving circuit is the same as or similar to the working principle of the above-mentioned GOA device, and will not be repeated here.
  • the GOA device includes at least two GOA units cascaded.
  • the GOA unit includes a pull-up control unit, a bootstrap unit, a pull-up unit, and a pull-down unit. And pull to maintain the unit.
  • This application uses the pull-up control unit and the bootstrap unit to sequentially control the control nodes of the n-th GOA unit to be located at the first high potential and the second high potential.
  • the n-level transmission signal outputs the gate driving signal, which increases the pulse width of the gate driving signal, and solves the technical problem of insufficient charging capacity of the existing display panel.

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Abstract

一种GOA器件及栅极驱动电路，通过上拉控制单元（100）与自举单元（200）依序控制第n级GOA单元的控制节点（Qn）位于第一高电位和第二高电位，上拉单元（300）依据该控制节点（Qn）的电位变化及第n级的级传信号输出栅极驱动信号，增加了栅极驱动信号的脉冲宽度，解决了现有显示面板充电能力不足的技术问题。

Description

GOA器件及栅极驱动电路
本申请要求于2019年10月16日提交中国专利局、申请号为201910983741.9、发明名称为“GOA器件及栅极驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板制造领域，尤其涉及一种GOA器件及栅极驱动电路。
 背景技术
阵列基板行驱动(Gate Drive On Array，GOA)技术，为将扫描线驱动电路集成在液晶面板的阵列基板上，从而在材料成本和制作工艺方面上降低产品成本。
对于高解析度以及高频率（例如120HZ）的显示面板，由于充电时间较短，扫描线的电容负荷较重，导致栅极脉冲信号的失真较严重，栅极信号线输出讯号的下降时间数值较大，导致错充风险高。而现有技术中，将栅极线转态时间点到数据转态时间点的时间加长，故而实际充电时间就更短，导致充电能力不足以引起显示面板显示异常的技术问题。
目前，亟需一种栅极驱动电路以解决上述技术问题。
 技术问题
本申请提供一种GOA器件及栅极驱动电路，以解决现有高解析度以及高频率显示面板工作时充电能力不足的技术问题。
 技术解决方案
本申请提出了一种GOA器件，包括级联的至少两个GOA单元，第n级GOA单元用于对第n级水平扫描线输出栅极驱动信号，其中，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；
所述上拉控制单元于第一阶段接收一启动信号而使所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位；
所述自举单元于第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至第二高电位；
所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一所述自举单元输出的所述时钟信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
所述下拉单元于第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
所述下拉维持单元于第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
在本申请的GOA器件中，所述上拉控制单元连接第n-4级GOA单元的级传信号端(STn-4)、第n-4级的栅极信号端(Gn-4)和所述第n级GOA单元的控制节点(Qn)；
在所述第一阶段中，所述上拉控制单元自所述第n-4级GOA单元的级传信号端(STn-4)接收所述启动信号，以及根据所述第n-4级的栅极信号端(Gn-4)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位。
在本申请的GOA器件中，
所述上拉控制单元包括一第十一薄膜晶体管(T11)；
所述第十一薄膜晶体管(T11)的栅极连接所述第n-4级GOA单元的级传信号输出端(STn-4)，所述第十一薄膜晶体管(T11)的源极连接所述第n-4级的栅极信号输出端(Gn-4)，所述第十一薄膜晶体管(T11)的漏极连接所述第n级GOA单元的控制节点(Qn)。
在本申请的GOA器件中，
所述自举单元连接所述第n级GOA单元的控制节点(Qn)、时钟信号端(CK)、及第n级GOA单元的级传信号端(STn)；
所述时钟信号端(CK)提供所述时钟信号；
所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至所述第一高电位。
在本申请的GOA器件中，所述自举单元包括一自举电容及一第二十二薄膜晶体管(T22)；
所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；
所述第二十二薄膜晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十二薄膜晶体管(T22)的源极连接所述时钟信号端(CK)，所述第二十二薄膜晶体管(T22)的漏极连接所述第n级GOA单元的级传信号端(STn)。
在本申请的GOA器件中，所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的级传信号端(STn)、及所述第n级的栅极信号端(Gn)；
所述第n级GOA单元的级传信号端(STn)用于提供一启动信号以控制所述上拉单元中的薄膜晶体管打开和关闭。
在本申请的GOA器件中，
所述上拉单元包括一第二十一薄膜晶体管(T21)；
所述第二十一薄膜晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十一薄膜晶体管(T21)的源极连接所述第n级GOA单元的级传信号端(STn)，所述第二十一薄膜晶体管(T21)的漏极连接所述第n级的栅极信号端(Gn)。
在本申请的GOA器件中，
所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+4级GOA单元的级传信号端(STn+4)、以及一第一直流低电平端(VSSQ)；
所述第一直流低电平端(VSSQ)提供所述第一直流低电平；
所述第三阶段开始于所述第n+4级GOA单元的级传信号端(STn+4)处于高电位时。
在本申请的GOA器件中，所述下拉单元包括一第三十一薄膜晶体管(T31)及一第四十一薄膜晶体管(T41)；
所述第三十一薄膜晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)，所述第四十一薄膜晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)；
所述第三十一薄膜晶体管(T31)和所述第四十一薄膜晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)，所述第三十一薄膜晶体管(T31)和第所述四十一薄膜晶体管(T41)的栅极共同连接所述第n+4级GOA单元的级传信号端(STn+4)。
本申请还提出了一种栅极驱动电路，其中，所述栅极驱动电路包括GOA器件，所述GOA器件包括级联的至少两个GOA单元，第n级GOA单元用于对第n级水平扫描线输出栅极驱动信号，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；
所述上拉控制单元于第一阶段接收一启动信号而使所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位；
所述自举单元于第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至第二高电位；
所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一所述自举单元输出的所述时钟信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
所述下拉单元于第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
所述下拉维持单元于第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
在本申请的栅极驱动电路中，所述上拉控制单元连接第n-4级GOA单元的级传信号端(STn-4)、第n-4级的栅极信号端(Gn-4)和所述第n级GOA单元的控制节点(Qn)；
在所述第一阶段中，所述上拉控制单元自所述第n-4级GOA单元的级传信号端(STn-4)接收所述启动信号，以及根据所述第n-4级的栅极信号端(Gn-4)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位。
在本申请的栅极驱动电路中，
所述上拉控制单元包括一第十一薄膜晶体管(T11)；
所述第十一薄膜晶体管(T11)的栅极连接所述第n-4级GOA单元的级传信号输出端(STn-4)，所述第十一薄膜晶体管(T11)的源极连接所述第n-4级的栅极信号输出端(Gn-4)，所述第十一薄膜晶体管(T11)的漏极连接所述第n级GOA单元的控制节点(Qn)。
在本申请的栅极驱动电路中，所述自举单元连接所述第n级GOA单元的控制节点(Qn)、时钟信号端(CK)、及第n级GOA单元的级传信号端(STn)；
所述时钟信号端(CK)提供所述时钟信号；
所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至所述第一高电位。
在本申请的栅极驱动电路中，所述自举单元包括一自举电容及一第二十二薄膜晶体管(T22)；
所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；
所述第二十二薄膜晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十二薄膜晶体管(T22)的源极连接所述时钟信号端(CK)，所述第二十二薄膜晶体管(T22)的漏极连接所述第n级GOA单元的级传信号端(STn)。
在本申请的栅极驱动电路中，所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的级传信号端(STn)、及所述第n级的栅极信号端(Gn)；
所述第n级GOA单元的级传信号端(STn)用于提供一启动信号以控制所述上拉单元中的薄膜晶体管打开和关闭。
在本申请的栅极驱动电路中，
所述上拉单元包括一第二十一薄膜晶体管(T21)；
所述第二十一薄膜晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十一薄膜晶体管(T21)的源极连接所述第n级GOA单元的级传信号端(STn)，所述第二十一薄膜晶体管(T21)的漏极连接所述第n级的栅极信号端(Gn)。
在本申请的栅极驱动电路中，所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+4级GOA单元的级传信号端(STn+4)、以及一第一直流低电平端(VSSQ)；
所述第一直流低电平端(VSSQ)提供所述第一直流低电平；
所述第三阶段开始于所述第n+4级GOA单元的级传信号端(STn+4)处于高电位时。
在本申请的栅极驱动电路中，所述下拉单元包括一第三十一薄膜晶体管(T31)及一第四十一薄膜晶体管(T41)；
所述第三十一薄膜晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)，所述第四十一薄膜晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)；
所述第三十一薄膜晶体管(T31)和所述第四十一薄膜晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)，所述第三十一薄膜晶体管(T31)和第所述四十一薄膜晶体管(T41)的栅极共同连接所述第n+4级GOA单元的级传信号端(STn+4)。
 有益效果
本申请通过所述上拉控制单元与自举单元依序控制第n级GOA单元的控制节点位于第一高电位和第二高电位，所述上拉单元依据所述控制节点的电位变化及第n级的级传信号输出栅极驱动信号，增加了栅极驱动信号的脉冲宽度，解决了现有显示面板充电能力不足的技术问题。
 附图说明
图1为本申请GOA器件的第一种电路结构图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
对于高解析度以及高频率（例如120HZ）的显示面板，由于充电时间较短，扫描线的电容负荷较重，导致栅极脉冲信号的失真较严重，栅极信号线输出讯号的下降时间数值较大，导致错充风险高。而现有技术中，将栅极线转态时间点到数据转态时间点的时间加长，故而实际充电时间就更短，导致充电能力不足以引起显示面板显示异常的技术问题。本申请基于上述技术问题提出了一种GOA器件。
请参阅图1，所述GOA器件包括级联的至少两个GOA单元，第n级GOA单元用于对第n级水平扫描线输出栅极驱动信号，其中，所述第n级GOA单元包括一上拉控制单元100、一自举单元200、一上拉单元300、一下拉单元以及400一下拉维持单元500；
所述上拉控制单元100于第一阶段接收一启动信号而使所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位；
所述自举单元200于第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至第二高电位；
所述上拉单元300依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一所述自举单元输出的所述时钟信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
所述下拉单元400于第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
所述下拉维持单元500于第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
本申请通过所述上拉控制单元与自举单元依序控制第n级GOA单元的控制节点位于第一高电位和第二高电位，所述上拉单元依据所述控制节点的电位变化及第n级的级传信号输出栅极驱动信号，增加了栅极驱动信号的脉冲宽度，解决了现有显示面板充电能力不足的技术问题。
下面将以第n级GOA单元的四个工作阶段为例进行说明。
请参阅图1，在第一阶段中，所述上拉控制单元100接收一启动信号而使所述第n级GOA单元的控制节点(Qn)被拉高至一第一高电位。
在本实施例中，所述上拉控制单元100连接第n-4级GOA单元的级传信号端(STn-4)、第n-4级的栅极信号端(Gn-4)和第n级GOA单元的控制节点(Qn)。所述启动信号是来自所述第n-4级GOA单元的级传信号端(STn-4)。
在本实施例中，当所述上拉控制单元100自所述第n-4级GOA单元的级传信号端(STn-4)接收所述启动信号时，所述上拉控制单元依据所述第n-4级的栅极信号端(Gn-4)的栅极信号使所述第n级GOA单元的控制节点(Qn)的电位被拉高处于一第一高电位，控制节点(Qn)的波形在对应级传信号端(STn-4)的启动信号输入期间处于第一高电位。
在本实施例中，所述上拉控制单元100具体包括一第十一薄膜晶体管(T11)。所述第十一薄膜晶体管(T11)的栅极是连接所述第n-4级GOA单元的级传信号输出端(STn-4)，以接收所述启动信号而打开第十一薄膜晶体管(T11)。所述第十一薄膜晶体管(T11)的源极连接所述第n-4级的栅极信号输出端(Gn-4)，以接收来自所述第n-4级的栅极信号端(Gn-4)的栅极信号。所述第十一薄膜晶体管(T11)的漏极则连接所述第n级GOA单元的控制节点(Qn)，以在第十一薄膜晶体管(T11)打开时将所述第n级GOA单元的控制节点(Qn)的电位拉高至所述第一高电位。
请参阅图1，在第二阶段中，所述自举单元200根据一时钟信号(CK)将所述第n级GOA单元的控制节点(Qn)拉高至一第二高电位。
在本实施例中，所述自举单元200连接所述第n级GOA单元的控制节点(Qn)、一时钟信号端(CK)及第n级GOA单元的级传信号端(STn)。
在本实施例中，所述时钟信号端(CK)用以提供所述时钟信号。
在本实施例中，所述第二阶段则开始于所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位之时，控制节点(Qn)的电位在对应时钟信号的作用下被再次拉高而处于第二高电位。
在本实施例中，所述第二高电位高于所述第一高电位，所述第二高电位可以是两倍的电压位准(VGH)。
在本实施例中，所述自举单元200包括一自举电容Cb及一第二十二薄膜晶体管(T22)。所述自举电容Cb连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)，所述自举电容Cb用于拉高并维持控制节点(Qn)的电位。所述第二十二薄膜晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十二薄膜晶体管(T22)的源极连接所述时钟信号端(CK)，所述第二十二薄膜晶体管(T22)的漏极连接所述第n级GOA单元的级传信号端(STn)。所述第二十二薄膜晶体管(T22)主要用以通过所述第n级GOA单元的级传信号端(STn)输出另一启动信号，以控制下一级GOA单元的打开和关闭。
在本实施例中，所述上拉单元300根据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一第n级GOA单元的级传信号(STn)输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)。
在本实施例中，所述上拉单元300根据控制节点(Qn)的电位变化与所述级传信号(STn)来生成所述栅极驱动信号。
在第二阶段中，所述栅极驱动信号(Gn)的波形在对应节点(Qn)处于第一高电位和第二高电位，其脉冲波形对应节点(Qn)的电位变化分两阶段抬升，其脉冲波形的宽度大约相当于所述时钟信号(CKn)的脉冲宽度的两倍。
在本实施例中，所述上拉单元300连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的级传信号端(STn)和所述第n级的栅极信号端(Gn)。
在本实施例中，所述第n级GOA单元的级传信号端(STn)用于提供一高电位的启动信号以控制所述上拉单元中的薄膜晶体管打开和关闭。
在本实施例中，所述上拉单元300包括一第二十一薄膜晶体管(T21)。所述第二十一薄膜晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十一薄膜晶体管(T21)的源极连接所述第n级GOA单元的级传信号端(STn)，所述第二十一薄膜晶体管(T21)的漏极连接所述第n级的栅极信号端(Gn)，以输出所述栅极驱动信号至第n级扫描线。
请参阅图1，在第三阶段中，所述下拉单元400将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平。
在本实施例中，所述下拉单元400连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+4级GOA单元的级传信号端(STn+4)以及一第一直流低电平端(VSSQ)。
在本实施例中，所述下拉单元400在所述第n+4级GOA单元的级传信号端(STn+4)输出高电位时，将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至所述第一直流低电平端(VSSQ)提供的第一直流低电平。
在本实施例中，所述第三阶段开始于第n+4级GOA单元的级传信号端(STn+4)处于高电位时，所述栅极驱动信号(Gn)的波形在对应级传信号端(STn+4)处于高电位的期间从高电位被拉低为低电位。
在本实施例中，所述下拉单元400主要包括一第三十一薄膜晶体管(T31)及一第四十一薄膜晶体管(T41)。所述第三十一薄膜晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)，所述第四十一薄膜晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)。
所述第三十一薄膜晶体管(T31)和第四十一薄膜晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)；所述第三十一薄膜晶体管(T31)和第四十一薄膜晶体管(T41)的栅极共同连接所述第n+4级GOA单元的级传信号端(STn+4)。所述第三十一薄膜晶体管(T31)和所述第四十一薄膜晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)，所述第三十一薄膜晶体管(T31)和第所述四十一薄膜晶体管(T41)的栅极共同连接所述第n+4级GOA单元的级传信号端(STn+4)。
请参阅图1，在第四阶段中，所述下拉维持单元500将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
在本实施例中，所述下拉维持单元500主要是连接所述第n级GOA单元的控制节点(Qn)、所述第n级的栅极信号端(Gn)、所述高压直流信号端、所述第一直流低电平端(VSSQ)、及所述第二直流低电平端(VSSG)。
在本实施例中，所述下拉维持单元将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于所述第二直流低电平端(VSSG)提供的第二直流低电平。
在本实施例中，所述下拉维持单元500可以包括第一下拉维持子单元501及第二下拉维持子单元502；
所述第一下拉维持子单元501包括第五十一薄膜晶体管(T51)、第五十二薄膜晶体管(T52)、第五十三薄膜晶体管(T53)、第五十四薄膜晶体管(T54)、第四十二薄膜晶体管(T42)以及第三十二薄膜晶体管(T32)。
所述第五十一薄膜晶体管(T51)的栅极以及漏极接入第一直流信号端LC1，所述第五十一薄膜晶体管(T51)的源极电性连接于所述第五十二薄膜晶体管(T52)的漏极以及所述第五十三薄膜晶体管(T53)的栅极。
所述第五十二薄膜晶体管(T52)的栅极电性连接至所述上拉控制模块的输出端，所述第五十二薄膜晶体管(T52)的源极电性连接于所述第一直流低电平端(VSSQ)。
所述第五十三薄膜晶体管(T53)的漏极接入第一直流信号端LC1，所述第五十三薄膜晶体管(T53)的源极电性连接至所述第五十四薄膜晶体管(T54)的漏极、所述第四十二薄膜晶体管(T42)的栅极以及所述第三十二薄膜晶体管(T32)的栅极。
所述第五十四薄膜晶体管(T54)的栅极电性连接至所述上拉控制模块的输出端，所述第五十四薄膜晶体管(T54)的源极电性连接于所述第一直流低电平端(VSSQ)。
所述第四十二薄膜晶体管(T42)的源极电性连接于所述第一直流低电平端(VSSQ)，所述第四十二薄膜晶体管(T42)的漏极电性连接至所述上拉控制模块的输出端。
所述第三十二薄膜晶体管(T32)的源极电性连接于所述第二直流低电平端(VSSG)，所述第三十二薄膜晶体管(T32)的漏极电性连接至所述本级的扫描信号的输出端。
所述第二下拉维持子单元502包括第六十一薄膜晶体管(T61)、第六十二薄膜晶体管(T62)、第六十三薄膜晶体管(T63)、第六十四薄膜晶体管(T64)、第四十三薄膜晶体管(T43)以及第三十三薄膜晶体管(T33)。
所述第六十一薄膜晶体管(T61)的栅极以及漏极接入第二直流信号端LC2，所述第六十一薄膜晶体管(T61)的源极电性连接于所述第六十二薄膜晶体管(T62)的漏极以及所述第六十三薄膜晶体管(T63)的栅极。
所述第六十二薄膜晶体管(T62)的栅极电性连接至所述上拉控制模块的输出端，所述第六十二薄膜晶体管(T62)的源极电性连接至所述第一直流低电平端(VSSQ)。
所述第六十三薄膜晶体管(T63)的漏极接入第二直流信号端LC2，所述第六十三薄膜晶体管(T63)的源极电性连接于所述第六十四薄膜晶体管(T64)的漏极、所述第四十三薄膜晶体管(T43)的栅极以及所述第三十三薄膜晶体管(T33)的栅极。
所述第六十四薄膜晶体管(T64)的栅极电性连接至所述上拉控制模块的输出端，所述第六十四薄膜晶体管(T64)的源极电性连接于所述第一直流低电平端(VSSQ)。
所述第四十三薄膜晶体管(T43)的源极电性连接于所述第一直流低电平端(VSSQ)，所述第四十三薄膜晶体管(T43)的漏极电性连接于所述上拉控制模块的输出端。
所述第三十三薄膜晶体管(T33)的源极电性连接于所述第二直流低电平端(VSSG)，所述第三十三薄膜晶体管(T33)的漏极电性连接于所述本级的扫描信号的输出端
在本实施例中，所述第一直流信号的电压可以小于第二直流信号的电压，故所述第三十一薄膜晶体管(T31)的漏极连接所述第一直流低电平端(VSSQ)，相较于连接第二直流低电平端(VSSG)，可相对减少所述第n级GOA单元的栅极信号端(Gn)输出的波形的下降时间(FallingTime)，从而可以解决因下降时间长而导致画面显示品质差的问题。
本申请还提出了一种栅极驱动电路，其中，所述栅极驱动电路包括上述GOA器件。所述栅极驱动电路的工作原理与上述GOA器件的工作原理相同或相似，此处不再赘述。
本申请提出了一种GOA器件及栅极驱动电路，该GOA器件包括级联的至少两个GOA单元，该GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元。本申请通过所述上拉控制单元与自举单元依序控制第n级GOA单元的控制节点位于第一高电位和第二高电位，所述上拉单元依据所述控制节点的电位变化及第n级的级传信号输出栅极驱动信号，增加了栅极驱动信号的脉冲宽度，解决了现有显示面板充电能力不足的技术问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (18)

  1. 一种GOA器件，包括级联的至少两个GOA单元，第n级GOA单元用于对第n级水平扫描线输出栅极驱动信号，其中，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；
    所述上拉控制单元于第一阶段接收一启动信号而使所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位；
    所述自举单元于第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至第二高电位；
    所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一所述自举单元输出的所述时钟信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
    所述下拉单元于第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
    所述下拉维持单元于第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
  2. 根据权利要求1所述的GOA器件，其中，
    所述上拉控制单元连接第n-4级GOA单元的级传信号端(STn-4)、第n-4级的栅极信号端(Gn-4)和所述第n级GOA单元的控制节点(Qn)；
    在所述第一阶段中，所述上拉控制单元自所述第n-4级GOA单元的级传信号端(STn-4)接收所述启动信号，以及根据所述第n-4级的栅极信号端(Gn-4)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位。
  3. 根据权利要求2所述的GOA器件，其中，
    所述上拉控制单元包括一第十一薄膜晶体管(T11)；
    所述第十一薄膜晶体管(T11)的栅极连接所述第n-4级GOA单元的级传信号输出端(STn-4)，所述第十一薄膜晶体管(T11)的源极连接所述第n-4级的栅极信号输出端(Gn-4)，所述第十一薄膜晶体管(T11)的漏极连接所述第n级GOA单元的控制节点(Qn)。
  4. 根据权利要求1所述的GOA器件，其中，
    所述自举单元连接所述第n级GOA单元的控制节点(Qn)、时钟信号端(CK)、及第n级GOA单元的级传信号端(STn)；
    所述时钟信号端(CK)提供所述时钟信号；
    所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至所述第一高电位。
  5. 根据权利要求4所述的GOA器件，其中，所述自举单元包括一自举电容及一第二十二薄膜晶体管(T22)；
    所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；
    所述第二十二薄膜晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十二薄膜晶体管(T22)的源极连接所述时钟信号端(CK)，所述第二十二薄膜晶体管(T22)的漏极连接所述第n级GOA单元的级传信号端(STn)。
  6. 根据权利要求1所述的GOA器件，其中，所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的级传信号端(STn)、及所述第n级的栅极信号端(Gn)；
    所述第n级GOA单元的级传信号端(STn)用于提供一启动信号以控制所述上拉单元中的薄膜晶体管打开和关闭。
  7. 根据权利要求6所述的GOA器件，其中，
    所述上拉单元包括一第二十一薄膜晶体管(T21)；
    所述第二十一薄膜晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十一薄膜晶体管(T21)的源极连接所述第n级GOA单元的级传信号端(STn)，所述第二十一薄膜晶体管(T21)的漏极连接所述第n级的栅极信号端(Gn) 。
  8. 根据权利要求1所述的GOA器件，其中，
    所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+4级GOA单元的级传信号端(STn+4)、以及一第一直流低电平端(VSSQ)；
    所述第一直流低电平端(VSSQ)提供所述第一直流低电平；
    所述第三阶段开始于所述第n+4级GOA单元的级传信号端(STn+4)处于高电位时。
  9. 根据权利要求8所述的GOA器件，其中，
    所述下拉单元包括一第三十一薄膜晶体管(T31)及一第四十一薄膜晶体管(T41)；
    所述第三十一薄膜晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)，所述第四十一薄膜晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)；
    所述第三十一薄膜晶体管(T31)和所述第四十一薄膜晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)，所述第三十一薄膜晶体管(T31)和第所述四十一薄膜晶体管(T41)的栅极共同连接所述第n+4级GOA单元的级传信号端(STn+4)。
  10. 一种栅极驱动电路，其中，所述栅极驱动电路包括GOA器件，所述GOA器件包括级联的至少两个GOA单元，第n级GOA单元用于对第n级水平扫描线输出栅极驱动信号，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；
    所述上拉控制单元于第一阶段接收一启动信号而使所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位；
    所述自举单元于第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至第二高电位；
    所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一所述自举单元输出的所述时钟信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
    所述下拉单元于第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
    所述下拉维持单元于第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
  11. 根据权利要求10所述的栅极驱动电路，其中，
    所述上拉控制单元连接第n-4级GOA单元的级传信号端(STn-4)、第n-4级的栅极信号端(Gn-4)和所述第n级GOA单元的控制节点(Qn)；
    在所述第一阶段中，所述上拉控制单元自所述第n-4级GOA单元的级传信号端(STn-4)接收所述启动信号，以及根据所述第n-4级的栅极信号端(Gn-4)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位。
  12. 根据权利要求11所述的栅极驱动电路，其中，
    所述上拉控制单元包括一第十一薄膜晶体管(T11)；
    所述第十一薄膜晶体管(T11)的栅极连接所述第n-4级GOA单元的级传信号输出端(STn-4)，所述第十一薄膜晶体管(T11)的源极连接所述第n-4级的栅极信号输出端(Gn-4)，所述第十一薄膜晶体管(T11)的漏极连接所述第n级GOA单元的控制节点(Qn)。
  13. 根据权利要求10所述的栅极驱动电路，其中，
    所述自举单元连接所述第n级GOA单元的控制节点(Qn)、时钟信号端(CK)、及第n级GOA单元的级传信号端(STn)；
    所述时钟信号端(CK)提供所述时钟信号；
    所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至所述第一高电位。
  14. 根据权利要求13所述的栅极驱动电路，其中，所述自举单元包括一自举电容及一第二十二薄膜晶体管(T22)；
    所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；
    所述第二十二薄膜晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十二薄膜晶体管(T22)的源极连接所述时钟信号端(CK)，所述第二十二薄膜晶体管(T22)的漏极连接所述第n级GOA单元的级传信号端(STn)。
  15. 根据权利要求10所述的栅极驱动电路，其中，所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的级传信号端(STn)、及所述第n级的栅极信号端(Gn)；
    所述第n级GOA单元的级传信号端(STn)用于提供一启动信号以控制所述上拉单元中的薄膜晶体管打开和关闭。
  16. 根据权利要求15所述的栅极驱动电路，其中，
    所述上拉单元包括一第二十一薄膜晶体管(T21)；
    所述第二十一薄膜晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二十一薄膜晶体管(T21)的源极连接所述第n级GOA单元的级传信号端(STn)，所述第二十一薄膜晶体管(T21)的漏极连接所述第n级的栅极信号端(Gn) 。
  17. 根据权利要求10所述的栅极驱动电路，其中，
    所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+4级GOA单元的级传信号端(STn+4)、以及一第一直流低电平端(VSSQ)；
    所述第一直流低电平端(VSSQ)提供所述第一直流低电平；
    所述第三阶段开始于所述第n+4级GOA单元的级传信号端(STn+4)处于高电位时。
  18. 根据权利要求17所述的栅极驱动电路，其中，
    所述下拉单元包括一第三十一薄膜晶体管(T31)及一第四十一薄膜晶体管(T41)；
    所述第三十一薄膜晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)，所述第四十一薄膜晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)；
    所述第三十一薄膜晶体管(T31)和所述第四十一薄膜晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)，所述第三十一薄膜晶体管(T31)和第所述四十一薄膜晶体管(T41)的栅极共同连接所述第n+4级GOA单元的级传信号端(STn+4)。
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