WO2021007932A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2021007932A1
WO2021007932A1 PCT/CN2019/104296 CN2019104296W WO2021007932A1 WO 2021007932 A1 WO2021007932 A1 WO 2021007932A1 CN 2019104296 W CN2019104296 W CN 2019104296W WO 2021007932 A1 WO2021007932 A1 WO 2021007932A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
potential
signal
node
Prior art date
Application number
PCT/CN2019/104296
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English (en)
French (fr)
Inventor
薛炎
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2021007932A1 publication Critical patent/WO2021007932A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Display
  • LCD TV mobile phone
  • PDA personal digital assistant
  • digital camera computer screen or laptop screen, etc.
  • GOA Gate Driver on Array
  • TFT Thin The Film Transistor
  • the GOA circuit has two basic functions: the first is to output the gate scan driving signal, which drives the gate line in the panel, and turns on the TFT in the display area to charge the pixels; the second is the shift register function, which acts as a gate After the output of the pole scan drive signal is completed, the next gate scan drive signal is output through clock control, and is passed on in sequence.
  • GOA technology can reduce the bonding process of an external integrated circuit (IC), which has the opportunity to increase production capacity and reduce product costs, and it can make LCD panels more suitable for manufacturing display products with narrow bezels.
  • IC external integrated circuit
  • the existing GOA circuit includes multi-level GOA units.
  • Each level of GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down module, and a pull-down maintenance module.
  • the pull-up control module is used to pull up the first The potential of the node
  • the pull-up module is used to output the scan signal under the control of the potential of the first node
  • the download module is used to output the level transmission signal under the control of the potential of the first node
  • the pull-down module is used to control the first node and the scan signal
  • the pull-down sustain module is used to maintain the potential of the first node and the scan signal at a low potential under the control of the potential of the first node.
  • the pull-down sustain module is provided with a device for maintaining the first node and the scan signal at a low potential.
  • a plurality of thin film transistors, the gates of the plurality of thin film transistors are electrically connected to an output terminal of an inverter, the input terminal of the inverter is electrically connected to a first node, and the inverter outputs when the first node is at a high potential
  • the low potential controls the plurality of thin film transistors to be turned off, and when the first node is at a low potential, the inverter outputs a high potential to control the plurality of thin film transistors to turn on so as to maintain the potentials of the first node and the scanning signal at a low potential.
  • the first node in each level of GOA unit is at a high potential for a short period of time and stays at a low potential for a long time. This results in multiple thin film transistors used to maintain the first node and the scan signal at a low potential. If it is in a forward bias for a long time and is subjected to a positive stress, its threshold voltage will gradually be forward biased, resulting in a decrease in the stability of the GOA circuit.
  • the object of the present invention is to provide a GOA circuit that can recover the threshold voltage offset of the thin film transistor in the pull-down maintenance module, and the GOA circuit has high stability.
  • the present invention first provides a GOA circuit including multi-level GOA units, each level of GOA unit includes a pull-up control module, a pull-up module, a downstream module, a pull-down module, a pull-down maintenance module, and offset recovery Control module
  • N be a positive integer, except for the first and last level GOA units, in the Nth level GOA unit,
  • the pull-up control module is connected to the first clock signal and the level transmission signal of the N-1th level GOA unit and is electrically connected to the first node, and is used to comply with the N-1th level GOA unit under the control of the first clock signal
  • the level transmission signal pulls up the potential of the first node
  • the pull-up module is connected to the second clock signal and is electrically connected to the first node, for outputting a scan signal according to the second clock signal under the control of the potential of the first node;
  • the download module is connected to the second clock signal and electrically connected to the first node, and is used to output a signal according to the second clock signal under the control of the potential of the first node;
  • the pull-down module is connected to the stage transmission signal, the first potential signal, the second potential signal, and the scanning signal of the N+1 level GOA unit, and is electrically connected to the first node for use in the N+1 level GOA unit Changing the potential of the first node to the potential of the first potential signal and changing the potential of the scanning signal to the potential of the second potential signal under the control of the stage transmission signal;
  • the pull-down maintenance module includes an inverter and a sub pull-down maintenance module; the input terminal of the inverter is electrically connected to a first node, and the output terminal is electrically connected to a second node; the sub pull-down maintenance module is connected to a first potential
  • the signal, the second potential signal, the scanning signal, and the level transmission signal are electrically connected to the first node and the second node, and are used to maintain the potential of the first node and the level transmission signal at the first potential under the control of the potential of the second node The potential of the signal and maintaining the potential of the scan signal at the potential of the second potential signal;
  • the offset recovery control module is connected to the first potential signal and the constant voltage low potential and is electrically connected to the second node for pulling the potential of the second node to the constant voltage low potential under the control of the first potential signal.
  • the working process of the GOA circuit includes successively alternating programming phases and blanking phases; in the programming phase, the first clock signal and the second clock signal are both pulse signals, and the first potential signal and the second potential signal Both are low potentials; in the blanking phase, the first clock signal and the second clock signal are both low potentials, and the first and second potential signals are both high potentials.
  • the waveforms of the first clock signal and the second clock signal are opposite, and the duty cycle is both 0.5.
  • Each level of GOA unit also includes a scan signal control module, the scan signal control module is connected to the first clock signal, the second clock signal, the constant voltage low potential and the scan signal, used for the first clock signal and the second clock signal Maintain the scanning signal at a constant voltage low potential when both are low potentials.
  • the scan signal control module includes a seventy-first thin film transistor, a seventy-second thin film transistor, a seventy-third thin film transistor, and a seventy-fourth thin film transistor; the gate of the seventy-first thin film transistor is connected to the second For a clock signal, the source is electrically connected to the drain of the seventy-third thin film transistor, and the drain is connected to the second potential signal; the gate of the seventy-second thin film transistor is connected to the first clock signal, and the source is electrically connected The drain of the seventy-third thin film transistor is connected to the second potential signal; the gate and source of the seventy-third thin film transistor are both connected to a constant voltage high potential, and the drain is electrically connected to the seventy-fourth The gate of the thin film transistor; the source of the seventy-fourth thin film transistor is connected to the scan signal, and the drain is connected to the constant voltage low potential.
  • the potential of the first potential signal is less than the potential of the second potential signal; in the blanking phase, the potential of the first potential signal is equal to the potential of the second potential signal.
  • the offset recovery control module includes an eighth thin film transistor; the gate of the eighth thin film transistor is connected to a first potential signal, the source is electrically connected to the second node, and the drain is connected to a constant voltage low potential.
  • N be a positive integer, except for the first and last level GOA units, in the Nth level GOA unit,
  • the pull-up control module includes an eleventh thin film transistor, a twelfth thin film transistor, and a sixth thin film transistor; the gate of the eleventh thin film transistor is connected to the first clock signal, and the source is connected to the N-1th stage For the stage signal of the GOA unit, the drain is electrically connected to the source of the twelfth thin film transistor; the gate of the twelfth thin film transistor is connected to the first clock signal, and the drain is electrically connected to the first node; The gate of the sixth thin film transistor is connected to the stage to transmit signals, the source is electrically connected to the drain of the eleventh thin film transistor, and the drain is electrically connected to the pull-up module;
  • the pull-up module includes a twenty-first thin film transistor, a twenty-third thin film transistor, and a bootstrap capacitor; the gate of the twenty-first thin film transistor is electrically connected to the first node, and the source is connected to the second clock signal , The drain output scan signal; the gate of the twenty-third thin film transistor is electrically connected to the first node, the source is connected to the second clock signal, and the drain is electrically connected to the drain of the sixth thin film transistor; One end of the capacitor is electrically connected to the first node, and the other end is connected to the scanning signal;
  • the download module includes a twenty-second thin film transistor; the gate of the twenty-second thin film transistor is electrically connected to the first node, the source is connected to the second clock signal, and the drain outputs the signal through the stage;
  • the pull-down module includes a thirty-first thin film transistor, a thirty-second thin film transistor, and a thirty-third thin film transistor; the gate of the thirty-first thin film transistor is connected to the stage transmission signal of the N+1th level GOA unit , The source is connected to the scan signal, and the drain is connected to the second potential signal; the gate of the thirty-second thin film transistor is connected to the stage transmission signal of the N+1 level GOA unit, and the source is electrically connected to the first node , The drain is electrically connected to the source of the thirty-third thin film transistor and the source of the sixth thin film transistor; the gate of the thirty-third thin film transistor is connected to the stage transmission signal of the N+1th stage GOA unit, and the drain The pole is connected to the first potential signal;
  • the inverter includes a fifty-first thin film transistor, a fifty-second thin film transistor, a fifty-third thin film transistor, and a fifty-fourth thin film transistor; the gate and source of the fifty-first thin film transistor are both connected Into the constant voltage high potential, the drain is electrically connected to the source of the fifty-second thin film transistor; the gate of the fifty-second thin film transistor is electrically connected to the first node, and the drain is connected to the first potential signal; The gate of the fifty-third thin film transistor is electrically connected to the drain of the fifty-first thin film transistor, the source is connected to a constant voltage and high potential, and the drain is electrically connected to the second node; the gate of the fifty-fourth thin film transistor The electrode is electrically connected to the first node, the source is electrically connected to the second node, and the drain is connected to the first potential signal;
  • the sub pull-down maintenance module includes the 41st thin film transistor, the 42nd thin film transistor, the 43rd thin film transistor, the 44th thin film transistor, and the 45th thin film transistor; the 41st thin film transistor
  • the gate is electrically connected to the second node, the source is connected to the scan signal, and the drain is connected to the second potential signal;
  • the gate of the forty-second thin film transistor is electrically connected to the second node, and the source is connected to the Signal, the drain is connected to the first potential signal;
  • the gate of the forty-third thin film transistor is electrically connected to the second node, the source is electrically connected to the drain of the sixth thin film transistor, and the drain is connected to the second potential signal
  • the gate of the forty-fourth thin film transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the source of the forty-fifth thin film transistor and the source of the sixth thin film transistor ;
  • the source of the eleventh thin film transistor is connected to the start signal.
  • the gates of the thirty-first thin film transistor, the thirty-second thin film transistor, and the thirty-third thin film transistor are all connected to the start signal.
  • each level of GOA unit of the GOA circuit of the present invention includes a pull-up control module, a pull-up module, a download module, a pull-down module, a pull-down maintenance module, and an offset recovery control module.
  • the drains of the thin film transistors whose gates are electrically connected to the second node are connected to the first potential signal or the second potential signal, and the offset recovery control module is connected to the first potential signal and the constant voltage low potential and is electrically connected to the second When the node is in the blanking phase, the first potential signal and the second potential signal are high.
  • the offset recovery control module pulls the potential of the second node to a constant voltage low potential, so that the pull-down maintains the gate voltage in the module.
  • the reverse bias of the thin film transistor that is connected to the second node restores the threshold voltage shift generated in the programming phase, and improves the stability of the GOA circuit.
  • FIG. 1 is a circuit diagram of the GOA circuit of the present invention.
  • Fig. 2 is a circuit diagram of the first-stage GOA unit of the GOA circuit of the present invention
  • Fig. 3 is a circuit diagram of the last stage GOA unit of the GOA circuit of the present invention.
  • FIG. 5 is a timing diagram of the Nth level GOA unit in the programming phase of the GOA circuit of the present invention.
  • the present invention provides a GOA circuit, including multi-level GOA units, each level of GOA unit includes a pull-up control module 10, a pull-up module 20, a downstream module 30, a pull-down module 40, a pull-down module The maintenance module 50 and the offset recovery control module 60.
  • N be a positive integer, except for the first and last level GOA units, in the Nth level GOA unit,
  • the pull-up control module 10 is connected to the first clock signal CK and the stage transmission signal Cout(N-1) of the N-1th stage GOA unit and is electrically connected to the first node Q(N) for the first clock signal Under the control of the signal CK, the potential of the first node Q(N) is pulled up according to the level transmission signal Cout(N-1) of the N-1th level GOA unit.
  • the pull-up module 20 is connected to the second clock signal XCK and electrically connected to the first node Q(N) for outputting the scan signal G() according to the second clock signal XCK under the control of the potential of the first node Q(N) N).
  • the download module 30 is connected to the second clock signal XCK and electrically connected to the first node Q(N) for outputting the stage transmission signal Cout according to the second clock signal XCK under the control of the potential of the first node Q(N) (N).
  • the pull-down module 40 is connected to the stage transmission signal Cout(N+1), the first potential signal VGL1, the second potential signal VGL2, and the scanning signal G(N) of the N+1th stage GOA unit, and is electrically connected to the first
  • the node Q(N) is used to change the potential of the first node Q(N) to the potential of the first potential signal VGL1 under the control of the stage transfer signal Cout(N+1) of the N+1th GOA unit
  • the potential of the scan signal G(N) changes to the potential of the second potential signal VGL2.
  • the pull-down maintenance module 50 includes an inverter 51 and a sub pull-down maintenance module 52.
  • the input terminal of the inverter 51 is electrically connected to the first node Q(N), and the output terminal is electrically connected to the second node QB(N).
  • the sub pull-down maintaining module 52 is connected to the first potential signal VGL1, the second potential signal VGL2, the scanning signal G(N), and the level transmission signal Cout(N), and is electrically connected to the first node Q(N) and the second node QB(N) is used to maintain the potential of the first node Q(N) and the level transfer signal Cout(N) at the potential of the first potential signal VGL1 and scan the signal under the control of the potential of the second node QB(N) The potential of G(N) is maintained at the potential of the second potential signal VGL2.
  • the offset recovery control module 60 is connected to the first potential signal VGL1 and the constant voltage low potential VGL3 and is electrically connected to the second node QB(N), for controlling the second node QB(N) under the control of the first potential signal VGL1
  • the potential of N) is pulled down to the constant voltage low potential VGL3.
  • the working process of the GOA circuit includes a programming phase 1 and a blanking phase 2 alternately in sequence.
  • the programming phase 1 the first clock signal CK and the second clock signal XCK are both pulse signals, and the first potential signal VGL1 and the second potential signal VGL2 are both low.
  • the blanking phase 2 the first clock signal CK and the second clock signal XCK are both low, and the first potential signal VGL1 and the second potential signal VGL2 are both high.
  • the waveforms of the first clock signal CK and the second clock signal XCK are opposite, and the duty cycle is both 0.5.
  • N be a positive integer. Except for the first and last level GOA units, in the Nth level GOA unit,
  • the pull-up control module 10 includes an eleventh thin film transistor T11, a twelfth thin film transistor T12, and a sixth thin film transistor T6.
  • the gate of the eleventh thin film transistor T11 is connected to the first clock signal CK
  • the source is connected to the stage transmission signal Cout(N-1) of the N-1 level GOA unit
  • the drain is electrically connected to the twelfth film Source of transistor T12.
  • the gate of the twelfth thin film transistor T12 is connected to the first clock signal CK, and the drain is electrically connected to the first node Q(N).
  • the gate of the sixth thin film transistor T6 is connected to the stage transmission signal Cout(N), the source is electrically connected to the drain of the eleventh thin film transistor T11, and the drain is electrically connected to the pull-up module 20.
  • the pull-up module 20 includes a twenty-first thin film transistor T21, a twenty-third thin film transistor T23, and a bootstrap capacitor Cbt.
  • the gate of the twenty-first thin film transistor T21 is electrically connected to the first node Q(N), the source is connected to the second clock signal XCK, and the drain outputs the scan signal G(N).
  • the gate of the twenty-third thin film transistor T23 is electrically connected to the first node Q(N), the source is connected to the second clock signal XCK, and the drain is electrically connected to the drain of the sixth thin film transistor T6.
  • One end of the bootstrap capacitor Cbt is electrically connected to the first node Q(N), and the other end is connected to the scanning signal G(N).
  • the download module 30 includes a twenty-second thin film transistor T22.
  • the gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q(N), the source is connected to the second clock signal XCK, and the drain outputs the stage signal Cout(N).
  • the pull-down module 40 includes a thirty-first thin film transistor T31, a thirty-second thin film transistor T32, and a thirty-third thin film transistor T33.
  • the gate of the thirty-first thin film transistor T31 is connected to the level transmission signal Cout(N+1) of the N+1th GOA unit, the source is connected to the scanning signal G(N), and the drain is connected to the second potential Signal VGL2.
  • the gate of the thirty-second thin film transistor T32 is connected to the level transmission signal Cout(N+1) of the N+1 level GOA unit, the source is electrically connected to the first node Q(N), and the drain is electrically connected
  • the gate of the thirty-third thin film transistor T33 is connected to the level transmission signal Cout(N+1) of the N+1th level GOA unit, and the drain is connected to the first potential signal VGL1.
  • the inverter 51 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, and a fifty-fourth thin film transistor T54.
  • the gate and source of the fifty-first thin film transistor T51 are both connected to the constant voltage high potential VGH, and the drain is electrically connected to the source of the fifty-second thin film transistor T52.
  • the gate of the fifty-second thin film transistor T52 is electrically connected to the first node Q(N), and the drain is connected to the first potential signal VGL1.
  • the gate of the fifty-third thin film transistor T53 is electrically connected to the drain of the fifty-first thin film transistor T51, the source is connected to the constant voltage high potential VGH, and the drain is electrically connected to the second node QB(N).
  • the gate of the fifty-fourth thin film transistor T54 is electrically connected to the first node Q(N), the source is electrically connected to the second node QB(N), and the drain is connected to the first potential signal VGL1.
  • the sub pull-down maintenance module 52 includes a forty-first thin film transistor T41, a forty-second thin film transistor T42, a forty-third thin film transistor T43, a forty-fourth thin film transistor T44, and a forty-fifth thin film transistor T45.
  • the gate of the forty-first thin film transistor T41 is electrically connected to the second node QB(N), the source is connected to the scan signal G(N), and the drain is connected to the second potential signal VGL2.
  • the gate of the forty-second thin film transistor T42 is electrically connected to the second node QB(N), the source is connected to the level transmission signal Cout(N-1), and the drain is connected to the first potential signal VGL1.
  • the gate of the forty-third thin film transistor T43 is electrically connected to the second node QB(N), the source is electrically connected to the drain of the sixth thin film transistor T6, and the drain is connected to the second potential signal VGL2.
  • the gate of the forty-fourth thin film transistor T44 is electrically connected to the second node QB(N), the source is electrically connected to the first node Q(N), and the drain is electrically connected to the source of the forty-fifth thin film transistor T45 And the source of the sixth thin film transistor T6.
  • the gate of the forty-fifth thin film transistor T45 is electrically connected to the second node QB(N), and the drain is connected to the first potential signal VGL1.
  • the offset recovery control module 60 includes an eighth thin film transistor T8.
  • the gate of the eighth thin film transistor T8 is connected to the first potential signal VGL1, the source is electrically connected to the second node QB(N), and the drain is connected to the constant voltage low potential VGL3.
  • the structure difference between the first-stage GOA unit and the Nth-stage GOA unit other than the first-stage GOA unit is that, in the first-stage GOA unit, the source of the eleventh thin film transistor T11 is connected Enter the start signal STV.
  • the structure difference between the last-stage GOA unit and the Nth-stage GOA unit except the last-stage is that in the last-stage GOA unit, the thirty-first thin film transistor T31 and the thirty-second thin film
  • the gates of the transistor T32 and the 33rd thin film transistor T33 are both connected to the start signal STV.
  • each level of GOA unit further includes a scan signal control module 70, which is connected to a first clock signal CK, a second clock signal XCK, a constant voltage low potential VGL3 and a scan signal G(N) is used to maintain the scan signal G(N) at the constant voltage low potential VGL3 when the first clock signal CK and the second clock signal XCK are both low.
  • a scan signal control module 70 which is connected to a first clock signal CK, a second clock signal XCK, a constant voltage low potential VGL3 and a scan signal G(N) is used to maintain the scan signal G(N) at the constant voltage low potential VGL3 when the first clock signal CK and the second clock signal XCK are both low.
  • the scan signal control module 70 includes a seventy-first thin film transistor T71, a seventy-second thin film transistor T72, a seventy-third thin film transistor T73, and a seventy-fourth thin film transistor T74.
  • the gate of the seventy-first thin film transistor T71 is connected to the second clock signal XCK
  • the source is electrically connected to the drain of the seventy-third thin film transistor T73
  • the drain is connected to the second potential signal VGL2.
  • the gate of the seventy-second thin film transistor T72 is connected to the first clock signal CK
  • the source is electrically connected to the drain of the seventy-third thin film transistor T73
  • the drain is connected to the second potential signal VGL2.
  • the gate and source of the seventy-third thin film transistor T73 are both connected to the constant voltage high potential VGH, and the drain is electrically connected to the gate of the seventy-fourth thin film transistor T74.
  • the source of the seventy-fourth thin film transistor T74 is connected to the scan signal G(N), and the drain is connected to the constant voltage low potential VGL3.
  • the potential of the first potential signal VGL1 is less than the potential of the second potential signal VGL2.
  • the potential of the first potential signal VGL1 is equal to the potential of the second potential signal VGL2.
  • the high potential of the start signal is 20V, and the low potential is -10V.
  • the high potential of the first clock signal CK and the second clock signal XCK is 20V, and the low potential is -10V.
  • the periods of the first clock signal CK and the second clock signal XCK are 30 ⁇ s.
  • the constant voltage high potential VGH is 20V, and the constant voltage low potential VGL3 is -6V.
  • the high potential of the first potential signal VGL1 is 20V, and the low potential is -10V.
  • the high potential of the second potential signal VGL2 is 20V, and the low potential is -6V.
  • the stage transmission signal Cout (N-1) of the N-1th GOA unit and the first clock signal CK are high, the second clock signal XCK is low, the eleventh thin film transistor T11 and the tenth
  • the second thin film transistor T12 is turned on, the first node Q(N) rises to a high potential, the twenty-first thin film transistor T21, the twenty-second thin film transistor T22, the twenty-third thin film transistor T23, and the fifty-second thin film transistor T52 ,
  • the fifty-fourth thin film transistor T54 is turned on, the second node QB(N) drops to a low potential, the forty-first thin film transistor T41, the 42nd thin film transistor T42, the forty-third thin film transistor T43, and the fortieth Four thin film transistor T44 level 45th thin film transistor T45 is turned off, 72nd thin film transistor T72 is turned on, 71st thin film transistor T71 is turned off, and the gate of the 74th thin film transistor T74 is pulled down to the second potential
  • the stage transfer signal Cout(N) and the scanning signal G(N) are at a low level. Then enter stage S2, the first clock signal CK becomes a low potential, the eleventh thin film transistor T11 and the twelfth thin film transistor T12 are turned off, and the second clock signal XCK becomes a high potential.
  • the first node Q( N) is coupled to a higher high potential, the twenty-first thin film transistor T21, the twenty-second thin film transistor T22, the twenty-third thin film transistor T23, the fifty-second thin film transistor T52, and the fifty-fourth thin film transistor T54 Turn on, the second node QB (N) maintains a low potential, the 41st thin film transistor T41, the 42nd thin film transistor T42, the 43rd thin film transistor T43, and the 44th thin film transistor T44.
  • the thin film transistor T45 is turned off, the seventy-first thin film transistor T71 is turned on, the seventy-second thin film transistor T72 is turned off, the gate of the seventy-fourth thin film transistor T74 maintains the low potential of the second potential signal VGL2, the seventy-fourth thin film transistor T74 is turned off. Because the second clock signal XCK is at a high level at this time, the stage transfer signal Cout(N) and the scanning signal G(N) are at a high level.
  • the first clock signal CK becomes high
  • the eleventh thin film transistor T11 and the twelfth thin film transistor T12 are turned on, and the stage transfer signal Cout(N+1) of the N+1 stage GOA unit becomes High potential
  • the thirty-first thin film transistor T31, the thirty-second thin film transistor T32, and the thirty-third thin film transistor T33 are turned on
  • the first node Q(N) and the scan signal G(N) become low potential
  • the second The eleventh thin film transistor T21, the twenty-second thin film transistor T22, the twenty-third thin film transistor T23, the fifty-second thin film transistor T52, and the fifty-fourth thin film transistor T54 are turned off, and the second node QB(N) becomes a high potential
  • the forty-first thin film transistor T41, the forty-second thin film transistor T42, the forty-third thin film transistor T43, the forty-fourth thin film transistor T44 and the forty-fifth thin film transistor T45 are turned on, and the first node Q(N )
  • the eighth thin film transistor T8 is always turned off, while the forty-first thin film transistor T41 and the forty-second thin film transistor T42, the forty-third thin film transistor T43, and the forty-fifth thin film transistor T45 are in a forward bias for a long time, and are subjected to a forward stress, and the threshold voltage will shift in a positive direction.
  • the threshold voltage will shift in a positive direction.
  • the eighth thin film transistor T8 is turned on to pull down the potential of the second node QB(N) and maintain it at the constant voltage low potential VGL3, that is
  • the gate potentials of the forty-first thin film transistor T41, the forty-second thin film transistor T42, the forty-third thin film transistor T43, and the forty-fifth thin film transistor T45 are negative, and the drain of the forty-first thin film transistor T41
  • the drain of the forty-third thin film transistor T43 is connected to the high potential of the second potential signal VGL2
  • the drain of the forty-second thin film transistor T42 and the 45th thin film transistor T45 is connected to the high of the first potential signal VGL1.
  • the forty-first thin film transistor T41, the forty-second thin film transistor T42, the forty-third thin film transistor T43, and the forty-fifth thin film transistor T45 are all in a reverse bias state and subjected to reverse stress, which can Effectively restore the forward shift of the threshold voltage of the 41st thin film transistor T41, the 42nd thin film transistor T42, the 43rd thin film transistor T43, and the 45th thin film transistor T45 in the programming phase 1, So as to effectively ensure the stability of the GOA circuit.
  • the seventy-first thin film transistor T71 and the seventy-second thin film transistor T72 are both turned off, so that the constant voltage low potential VGH Writing into the gate of the seventy-fourth thin-film transistor T74 through the seventy-third thin-film transistor T73 makes the seventy-fourth thin-film transistor T74 turn on to maintain the potential of the scanning signal G(N) at the constant voltage low potential VGL3, thereby In the blanking phase 2, the scanning signal G(N) is always at a low level, which improves the reliability of the GOA circuit.
  • each level of GOA unit of the GOA circuit of the present invention includes a pull-up control module, a pull-up module, a download module, a pull-down module, a pull-down maintenance module, and an offset recovery control module.
  • the drain of the thin film transistor whose gate is electrically connected to the second node is connected to the first potential signal or the second potential signal
  • the offset recovery control module is connected to the first potential signal and the constant voltage low potential and is electrically connected to the second node
  • the offset recovery control module pulls down the potential of the second node to a constant voltage low potential, so that the pull-down maintains the electrical connection of the gate in the module
  • the reverse bias of the thin film transistor of the second node recovers the threshold voltage shift generated in the programming stage, and improves the stability of the GOA circuit.

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Abstract

一种GOA电路，GOA电路的每一级GOA单元均包括上拉控制模块（10）、上拉模块（20）、下传模块（30）、下拉模块（40）、下拉维持模块（50）及偏移恢复控制模块（60），下拉维持模块（50）中的多个栅极电性连接第二节点（QB（N））的薄膜晶体管的漏极接入第一电位信号（VGL1）或第二电位信号（VGL2），偏移恢复控制模块（60）接入第一电位信号（VGL1）及恒压低电位（VGL3）并电性连接第二节点（QB（N）），当处于消隐阶段（2）时，第一电位信号（VGL1）及第二电位信号（VGL2）为高电位，此时偏移恢复控制模块（60）将第二节点（QB（N））的电位下拉至恒压低电位（VGL3），使得下拉维持模块（50）中栅极电性连接第二节点（QB（N））的薄膜晶体管反向偏置对编程阶段（1）产生的阈值电压偏移进行恢复，提升GOA电路的稳定性。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
 背景技术
液晶显示器（Liquid Crystal Display，LCD）及有机发光二极管显示装置（Organic Light Emitting Display，OLED）等平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理（PDA）、数字相机、计算机屏幕或笔记本电脑屏幕等。
GOA（Gate Driver on Array）技术即阵列基板行驱动技术，是利用薄膜晶体管（Thin Film Transistor，TFT）阵列制程将栅极扫描驱动电路制作在LCD及OLED显示装置的TFT阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点。GOA电路具有两项基本功能：第一是输出栅极扫描驱动信号，驱动面板内的栅极线，打开显示区内的TFT，以对像素进行充电；第二是移位寄存功能，当一个栅极扫描驱动信号输出完成后，通过时钟控制进行下一个栅极扫描驱动信号的输出，并依次传递下去。GOA技术能减少外接集成电路（IC）的焊接（bonding）工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框的显示产品。
现有的GOA电路包括多级GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块、下拉模块及下拉维持模块，其中，上拉控制模块用于上拉第一节点的电位，上拉模块用于在第一节点的电位控制下输出扫描信号，下传模块用于在第一节点的电位控制下输出级传信号，下拉模块用于对第一节点及扫描信号的电位进行下拉，而下拉维持模块用于受第一节点的电位控制将第一节点及扫描信号的电位维持在低电位，下拉维持模块中设置有用于维持第一节点及扫描信号为低电位的多个薄膜晶体管，该多个薄膜晶体管的栅极与一反相器的输出端电性连接，反相器的输入端电性连接第一节点，在第一节点为高电位时反相器输出低电位控制该多个薄膜晶体管截止，在第一节点为低电位时反相器输出高电位控制该多个薄膜晶体管导通从而将第一节点及扫描信号的电位维持为低电位。在GOA电路工作时，每一级GOA单元中第一节点为高电位的时长较短，长时间处于低电位时刻，这导致用于维持第一节点及扫描信号为低电位的多个薄膜晶体管在长时间内处于正向偏置，受到正向的应力，其阈值电压会逐渐发生正偏，导致GOA电路的稳定性下降。
 技术问题
本发明的目的在于提供一种GOA电路，能够对下拉维持模块中薄膜晶体管的阈值电压偏移进行恢复，GOA电路的稳定性较高。
 技术解决方案
为实现上述目的，本发明首先提供一种 GOA电路，包括多级GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块及偏移恢复控制模块；
设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
所述上拉控制模块接入第一时钟信号及第N-1级GOA单元的级传信号并电性连接第一节点，用于在第一时钟信号的控制下依据第N-1级GOA单元的级传信号上拉第一节点的电位；
所述上拉模块接入第二时钟信号并电性连接第一节点，用于在第一节点的电位控制下依据第二时钟信号输出扫描信号；
所述下传模块接入第二时钟信号并电性连接第一节点，用于在第一节点的电位控制下依据第二时钟信号输出级传信号；
所述下拉模块接入第N+1级GOA单元的级传信号、第一电位信号、第二电位信号及扫描信号，并电性连接第一节点，用于在第N+1级GOA单元的级传信号的控制下将第一节点的电位变化至第一电位信号的电位并将扫描信号的电位变化至第二电位信号的电位；
所述下拉维持模块包括反相器及子下拉维持模块；所述反相器的输入端电性连接第一节点，输出端电性连接第二节点；所述子下拉维持模块接入第一电位信号、第二电位信号、扫描信号、级传信号并电性连接第一节点及第二节点，用于在第二节点的电位控制下将第一节点、级传信号的电位维持在第一电位信号的电位并将扫描信号的电位维持在第二电位信号的电位；
所述偏移恢复控制模块接入第一电位信号及恒压低电位并电性连接第二节点，用于在第一电位信号的控制下将第二节点的电位下拉至恒压低电位。
所述GOA电路的工作过程包括依次交替的编程阶段及消隐阶段；在编程阶段中，所述第一时钟信号及第二时钟信号均为脉冲信号，所述第一电位信号及第二电位信号均为低电位；在消隐阶段中，所述第一时钟信号及第二时钟信号均为低电位，所述第一电位信号及第二电位信号均为高电位。
在编程阶段，所述第一时钟信号与第二时钟信号的波形相反，且占空比均为0.5。
每一级GOA单元还包括扫描信号控制模块，所述扫描信号控制模块接入第一时钟信号、第二时钟信号、恒压低电位及扫描信号，用于在第一时钟信号及第二时钟信号均为低电位时将扫描信号维持在恒压低电位。
所述扫描信号控制模块包括第七十一薄膜晶体管、第七十二薄膜晶体管、第七十三薄膜晶体管、第七十四薄膜晶体管；所述第七十一薄膜晶体管的栅极接入第二时钟信号，源极电性连接第七十三薄膜晶体管的漏极，漏极接入第二电位信号；所述第七十二薄膜晶体管的栅极接入第一时钟信号，源极电性连接第七十三薄膜晶体管的漏极，漏极接入第二电位信号；所述第七十三薄膜晶体管的栅极及源极均接入恒压高电位，漏极电性连接第七十四薄膜晶体管的栅极；所述第七十四薄膜晶体管的源极接入扫描信号，漏极接入恒压低电位。
在编程阶段，所述第一电位信号的电位小于第二电位信号的电位；在消隐阶段，所述第一电位信号的电位等于第二电位信号的电位。
所述偏移恢复控制模块包括第八薄膜晶体管；所述第八薄膜晶体管的栅极接入第一电位信号，源极电性连接第二节点，漏极接入恒压低电位。
设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
所述上拉控制模块包括第十一薄膜晶体管、第十二薄膜晶体管及第六薄膜晶体管；所述第十一薄膜晶体管的栅极接入第一时钟信号，源极接入第N-1级GOA单元的级传信号，漏极电性连接第十二薄膜晶体管的源极；所述第十二薄膜晶体管的栅极接入第一时钟信号，漏极电性连接第一节点；所述第六薄膜晶体管的栅极接入级传信号，源极电性连接第十一薄膜晶体管的漏极，漏极电性连接上拉模块；
所述上拉模块包括第二十一薄膜晶体管、第二十三薄膜晶体管及自举电容；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入第二时钟信号，漏极输出扫描信号；所述第二十三薄膜晶体管的栅极电性连接第一节点，源极接入第二时钟信号，漏极电性连接第六薄膜晶体管的漏极；所述自举电容的一端电性连接第一节点，另一端接入扫描信号；
所述下传模块包括第二十二薄膜晶体管；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入第二时钟信号，漏极输出级传信号；
所述下拉模块包括第三十一薄膜晶体管、第三十二薄膜晶体管及第三十三薄膜晶体管；所述第三十一薄膜晶体管的栅极接入第N+1级GOA单元的级传信号，源极接入扫描信号，漏极接入第二电位信号；所述第三十二薄膜晶体管的栅极接入第N+1级GOA单元的级传信号，源极电性连接第一节点，漏极电性连接第三十三薄膜晶体管的源极及第六薄膜晶体管的源极；所述第三十三薄膜晶体管的栅极接入第N+1级GOA单元的级传信号，漏极接入第一电位信号；
所述反相器包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管及第五十四薄膜晶体管；所述第五十一薄膜晶体管的栅极及源极均接入恒压高电位，漏极电性连接第五十二薄膜晶体管的源极；所述第五十二薄膜晶体管的栅极电性连接第一节点，漏极接入第一电位信号；所述第五十三薄膜晶体管的栅极电性连接第五十一薄膜晶体管的漏极，源极接入恒压高电位，漏极电性连接第二节点；所述第五十四薄膜晶体管的栅极电性连接第一节点，源极电性连接第二节点，漏极接入第一电位信号；
所述子下拉维持模块包括第四十一薄膜晶体管、第四十二薄膜晶体管、第四十三薄膜晶体管、第四十四薄膜晶体管、第四十五薄膜晶体管；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入扫描信号，漏极接入第二电位信号；所述第四十二薄膜晶体管的栅极电性连接第二节点，源极接入级传信号，漏极接入第一电位信号；所述第四十三薄膜晶体管的栅极电性连接第二节点，源极电性连接第六薄膜晶体管的漏极，漏极接入第二电位信号；所述第四十四薄膜晶体管的栅极电性连接第二节点，源极电性连接第一节点，漏极电性连接第四十五薄膜晶体管的源极及第六薄膜晶体管的源极；所述第四十五薄膜晶体管的栅极电性连接第二节点，漏极接入第一电位信号。
在第一级GOA单元中，所述第十一薄膜晶体管的源极接入起始信号。
在最后一级GOA单元中，所述第三十一薄膜晶体管、第三十二薄膜晶体管及第三十三薄膜晶体管的栅极均接入起始信号。
 有益效果
本发明的有益效果：本发明的GOA电路的每一级GOA单元均包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块及偏移恢复控制模块，下拉维持模块中的多个栅极电性连接第二节点的薄膜晶体管的漏极接入第一电位信号或第二电位信号，偏移恢复控制模块接入第一电位信号及恒压低电位并电性连接第二节点，当处于消隐阶段时，第一电位信号及第二电位信号为高电位，此时偏移恢复控制模块将第二节点的电位下拉至恒压低电位，使得下拉维持模块中栅极电性连接第二节点的薄膜晶体管反向偏置对编程阶段产生的阈值电压偏移进行恢复，提升GOA电路的稳定性。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的GOA电路的电路图；
图2为本发明的GOA电路的第一级GOA单元的电路图；
图3为本发明的GOA电路的最后一级GOA单元的电路图；
图4为本发明的GOA电路的信号时序图；
图5为本发明的GOA电路在编程阶段中第N级GOA单元的时序图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1至图5，本发明提供一种GOA电路，包括多级GOA单元，每一级GOA单元均包括上拉控制模块10、上拉模块20、下传模块30、下拉模块40、下拉维持模块50及偏移恢复控制模块60。
设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
所述上拉控制模块10接入第一时钟信号CK及第N-1级GOA单元的级传信号Cout(N-1)并电性连接第一节点Q(N)，用于在第一时钟信号CK的控制下依据第N-1级GOA单元的级传信号Cout(N-1)上拉第一节点Q(N)的电位。
所述上拉模块20接入第二时钟信号XCK并电性连接第一节点Q(N)，用于在第一节点Q(N)的电位控制下依据第二时钟信号XCK输出扫描信号G(N)。
所述下传模块30接入第二时钟信号XCK并电性连接第一节点Q(N)，用于在第一节点Q(N)的电位控制下依据第二时钟信号XCK输出级传信号Cout(N)。
所述下拉模块40接入第N+1级GOA单元的级传信号Cout(N+1)、第一电位信号VGL1、第二电位信号VGL2及扫描信号G(N)，并电性连接第一节点Q(N)，用于在第N+1级GOA单元的级传信号Cout(N+1)的控制下将第一节点Q(N)的电位变化至第一电位信号VGL1的电位并将扫描信号G(N)的电位变化至第二电位信号VGL2的电位。
所述下拉维持模块50包括反相器51及子下拉维持模块52。所述反相器51的输入端电性连接第一节点Q(N)，输出端电性连接第二节点QB(N)。所述子下拉维持模块52接入第一电位信号VGL1、第二电位信号VGL2、扫描信号G(N)、级传信号Cout(N)并电性连接第一节点Q(N)及第二节点QB(N)，用于在第二节点QB(N)的电位控制下将第一节点Q(N)、级传信号Cout(N)的电位维持在第一电位信号VGL1的电位并将扫描信号G(N)的电位维持在第二电位信号VGL2的电位。
所述偏移恢复控制模块60接入第一电位信号VGL1及恒压低电位VGL3并电性连接第二节点QB(N)，用于在第一电位信号VGL1的控制下将第二节点QB(N)的电位下拉至恒压低电位VGL3。
具体地，请参阅图4，所述GOA电路的工作过程包括依次交替的编程阶段1及消隐阶段2。在编程阶段1中，所述第一时钟信号CK及第二时钟信号XCK均为脉冲信号，所述第一电位信号VGL1及第二电位信号VGL2均为低电位。在消隐阶段2中，所述第一时钟信号CK及第二时钟信号XCK均为低电位，所述第一电位信号VGL1及第二电位信号VGL2均为高电位。
进一步地，请参阅图4，在编程阶段1，所述第一时钟信号CK与第二时钟信号XCK的波形相反，且占空比均为0.5。
具体地，请参阅图1，设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
所述上拉控制模块10包括第十一薄膜晶体管T11、第十二薄膜晶体管T12及第六薄膜晶体管T6。所述第十一薄膜晶体管T11的栅极接入第一时钟信号CK，源极接入第N-1级GOA单元的级传信号Cout(N-1)，漏极电性连接第十二薄膜晶体管T12的源极。所述第十二薄膜晶体管T12的栅极接入第一时钟信号CK，漏极电性连接第一节点Q(N)。所述第六薄膜晶体管T6的栅极接入级传信号Cout(N)，源极电性连接第十一薄膜晶体管T11的漏极，漏极电性连接上拉模块20。
所述上拉模块20包括第二十一薄膜晶体管T21、第二十三薄膜晶体管T23及自举电容Cbt。所述第二十一薄膜晶体管T21的栅极电性连接第一节点Q(N)，源极接入第二时钟信号XCK，漏极输出扫描信号G(N)。所述第二十三薄膜晶体管T23的栅极电性连接第一节点Q(N)，源极接入第二时钟信号XCK，漏极电性连接第六薄膜晶体管T6的漏极。所述自举电容Cbt的一端电性连接第一节点Q(N)，另一端接入扫描信号G(N)。
所述下传模块30包括第二十二薄膜晶体管T22。所述第二十二薄膜晶体管T22的栅极电性连接第一节点Q(N)，源极接入第二时钟信号XCK，漏极输出级传信号Cout(N)。
所述下拉模块40包括第三十一薄膜晶体管T31、第三十二薄膜晶体管T32及第三十三薄膜晶体管T33。所述第三十一薄膜晶体管T31的栅极接入第N+1级GOA单元的级传信号Cout(N+1)，源极接入扫描信号G(N)，漏极接入第二电位信号VGL2。所述第三十二薄膜晶体管T32的栅极接入第N+1级GOA单元的级传信号Cout(N+1)，源极电性连接第一节点Q(N)，漏极电性连接第三十三薄膜晶体管T33的源极及第六薄膜晶体管T6的源极。所述第三十三薄膜晶体管T33的栅极接入第N+1级GOA单元的级传信号Cout(N+1)，漏极接入第一电位信号VGL1。
所述反相器51包括第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53及第五十四薄膜晶体管T54。所述第五十一薄膜晶体管T51的栅极及源极均接入恒压高电位VGH，漏极电性连接第五十二薄膜晶体管T52的源极。所述第五十二薄膜晶体管T52的栅极电性连接第一节点Q(N)，漏极接入第一电位信号VGL1。所述第五十三薄膜晶体管T53的栅极电性连接第五十一薄膜晶体管T51的漏极，源极接入恒压高电位VGH，漏极电性连接第二节点QB(N)。所述第五十四薄膜晶体管T54的栅极电性连接第一节点Q(N)，源极电性连接第二节点QB(N)，漏极接入第一电位信号VGL1。
所述子下拉维持模块52包括第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、第四十四薄膜晶体管T44、第四十五薄膜晶体管T45。所述第四十一薄膜晶体管T41的栅极电性连接第二节点QB(N)，源极接入扫描信号G(N)，漏极接入第二电位信号VGL2。所述第四十二薄膜晶体管T42的栅极电性连接第二节点QB(N)，源极接入级传信号Cout(N-1)，漏极接入第一电位信号VGL1。所述第四十三薄膜晶体管T43的栅极电性连接第二节点QB(N)，源极电性连接第六薄膜晶体管T6的漏极，漏极接入第二电位信号VGL2。所述第四十四薄膜晶体管T44的栅极电性连接第二节点QB(N)，源极电性连接第一节点Q(N)，漏极电性连接第四十五薄膜晶体管T45的源极及第六薄膜晶体管T6的源极。所述第四十五薄膜晶体管T45的栅极电性连接第二节点QB(N)，漏极接入第一电位信号VGL1。
所述偏移恢复控制模块60包括第八薄膜晶体管T8。所述第八薄膜晶体管T8的栅极接入第一电位信号VGL1，源极电性连接第二节点QB(N)，漏极接入恒压低电位VGL3。
进一步地，请参阅图2，第一级GOA单元与除了第一级以外的第N级GOA单元的结构区别在于，在第一级GOA单元中，所述第十一薄膜晶体管T11的源极接入起始信号STV。请参阅图3，最后一级GOA单元与除了最后一级以外的第N级GOA单元的结构区别在于，在最后一级GOA单元中，所述第三十一薄膜晶体管T31、第三十二薄膜晶体管T32及第三十三薄膜晶体管T33的栅极均接入起始信号STV。
具体地，请参阅图1，每一级GOA单元还包括扫描信号控制模块70，所述扫描信号控制模块70接入第一时钟信号CK、第二时钟信号XCK、恒压低电位VGL3及扫描信号G(N)，用于在第一时钟信号CK及第二时钟信号XCK均为低电位时将扫描信号G(N)维持在恒压低电位VGL3。
进一步地，请参阅图1，所述扫描信号控制模块70包括第七十一薄膜晶体管T71、第七十二薄膜晶体管T72、第七十三薄膜晶体管T73、第七十四薄膜晶体管T74。所述第七十一薄膜晶体管T71的栅极接入第二时钟信号XCK，源极电性连接第七十三薄膜晶体管T73的漏极，漏极接入第二电位信号VGL2。所述第七十二薄膜晶体管T72的栅极接入第一时钟信号CK，源极电性连接第七十三薄膜晶体管T73的漏极，漏极接入第二电位信号VGL2。所述第七十三薄膜晶体管T73的栅极及源极均接入恒压高电位VGH，漏极电性连接第七十四薄膜晶体管T74的栅极。所述第七十四薄膜晶体管T74的源极接入扫描信号G(N)，漏极接入恒压低电位VGL3。
具体地，在编程阶段1，所述第一电位信号VGL1的电位小于第二电位信号VGL2的电位。在消隐阶段2，所述第一电位信号VGL1的电位等于第二电位信号VGL2的电位。
优选地，所述起始信号的高电位为20V，低电位为-10V。所述第一时钟信号CK及第二时钟信号XCK的高电位为20V，低电位为-10V，第一时钟信号CK及第二时钟信号XCK的周期为30μs。所述恒压高电位VGH为20V，所述恒压低电位VGL3为-6V。所述第一电位信号VGL1的高电位为20V，低电位为-10V。所述第二电位信号VGL2的高电位为20V，低电位为-6V。
以图1所示的实施例为例并结合图5，本发明的GOA电路的第N级GOA单元在编程阶段1内的工作过程如下：
首先进入阶段S1，第N-1级GOA单元的级传信号Cout(N-1)及第一时钟信号CK为高电位，第二时钟信号XCK为低电位，第十一薄膜晶体管T11及第十二薄膜晶体管T12导通，第一节点Q(N)上升为高电位，第二十一薄膜晶体管T21、第二十二薄膜晶体管T22、第二十三薄膜晶体管T23、第五十二薄膜晶体管T52、第五十四薄膜晶体管T54导通，第二节点QB(N)降为低电位，第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、第四十四薄膜晶体管T44级第四十五薄膜晶体管T45截止，第七十二薄膜晶体管T72导通，第七十一薄膜晶体管T71截止，第七十四薄膜晶体管T74的栅极被拉低至第二电位信号VGL2的低电位，第七十四薄膜晶体管T74截止，由于此时第二时钟信号XCK为低电位，级传信号Cout(N)与扫描信号G(N)为低电位。随后进入阶段S2，第一时钟信号CK变为低电位，第十一薄膜晶体管T11及第十二薄膜晶体管T12截止，第二时钟信号XCK变为高电位，利用存储电容Cbt，第一节点Q(N)被耦合至更高的高电位，第二十一薄膜晶体管T21、第二十二薄膜晶体管T22、第二十三薄膜晶体管T23、第五十二薄膜晶体管T52、第五十四薄膜晶体管T54导通，第二节点QB(N)维持低电位，第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、第四十四薄膜晶体管T44级第四十五薄膜晶体管T45截止，第七十一薄膜晶体管T71导通，第七十二薄膜晶体管T72截止，第七十四薄膜晶体管T74的栅极保持第二电位信号VGL2的低电位，第七十四薄膜晶体管T74截止，由于此时第二时钟信号XCK为高电位，级传信号Cout(N)与扫描信号G(N)为高电位。而后进入阶段S3，第一时钟信号CK变为高电位，第十一薄膜晶体管T11及第十二薄膜晶体管T12导通，第N+1级GOA单元的级传信号Cout(N+1)变为高电位，第三十一薄膜晶体管T31、第三十二薄膜晶体管T32及第三十三薄膜晶体管T33导通，第一节点Q(N)及扫描信号G(N)变为低电位，第二十一薄膜晶体管T21、第二十二薄膜晶体管T22、第二十三薄膜晶体管T23、第五十二薄膜晶体管T52、第五十四薄膜晶体管T54关闭，第二节点QB(N)变为高电位，第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、第四十四薄膜晶体管T44级第四十五薄膜晶体管T45导通，将第一节点Q(N)、扫描信号G(N)及级传信号Cout(N)维持为低电位，第七十二薄膜晶体管T72导通，第七十一薄膜晶体管T71截止，第七十四薄膜晶体管T74的栅极保持第二电位信号VGL2的低电位，第七十四薄膜晶体管T74截止。
需要说明的是，本发明的GOA电路在编程阶段1中，由于第一电位信号VGL1始终为低电位，第八薄膜晶体管T8始终截止，而第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、及第四十五薄膜晶体管T45长时间处于正向偏置，受到正向应力，阈值电压会发生正向偏移。而本发明中，在编程阶段1结束后，进入消隐阶段2，在消隐阶段2内，第一电位信号VGL1及第二电位信号VGL2由低电位变为高电位，且第一时钟信号CK及第二时钟信号XCK均为低电位，使得在消隐阶段2中，第八薄膜晶体管T8导通，将第二节点QB(N)的电位下拉并维持在恒压低电位VGL3上，也即第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、及第四十五薄膜晶体管T45的栅极电位为负电位，而第四十一薄膜晶体管T41的漏极、第四十三薄膜晶体管T43的漏极接入第二电位信号VGL2的高电位，第四十二薄膜晶体管T42级第四十五薄膜晶体管T45的漏极接入第一电位信号VGL1的高电位，使得第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、及第四十五薄膜晶体管T45均处于反向偏置状态，受到反向的应力，能够有效地对在编程阶段1中第四十一薄膜晶体管T41、第四十二薄膜晶体管T42、第四十三薄膜晶体管T43、及第四十五薄膜晶体管T45的阈值电压正向偏移得到恢复，从而有效地保证了GOA电路的稳定性。另外，在消隐阶段2内，由于第一时钟信号CK及第二时钟信号XCK均为低电位，第七十一薄膜晶体管T71及第七十二薄膜晶体管T72均截止，使得恒压低电位VGH经过第七十三薄膜晶体管T73写入第七十四薄膜晶体管T74的栅极使得第七十四薄膜晶体管T74导通，以将扫描信号G(N)的电位保持为恒压低电位VGL3，从而使得在消隐阶段2内扫描信号G(N)始终为低电位，提升GOA电路的可靠性。
综上所述，本发明的GOA电路的每一级GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块及偏移恢复控制模块，下拉维持模块中的多个栅极电性连接第二节点的薄膜晶体管的漏极接入第一电位信号或第二电位信号，偏移恢复控制模块接入第一电位信号及恒压低电位并电性连接第二节点，当处于消隐阶段时，第一电位信号及第二电位信号为高电位，此时偏移恢复控制模块将第二节点的电位下拉至恒压低电位，使得下拉维持模块中栅极电性连接第二节点的薄膜晶体管反向偏置对编程阶段产生的阈值电压偏移进行恢复，提升GOA电路的稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种GOA电路，包括多级GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块及偏移恢复控制模块；
    设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
    所述上拉控制模块接入第一时钟信号及第N-1级GOA单元的级传信号并电性连接第一节点，用于在第一时钟信号的控制下依据第N-1级GOA单元的级传信号上拉第一节点的电位；
    所述上拉模块接入第二时钟信号并电性连接第一节点，用于在第一节点的电位控制下依据第二时钟信号输出扫描信号；
    所述下传模块接入第二时钟信号并电性连接第一节点，用于在第一节点的电位控制下依据第二时钟信号输出级传信号；
    所述下拉模块接入第N+1级GOA单元的级传信号、第一电位信号、第二电位信号及扫描信号，并电性连接第一节点，用于在第N+1级GOA单元的级传信号的控制下将第一节点的电位变化至第一电位信号的电位并将扫描信号的电位变化至第二电位信号的电位；
    所述下拉维持模块包括反相器及子下拉维持模块；所述反相器的输入端电性连接第一节点，输出端电性连接第二节点；所述子下拉维持模块接入第一电位信号、第二电位信号、扫描信号、级传信号并电性连接第一节点及第二节点，用于在第二节点的电位控制下将第一节点、级传信号的电位维持在第一电位信号的电位并将扫描信号的电位维持在第二电位信号的电位；
    所述偏移恢复控制模块接入第一电位信号及恒压低电位并电性连接第二节点，用于在第一电位信号的控制下将第二节点的电位下拉至恒压低电位。
  2. 如权利要求1所述的GOA电路，其中，所述GOA电路的工作过程包括依次交替的编程阶段及消隐阶段；在编程阶段中，所述第一时钟信号及第二时钟信号均为脉冲信号，所述第一电位信号及第二电位信号均为低电位；在消隐阶段中，所述第一时钟信号及第二时钟信号均为低电位，所述第一电位信号及第二电位信号均为高电位。
  3. 如权利要求2所述的GOA电路，其中，在编程阶段，所述第一时钟信号与第二时钟信号的波形相反，且占空比均为0.5。
  4. 如权利要求3所述的GOA电路，其中，每一级GOA单元还包括扫描信号控制模块，所述扫描信号控制模块接入第一时钟信号、第二时钟信号、恒压低电位及扫描信号，用于在第一时钟信号及第二时钟信号均为低电位时将扫描信号维持在恒压低电位。
  5. 如权利要求4所述的GOA电路，其中，所述扫描信号控制模块包括第七十一薄膜晶体管、第七十二薄膜晶体管、第七十三薄膜晶体管、第七十四薄膜晶体管；所述第七十一薄膜晶体管的栅极接入第二时钟信号，源极电性连接第七十三薄膜晶体管的漏极，漏极接入第二电位信号；所述第七十二薄膜晶体管的栅极接入第一时钟信号，源极电性连接第七十三薄膜晶体管的漏极，漏极接入第二电位信号；所述第七十三薄膜晶体管的栅极及源极均接入恒压高电位，漏极电性连接第七十四薄膜晶体管的栅极；所述第七十四薄膜晶体管的源极接入扫描信号，漏极接入恒压低电位。
  6. 如权利要求2所述的GOA电路，其中，在编程阶段，所述第一电位信号的电位小于第二电位信号的电位；在消隐阶段，所述第一电位信号的电位等于第二电位信号的电位。
  7. 如权利要求1所述的GOA电路，其中，所述偏移恢复控制模块包括第八薄膜晶体管；所述第八薄膜晶体管的栅极接入第一电位信号，源极电性连接第二节点，漏极接入恒压低电位。
  8. 如权利要求1所述的GOA电路，其中，设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
    所述上拉控制模块包括第十一薄膜晶体管、第十二薄膜晶体管及第六薄膜晶体管；所述第十一薄膜晶体管的栅极接入第一时钟信号，源极接入第N-1级GOA单元的级传信号，漏极电性连接第十二薄膜晶体管的源极；所述第十二薄膜晶体管的栅极接入第一时钟信号，漏极电性连接第一节点；所述第六薄膜晶体管的栅极接入级传信号，源极电性连接第十一薄膜晶体管的漏极，漏极电性连接上拉模块；
    所述上拉模块包括第二十一薄膜晶体管、第二十三薄膜晶体管及自举电容；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入第二时钟信号，漏极输出扫描信号；所述第二十三薄膜晶体管的栅极电性连接第一节点，源极接入第二时钟信号，漏极电性连接第六薄膜晶体管的漏极；所述自举电容的一端电性连接第一节点，另一端接入扫描信号；
    所述下传模块包括第二十二薄膜晶体管；所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入第二时钟信号，漏极输出级传信号；
    所述下拉模块包括第三十一薄膜晶体管、第三十二薄膜晶体管及第三十三薄膜晶体管；所述第三十一薄膜晶体管的栅极接入第N+1级GOA单元的级传信号，源极接入扫描信号，漏极接入第二电位信号；所述第三十二薄膜晶体管的栅极接入第N+1级GOA单元的级传信号，源极电性连接第一节点，漏极电性连接第三十三薄膜晶体管的源极及第六薄膜晶体管的源极；所述第三十三薄膜晶体管的栅极接入第N+1级GOA单元的级传信号，漏极接入第一电位信号；
    所述反相器包括第五十一薄膜晶体管、第五十二薄膜晶体管、第五十三薄膜晶体管及第五十四薄膜晶体管；所述第五十一薄膜晶体管的栅极及源极均接入恒压高电位，漏极电性连接第五十二薄膜晶体管的源极；所述第五十二薄膜晶体管的栅极电性连接第一节点，漏极接入第一电位信号；所述第五十三薄膜晶体管的栅极电性连接第五十一薄膜晶体管的漏极，源极接入恒压高电位，漏极电性连接第二节点；所述第五十四薄膜晶体管的栅极电性连接第一节点，源极电性连接第二节点，漏极接入第一电位信号；
    所述子下拉维持模块包括第四十一薄膜晶体管、第四十二薄膜晶体管、第四十三薄膜晶体管、第四十四薄膜晶体管、第四十五薄膜晶体管；所述第四十一薄膜晶体管的栅极电性连接第二节点，源极接入扫描信号，漏极接入第二电位信号；所述第四十二薄膜晶体管的栅极电性连接第二节点，源极接入级传信号，漏极接入第一电位信号；所述第四十三薄膜晶体管的栅极电性连接第二节点，源极电性连接第六薄膜晶体管的漏极，漏极接入第二电位信号；所述第四十四薄膜晶体管的栅极电性连接第二节点，源极电性连接第一节点，漏极电性连接第四十五薄膜晶体管的源极及第六薄膜晶体管的源极；所述第四十五薄膜晶体管的栅极电性连接第二节点，漏极接入第一电位信号。
  9. 如权利要求8所述的GOA电路，其中，在第一级GOA单元中，所述第十一薄膜晶体管的源极接入起始信号。
  10. 如权利要求8所述的GOA电路，其中，在最后一级GOA单元中，所述第三十一薄膜晶体管、第三十二薄膜晶体管及第三十三薄膜晶体管的栅极均接入起始信号。
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