WO2021168965A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2021168965A1
WO2021168965A1 PCT/CN2020/081564 CN2020081564W WO2021168965A1 WO 2021168965 A1 WO2021168965 A1 WO 2021168965A1 CN 2020081564 W CN2020081564 W CN 2020081564W WO 2021168965 A1 WO2021168965 A1 WO 2021168965A1
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WIPO (PCT)
Prior art keywords
transistor
node
electrically connected
signal
drain
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Application number
PCT/CN2020/081564
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English (en)
French (fr)
Inventor
薛炎
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/755,583 priority Critical patent/US10950155B1/en
Publication of WO2021168965A1 publication Critical patent/WO2021168965A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA Gate Driveron Array
  • the existing GOA circuit is complicated, its allowable threshold deviation range is small, and its stability is poor.
  • the GOA circuit and the display panel provided by the embodiments of the present application reduce the number of transistors electrically connected to the first node in the GOA circuit, thereby reducing the leakage path of the first node.
  • the GOA circuit can perform the operation on the pixel circuit during the blank time. Real-time compensation further improves the stability of the GOA circuit.
  • the embodiments of the present application provide a GOA circuit and a display panel to solve the technical problem of poor stability of the GOA circuit in the prior art.
  • This application provides a GOA circuit, including:
  • each level of GOA unit includes: pull-up control module, pull-up module, first pull-down module, second pull-down module, first pull-down maintenance module, second pull-down maintenance module, logic Addressing module and inverter module;
  • the pull-up control module is connected to the upper-level transmission signal, and is electrically connected to the first node and the fourth node, and is used for under the control of the upper-level transmission signal and the potential of the fourth node Outputting the upper-level transmission signal to the first node;
  • the pull-up module is connected to a first clock signal, a second clock signal, and a third clock signal, and is electrically connected to the first node, the fifth node, the sixth node, and the seventh node for Under the control of the potential of the first node, output the transmission signal of the current level, the first scan signal of the current level, and the second scan signal of the current level;
  • the first pull-down module accesses the next-level transmission signal and the first reference low-level signal, and is electrically connected to the first node and the fourth node, and is used for scanning according to the next-level Signal, the first reference low level signal, and the potential of the fourth node pull down the potential of the first node;
  • the second pull-down module is connected to the upper-level transmission signal, the reset signal, and the second reference low-level signal, and is electrically connected to the second node and the third node, and is configured to perform according to the upper-level The level transmission signal, the reset signal, the second reference low level signal, and the potential of the third node pull down the potential of the second node;
  • the first pull-down maintaining module accesses the first reference low level signal, and is electrically connected to the first node, the second node, and the fourth node, and is used to connect to the first node, the second node, and the fourth node. After the pull-down module pulls down the potential of the first node, maintain the low potential of the first node according to the first reference low level signal, the potential of the second node, and the potential of the fourth node;
  • the second pull-down maintaining module accesses the first reference low level signal and the third reference low level signal, and is electrically connected to the second node, the fifth node, the sixth node, and the seventh node, It is used to maintain the level transmission signal of the current level, the first scan signal of the current level, and the potential of the second node according to the first reference low level signal, the third reference low level signal, and the potential of the second node.
  • the logical addressing module accesses the upper-level transmission signal, the reference high-level signal, the first reference low-level signal, the reset signal, the first control signal, and the second control signal, and It is electrically connected to the first node and the second node. Used for controlling the first node according to the upper level transmission signal, the reference high level signal, the reset signal, the first control signal, and the potential of the second node during the blank time The potential.
  • the inverter module is connected to the second reference low-level signal and the reference high-level signal, and is electrically connected to the first node and the second node for connecting the second The potentials of the node and the first node are kept in reverse phase.
  • the pull-up control module includes: an eleventh transistor and a twelfth transistor;
  • the gate of the eleventh transistor, the source of the eleventh transistor, and the gate of the twelfth transistor are all connected to the upper-level transmission signal, and the drain of the eleventh transistor
  • the source of the twelfth transistor is electrically connected to the fourth node, and the drain of the twelfth transistor is electrically connected to the first node.
  • the pull-up module includes: a sixth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a first capacitor, and a second capacitor;
  • the gate of the sixth transistor, the gate of the twenty-first transistor, the gate of the twenty-second transistor, the gate of the twenty-third transistor, the first capacitor of the first capacitor The first terminal of the second capacitor and the first terminal are both electrically connected to the first node, the drain of the sixth transistor is electrically connected to the fourth node, and the source of the sixth transistor is electrically connected to the fourth node.
  • the second terminal of the first capacitor and the drain of the twenty-second transistor are electrically connected to the sixth node, and the source of the twenty-first transistor is connected to the third clock signal, so The drain of the twenty-first transistor and the second terminal of the second capacitor are electrically connected to the seventh node, and the source of the twenty-second transistor is connected to the second clock signal, so The source of the twenty-third transistor is connected to the first clock signal, and the drain of the twenty-third transistor is electrically connected to the fifth node.
  • the first pull-down unit includes a thirty-first transistor and a thirty-second transistor;
  • the gates of the thirty-first transistor and the thirty-second transistor are both connected to the next-level transmission signal, and the drain of the thirty-first transistor is electrically connected to the first node,
  • the source of the thirty-first transistor and the drain of the thirty-second transistor are both electrically connected to the fourth node, and the source of the thirty-second transistor is electrically connected to the first Reference low-level signal.
  • the second pull-down unit includes a fifty-fifth transistor, a one-hundred-one transistor, and a one-hundred-two transistor;
  • the gate of the fifty-fifth transistor is connected to the upper-level transmission signal, the source of the fifty-fifth transistor and the source of the one-hundred second transistor are both connected to the second With reference to a low-level signal, the drain of the fifty-fifth transistor and the drain of the one-hundred-one transistor are both electrically connected to the second node, and the gate of the one-hundred-two transistor Is electrically connected to the third node, the drain of the one-hundred second transistor is electrically connected to the source of the one-hundred one transistor, and the gate of the one-hundred first transistor is connected to The reset signal.
  • the first pull-down sustain unit includes a forty-fourth transistor and a forty-fifth transistor;
  • the gates of the forty-fourth transistor and the forty-fifth transistor are electrically connected to the second node, and the drain of the forty-fourth transistor is electrically connected to the first node, so The source of the forty-fourth transistor and the drain of the forty-fifth transistor are electrically connected to the fourth node, and the source of the forty-fifth transistor is connected to the first reference low voltage Flat signal.
  • the second pull-down sustain unit includes a forty-first transistor, a forty-second transistor, and a forty-third transistor;
  • the gate of the forty-first transistor, the gate of the forty-second transistor, and the gate of the forty-third transistor are all electrically connected to the second node, and the forty-first transistor
  • the source of the forty-second transistor and the source of the forty-second transistor are both connected to the third reference low-level signal
  • the drain of the forty-first transistor is electrically connected to the seventh node
  • the The drain of the forty-two transistor is electrically connected to the sixth node
  • the source of the forty-third transistor is electrically connected to the first reference low level signal
  • the drain of the forty-third transistor is electrically connected to the sixth node.
  • the pole is electrically connected to the fifth node.
  • the logical addressing module includes the thirty-third transistor, the thirty-fourth transistor, the seventy-first transistor, the seventy-second transistor, the seventy-third transistor, and the eighty-first transistor.
  • the gate of the thirty-third transistor is electrically connected to the second node, the source of the thirty-third transistor is connected to the first reference low-level signal, and the The drain is electrically connected to the source of the thirty-fourth transistor, the gate of the thirty-fourth transistor is connected to the first control signal, the drain of the thirty-fourth transistor, the first control signal.
  • the drain of the eighty-one transistor and the source of the eighty-second transistor are electrically connected, the gate of the eighty-first transistor, the gate of the seventy-third transistor, and the seventy-two transistor
  • the drain of the third capacitor and the second end of the third capacitor are electrically connected to the third node, the source of the eighty-first transistor is electrically connected to the drain of the seventy-third transistor, so
  • the gate of the 82nd transistor is connected to the reset signal, the drain of the 82nd transistor is electrically connected to the first node, and the first end of the third capacitor is connected to the With reference to the high-level signal, the gate of
  • the inverter module includes a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, and a fifty-fourth transistor;
  • the gate of the fifty-first transistor, the source of the fifty-first transistor, and the source of the fifty-third transistor are all connected to the reference high-level signal, and the fifty-first transistor
  • the drain of the fifty-third transistor, the gate of the fifty-third transistor, and the drain of the fifty-second transistor are electrically connected, and the drain of the fifty-third transistor is connected to the source of the fifty-fourth transistor Both are electrically connected to the second node, the drain of the fifty-fourth transistor and the source of the fifty-second transistor are both connected to the second reference low level signal, and the fifty-fourth transistor
  • the gates of the four transistors and the gates of the fifty-second transistor are both electrically connected to the first node.
  • the present application also provides a display panel, which includes a GOA circuit
  • the GOA circuit includes: a multi-level transmission of GOA units, each level of GOA unit includes: a pull-up control module, a pull-up module, and a first pull-down module , The second pull-down module, the first pull-down maintenance module, the second pull-down maintenance module, the logic addressing module, and the inverter module;
  • the pull-up control module is connected to the upper-level transmission signal, and is electrically connected to the first node and the fourth node, and is used for under the control of the upper-level transmission signal and the potential of the fourth node Outputting the upper-level transmission signal to the first node;
  • the pull-up module is connected to a first clock signal, a second clock signal, and a third clock signal, and is electrically connected to the first node, the fifth node, the sixth node, and the seventh node for Under the control of the potential of the first node, output the transmission signal of the current level, the first scan signal of the current level, and the second scan signal of the current level;
  • the first pull-down module accesses the next-level transmission signal and the first reference low-level signal, and is electrically connected to the first node and the fourth node, and is used for scanning according to the next-level Signal, the first reference low level signal, and the potential of the fourth node pull down the potential of the first node;
  • the second pull-down module is connected to the upper-level transmission signal, the reset signal, and the second reference low-level signal, and is electrically connected to the second node and the third node, and is configured to perform according to the upper-level The level transmission signal, the reset signal, the second reference low level signal, and the potential of the third node pull down the potential of the second node;
  • the first pull-down maintaining module accesses the first reference low level signal, and is electrically connected to the first node, the second node, and the fourth node, and is used to connect to the first node, the second node, and the fourth node. After the pull-down module pulls down the potential of the first node, maintain the low potential of the first node according to the first reference low level signal, the potential of the second node, and the potential of the fourth node;
  • the second pull-down maintaining module accesses the first reference low level signal and the third reference low level signal, and is electrically connected to the second node, the fifth node, the sixth node, and
  • the seventh node is configured to maintain the current-level transmission signal and the current-level first-level transmission signal according to the first reference low-level signal, the third reference low-level signal, and the potential of the second node A scan signal and the low potential of the second scan signal of the current level;
  • the logical addressing module accesses the upper-level transmission signal, the reference high-level signal, the first reference low-level signal, the reset signal, the first control signal, and the second control signal, and It is electrically connected to the first node and the second node. Used for controlling the first node according to the upper level transmission signal, the reference high level signal, the reset signal, the first control signal, and the potential of the second node during the blank time The potential;
  • the inverter module is connected to the second reference low-level signal and the reference high-level signal, and is electrically connected to the first node and the second node for connecting the second The potentials of the node and the first node are kept in reverse phase.
  • the pull-up control module includes: an eleventh transistor and a twelfth transistor; the gate of the eleventh transistor, the source of the eleventh transistor, and the The gates of the twelve transistors are all connected to the upper-level transmission signal, the drain of the eleventh transistor and the source of the twelfth transistor are electrically connected to the fourth node, and the The drain of the twelfth transistor is electrically connected to the first node.
  • the pull-up module includes: a sixth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a first capacitor, and a second capacitor;
  • the gate of the transistor, the gate of the twenty-first transistor, the gate of the twenty-second transistor, the gate of the twenty-third transistor, the first end of the first capacitor, and the The first end of the second capacitor is electrically connected to the first node
  • the drain of the sixth transistor is electrically connected to the fourth node
  • the second terminal of the twenty-second transistor and the drain of the twenty-second transistor are electrically connected to the sixth node
  • the source of the twenty-first transistor is connected to the third clock signal
  • the drain of a transistor and the second end of the second capacitor are electrically connected to the seventh node, the source of the twenty-second transistor is connected to the second clock signal, and the twentieth The source of the three transistor is connected to the first clock signal, and the drain of the twenty-third
  • the first pull-down unit includes a thirty-first transistor and a thirty-second transistor;
  • the gates of the thirty-first transistor and the thirty-second transistor are both connected to the next-level transmission signal, and the drain of the thirty-first transistor is electrically connected to the first node,
  • the source of the thirty-first transistor and the drain of the thirty-second transistor are both electrically connected to the fourth node, and the source of the thirty-second transistor is electrically connected to the first Reference low-level signal.
  • the second pull-down unit includes a fifty-fifth transistor, a one-hundred-one transistor, and a one-hundred-two transistor;
  • the gate of the fifty-fifth transistor is connected to the upper-level transmission signal, the source of the fifty-fifth transistor and the source of the one-hundred second transistor are both connected to the second With reference to a low-level signal, the drain of the fifty-fifth transistor and the drain of the one-hundred-one transistor are both electrically connected to the second node, and the gate of the one-hundred-two transistor Is electrically connected to the third node, the drain of the one-hundred second transistor is electrically connected to the source of the one-hundred one transistor, and the gate of the one-hundred first transistor is connected to The reset signal.
  • the first pull-down sustain unit includes a forty-fourth transistor and a forty-fifth transistor;
  • the gates of the forty-fourth transistor and the forty-fifth transistor are electrically connected to the second node, and the drain of the forty-fourth transistor is electrically connected to the first node, so The source of the forty-fourth transistor and the drain of the forty-fifth transistor are electrically connected to the fourth node, and the source of the forty-fifth transistor is connected to the first reference low voltage Flat signal.
  • the second pull-down sustain unit includes a forty-first transistor, a forty-second transistor, and a forty-third transistor;
  • the gate of the forty-first transistor, the gate of the forty-second transistor, and the gate of the forty-third transistor are all electrically connected to the second node, and the forty-first transistor
  • the source of the forty-second transistor and the source of the forty-second transistor are both connected to the third reference low-level signal
  • the drain of the forty-first transistor is electrically connected to the seventh node
  • the The drain of the forty-two transistor is electrically connected to the sixth node
  • the source of the forty-third transistor is electrically connected to the first reference low level signal
  • the drain of the forty-third transistor is electrically connected to the sixth node.
  • the pole is electrically connected to the fifth node.
  • the logical addressing module includes the thirty-third transistor, the thirty-fourth transistor, the seventy-first transistor, the seventy-second transistor, the seventy-third transistor, and the eighty-first transistor.
  • the gate of the thirty-third transistor is electrically connected to the second node, the source of the thirty-third transistor is connected to the first reference low-level signal, and the The drain is electrically connected to the source of the thirty-fourth transistor, the gate of the thirty-fourth transistor is connected to the first control signal, the drain of the thirty-fourth transistor, the first control signal.
  • the drain of the eighty-one transistor and the source of the eighty-second transistor are electrically connected, the gate of the eighty-first transistor, the gate of the seventy-third transistor, and the seventy-two transistor
  • the drain of the third capacitor and the second end of the third capacitor are electrically connected to the third node, the source of the eighty-first transistor is electrically connected to the drain of the seventy-third transistor, so
  • the gate of the 82nd transistor is connected to the reset signal, the drain of the 82nd transistor is electrically connected to the first node, and the first end of the third capacitor is connected to the With reference to the high-level signal, the gate of
  • the inverter module includes a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, and a fifty-fourth transistor;
  • the gate of the fifty-first transistor, the source of the fifty-first transistor, and the source of the fifty-third transistor are all connected to the reference high-level signal, and the fifty-first transistor
  • the drain of the fifty-third transistor, the gate of the fifty-third transistor, and the drain of the fifty-second transistor are electrically connected, and the drain of the fifty-third transistor is connected to the source of the fifty-fourth transistor Both are electrically connected to the second node, the drain of the fifty-fourth transistor and the source of the fifty-second transistor are both connected to the second reference low level signal, and the fifty-fourth transistor
  • the gates of the four transistors and the gates of the fifty-second transistor are both electrically connected to the first node.
  • the GOA circuit and the display panel provided by the embodiments of the present application reduce the number of transistors electrically connected to the first node in the GOA circuit, thereby reducing the leakage path of the first node.
  • the GOA circuit can perform the operation on the pixel circuit during the blank time. Real-time compensation further improves the stability of the GOA circuit.
  • FIG. 1 is a schematic diagram of the structure of a GOA circuit provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a GOA unit in the GOA circuit provided by an embodiment of the application;
  • FIG. 3 is a schematic circuit diagram of a GOA unit in the GOA circuit provided by an embodiment of the application;
  • FIG. 5 is a first signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of this application;
  • FIG. 6 is a second signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of a pixel circuit provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other pole is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the drain, and the output end is the source.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • the GOA circuit provided by the embodiment of the present application includes a multi-stage transmission GOA unit.
  • Figure 1 takes the n-2th level GOA unit, the nth level GOA unit and the n+2 level GOA unit of the level transmission as examples.
  • the scan signal output by the n-th GOA unit is at a high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel, and perform data signals on the pixel electrode in each pixel.
  • the nth level transmission signal is used to control the work of the n+2 level GOA unit; when the n+2 level GOA unit is working, the scan signal output by the n+2 level GOA unit is high, and the nth level The scanning signal output by the GOA unit is low.
  • FIG. 2 is a schematic structural diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the GOA unit includes: a pull-up control module 101, a pull-up module 102, a first pull-down module 103, a second pull-down module 104, a first pull-down maintenance module 105, a second pull-down maintenance module 106, Logic addressing module 107 and inverter module 108.
  • the pull-up control module 101 is connected to the upper level transmission signal count(n-2), and is electrically connected to the first node Q and the fourth node N, for transmitting the signal count(n- Under the control of 2), the upper level transmission signal count(n-2) is output to the first node Q.
  • the pull-up module 102 accesses the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3, and is electrically connected to the first node Q, the fifth node A, the sixth node B, and the seventh node C , Which is used to output the transfer signal count(n) of the current stage and the first scan signal WR( n) and the second scan signal RD(n) of this stage.
  • the first pull-down module 103 is connected to the next level transmission signal count(n+2) and the first reference low level signal VGL1, and is electrically connected to the first node Q and the fourth node N for The next level scan signal count(n+2), the first reference low level signal VGL1 and the potential of the fourth node N pull down the potential of the first node Q.
  • the second pull-down module 104 is connected to the upper level transmission signal count(n-2), the reset signal Reset, and the second reference low level signal VGL2, and is electrically connected to the second node QB and the third node M , Used to pull down the potential of the second node QB according to the upper level transfer signal count(n-2), the reset signal Reset, the second reference low level signal VGL2, and the potential of the third node M.
  • the first pull-down maintaining module 105 accesses the first reference low level signal VGL1, and is electrically connected to the first node Q, the second node QB, and the fourth node N, and is used to pull down the first pull-down module 103 After the potential of the first node Q, the low potential of the first node Q is maintained according to the first reference low level signal VGL1, the potential of the second node QB, and the potential of the fourth node N.
  • the second pull-down maintaining module 106 accesses the first reference low level signal VGL1 and the third reference low level signal VGL3, and is electrically connected to the second node QB, the fifth node A, the sixth node B, and the seventh node QB.
  • Node C is used to maintain the level transfer signal count(n) of the current level and the first scan signal WR(n ) And the low potential of the second scan signal RD(n) of this stage.
  • the logical addressing module 107 is connected to the upper level transmission signal count(n-2), the reference high level signal VGH, the first reference low level signal VGL1, the reset signal Reset, the first control signal LSP, and the first control signal LSP.
  • the second control signal VST is electrically connected to the first node Q and the second node QB. Used in the blank time according to the upper level transmission signal count(n-2), the reference high level signal VGH, the first reference low level signal VGL1, the reset signal Reset, the first control signal LSP, and the second control The signal VST and the potential of the second node QB control the potential of the first node Q.
  • the inverter module 108 is connected to the second reference low level signal VGL2 and the reference high level signal VGH, and is electrically connected to the first node Q and the second node QB for connecting the second node QB and the first node QB.
  • the potential of the node Q remains inverted.
  • the GOA circuit provided by the embodiments of the present application reduces the number of transistors electrically connected between the source and drain and the first node, thereby reducing the leakage path of the first node Q and improving the stability of the GOA circuit.
  • FIG. 3 is a schematic circuit diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the pull-up control module 101 includes an eleventh transistor T11 and a twelfth transistor T12.
  • the gate of the eleventh transistor T11, the source of the eleventh transistor T11, and the gate of the twelfth transistor T12 are all connected to the upper-level transmission signal Cout(n-2).
  • the drain of the eleventh transistor T11 and the source of the twelfth transistor T12 are both electrically connected to the fourth node N.
  • the drain of the twelfth transistor T12 is electrically connected to the first node Q.
  • the pull-up module 102 includes a sixth transistor T6, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a first capacitor C1, and a second capacitor C2.
  • the drain of the sixth transistor T6 is electrically connected to the fourth node N.
  • the source of the sixth transistor T6, the second terminal of the first capacitor C1, and the drain of the twenty-second transistor T22 are all electrically connected to the sixth node B.
  • the source of the twenty-first transistor T21 is connected to the third clock signal CK3.
  • the drain of the twenty-first transistor T21 and the second terminal of the second capacitor C2 are both electrically connected to the seventh node C.
  • the source of the twenty-second transistor T22 is connected to the second clock signal CK2.
  • the source of the twenty-third transistor T23 is connected to the first clock signal CK1.
  • the drain of the twenty-third transistor T23 is electrically connected to the fifth node B.
  • the first pull-down unit 103 includes a thirty-first transistor T31 and a thirty-second transistor T32.
  • the gates of the thirty-first transistor T31 and the thirty-second transistor T32 are both connected to the next-stage transmission signal Cout(n-2).
  • the drain of the thirty-first transistor T31 is electrically connected to the first node Q.
  • the source of the thirty-first transistor T31 and the drain of the thirty-second transistor T32 are both electrically connected to the fourth node N.
  • the source of the thirty-second transistor T32 is electrically connected to the first reference low level signal VGL1.
  • the second pull-down unit 104 includes a fifty-fifth transistor T55, a one-hundred-one transistor T101, and a one-hundred-two transistor T102.
  • the gate of the fifty-fifth transistor T55 is connected to the upper-level transmission signal Cout(n-2).
  • the source of the fifty-fifth transistor T55 and the source of the one-hundred-two transistor T102 are both connected to the second reference low level signal VGL2.
  • the drain of the fifty-fifth transistor T55 and the drain of the one-hundred-one transistor T101 are both electrically connected to the second node QB.
  • the gate of the one hundred and second transistor T102 is electrically connected to the third node M.
  • the drain of the one-hundred and second transistor T102 is electrically connected to the source of the one-hundred-first transistor T101.
  • the gate of the one hundred and one transistor T101 is connected to the reset signal Reset.
  • the first pull-down sustain unit 105 includes a forty-fourth transistor T44 and a forty-fifth transistor T45.
  • the gates of the forty-fourth transistor T44 and the forty-fifth transistor T45 are electrically connected to the second node QB.
  • the drain of the forty-fourth transistor T44 is electrically connected to the first node Q.
  • the source of the forty-fourth transistor T44 and the drain of the forty-fifth transistor T45 are electrically connected to the fourth node N.
  • the source of the forty-fifth transistor T45 is connected to the first reference low level signal VGL1.
  • the second pull-down sustain unit 106 includes a forty-first transistor T41, a forty-second transistor T42, and a forty-third transistor T43.
  • the gate of the forty-first transistor T41, the gate of the forty-second transistor T42, and the gate of the forty-third transistor T43 are all electrically connected to the second node QB.
  • the source of the forty-first transistor T41 and the source of the forty-second transistor T42 are both connected to the third reference low level signal VGL3.
  • the drain of the forty-first transistor T41 is electrically connected to the seventh node C.
  • the drain of the forty-second transistor T42 is electrically connected to the sixth node B.
  • the source of the forty-third transistor T43 is electrically connected to the first reference low level signal VGL1.
  • the drain of the forty-third transistor T43 is electrically connected to the fifth node A.
  • the logical addressing module 107 includes the thirty-third transistor T33, the thirty-fourth transistor T34, the seventy-first transistor T71, the seventy-second transistor T72, the seventy-third transistor T73, the eighty-first transistor T81, and the eighty-first transistor T81. Twelve transistors T82 and a third capacitor C3.
  • the source of the thirty-third transistor T33 is connected to the first reference low level signal VGL1.
  • the drain of the thirty-third transistor T33 is electrically connected to the source of the thirty-fourth transistor T34.
  • the gate of the thirty-fourth transistor T34 is connected to the first control signal LSP.
  • the drain of the thirty-fourth transistor T34, the drain of the eighty-first transistor T81, and the source of the eighty-second transistor T82 are electrically connected.
  • the gate of the eighty-first transistor T81, the gate of the seventy-third transistor T73, the drain of the seventy-second transistor T72, and the second terminal of the third capacitor C1 are all electrically connected to the third node M.
  • the source of the eighty-first transistor T81 is electrically connected to the drain T73 of the seventy-third transistor.
  • the gate of the eighty-second transistor T82 is connected to the reset signal Reset.
  • the drain of the eighty-second transistor T82 is electrically connected to the first node Q.
  • the first terminal of the third capacitor C3 is connected to the reference high-level signal VGH, and the gate of the seventy-first transistor T71 and the gate of the seventy-second transistor T72 are both connected to the second control signal VST.
  • the source of the seventy-first transistor T71 is connected to the upper-level transmission signal Cout(n-2).
  • the drain of the seventy-first transistor T71, the source of the seventy-second transistor T72, and the source of the seventy-third transistor T73 are electrically connected.
  • the inverter module 108 includes a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53, and a fifty-fourth transistor T54.
  • the gate of the fifty-first transistor T51, the source of the fifty-first transistor T51, and the source of the fifty-third transistor T53 are all connected to the reference high-level signal VGH.
  • the drain of the fifty-first transistor T51, the gate of the fifty-third transistor T53, and the drain of the fifty-second transistor T52 are electrically connected.
  • the drain of the fifty-third transistor T53 and the source of the fifty-fourth transistor T54 are electrically connected to the second node QB.
  • the drain of the fifty-fourth transistor T54 and the source of the fifty-second transistor T52 are both connected to the second reference low level signal VGL2.
  • the gate of the fifty-fourth transistor T54 and the gate of the fifty-second transistor T52 are both electrically connected to the first node Q.
  • the GOA circuit provided by the embodiment of the present application reduces the leakage path of the first node Q by reducing the number of transistors whose source and drain are electrically connected to the first node.
  • the GOA circuit by designing a depletion type circuit, for example, the drain of the eleventh transistor T11 and the source of the twelfth transistor T12 are electrically connected to the fourth node N and the thirty-first transistor T31.
  • the source and the drain of the thirty-second transistor T32 are electrically connected to the fourth node N, and the source of the forty-fourth transistor T44 and the drain of the forty-fifth transistor T45 are both electrically connected to the fourth node N
  • the fourth node N is also a high potential, so that the eleventh transistor T11, the twelfth transistor T12, the thirty-first transistor T31, the thirty-second transistor T32, and the fourth
  • the leakage of the fourteenth transistor T44 and the forty-fifth transistor T45 is reduced, which further reduces the leakage of the GOA circuit, and effectively improves the stability of the GOA circuit compared with the prior art.
  • FIG. 4 is the signal voltage value of a GOA unit in the GOA circuit provided by the embodiment of the present application
  • FIG. 5 is the first signal of a GOA unit in the GOA circuit provided by the embodiment of the present application. Timing diagram.
  • the upper-level transmission signal Cout(n-2) rises to a high potential
  • the eleventh transistor T11 and the twelfth transistor T12 are both turned on, and the potential of the first node Q is pulled to a high potential, making the fifth
  • the twelve transistor T52, the fifty-fourth transistor T54, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are all turned on. Since the inverter module 108 is connected between the first node Q and the second node QB, the potential of the first node Q and the potential of the second node QB are inverted, therefore, the second node QB is at a low potential, so that the forty-first node QB is at a low potential.
  • the transistor 41, the forty-second transistor 42, the forty-third transistor 43, the forty-fourth transistor 44, and the forty-fifth transistor T45 are all off.
  • the next level transmission signal Cout(n+2) is at a low level, so that both the thirty-first transistor T31 and the thirty-second transistor T32 are turned off.
  • the second control signal VST is at a low level, so that the thirty-third transistor T33 and the thirty-fourth transistor T34 are turned off.
  • the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are all low, then the current level transmits the signal Cout(n), the current level first scan signal WR(n), and the current level second scan signal RD(n) all output low potential.
  • the first control signal LSP rises to a high potential, so that the seventy-first transistor T71 and the seventy-second transistor T72 are turned on, and the third node M is raised to a high potential, so that the eighty-first transistor T81 is turned on.
  • the reset signal Reset is at a low level, so that the eighty-second transistor T82 is turned off.
  • the upper-level transmission signal Cout(n-2) rises to a high potential, so that the fifty-fifth transistor T55 is turned on. Since the open source of the fifty-fifth transistor T55 is connected to the second reference low-level signal, the fifty-fifth transistor T55 outputs a low-level signal, which further pulls the potential of the second node QB down to a low potential, so that the second Node QB's falling time (fall time) is better.
  • the first control signal LSP drops from a high level to a low level, so that the seventy-first transistor T71 and the seventy-second transistor T72 are both turned off, the third node M continues to maintain a high potential, and the first node Q The potential continues to be high.
  • the potential of the second node QB, the transmission signal Cout(n) of the current stage, the first scan signal WR(n) of the current stage, and the second scan signal RD(n) of the current stage continue to maintain a low potential.
  • the upper level Cout(n-2) changes from a high level to a low level, so that the eleventh transistor T11 and the twelfth transistor T12 are turned off.
  • the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 all change from a low level to a high level. Therefore, the current level transmission signal Cout(n), the current level first scan signal WR(n), and the current level The level of the second scan signal RD(n) is raised to a high level.
  • the first scan signal WR(n) of the current level and the second scan signal RD(n) of the current level cause the scan line corresponding to the GOA unit of the current level to be charged, and a row of pixels corresponding to the scan line of the current level is turned on. The pixels are lit.
  • the potential of the first node Q is coupled to a higher potential, ensuring that the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on , So as to ensure that the transmission signal Cout(n) of the current level, the first scan signal WR(n) of the current level, and the second scan signal RD(n) of the current level are all high-level signals.
  • the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 all change from high to low, so that the transmission signal Cout(n) of the current stage and the first scan signal WR(n) of the current stage ) And the second scan signal RD(n) of this stage are both pulled down to a low level.
  • FIG. 6 is a second signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the reset signal Reset rises to a high potential, so that the eighty-second transistor T82 is turned on, and the potential of the first node Q is pulled to a high potential, so that the fifty-second transistor T52, the fifty-fourth transistor T54, and the second The eleven transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are all turned on. Since the inverter module 108 is connected between the first node Q and the second node QB, the potential of the first node Q and the potential of the second node QB are inverted, therefore, the second node QB is at a low potential, so that the forty-first node QB is at a low potential.
  • the transistor 41, the forty-second transistor 42, the forty-third transistor 43, the forty-fourth transistor 44, and the forty-fifth transistor T45 are all off.
  • the next level transmission signal Cout(n+2) is at a low level, so that both the thirty-first transistor T31 and the thirty-second transistor T32 are turned off.
  • the second control signal VST is at a low level, so that the thirty-third transistor T33 and the thirty-fourth transistor T34 are turned off.
  • the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 are all low, then the current level transmits the signal Cout(n), the current level first scan signal WR(n), and the current level second scan signal RD(n) all output low potential.
  • the reset signal Reset changes from a high level to a low level, so that the eighty-second transistor T82 is turned off.
  • the first clock signal CK1 continues to maintain a low level, and the second clock signal CK2 and the third clock signal CK3 rise to a high level, so that the transmission signal Cout(n) of the current level maintains a low level, and the first scan signal WR(n ) And the second scan signal RD(n) of this stage output high potential.
  • the potential of the first node Q is coupled to a higher potential, ensuring that the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are turned on , So as to ensure that the transmission signal Cout(n) of the current level maintains a low level, and the first scan signal WR(n) of the current level and the second scan signal RD(n) of the current level are output as high level signals.
  • the second clock signal CK2 and the third clock signal CK3 drop to a low potential
  • the potential of the first node Q is coupled to the reference high-level signal VGH
  • the first scan signal WR(n) of this stage and the first scan signal of this stage
  • the second scan signal RD(n) is pulled down to a low level.
  • the second control signal VST and the reset signal Reset rise from low to high
  • the thirty-fourth transistor T34, the eighty-second transistor T82, and the one-hundred-one transistor T101 are turned on, and the third node M
  • the electric potential and the electric potential of the first node Q are both pulled to a low electric potential
  • the electric potential of the second node QB rises to a high electric potential.
  • the second scan signal RD(n) continues to maintain a low level.
  • the GOA circuit provided by the embodiment of the application can compensate the pixel circuit during the blank time.
  • the simulation result of the GOA circuit shows that when the threshold voltage of the GOA circuit is negatively biased by -6V, the output of the GOA circuit is still valid until the threshold of the GOA circuit When the voltage is negatively biased at -8V, the output of the GOA circuit fails.
  • the stability of the GOA circuit is effectively improved, thereby reducing the development difficulty of the TFT (Thin Film Transistor) process.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes a display area and a GOA circuit 200 integratedly arranged on the edge of the display area 100; wherein, the structure and principle of the GOA circuit 200 are similar to the above-mentioned GOA circuit, and will not be repeated here.

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Abstract

本申请实施例提供的GOA电路及显示面板，通过减少GOA电路中与第一节点电性连接的晶体管数量，从而减少第一节点的漏电路径，同时该GOA电路能够在空白时间内对像素电路进行实时补偿，进一步提高GOA电路的稳定性。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
阵列基板栅极驱动技术(Gate Driveron Array，简称GOA)，是将栅极驱动电路集成在显示面板的阵列基板上，以实现逐行扫描的驱动方式，从而可以省掉栅极驱动电路部分，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。然而，现有的GOA电路电路复杂，自身允许的阈值偏差范围范围较小，稳定性较差。
 技术问题
现有的GOA电路电路复杂，自身允许的阈值偏差范围范围较小，稳定性较差。本申请实施例提供的GOA电路及显示面板，通过减少GOA电路中与第一节点电性连接的晶体管数量，从而减少第一节点的漏电路径，同时该GOA电路能够在空白时间内对像素电路进行实时补偿，进一步提高GOA电路的稳定性。
 技术解决方案
本申请实施例提供一种GOA电路及显示面板，以解决现有技术中GOA电路稳定性差的技术问题。
本申请提供了一种GOA电路，包括：
多级级传的GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、第一下拉模块、第二下拉模块、第一下拉维持模块、第二下拉维持模块、逻辑寻址模块以及反相器模块；
所述上拉控制模块接入上一级级传信号，并电性连接于第一节点和第四节点，用于在所述上一级级传信号及所述第四节点的电位的控制下将所述上一级级传信号输出至所述第一节点；
所述上拉模块接入第一时钟信号、第二时钟信号和第三时钟信号，并电性连接于所述第一节点、第五节点、第六节点以及第七节点，用于在所述第一节点的电位控制下输出本级级传信号、本级第一扫描信号以及本级第二扫描信号；
所述第一下拉模块接入下一级级传信号和第一参考低电平信号，并电性连接于所述第一节点和所述第四节点，用于根据所述下一级扫描信号、所述第一参考低电平信号及所述第四节点的电位下拉所述第一节点的电位；
所述第二下拉模块接入所述上一级级传信号、重置信号以及第二参考低电平信号，并电性连接于第二节点以及第三节点，用于根据所述上一级级传信号、所述重置信号、所述第二参考低电平信号以及所述第三节点的电位下拉所述第二节点的电位；
所述第一下拉维持模块接入所述第一参考低电平信号，并电性连接于所述第一节点、所述第二节点及所述第四节点，用于在所述第一下拉模块下拉所述第一节点的电位后，根据所述第一参考低电平信号、所述第二节点的电位及所述第四节点的电位维持所述第一节点的低电位；
所述第二下拉维持模块接入所述第一参考低电平信号与第三参考低电平信号，并电性连接于所述第二节点、第五节点、第六节点以及第七节点，用于根据所述第一参考低电平信号、所述第三参考低电平信号以及所述第二节点的电位维持所述本级级传信号、所述本级第一扫描信号以及所述本级第二扫描信号的的低电位；
所述逻辑寻址模块接入所述上一级级传信号、参考高电平信号、所述第一参考低电平信号、所述重置信号、第一控制信号以及第二控制信号，并电性连接于所述第一节点和所述第二节点。用于在空白时间内根据所述上一级级传信号、所述参考高电平信号、所述重置信号、所述第一控制信号以及所述第二节点的电位控制所述第一节点的电位。
所述反相器模块接入所述第二参考低电平信号和所述参考高电平信号，并电性连接于所述第一节点及所述第二节点，用于将所述第二节点与所述第一节点的电位保持反相。
在本申请提供的GOA电路中，所述上拉控制模块包括：第十一晶体管和第十二晶体管；
所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的栅极均接入所述上一级级传信号，所述第十一晶体管的漏极与所述第十二晶体管的源极均电性连接于所述的第四节点，所述第十二晶体管的漏极电性连接于所述第一节点。
在本申请提供的GOA电路中，所述上拉模块包括：第六晶体管、第二十一晶体管、第二十二晶体管、第二十三晶体管、第一电容以及第二电容；
所述第六晶体管的栅极、所述第二十一晶体管的栅极、所述第二十二晶体管的栅极、所述第二十三晶体管的栅极、所述第一电容的第一端以及所述第二电容的第一端均电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第四节点，所述第六晶体管的源极、所述第一电容的第二端以及所述第二十二晶体管的漏极均电性连接于所述第六节点，所述第二十一晶体管的源极接入所述第三时钟信号，所述第二十一晶体管的漏极及所述第二电容的第二端均电性连接于所述第七节点，所述第二十二晶体管的源极接入所述第二时钟信号，所述第二十三晶体管的源极接入所述第一时钟信号，所述第二十三晶体管的漏极电性连接于所述第五节点。
在本申请提供的GOA电路中，所述第一下拉单元包括第三十一晶体管和第三十二晶体管；
所述第三十一晶体管和所述第三十二晶体管的栅极均接入所述下一级级传信号，所述第三十一晶体管的漏极电性连接于所述第一节点，所述第三十一晶体管的源极与所述第三十二晶体管的漏极均电性连接于所述第四节点，所述第三十二晶体管的源极电性连接于所述第一参考低电平信号。
在本申请提供的GOA电路中，所述第二下拉单元包括第五十五晶体管、第一百零一晶体管和第一百零二晶体管；
所述第五十五晶体管的栅极接入所述上一级级传信号，所述第五十五晶体管的源极与所述第一百零二晶体管的源极均接入所述第二参考低电平信号，所述第五十五晶体管的漏极和所述第一百零一晶体管的漏极均电性连接于所述第二节点，所述第一百零二晶体管的栅极电性连接于所述第三节点，所述第一百零二晶体管的漏极与所述第一百零一晶体管的源极电性连接，所述第一百零一晶体管的栅极接入所述重置信号。
在本申请提供的GOA电路中，所述第一下拉维持单元包括第四十四晶体管和第四十五晶体管；
所述第四十四晶体管和所述第四十五晶体管的栅极均电性连接于所述第二节点，所述第四十四晶体管的漏极电性连接于所述第一节点，所述第四十四晶体管的源极与所述第四十五晶体管的漏极均电性连接于所述第四节点，所述第四十五晶体管的源极接入所述第一参考低电平信号。
在本申请提供的GOA电路中，所述第二下拉维持单元包括第四十一晶体管、第四十二晶体管和第四十三晶体管；
所述第四十一晶体管的栅极、所述第四十二晶体管的栅极以及所述第四十三晶体管的栅极均电性连接于所述第二节点，所述第四十一晶体管的源极与所述第四十二晶体管的源极均接入所述第三参考低电平信号，所述第四十一晶体管的漏极电性连接于所述第七节点，所述第四十二晶体管的漏极电性连接于所述第六节点，所述第四十三晶体管的源极电性连接于所述第一参考低电平信号，所述第四十三晶体管的漏极电性连接于所述第五节点。
在本申请提供的GOA电路中，所述逻辑寻址模块包括第三十三晶体管、第三十四晶体管、第七十一晶体管、第七十二晶体管、第七十三晶体管、第八十一晶体管、第八十二晶体管以及第三电容；
所述第三十三晶体管的栅极电性连接于所述第二节点，所述第三十三晶体管的源极接入所述第一参考低电平信号，所述第三十三晶体管的漏极与所述第三十四晶体管的源极电性连接，所述第三十四晶体管的栅极接入所述第一控制信号，所述第三十四晶体管的漏极、所述第八十一晶体管的漏极以及所述第八十二晶体管的源极电性连接，所述第八十一晶体管的栅极、所述第七十三晶体管的栅极、所述七十二晶体管的漏极以及所述第三电容的第二端均电性连接于所述第三节点，所述第八十一晶体管的源极与所述第七十三晶体管的漏极电性连接，所述第八十二晶体管的栅极接入所述重置信号，所述第八十二晶体管的漏极电性连接于所述第一节点，所述第三电容的第一端接入所述参考高电平信号，所述第七十一晶体管的栅极和第七十二晶体管的栅极均接入所述第二控制信号，所述第七十一晶体管的源极接入所述上一级级传信号，所述第七十一晶体管的漏极、所述第七十二晶体管的源极以及所述第七十三晶体管的源极电性连接。
在本申请提供的GOA电路中，所述反相器模块包括第五十一晶体管、第五十二晶体管、第五十三晶体管以及第五十四晶体管；
所述第五十一晶体管的栅极、所述第五十一晶体管的源极以及所述第五十三晶体管的源极均接入所述参考高电平信号，所述第五十一晶体管的漏极、所述第五十三晶体管的栅极以及所述第五十二晶体管的漏极电性连接，所述第五十三晶体管的漏极与所述第五十四晶体管的源极均电性连接于所述第二节点，所述第五十四晶体管的漏极与所述第五十二晶体管的源极均接入所述第二参考低电平信号，所述第五十四晶体管的栅极与所述第五十二晶体管的栅极均电性连接于所述第一节点。
本申请还提供一种显示面板，其包括GOA电路，所述GOA电路包括：多级级传的GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、第一下拉模块、第二下拉模块、第一下拉维持模块、第二下拉维持模块、逻辑寻址模块以及反相器模块；
所述上拉控制模块接入上一级级传信号，并电性连接于第一节点和第四节点，用于在所述上一级级传信号及所述第四节点的电位的控制下将所述上一级级传信号输出至所述第一节点；
所述上拉模块接入第一时钟信号、第二时钟信号和第三时钟信号，并电性连接于所述第一节点、第五节点、第六节点以及第七节点，用于在所述第一节点的电位控制下输出本级级传信号、本级第一扫描信号以及本级第二扫描信号；
所述第一下拉模块接入下一级级传信号和第一参考低电平信号，并电性连接于所述第一节点和所述第四节点，用于根据所述下一级扫描信号、所述第一参考低电平信号及所述第四节点的电位下拉所述第一节点的电位；
所述第二下拉模块接入所述上一级级传信号、重置信号以及第二参考低电平信号，并电性连接于第二节点以及第三节点，用于根据所述上一级级传信号、所述重置信号、所述第二参考低电平信号以及所述第三节点的电位下拉所述第二节点的电位；
所述第一下拉维持模块接入所述第一参考低电平信号，并电性连接于所述第一节点、所述第二节点及所述第四节点，用于在所述第一下拉模块下拉所述第一节点的电位后，根据所述第一参考低电平信号、所述第二节点的电位及所述第四节点的电位维持所述第一节点的低电位；
所述第二下拉维持模块接入所述第一参考低电平信号与第三参考低电平信号，并电性连接于所述第二节点、所述第五节点、所述第六节点以及所述第七节点，用于根据所述第一参考低电平信号、所述第三参考低电平信号以及所述第二节点的电位维持所述本级级传信号、所述本级第一扫描信号以及所述本级第二扫描信号的的低电位；
所述逻辑寻址模块接入所述上一级级传信号、参考高电平信号、所述第一参考低电平信号、所述重置信号、第一控制信号以及第二控制信号，并电性连接于所述第一节点和所述第二节点。用于在空白时间内根据所述上一级级传信号、所述参考高电平信号、所述重置信号、所述第一控制信号以及所述第二节点的电位控制所述第一节点的电位；
所述反相器模块接入所述第二参考低电平信号和所述参考高电平信号，并电性连接于所述第一节点及所述第二节点，用于将所述第二节点与所述第一节点的电位保持反相。
在本申请提供的显示面板中，所述上拉控制模块包括：第十一晶体管和第十二晶体管；所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的栅极均接入所述上一级级传信号，所述第十一晶体管的漏极与所述第十二晶体管的源极均电性连接于所述第四节点，所述第十二晶体管的漏极电性连接于所述第一节点。
在本申请提供的显示面板中，所述上拉模块包括：第六晶体管、第二十一晶体管、第二十二晶体管、第二十三晶体管、第一电容以及第二电容；所述第六晶体管的栅极、所述第二十一晶体管的栅极、所述第二十二晶体管的栅极、所述第二十三晶体管的栅极、所述第一电容的第一端以及所述第二电容的第一端均电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第四节点，所述第六晶体管的源极、所述第一电容的第二端以及所述第二十二晶体管的漏极均电性连接于所述第六节点，所述第二十一晶体管的源极接入所述第三时钟信号，所述第二十一晶体管的漏极及所述第二电容的第二端均电性连接于所述第七节点，所述第二十二晶体管的源极接入所述第二时钟信号，所述第二十三晶体管的源极接入所述第一时钟信号，所述第二十三晶体管的漏极电性连接于所述第五节点。
在本申请提供的显示面板中，所述第一下拉单元包括第三十一晶体管和第三十二晶体管；
所述第三十一晶体管和所述第三十二晶体管的栅极均接入所述下一级级传信号，所述第三十一晶体管的漏极电性连接于所述第一节点，所述第三十一晶体管的源极与所述第三十二晶体管的漏极均电性连接于所述第四节点，所述第三十二晶体管的源极电性连接于所述第一参考低电平信号。
在本申请提供的显示面板中，所述第二下拉单元包括第五十五晶体管、第一百零一晶体管和第一百零二晶体管；
所述第五十五晶体管的栅极接入所述上一级级传信号，所述第五十五晶体管的源极与所述第一百零二晶体管的源极均接入所述第二参考低电平信号，所述第五十五晶体管的漏极和所述第一百零一晶体管的漏极均电性连接于所述第二节点，所述第一百零二晶体管的栅极电性连接于所述第三节点，所述第一百零二晶体管的漏极与所述第一百零一晶体管的源极电性连接，所述第一百零一晶体管的栅极接入所述重置信号。
在本申请提供的显示面板中，所述第一下拉维持单元包括第四十四晶体管和第四十五晶体管；
所述第四十四晶体管和所述第四十五晶体管的栅极均电性连接于所述第二节点，所述第四十四晶体管的漏极电性连接于所述第一节点，所述第四十四晶体管的源极与所述第四十五晶体管的漏极均电性连接于所述第四节点，所述第四十五晶体管的源极接入所述第一参考低电平信号。
在本申请提供的显示面板中，所述第二下拉维持单元包括第四十一晶体管、第四十二晶体管和第四十三晶体管；
所述第四十一晶体管的栅极、所述第四十二晶体管的栅极以及所述第四十三晶体管的栅极均电性连接于所述第二节点，所述第四十一晶体管的源极与所述第四十二晶体管的源极均接入所述第三参考低电平信号，所述第四十一晶体管的漏极电性连接于所述第七节点，所述第四十二晶体管的漏极电性连接于所述第六节点，所述第四十三晶体管的源极电性连接于所述第一参考低电平信号，所述第四十三晶体管的漏极电性连接于所述第五节点。
在本申请提供的显示面板中，所述逻辑寻址模块包括第三十三晶体管、第三十四晶体管、第七十一晶体管、第七十二晶体管、第七十三晶体管、第八十一晶体管、第八十二晶体管以及第三电容；
所述第三十三晶体管的栅极电性连接于所述第二节点，所述第三十三晶体管的源极接入所述第一参考低电平信号，所述第三十三晶体管的漏极与所述第三十四晶体管的源极电性连接，所述第三十四晶体管的栅极接入所述第一控制信号，所述第三十四晶体管的漏极、所述第八十一晶体管的漏极以及所述第八十二晶体管的源极电性连接，所述第八十一晶体管的栅极、所述第七十三晶体管的栅极、所述七十二晶体管的漏极以及所述第三电容的第二端均电性连接于所述第三节点，所述第八十一晶体管的源极与所述第七十三晶体管的漏极电性连接，所述第八十二晶体管的栅极接入所述重置信号，所述第八十二晶体管的漏极电性连接于所述第一节点，所述第三电容的第一端接入所述参考高电平信号，所述第七十一晶体管的栅极和第七十二晶体管的栅极均接入所述第二控制信号，所述第七十一晶体管的源极接入所述上一级级传信号，所述第七十一晶体管的漏极、所述第七十二晶体管的源极以及所述第七十三晶体管的源极电性连接。
在本申请提供的显示面板中，所述反相器模块包括第五十一晶体管、第五十二晶体管、第五十三晶体管以及第五十四晶体管；
所述第五十一晶体管的栅极、所述第五十一晶体管的源极以及所述第五十三晶体管的源极均接入所述参考高电平信号，所述第五十一晶体管的漏极、所述第五十三晶体管的栅极以及所述第五十二晶体管的漏极电性连接，所述第五十三晶体管的漏极与所述第五十四晶体管的源极均电性连接于所述第二节点，所述第五十四晶体管的漏极与所述第五十二晶体管的源极均接入所述第二参考低电平信号，所述第五十四晶体管的栅极与所述第五十二晶体管的栅极均电性连接于所述第一节点。
 有益效果
本申请实施例提供的GOA电路及显示面板，通过减少GOA电路中与第一节点电性连接的晶体管数量，从而减少第一节点的漏电路径，同时该GOA电路能够在空白时间内对像素电路进行实时补偿，进一步提高GOA电路的稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA电路的结构示意图；
图2为本申请实施例提供的GOA电路中一GOA单元的结构示意图；
图3为本申请实施例提供的GOA电路中一GOA单元的电路示意图；
图4为本申请实施例提供的GOA电路中一GOA单元的信号电压值；
图5为本申请实施例提供的GOA电路中一GOA单元的第一信号时序图；
图6为本申请实施例提供的GOA电路中一GOA单元的第二信号时序图；
图7为本申请实施例提供的像素电路的结构示意图；
图8为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为漏极、输出端为源极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的GOA电路的结构示意图。如图1所示，本申请实施例提供的GOA电路包括多级级传的GOA单元。图1以级传的第n-2级GOA单元、第n级GOA单元和第n+2级GOA单元为例。
当第n级GOA单元工作时，第n级GOA单元输出的扫描信号为高电位，用于打开显示面板中一行中每个像素的晶体管开关，并通过数据信号对每个像素中的像素电极进行充电；第n级级传信号用于控制第n+2级GOA单元的工作；当第n+2级GOA单元工作时，第n+2级GOA单元输出的扫描信号为高电位，同时第n级GOA单元输出的扫描信号为低电位。
请参阅图2，图2为本申请实施例提供的GOA电路中一GOA单元的结构示意图。如图2所示，该GOA单元包括：上拉控制模块101、上拉模块102、第一下拉模块103、第二下拉模块104、第一下拉维持模块105、第二下拉维持模块106、逻辑寻址模块107以及反相器模块108。
其中，上拉控制模块101接入上一级级传信号count(n-2)，并电性连接于第一节点Q和第四节点N，用于在上一级级传信号count(n-2)的控制下将上一级级传信号count(n-2)输出至所述第一节点Q。
其中，上拉模块102接入第一时钟信号CK1、第二时钟信号CK2和第三时钟信号CK3，并电性连接于第一节点Q、第五节点A、第六节点B以及第七节点C，用于在第一节点Q的电位、第一时钟信号CK1、第二时钟信号CK2和第三时钟信号CK3的控制下输出本级级传信号count(n)、本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)。
其中，第一下拉模块103接入下一级级传信号count(n+2)和第一参考低电平信号VGL1，并电性连接于第一节点Q和第四节点N，用于根据下一级扫描信号count(n+2)、第一参考低电平信号VGL1及第四节点N的电位下拉第一节点Q的电位。
其中，第二下拉模块104接入上一级级传信号count(n-2)、重置信号Reset以及第二参考低电平信号VGL2，并电性连接于第二节点QB以及第三节点M，用于根据上一级级传信号count(n-2)、重置信号Reset、第二参考低电平信号VGL2以及第三节点M的电位下拉第二节点QB的电位。
其中，第一下拉维持模块105接入第一参考低电平信号VGL1，并电性连接于第一节点Q、第二节点QB及第四节点N，用于在第一下拉模块103下拉第一节点Q的电位后，根据第一参考低电平信号VGL1、第二节点QB的电位及第四节点N的电位维持第一节点Q的低电位。
其中，第二下拉维持模块106接入第一参考低电平信号VGL1、第三参考低电平信号VGL3，并电性连接于第二节点QB、第五节点A、第六节点B以及第七节点C，用于根据第一参考低电平信号VGL1、第三参考低电平信号VGL3及第二节点QB的电位维持本级级传信号count(n)、本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)的低电位。
其中，逻辑寻址模块107接入上一级级传信号count(n-2)、参考高电平信号VGH、第一参考低电平信号VGL1、重置信号Reset、第一控制信号LSP以及第二控制信号VST，并电性连接于第一节点Q和第二节点QB。用于在空白时间内根据上一级级传信号count(n-2)、参考高电平信号VGH、第一参考低电平信号VGL1、重置信号Reset、第一控制信号LSP以及第二控制信号VST以及第二节点QB的电位控制第一节点Q的电位。
其中，反相器模块108接入第二参考低电平信号VGL2和参考高电平信号VGH，并电性连接于第一节点Q及第二节点QB，用于将第二节点QB与第一节点Q的电位保持反相。
需要说明的是，本申请实施例提供的GOA电路通过减少源漏极与第一节点电性连接的晶体管数量，从而减少第一节点Q的漏电路径，提高GOA电路的稳定性。
请参阅图3，图3为本申请实施例提供的GOA电路中一GOA单元的电路示意图。如图3所示，上拉控制模块101包括第十一晶体管T11和第十二晶体管T12。第十一晶体管T11的栅极、第十一晶体管T11的源极以及第十二晶体管T12的栅极均接入上一级级传信号Cout(n-2)。第十一晶体管T11的漏极与第十二晶体管T12的源极均电性连接于第四节点N。第十二晶体管T12的漏极电性连接于第一节点Q。
上拉模块102包括第六晶体管T6、第二十一晶体管T21、第二十二晶体管T22、第二十三晶体管T23、第一电容C1以及第二电容C2。第六晶体管T6、第二十一晶体管T21的栅极、第二十二晶体管T22的栅极、第二十三晶体管T23的栅极、第一电容C1的第一端以及第二电容C2的第一端均电性连接于第一节点Q。第六晶体管T6的漏极电性连接于第四节点N。第六晶体管T6的源极、第一电容C1的第二端以及第二十二晶体管T22的漏极均电性连接于第六节点B。第二十一晶体管T21的源极接入第三时钟信号CK3。第二十一晶体管T21的漏极及第二电容C2的第二端均电性连接于第七节点C。第二十二晶体管T22的源极接入第二时钟信号CK2。第二十三晶体管T23的源极接入第一时钟信号CK1。第二十三晶体管T23的漏极电性连接于第五节点B。
第一下拉单元103包括第三十一晶体管T31和第三十二晶体管T32。第三十一晶体管T31和第三十二晶体管T32的栅极均接入下一级级传信号Cout(n-2)。第三十一晶体管T31的漏极电性连接于第一节点Q。第三十一晶体管T31的源极与第三十二晶体管T32的漏极均电性连接于第四节点N。第三十二晶体管T32的源极电性连接于第一参考低电平信号VGL1。
第二下拉单元104包括第五十五晶体管T55、第一百零一晶体管T101和第一百零二晶体管T102。第五十五晶体管T55的栅极接入上一级级传信号Cout(n-2)。第五十五晶体管T55的源极与第一百零二晶体管T102的源极均接入第二参考低电平信号VGL2。第五十五晶体管T55的漏极和第一百零一晶体管T101的漏极均电性连接于第二节点QB。第一百零二晶体管T102的栅极电性连接于第三节点M。第一百零二晶体管T102的漏极与第一百零一晶体管T101的源极电性连接。第一百零一晶体管T101的栅极接入重置信号Reset。
第一下拉维持单元105包括第四十四晶体管T44和第四十五晶体管T45。第四十四晶体管T44和第四十五T45的栅极均电性连接于第二节点QB。第四十四晶体管T44的漏极电性连接于第一节点Q。第四十四晶体管T44的源极与第四十五晶体管T45的漏极均电性连接于第四节点N。第四十五晶体管T45的源极接入第一参考低电平信号VGL1。
第二下拉维持单元106包括第四十一晶体管T41、第四十二晶体管T42和第四十三晶体管T43。第四十一晶体管T41的栅极、第四十二晶体管T42的栅极以及第四十三晶体管T43的栅极均电性连接于第二节点QB。第四十一晶体管T41的源极与第四十二晶体管T42的源极均接入第三参考低电平信号VGL3。第四十一晶体管T41的漏极电性连接于第七节点C。第四十二晶体管T42的漏极电性连接于第六节点B。第四十三晶体管T43的源极电性连接于第一参考低电平信号VGL1。第四十三晶体管T43的漏极电性连接于第五节点A。
逻辑寻址模块107包括第三十三晶体管T33、第三十四晶体管T34、第七十一晶体管T71、第七十二晶体管T72、第七十三晶体管T73、第八十一晶体管T81、第八十二晶体管T82以及第三电容C3。第三十三晶体管T33的源极接入第一参考低电平信号VGL1。第三十三晶体管T33的漏极与第三十四晶体管T34的源极电性连接。第三十四晶体管T34的栅极接入第一控制信号LSP。第三十四晶体管T34的漏极、第八十一晶体管T81的漏极以及第八十二晶体管T82的源极电性连接。第八十一晶体管T81的栅极、第七十三晶体管T73的栅极、七十二晶体管T72的漏极以及第三电容C1的第二端均电性连接于第三节点M。第八十一晶体管T81的源极与第七十三晶体管的漏极电性T73连接。第八十二晶体管T82的栅极接入重置信号Reset。第八十二晶体管T82的漏极电性连接于第一节点Q。第三电容C3的第一端接入参考高电平信号VGH，第七十一晶体管T71的栅极和第七十二晶体管T72的栅极均接入第二控制信号VST。第七十一晶体管T71的源极接入上一级级传信号Cout(n-2)。第七十一晶体管T71的漏极、第七十二晶体管T72的源极以及第七十三晶体管T73的源极电性连接。
反相器模块108包括第五十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53以及第五十四晶体管T54。第五十一晶体管T51的栅极、第五十一晶体管T51的源极以及第五十三晶体管T53的源极均接入参考高电平信号VGH。第五十一晶体管T51的漏极、第五十三晶体管T53的栅极以及第五十二晶体管T52的漏极电性连接。第五十三晶体管T53的漏极与第五十四晶体管T54的源极均电性连接于第二节点QB。第五十四晶体管T54的漏极与第五十二晶体管T52的源极均接入第二参考低电平信号VGL2。第五十四晶体管T54的栅极与第五十二晶体管T52的栅极均电性连接于第一节点Q。
需要说明的是，本申请实施例提供的GOA电路通过减少源漏极与第一节点电性连接的晶体管数量，从而减少第一节点Q的漏电路径。同时，在GOA电路中，通过设计耗尽型电路，比如，第十一晶体管T11的漏极与第十二晶体管T12的源极均电性连接于第四节点N、第三十一晶体管T31的源极与第三十二晶体管T32的漏极均电性连接于第四节点N以及第四十四晶体管T44的源极与第四十五晶体管T45的漏极均电性连接于第四节点N，当第一节点Q升为高电位时，第四节点N也为高电位，使得第十一晶体管T11、第十二晶体管T12、第三十一晶体管T31、第三十二晶体管T32、第四十四晶体管T44以及第四十五晶体管T45的漏电减少，进一步减少了GOA电路的漏电，与现有技术相比，有效地提高了GOA电路的稳定性。
具体的，请参阅图4和图5，图4是本申请实施例提供的GOA电路中一GOA单元的信号电压值，图5是本申请实施例提供的GOA电路中一GOA单元的第一信号时序图。
在B1阶段，上一级级传信号Cout(n-2)升为高电位，第十一晶体管T11、第十二晶体管T12均打开，第一节点Q的电位被拉升至高电位，使得第五十二晶体管T52、第五十四晶体管T54、第二十一晶体管T21、第二十二晶体管T22以及第二十三晶体管T23均打开。由于第一节点Q与第二节点QB之间连接反相器模块108，第一节点Q的电位与第二节点QB的电位反相，因此，第二节点QB处于低电位，使得第四十一晶体管41、第四十二晶体管42、第四十三晶体管43、第四十四晶体管44以及第四十五晶体管T45均关闭。同时，下一级级传信号Cout(n+2)为低电位，使得第三十一晶体管T31及第三十二晶体管T32均关闭。第二控制信号VST为低电位，使得第三十三晶体管T33及第三十四晶体管T34关闭。第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3均为低电位，则本级级传信号Cout(n)，本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)均输出低电位。第一控制信号LSP升为高电位，使得第七十一晶体管T71及第七十二晶体管T72打开，第三节点M被抬升为高电位，使得第八十一晶体管T81打开。重置信号Reset为低电位，使得第八十二晶体管T82关闭。
需要说明的是，在B1阶段，上一级级传信号Cout(n-2)升为高电位，使得第五十五晶体管T55打开。由于第五十五晶体管T55打开的源极接入第二参考低电平信号，第五十五晶体管T55输出低电平信号，进一步将第二节点QB的电位拉低至低电位，使得第二节点QB的falling time（下降时间）更好。
在B2阶段，第一控制信号LSP由高电位降为低电位，使得第七十一晶体管T71及第七十二晶体管T72均关闭，第三节点M的电位继续维持高电位，第一节点Q的电位继续保持为高电位。第二节点QB的电位、本级级传信号Cout(n)、本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)继续保持为低电位。
在B3阶段，上一级级传Cout(n-2)由高电位变为低电位，使得第十一晶体管T11及第十二晶体管T12关闭。第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3均由低电位变为高电位，因此，本级级传信号Cout(n)、本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)的电位被抬升至高电位。在该阶段，本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)，使得本级GOA单元对应的扫描线被充电，打开本级扫描线对应的一行像素，该行像素被点亮。
同时由于第一电容C1及第二电容C2的存在，第一节点Q的电位被耦合至更高电位，保证第二十一晶体管T21、第二十二晶体管T22以及第二十三晶体管T23的打开，从而保证本级级传信号Cout(n)、本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)均为高电位信号。
在B4阶段，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3均由高电位变为低电位，使得本级级传信号Cout(n)、本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)均被拉低至低电位。
请参阅图4和图6，图6为本申请实施例提供的GOA电路中一GOA单元的第二信号时序图。
在S1阶段，重置信号Reset升为高电位，使得第八十二晶体管T82打开，第一节点Q的电位被拉至高电位，使得第五十二晶体管T52、第五十四晶体管T54、第二十一晶体管T21、第二十二晶体管T22以及第二十三晶体管T23均打开。由于第一节点Q与第二节点QB之间连接反相器模块108，第一节点Q的电位与第二节点QB的电位反相，因此，第二节点QB处于低电位，使得第四十一晶体管41、第四十二晶体管42、第四十三晶体管43、第四十四晶体管44以及第四十五晶体管T45均关闭。同时，下一级级传信号Cout(n+2)为低电位，使得第三十一晶体管T31及第三十二晶体管T32均关闭。第二控制信号VST为低电位，使得第三十三晶体管T33及第三十四晶体管T34关闭。第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3均为低电位，则本级级传信号Cout(n)，本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)均输出低电位。
在S2阶段，重置信号Reset由高电位变为低电位，使得第八十二晶体管T82关闭。第一时钟信号CK1持续保持为低电位，第二时钟信号CK2及第三时钟信号CK3升为高电位，使得本级级传信号Cout(n)维持低电位，本级第一扫描信号WR(n)与本级第二扫描信号RD(n)输出高电位。同时由于第一电容C1及第二电容C2的存在，第一节点Q的电位被耦合至更高电位，保证第二十一晶体管T21、第二十二晶体管T22以及第二十三晶体管T23的打开，从而保证本级级传信号Cout(n)维持低电位、本级第一扫描信号WR(n)以及本级第二扫描信号RD(n)输出为高电位信号。
在S3阶段，第二时钟信号CK2及第三时钟信号CK3降为低电位，第一节点Q的电位被耦合至参考高电平信号VGH，本级第一扫描信号WR(n)与本级第二扫描信号RD(n)被拉低为低电位。
在S4阶段，第二控制信号VST及重置信号Reset由低电位升为高电位，第三十四晶体管T34、第八十二晶体管T82以及第一百零一晶体管T101打开，第三节点M的电位以及第一节点Q的电位均被拉至低电位，第二节点QB的电位升为高电位，本级级传信号Cout(n)、本级第一扫描信号WR(n)与本级第二扫描信号RD(n)持续维持低电位。
本申请实施例提供的GOA电路能够在空白时间内对像素电路进行补偿，由GOA电路的模拟结果显示，当GOA电路的阈值电压负偏-6V时，GOA电路输出仍有效，直至GOA电路的阈值电压负偏-8V时，GOA电路输出失效，与现有技术相比，有效地提高了GOA电路的稳定性，从而降低TFT（Thin Film Transistor，薄膜晶体管）制程的开发难度。
需要说明的是，本申请实施例提供的像素电路如图7所示，该像素电路为本来领域技术人员所理解的技术，这里不再赘述。
请参阅图8，图8为本申请实施例提供的显示面板的结构示意图。如图8所示，该显示面板包括显示区域以及集成设置在显示区域100边缘上的GOA电路200；其中，该GOA电路200与上述的GOA电路的结构和原理类似，这里不再赘述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种GOA电路，其包括多级级传的GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、第一下拉模块、第二下拉模块、第一下拉维持模块、第二下拉维持模块、逻辑寻址模块以及反相器模块；
    所述上拉控制模块接入上一级级传信号，并电性连接于第一节点和第四节点，用于在所述上一级级传信号及所述第四节点的电位的控制下将所述上一级级传信号输出至所述第一节点；
    所述上拉模块接入第一时钟信号、第二时钟信号和第三时钟信号，并电性连接于所述第一节点、第五节点、第六节点以及第七节点，用于在所述第一节点的电位控制下输出本级级传信号、本级第一扫描信号以及本级第二扫描信号；
    所述第一下拉模块接入下一级级传信号和第一参考低电平信号，并电性连接于所述第一节点和所述第四节点，用于根据所述下一级扫描信号、所述第一参考低电平信号及所述第四节点的电位下拉所述第一节点的电位；
    所述第二下拉模块接入所述上一级级传信号、重置信号以及第二参考低电平信号，并电性连接于第二节点以及第三节点，用于根据所述上一级级传信号、所述重置信号、所述第二参考低电平信号以及所述第三节点的电位下拉所述第二节点的电位；
    所述第一下拉维持模块接入所述第一参考低电平信号，并电性连接于所述第一节点、所述第二节点及所述第四节点，用于在所述第一下拉模块下拉所述第一节点的电位后，根据所述第一参考低电平信号、所述第二节点的电位及所述第四节点的电位维持所述第一节点的低电位；
    所述第二下拉维持模块接入所述第一参考低电平信号与第三参考低电平信号，并电性连接于所述第二节点、所述第五节点、所述第六节点以及所述第七节点，用于根据所述第一参考低电平信号、所述第三参考低电平信号以及所述第二节点的电位维持所述本级级传信号、所述本级第一扫描信号以及所述本级第二扫描信号的的低电位；
    所述逻辑寻址模块接入所述上一级级传信号、参考高电平信号、所述第一参考低电平信号、所述重置信号、第一控制信号以及第二控制信号，并电性连接于所述第一节点和所述第二节点，用于在空白时间内根据所述上一级级传信号、所述参考高电平信号、所述重置信号、所述第一控制信号以及所述第二节点的电位控制所述第一节点的电位；
    所述反相器模块接入所述第二参考低电平信号和所述参考高电平信号，并电性连接于所述第一节点及所述第二节点，用于将所述第二节点与所述第一节点的电位保持反相。
  2. 根据权利要求1所述的GOA电路，其中，所述上拉控制模块包括：第十一晶体管和第十二晶体管；
    所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的栅极均接入所述上一级级传信号，所述第十一晶体管的漏极与所述第十二晶体管的源极均电性连接于所述第四节点，所述第十二晶体管的漏极电性连接于所述第一节点。
  3. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括：第六晶体管、第二十一晶体管、第二十二晶体管、第二十三晶体管、第一电容以及第二电容；
    所述第六晶体管的栅极、所述第二十一晶体管的栅极、所述第二十二晶体管的栅极、所述第二十三晶体管的栅极、所述第一电容的第一端以及所述第二电容的第一端均电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第四节点，所述第六晶体管的源极、所述第一电容的第二端以及所述第二十二晶体管的漏极均电性连接于所述第六节点，所述第二十一晶体管的源极接入所述第三时钟信号，所述第二十一晶体管的漏极及所述第二电容的第二端均电性连接于所述第七节点，所述第二十二晶体管的源极接入所述第二时钟信号，所述第二十三晶体管的源极接入所述第一时钟信号，所述第二十三晶体管的漏极电性连接于所述第五节点。
  4. 根据权利要求1所述的GOA电路，其中，所述第一下拉单元包括第三十一晶体管和第三十二晶体管；
    所述第三十一晶体管和所述第三十二晶体管的栅极均接入所述下一级级传信号，所述第三十一晶体管的漏极电性连接于所述第一节点，所述第三十一晶体管的源极与所述第三十二晶体管的漏极均电性连接于所述第四节点，所述第三十二晶体管的源极电性连接于所述第一参考低电平信号。
  5. 根据权利要求1所述的GOA电路，其中，所述第二下拉单元包括第五十五晶体管、第一百零一晶体管和第一百零二晶体管；
    所述第五十五晶体管的栅极接入所述上一级级传信号，所述第五十五晶体管的源极与所述第一百零二晶体管的源极均接入所述第二参考低电平信号，所述第五十五晶体管的漏极和所述第一百零一晶体管的漏极均电性连接于所述第二节点，所述第一百零二晶体管的栅极电性连接于所述第三节点，所述第一百零二晶体管的漏极与所述第一百零一晶体管的源极电性连接，所述第一百零一晶体管的栅极接入所述重置信号。
  6. 根据权利要求1所述的GOA 电路，其中，所述第一下拉维持单元包括第四十四晶体管和第四十五晶体管；
    所述第四十四晶体管和所述第四十五晶体管的栅极均电性连接于所述第二节点，所述第四十四晶体管的漏极电性连接于所述第一节点，所述第四十四晶体管的源极与所述第四十五晶体管的漏极均电性连接于所述第四节点，所述第四十五晶体管的源极接入所述第一参考低电平信号。
  7. 根据权利要求1所述的GOA电路，其中，所述第二下拉维持单元包括第四十一晶体管、第四十二晶体管和第四十三晶体管；
    所述第四十一晶体管的栅极、所述第四十二晶体管的栅极以及所述第四十三晶体管的栅极均电性连接于所述第二节点，所述第四十一晶体管的源极与所述第四十二晶体管的源极均接入所述第三参考低电平信号，所述第四十一晶体管的漏极电性连接于所述第七节点，所述第四十二晶体管的漏极电性连接于所述第六节点，所述第四十三晶体管的源极电性连接于所述第一参考低电平信号，所述第四十三晶体管的漏极电性连接于所述第五节点。
  8. 根据权利要求1所述的GOA电路，其中，所述逻辑寻址模块包括第三十三晶体管、第三十四晶体管、第七十一晶体管、第七十二晶体管、第七十三晶体管、第八十一晶体管、第八十二晶体管以及第三电容；
    所述第三十三晶体管的栅极电性连接于所述第二节点，所述第三十三晶体管的源极接入所述第一参考低电平信号，所述第三十三晶体管的漏极与所述第三十四晶体管的源极电性连接，所述第三十四晶体管的栅极接入所述第一控制信号，所述第三十四晶体管的漏极、所述第八十一晶体管的漏极以及所述第八十二晶体管的源极电性连接，所述第八十一晶体管的栅极、所述第七十三晶体管的栅极、所述七十二晶体管的漏极以及所述第三电容的第二端均电性连接于所述第三节点，所述第八十一晶体管的源极与所述第七十三晶体管的漏极电性连接，所述第八十二晶体管的栅极接入所述重置信号，所述第八十二晶体管的漏极电性连接于所述第一节点，所述第三电容的第一端接入所述参考高电平信号，所述第七十一晶体管的栅极和第七十二晶体管的栅极均接入所述第二控制信号，所述第七十一晶体管的源极接入所述上一级级传信号，所述第七十一晶体管的漏极、所述第七十二晶体管的源极以及所述第七十三晶体管的源极电性连接。
  9. 根据权利要求1所述的GOA电路，其中，所述反相器模块包括第五十一晶体管、第五十二晶体管、第五十三晶体管以及第五十四晶体管；
    所述第五十一晶体管的栅极、所述第五十一晶体管的源极以及所述第五十三晶体管的源极均接入所述参考高电平信号，所述第五十一晶体管的漏极、所述第五十三晶体管的栅极以及所述第五十二晶体管的漏极电性连接，所述第五十三晶体管的漏极与所述第五十四晶体管的源极均电性连接于所述第二节点，所述第五十四晶体管的漏极与所述第五十二晶体管的源极均接入所述第二参考低电平信号，所述第五十四晶体管的栅极与所述第五十二晶体管的栅极均电性连接于所述第一节点。
  10. 一种显示面板，其包括GOA电路，所述GOA电路包括多级级传的GOA单元，每一级GOA单元均包括：上拉控制模块、上拉模块、第一下拉模块、第二下拉模块、第一下拉维持模块、第二下拉维持模块、逻辑寻址模块以及反相器模块；
    所述上拉控制模块接入上一级级传信号，并电性连接于第一节点和第四节点，用于在所述上一级级传信号及所述第四节点的电位的控制下将所述上一级级传信号输出至所述第一节点；
    所述上拉模块接入第一时钟信号、第二时钟信号和第三时钟信号，并电性连接于所述第一节点、第五节点、第六节点以及第七节点，用于在所述第一节点的电位控制下输出本级级传信号、本级第一扫描信号以及本级第二扫描信号；
    所述第一下拉模块接入下一级级传信号和第一参考低电平信号，并电性连接于所述第一节点和所述第四节点，用于根据所述下一级扫描信号、所述第一参考低电平信号及所述第四节点的电位下拉所述第一节点的电位；
    所述第二下拉模块接入所述上一级级传信号、重置信号以及第二参考低电平信号，并电性连接于第二节点以及第三节点，用于根据所述上一级级传信号、所述重置信号、所述第二参考低电平信号以及所述第三节点的电位下拉所述第二节点的电位；
    所述第一下拉维持模块接入所述第一参考低电平信号，并电性连接于所述第一节点、所述第二节点及所述第四节点，用于在所述第一下拉模块下拉所述第一节点的电位后，根据所述第一参考低电平信号、所述第二节点的电位及所述第四节点的电位维持所述第一节点的低电位；
    所述第二下拉维持模块接入所述第一参考低电平信号与第三参考低电平信号，并电性连接于所述第二节点、所述第五节点、所述第六节点以及所述第七节点，用于根据所述第一参考低电平信号、所述第三参考低电平信号以及所述第二节点的电位维持所述本级级传信号、所述本级第一扫描信号以及所述本级第二扫描信号的的低电位；
    所述逻辑寻址模块接入所述上一级级传信号、参考高电平信号、所述第一参考低电平信号、所述重置信号、第一控制信号以及第二控制信号，并电性连接于所述第一节点和所述第二节点，用于在空白时间内根据所述上一级级传信号、所述参考高电平信号、所述重置信号、所述第一控制信号以及所述第二节点的电位控制所述第一节点的电位；
    所述反相器模块接入所述第二参考低电平信号和所述参考高电平信号，并电性连接于所述第一节点及所述第二节点，用于将所述第二节点与所述第一节点的电位保持反相。
  11. 根据权利要求10所述的显示面板，其中，所述上拉控制模块包括：第十一晶体管和第十二晶体管；
    所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的栅极均接入所述上一级级传信号，所述第十一晶体管的漏极与所述第十二晶体管的源极均电性连接于所述第四节点，所述第十二晶体管的漏极电性连接于所述第一节点。
  12. 根据权利要求10所述的显示面板，其中，所述上拉模块包括：第六晶体管、第二十一晶体管、第二十二晶体管、第二十三晶体管、第一电容以及第二电容；
    所述第六晶体管的栅极、所述第二十一晶体管的栅极、所述第二十二晶体管的栅极、所述第二十三晶体管的栅极、所述第一电容的第一端以及所述第二电容的第一端均电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第四节点，所述第六晶体管的源极、所述第一电容的第二端以及所述第二十二晶体管的漏极均电性连接于所述第六节点，所述第二十一晶体管的源极接入所述第三时钟信号，所述第二十一晶体管的漏极及所述第二电容的第二端均电性连接于所述第七节点，所述第二十二晶体管的源极接入所述第二时钟信号，所述第二十三晶体管的源极接入所述第一时钟信号，所述第二十三晶体管的漏极电性连接于所述第五节点。
  13. 根据权利要求10所述的显示面板，其中，所述第一下拉单元包括第三十一晶体管和第三十二晶体管；
    所述第三十一晶体管和所述第三十二晶体管的栅极均接入所述下一级级传信号，所述第三十一晶体管的漏极电性连接于所述第一节点，所述第三十一晶体管的源极与所述第三十二晶体管的漏极均电性连接于所述第四节点，所述第三十二晶体管的源极电性连接于所述第一参考低电平信号。
  14. 根据权利要求10所述的显示面板，其中，所述第二下拉单元包括第五十五晶体管、第一百零一晶体管和第一百零二晶体管；
    所述第五十五晶体管的栅极接入所述上一级级传信号，所述第五十五晶体管的源极与所述第一百零二晶体管的源极均接入所述第二参考低电平信号，所述第五十五晶体管的漏极和所述第一百零一晶体管的漏极均电性连接于所述第二节点，所述第一百零二晶体管的栅极电性连接于所述第三节点，所述第一百零二晶体管的漏极与所述第一百零一晶体管的源极电性连接，所述第一百零一晶体管的栅极接入所述重置信号。
  15. 根据权利要求10所述的显示面板，其中，所述第一下拉维持单元包括第四十四晶体管和第四十五晶体管；
    所述第四十四晶体管和所述第四十五晶体管的栅极均电性连接于所述第二节点，所述第四十四晶体管的漏极电性连接于所述第一节点，所述第四十四晶体管的源极与所述第四十五晶体管的漏极均电性连接于所述第四节点，所述第四十五晶体管的源极接入所述第一参考低电平信号。
  16. 根据权利要求10所述的显示面板，其中，所述第二下拉维持单元包括第四十一晶体管、第四十二晶体管和第四十三晶体管；
    所述第四十一晶体管的栅极、所述第四十二晶体管的栅极以及所述第四十三晶体管的栅极均电性连接于所述第二节点，所述第四十一晶体管的源极与所述第四十二晶体管的源极均接入所述第三参考低电平信号，所述第四十一晶体管的漏极电性连接于所述第七节点，所述第四十二晶体管的漏极电性连接于所述第六节点，所述第四十三晶体管的源极电性连接于所述第一参考低电平信号，所述第四十三晶体管的漏极电性连接于所述第五节点。
  17. 根据权利要求10所述的显示面板，其中，所述逻辑寻址模块包括第三十三晶体管、第三十四晶体管、第七十一晶体管、第七十二晶体管、第七十三晶体管、第八十一晶体管、第八十二晶体管以及第三电容；
    所述第三十三晶体管的栅极电性连接于所述第二节点，所述第三十三晶体管的源极接入所述第一参考低电平信号，所述第三十三晶体管的漏极与所述第三十四晶体管的源极电性连接，所述第三十四晶体管的栅极接入所述第一控制信号，所述第三十四晶体管的漏极、所述第八十一晶体管的漏极以及所述第八十二晶体管的源极电性连接，所述第八十一晶体管的栅极、所述第七十三晶体管的栅极、所述七十二晶体管的漏极以及所述第三电容的第二端均电性连接于所述第三节点，所述第八十一晶体管的源极与所述第七十三晶体管的漏极电性连接，所述第八十二晶体管的栅极接入所述重置信号，所述第八十二晶体管的漏极电性连接于所述第一节点，所述第三电容的第一端接入所述参考高电平信号，所述第七十一晶体管的栅极和第七十二晶体管的栅极均接入所述第二控制信号，所述第七十一晶体管的源极接入所述上一级级传信号，所述第七十一晶体管的漏极、所述第七十二晶体管的源极以及所述第七十三晶体管的源极电性连接。
  18. 根据权利要求10所述的显示面板，其中，所述反相器模块包括第五十一晶体管、第五十二晶体管、第五十三晶体管以及第五十四晶体管；
    所述第五十一晶体管的栅极、所述第五十一晶体管的源极以及所述第五十三晶体管的源极均接入所述参考高电平信号，所述第五十一晶体管的漏极、所述第五十三晶体管的栅极以及所述第五十二晶体管的漏极电性连接，所述第五十三晶体管的漏极与所述第五十四晶体管的源极均电性连接于所述第二节点，所述第五十四晶体管的漏极与所述第五十二晶体管的源极均接入所述第二参考低电平信号，所述第五十四晶体管的栅极与所述第五十二晶体管的栅极均电性连接于所述第一节点。
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