WO2019075792A1 - 一种goa电路及液晶面板、显示装置 - Google Patents

一种goa电路及液晶面板、显示装置 Download PDF

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WO2019075792A1
WO2019075792A1 PCT/CN2017/109302 CN2017109302W WO2019075792A1 WO 2019075792 A1 WO2019075792 A1 WO 2019075792A1 CN 2017109302 W CN2017109302 W CN 2017109302W WO 2019075792 A1 WO2019075792 A1 WO 2019075792A1
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thin film
film transistor
clock signal
circuit
gate
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PCT/CN2017/109302
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English (en)
French (fr)
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吕晓文
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/742,165 priority Critical patent/US10217430B1/en
Publication of WO2019075792A1 publication Critical patent/WO2019075792A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a GOA (Gate Driver On Array) circuit, a liquid crystal panel, and a display device.
  • GOA Gate Driver On Array
  • GOA Chip On Flex/Film
  • the pull-up control circuit 1 is responsible for controlling the opening time of the pull-up circuit 2 to achieve pre-charging of the pre-charging point potential signal Q(N), and generally connecting the downlink signal and the gate output signal transmitted by the upper-level GOA structural unit;
  • the pull-up circuit 2 mainly increases the potential of the gate output signal G(N) to control the opening of the Gate;
  • the downstream circuit 3 mainly controls the opening and closing of signals in the next-stage GOA structural unit;
  • the pull-down circuit 4 is responsible for the first time Pull down the Q(N) and G(N) point potentials to VSS to turn off the G(N) point signal;
  • the pull-down sustain circuit 5 is responsible for maintaining the Q(N) and G(N) point potentials at VSS, ie Negative potential, usually two pull-down maintenance modules alternate; bootstrap capacitor 6 is responsible for the secondary rise of Q (N) point, which is beneficial to the G (N) output of the pull-up circuit.
  • a Darlington structure inverter can be employed, so that the single-stage GOA structural unit of FIG. 1 can be transformed into the single-stage GOA structural unit of FIG.
  • two pull-down maintaining circuits 5 are alternately operated to prevent the thin film transistors T32, T42, T33, and T43 from being subjected to PBS (Positive Bias Stress) for a long time so that the threshold voltage Vth of the device is positive. Severe deflection causes the circuit to fail.
  • PBS Positive Bias Stress
  • the two pull-down sustain circuits 5 respectively use the inverted signals LC1 and LC2, that is, the potentials of LC1 and LC2 are different at the same time, but when LC1 is high, the pull-down of the left side of the single-stage GOA structural unit is maintained.
  • the circuit 5 operates such that the thin film transistors T42 and T32 are connected to the circuit point P(N) for a long period of time, causing a positive deflection of the threshold voltage Vth of the thin film transistors T42 and T32; likewise, after a period of time, LC1 and The LC2 potential is interchanged, and the pull-down sustain circuit 5 on the right side of the single-stage GOA structure unit operates, so that the gate connection circuit point K(N) of the thin film transistors T43 and T33 is in a high potential state for a long period of time, thereby causing the threshold voltage Vth of the thin film transistors T43 and T33. Positive deflection occurs.
  • the threshold voltage Vth of the thin film transistors T32, T42, T33, and T43 is positive. The deflection is getting worse and worse, causing the entire GOA circuit to fail.
  • the technical problem to be solved by the embodiments of the present invention is to provide a GOA circuit, a liquid crystal panel, and a display device, which can effectively correct the forward deflection problem of the threshold voltage of the thin film transistor in the pull-down sustain circuit in the single-stage GOA structural unit, thereby improving the GOA. Circuit reliability and stability.
  • an embodiment of the present invention provides a GOA circuit including a plurality of cascaded GOA structural units, and each single-level GOA structural unit is corresponding to the display area of the display panel according to the Nth-level GOA structural unit.
  • a row of pixel units outputting a row scan signal;
  • the Nth stage GOA structure unit includes a pull-up control circuit, a pull-up circuit, a down-transfer circuit, a pull-down circuit, a pull-down sustain circuit, and a bootstrap capacitor, and N is a positive integer;
  • the pull-down maintaining circuit includes a first pull-down sustain sub-circuit and a second pull-down sustain sub-circuit that work alternately: wherein
  • the first pull-down maintaining sub-circuit includes:
  • a drain of the first thin film transistor is connected to a first clock signal, and a source is connected to the first circuit point;
  • the drain of the second thin film transistor is in communication with the gate, and the drain and the gate are connected to the first clock signal, and the source is connected to the gate of the first thin film transistor;
  • a drain of the third thin film transistor is connected to a source of the second thin film transistor, and a gate is connected to a precharge potential signal, and a source is connected to a DC low voltage signal;
  • a drain of the fourth thin film transistor is connected to the first circuit point, and a gate is connected to the pre-charge point potential signal, and a source is connected to the DC low-voltage signal;
  • a drain of the sixth thin film transistor is connected to the precharge point potential signal And the gate is connected to the first circuit point, and the source is connected to the first reverse clock signal;
  • the potentials of the first reverse clock signal and the first clock signal at respective same times should be relatively set to be different;
  • the second pull-down maintaining sub-circuit includes:
  • the eighth thin film transistor, the drain of the eighth thin film transistor is in communication with the gate, and the drain and the gate are connected to the second clock signal, and the source is connected to the gate of the seventh thin film transistor;
  • a ninth thin film transistor a drain of the ninth thin film transistor is connected to a source of the eighth thin film transistor, and a gate is connected to the precharge point potential signal, and a source is connected to the DC low voltage signal;
  • a drain of the tenth thin film transistor is connected to the second circuit point, and a gate is connected to the precharge point potential signal, and a source is connected to the DC low voltage signal;
  • An eleventh thin film transistor a drain of the eleventh thin film transistor is connected to a gate output signal, and a gate is connected to the second circuit point, and a source is connected to the second reverse clock signal;
  • a drain of the twelfth thin film transistor is connected to the precharge point potential signal, and a gate is connected to the second circuit point, and a source is connected to the second reverse clock signal;
  • the first reverse clock signal and the second clock signal have the same frequency and potential.
  • the first reverse clock signal and the second clock signal are from the same signal source.
  • the second reverse clock signal has the same frequency and potential as the first clock signal.
  • the second reverse clock signal and the first clock signal are from the same signal source.
  • the potentials of the first clock signal and the second reverse clock signal are both -8V
  • the potentials of the second clock signal and the first reverse clock signal are both 28V or 8V.
  • the pull-up circuit of the Nth-level GOA structural unit includes a thirteenth thin film transistor, the drain of the thirteenth thin film transistor is connected to the Nth-level clock signal, and the gate is connected to the pre-charge potential signal. A source is coupled to the gate output signal.
  • the pull-down circuit of the Nth-level GOA structural unit includes a fourteenth thin film transistor and a fifteenth transistor;
  • the drain of the fourteenth thin film transistor is connected to the gate output signal, and the gate is connected to the gate output signal of the N+1th GOA structural unit, and the source is connected to the DC low voltage signal;
  • a drain of the fifteenth thin film transistor is connected to the precharge potential signal, and a gate is simultaneously connected to a gate output signal of the (N+1)th stage GOA structural unit and a gate of the fourteenth thin film transistor
  • the source is connected to the DC low voltage signal.
  • an embodiment of the present invention further provides a liquid crystal panel including a GOA circuit
  • the GOA circuit includes a plurality of cascaded GOA structural units, each of which outputs a line scan signal to a corresponding row of pixel units in a display area of the display panel according to the Nth stage GOA structural unit;
  • the stage GOA structural unit includes a pull-up control circuit, a pull-up circuit, a downlink circuit, a pull-down circuit, a pull-down sustain circuit, and a bootstrap capacitor, and N is a positive integer;
  • the pull-down maintaining circuit includes a first pull-down sustain sub-circuit and a second pull-down sustain sub-circuit that work alternately: wherein
  • the first pull-down maintaining sub-circuit includes:
  • a drain of the first thin film transistor is connected to a first clock signal, and a source is connected to the first circuit point;
  • the drain of the second thin film transistor is in communication with the gate, and the drain and the gate are connected to the first clock signal, and the source is connected to the gate of the first thin film transistor;
  • a drain of the third thin film transistor is connected to a source of the second thin film transistor, and a gate is connected to a precharge potential signal, and a source is connected to a DC low voltage signal;
  • a drain of the fourth thin film transistor is connected to the first circuit point, and a gate is connected to the pre-charge point potential signal, and a source is connected to the DC low-voltage signal;
  • a drain of the fifth thin film transistor is connected to a gate output signal, and a gate is connected to the first circuit point, and a source is connected to the first reverse clock signal;
  • a drain of the sixth thin film transistor is connected to the pre-charge point potential signal, and a gate is connected to the first circuit point, and a source is connected to the first reverse clock signal;
  • the potentials of the first reverse clock signal and the first clock signal at respective same times should be relatively set to be different;
  • the second pull-down maintaining sub-circuit includes:
  • a drain of the seventh thin film transistor is connected to the second clock signal, and a source is connected to the second circuit point;
  • the eighth thin film transistor, the drain of the eighth thin film transistor is in communication with the gate, and the drain and the gate are connected to the second clock signal, and the source is connected to the gate of the seventh thin film transistor;
  • a ninth thin film transistor a drain of the ninth thin film transistor is connected to a source of the eighth thin film transistor, and a gate is connected to the precharge point potential signal, and a source is connected to the DC low voltage signal;
  • a drain of the tenth thin film transistor is connected to the second circuit point, and a gate is connected to the precharge point potential signal, and a source is connected to the DC low voltage signal;
  • An eleventh thin film transistor a drain of the eleventh thin film transistor is connected to a gate output signal, and a gate is connected to the second circuit point, and a source is connected to the second reverse clock signal;
  • a drain of the twelfth thin film transistor is connected to the precharge point potential signal, and a gate is connected to the second circuit point, and a source is connected to the second reverse clock signal;
  • the potentials of the second clock signal and the first clock signal at respective same times should be oppositely set to be different, and the second clock signal and the second reverse clock signal are at the same time.
  • the potentials on the top should be set to be different.
  • the first reverse clock signal and the second clock signal have the same frequency and potential, and the first reverse clock signal and the second clock signal are from the same signal source.
  • the second reverse clock signal has the same frequency and potential as the first clock signal, and the second reverse clock signal and the first clock signal are from the same signal source.
  • the potentials of the first clock signal and the second reverse clock signal are both -8V
  • the potentials of the second clock signal and the first reverse clock signal are both 28V or 8V.
  • an embodiment of the present invention further provides a display device, including a liquid crystal panel, and the liquid crystal panel includes a GOA circuit;
  • the GOA circuit includes a plurality of cascaded GOA structural units, each of which outputs a line scan signal to a corresponding row of pixel units in a display area of the display panel according to the Nth stage GOA structural unit;
  • the stage GOA structural unit includes a pull-up control circuit, a pull-up circuit, a downlink circuit, a pull-down circuit, a pull-down sustain circuit, and a bootstrap capacitor, and N is a positive integer;
  • the pull-down maintaining circuit includes a first pull-down sustain sub-circuit and a second pull-down sustain sub-circuit that work alternately: wherein
  • the first pull-down maintaining sub-circuit includes:
  • a drain of the first thin film transistor is connected to a first clock signal, and a source is connected to the first circuit point;
  • the drain of the second thin film transistor is in communication with the gate, and the drain and the gate are connected to the first clock signal, and the source is connected to the gate of the first thin film transistor;
  • a drain of the third thin film transistor is connected to a source of the second thin film transistor, and a gate is connected to a precharge potential signal, and a source is connected to a DC low voltage signal;
  • a drain of the fourth thin film transistor is connected to the first circuit point, and a gate is connected to the pre-charge point potential signal, and a source is connected to the DC low-voltage signal;
  • a drain of the fifth thin film transistor is connected to a gate output signal, and a gate is connected to the first circuit point, and a source is connected to the first reverse clock signal;
  • a drain of the sixth thin film transistor is connected to the pre-charge point potential signal, and a gate is connected to the first circuit point, and a source is connected to the first reverse clock signal;
  • the potentials of the first reverse clock signal and the first clock signal at respective same times should be relatively set to be different;
  • the second pull-down maintaining sub-circuit includes:
  • a drain of the seventh thin film transistor is connected to the second clock signal, and a source is connected to the second circuit point;
  • the eighth thin film transistor, the drain of the eighth thin film transistor is in communication with the gate, and the drain and the gate are connected to the second clock signal, and the source is connected to the gate of the seventh thin film transistor;
  • a ninth thin film transistor a drain of the ninth thin film transistor is connected to a source of the eighth thin film transistor, and a gate is connected to the precharge point potential signal, and a source is connected to the DC low voltage signal;
  • a drain of the tenth thin film transistor is connected to the second circuit point, and a gate is connected to the precharge point potential signal, and a source is connected to the DC low voltage signal;
  • An eleventh thin film transistor a drain of the eleventh thin film transistor is connected to a gate output signal, and a gate is connected to the second circuit point, and a source is connected to the second reverse clock signal;
  • a drain of the twelfth thin film transistor is connected to the precharge point potential signal, and a gate is connected to the second circuit point, and a source is connected to the second reverse clock signal;
  • the potentials of the second clock signal and the first clock signal at respective same times should be oppositely set to be different, and the second clock signal and the second reverse clock signal are at the same time.
  • the potentials on the top should be set to be different.
  • the first reverse clock signal and the second clock signal have the same frequency and potential.
  • the first reverse clock signal and the second clock signal are from the same signal source.
  • the second reverse clock signal has the same frequency and power as the first clock signal Bit.
  • the second reverse clock signal and the first clock signal are from the same signal source.
  • the potentials of the first clock signal and the second reverse clock signal are both -8V
  • the potentials of the second clock signal and the first reverse clock signal are both 28V or 8V.
  • the pull-up circuit of the Nth-level GOA structural unit includes a thirteenth thin film transistor, the drain of the thirteenth thin film transistor is connected to the Nth-level clock signal, and the gate is connected to the pre-charge potential signal. A source is coupled to the gate output signal.
  • the pull-down circuit of the Nth-level GOA structural unit includes a fourteenth thin film transistor and a fifteenth transistor;
  • the drain of the fourteenth thin film transistor is connected to the gate output signal, and the gate is connected to the gate output signal of the N+1th GOA structural unit, and the source is connected to the DC low voltage signal;
  • a drain of the fifteenth thin film transistor is connected to the precharge potential signal, and a gate is simultaneously connected to a gate output signal of the (N+1)th stage GOA structural unit and a gate of the fourteenth thin film transistor
  • the source is connected to the DC low voltage signal.
  • the source connection of the corresponding thin film transistors T32 and T42 in the pull-down sustaining sub-circuit of each single-stage GOA structural unit is converted into a pressure by a DC low-voltage signal in the GOA circuit.
  • the first reverse clock signal having a smaller effect is applied, and the source connection of the corresponding thin film transistors T33 and T43 on the other pull-down sustain sub-circuit is converted by the DC low-voltage signal into a second reverse clock signal having a smaller pressure effect, so that
  • Each single-stage GOA structural unit can alternately correct the problem of positive deflection of the threshold voltage of the thin film transistor on the corresponding pull-down sustain sub-circuit when the non-operating state is in use, thereby reducing the overall pressure effect of the pull-down maintaining circuit, thereby effectively correcting the single-stage GOA.
  • the threshold voltage of the thin film transistor in the pull-down sustain circuit exhibits a forward deflection problem, thereby improving the reliability and stability of the GOA circuit.
  • FIG. 1 is a circuit diagram of a single-stage GOA structural unit in the prior art
  • FIG. 2 is another circuit diagram of a single-stage GOA structural unit in the prior art
  • FIG. 3 is a circuit diagram of a single-stage GOA structural unit in a GOA circuit according to Embodiment 1 of the present invention.
  • FIG. 4 is an output waveform diagram of signals on a pull-down sustain circuit in the single-stage GOA structural unit of FIG.
  • a GOA circuit including a plurality of cascaded GOA structural units, each of which has a corresponding row of pixels in a display area of the display panel according to the Nth-level GOA structural unit.
  • the unit outputs a line scan signal, which is described in detail in the Nth stage GOA structural unit for convenience of description.
  • the Nth stage GOA structural unit includes a pull-up control circuit 1, a pull-up circuit 2, a downlink circuit 3, a pull-down circuit 4, a pull-down sustain circuit 5, and a bootstrap capacitor 6, and N is a positive integer; ,
  • the pull-down maintaining circuit 5 includes a first pull-down sustain sub-circuit and a second pull-down sustain sub-circuit that operate alternately: wherein
  • the first pull-down maintaining sub-circuit includes:
  • the first thin film transistor T53, the drain of the first thin film transistor T53 is connected to the first clock signal LC1, and the source is connected to the first circuit point P (N);
  • the second thin film transistor T51, the drain of the second thin film transistor T51 is connected to the gate, and the drain and the gate are connected to the first clock signal LC1, and the source is connected to the gate of the first thin film transistor T53;
  • the third thin film transistor T52, the drain of the third thin film transistor T52 is connected to the source of the second thin film transistor T51, and the gate is connected to the precharge potential signal Q(N), and the source is connected to the DC low voltage signal VSS;
  • the fourth thin film transistor T54, the drain of the fourth thin film transistor T54 is connected to the first circuit point P (N), and the gate is connected to the precharge point potential signal Q (N), and the source is connected to the DC low voltage signal VSS;
  • the fifth thin film transistor (T32), the fifth thin film transistor T32 has a drain connected to the gate output signal G(N), and the gate is connected to the first circuit point P(N), and the source is connected to the first reverse clock signal M1;
  • the sixth thin film transistor T42 has a drain connected to the precharge point potential signal Q(N), and the gate is connected to the first circuit point P(N), and the source is connected to the first reverse clock signal M1;
  • the potentials of the first reverse clock signal M1 and the first clock signal LC1 at the same time should be relatively set to be different;
  • the second pull-down maintaining sub-circuit includes:
  • the seventh thin film transistor T63 the seventh thin film transistor T63 has a drain connected to the second clock signal LC2, and the source is connected to the second circuit point K (N);
  • the eighth thin film transistor T61, the eighth thin film transistor T61 has a drain connected to the gate, and the drain and the gate are connected to the second clock signal LC2, and the source is connected to the gate of the seventh thin film transistor T63;
  • the ninth thin film transistor T62, the drain of the ninth thin film transistor T62 is connected to the source of the eighth thin film transistor T61, and the gate is connected to the precharge potential signal Q(N), and the source is connected to the DC low voltage signal VSS;
  • the tenth thin film transistor T64 has a drain connected to the second circuit point K(N), and the gate is connected to the precharge point potential signal Q(N), and the source is connected to the DC low voltage signal VSS;
  • the eleventh thin film transistor T33 has a drain connected to the gate output signal No. G(N), and the gate is connected to the second circuit point K(N), and the source is connected to the second reverse clock signal M2;
  • the twelfth thin film transistor T43, the drain of the twelfth thin film transistor T43 is connected to the precharge potential signal Q(N), and the gate is connected to the second circuit point K(N), and the source is connected to the second reverse clock signal M2. ;
  • the potentials of the second clock signal LC2 and the first clock signal LC1 at the same time should be relatively different, and the potentials of the second clock signal LC2 and the second reverse clock signal M2 at the same time are Should be set to be different.
  • the conventional pull-down maintaining circuit 5 introduces two alternately operating pull-down sustain sub-circuits (ie, the first pull-down sustain sub-circuit and the second pull-down sustain sub-circuit), and adopt the corresponding reversed a clock signal LC1 and a second clock signal LC2 (ie, when the output voltage waveform of the first clock signal LC1 is at the same time, the output voltage waveform of the second clock signal LC1 is a negative potential, and vice versa),
  • the forward deflection problem of the corresponding thin film transistor on the pull-down sustain circuit 5 is reduced, but the forward deflection of the corresponding thin film transistor on the pull-down sustain circuit 5 cannot be reversely corrected, so that the first reverse clock signal is introduced on the pull-down sustain sub-circuit, respectively.
  • the corresponding thin film transistor on the pull-down maintaining circuit 5 is no longer connected with the DC low voltage signal, but is connected to the corresponding reverse clock signal, so that the working pull maintaining sub-circuit continues to remain in operation, and the other pull-up maintaining sub-circuit does not work. It is possible to simultaneously reduce the pressure effect of its corresponding thin film transistor and reversely correct the forward deflection.
  • FIG. 4 it is a waveform output diagram of each signal on the pull-down maintaining circuit 5 in the Nth stage GOA structural unit, and the first clock signal LC1 on the first pull-down maintaining sub-circuit is at a high level in a certain period of time (at this time)
  • the first pull-down maintaining sub-circuit operates, and the second pull-down maintaining sub-circuit does not work), the first reverse clock signal M1 corresponding to the same period is low, and the second clock signal LC2 is also low, the second counter
  • the clock signal M2 is at a high potential (in this case, the forward deflection problem of the second pull-down maintaining sub-circuit is reverse corrected); similarly, the first clock signal LC1 on the first pull-down sustain sub-circuit is low in another period.
  • the first reverse clock signal M1 corresponding to the same period of time is at a high potential (in this case, the forward deflection problem of the first pull-down sustaining sub-circuit is reverse corrected), and the second clock signal LC2 is also high (when the first pull-down sustain sub-circuit is not working, and the second pull-down sustain sub-circuit is operating), the second reverse clock signal M2 is low.
  • the first reverse clock signal M1 and the second clock signal LC2 are set to have the same potential or the same potential at the same frequency (but the potential cannot be different), and the second reverse clock signal M2 and the same A clock signal LC1 can also be set to the same potential or the same frequency at the same frequency (but the potential cannot be different).
  • the first reverse clock signal M1 and the second clock signal LC2 are set to the same potential of the same frequency, and from the same signal source, that is, the first reverse clock signal M1 can directly adopt the second clock signal LC2;
  • the second reverse clock signal M2 and the first clock signal LC1 are also set to the same potential of the same frequency, and the second clock signal LC1 can be directly used from the same signal source, that is, the second reverse clock signal M2.
  • the first clock signal LC1 and the second reverse clock signal M2 have the same potential.
  • the second clock signal LC2 and the first reverse clock signal M1 have the same potential, and -8V is used; or The first clock signal LC1 and the second reverse clock signal M2 have the same potential.
  • -8V the second clock signal LC2 and the first reverse clock signal M1 have the same potential, and 28V or 8V is used.
  • the first reverse clock signal M1 and the second clock signal LC2 are set to different potentials of the same frequency; the second reverse clock signal M2 and the first clock signal LC1 are also set to different potentials of the same frequency.
  • the first clock signal LC1 is 28V or 8V
  • the first reverse clock signal is -5V
  • the second clock signal LC2 is -8V
  • the second reverse clock signal is +10V
  • the first clock signal LC1 When -8V is used, the first reverse clock signal is +5V, the second clock signal LC2 is 28V or 8V, and the second reverse clock signal is -10V.
  • the pull-up circuit 2 of the N-th stage GOA structural unit includes a thirteenth thin film transistor T21, and the drain of the thirteenth thin film transistor T21 is connected to the Nth-level clock signal CK(N), and the gate The precharge potential signal Q(N) is connected, and the source is connected to the gate output signal G(N).
  • the pull-down circuit of the Nth-level GOA structural unit includes a fourteenth thin film transistor T31 and a fifteenth transistor T41;
  • the drain of the fourteenth thin film transistor T31 is connected to the gate output signal G(N), and the gate is connected to the gate output signal G(N+1) of the N+1th GOA structural unit, and the source is connected to the DC low voltage signal VSS. ;
  • the drain of the fifteenth thin film transistor T41 is connected to the precharge potential signal Q(N), and the gate is simultaneously connected to the gate output signal G(N+1) of the N+1th GOA structural unit and the fourteenth thin film transistor
  • the gate of T31 is connected to the DC low voltage signal VSS.
  • the second embodiment of the present invention provides a liquid crystal panel, which includes the GOA circuit of the first embodiment of the present invention, and has the same structure and connection relationship with the GOA circuit of the first embodiment of the present invention.
  • a liquid crystal panel which includes the GOA circuit of the first embodiment of the present invention, and has the same structure and connection relationship with the GOA circuit of the first embodiment of the present invention.
  • the third embodiment of the present invention further provides a display device comprising the liquid crystal panel of the second embodiment of the present invention, which has the same structure and the liquid crystal panel of the second embodiment of the present invention.
  • a display device comprising the liquid crystal panel of the second embodiment of the present invention, which has the same structure and the liquid crystal panel of the second embodiment of the present invention.
  • each single-stage GOA structural unit Converting into a first reverse clock signal with a smaller pressure effect, and converting the source connection of the corresponding thin film transistors T33 and T43 on the other pull-down sustain sub-circuit from a DC low-voltage signal to a second reverse clock having a smaller pressure effect
  • the signal enables each single-stage GOA structural unit to alternately correct the problem of positive deflection of the threshold voltage of the thin film transistor on the corresponding pull-down sustain sub-circuit when the non-operating state is in use, thereby reducing the overall pressure effect of the pull-down maintaining circuit, thereby effectively correcting
  • the threshold voltage of the thin film transistor in the pull-down sustain circuit in the single-stage GOA structural unit exhibits a forward deflection problem, thereby improving the reliability and stability of the GOA circuit.

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Abstract

一种GOA电路，包括多个级联的GOA结构单元，GOA结构单元包括上拉控制电路（1）、上拉电路（2）、下传电路（3）、下拉电路（4）、下拉维持电路（5）和自举电容（6）；下拉维持电路（5）中薄膜晶体管T42和T32的源极连接由直流低压信号（VSS）转变成第一反向时钟信号（M1），薄膜晶体管T43和T33的源极连接由直流低压信号（VSS）转变成第二反向时钟信号（M2），而第一反向时钟信号（M1）与下拉维持电路（5）中第一时钟信号（LC1）在各时刻电位相异，以及第二反向时钟信号（M2）与下拉维持电路（5）中第二时钟信号（LC2）在各时刻电位相异。该电路能够有效纠正单级GOA结构单元中下拉维持电路（5）内薄膜晶体管的阈值电压出现正向偏转问题，提高GOA电路的可靠性和稳定性。

Description

一种GOA电路及液晶面板、显示装置
本申请要求于2017年10月20日提交中国专利局、申请号为201710986238.X、发明名称为“一种GOA电路及液晶面板、显示装置”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种GOA(Gate Driver On Array，阵列基板行驱动)电路及液晶面板、显示装置。
背景技术
液晶显示器具有低辐射、体积小及低耗能等优点，已逐渐在部分应用中取代传统的阴极射线管显示器，因而被广泛地应用于笔记本电脑、个人数字助理PDA、平面电视或移动电话等产品上。传统液晶显示器的方式是利用外部驱动芯片来驱动面板上的芯片以显示图像，但为了减少元件数目并降低制造成本，近年来逐渐发展成将驱动电路结构直接制作于显示面板上，例如采用GOA技术，即将栅极驱动电路集成在玻璃基板上，形成对液晶面板的扫描驱动。
GOA技术相比传统COF(Chip On Flex/Film，覆晶薄膜)技术，不仅可以大幅度节约制造成本，而且省去了Gate侧COF的Bonging制程，对产能提升也是极为有利的。因此，GOA是未来液晶面板发展的重点技术。
如图1所示，现有的GOA电路，通常包括级联的多个单级GOA结构单元，每一级GOA结构单元均对应驱动一级水平扫描线。GOA结构单元的主要结构包括上拉控制电路①，上拉电路②，下传电路③，下拉电路④和 下拉维持电路⑤，以及负责电位抬升的自举电容⑥。其中，上拉控制电路①负责控制上拉电路②的打开时间为预充点电位信号Q(N)实现预充电，一般连接上一级GOA结构单元传递过来的下传信号和栅极输出信号；上拉电路②主要为提高栅极输出信号G(N)电位，控制Gate的打开；下传电路③主要为控制下一级GOA结构单元中信号的打开和关闭；下拉电路④负责在第一时间拉低Q(N)、G(N)点电位至VSS，从而关闭G(N)点信号；下拉维持电路⑤则负责将Q(N)、G(N)点电位维持在VSS不变，即负电位，通常有两个下拉维持模块交替作用；自举电容⑥则负责Q(N)点的二次抬升，这样有利于上拉电路的G(N)输出。
由于下拉维持电路⑤的电子元件实际上是一种反相器，可以采用达灵顿结构反向器，因此图1的单级GOA结构单元可变换成图2的单级GOA结构单元。在图2中，通常情况下会设置两个下拉维持电路⑤交替工作防止薄膜晶体管T32、T42、T33、T43长时间受到PBS(Positive Bias Stress，正偏压应力)而使器件的阈值电压Vth正向偏转严重导致电路失效。
然而，图2中两个下拉维持电路⑤分别采用反相讯号LC1和LC2，即同一时刻上LC1和LC2的电位相异，但是在LC1为高电位时，单级GOA结构单元左侧的下拉维持电路⑤工作，使得薄膜晶体管T42和T32栅极连接电路点P(N)长期处于高电位状态，从而导致薄膜晶体管T42和T32阈值电压Vth出现正向偏转；同样，再待一段时间过后，LC1和LC2电位互换，单级GOA结构单元右侧的下拉维持电路⑤工作，使得薄膜晶体管T43和T33栅极连接电路点K(N)长期处于高电位状态，从而导致薄膜晶体管T43和T33阈值电压Vth出现正向偏转。以此重复，则随着单级GOA结构单元使用时间的增长，则薄膜晶体管T32、T42、T33、T43的阈值电压Vth正向 偏转越来越严重，从而导致整个GOA电路失效。
发明内容
本发明实施例所要解决的技术问题在于，提供一种GOA电路及液晶面板、显示装置，能够有效纠正单级GOA结构单元中下拉维持电路内薄膜晶体管的阈值电压出现正向偏转问题，从而提高GOA电路的可靠性和稳定性。
为了解决上述技术问题，本发明实施例提供了一种GOA电路，包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括上拉控制电路、上拉电路、下传电路、下拉电路、下拉维持电路和自举电容，且N为正整数；其中，
所述下拉维持电路包括交替工作的第一下拉维持子电路和第二下拉维持子电路：其中，
所述第一下拉维持子电路包括：
第一薄膜晶体管，所述第一薄膜晶体管的漏极连接第一时钟信号，且源极连接第一电路点；
第二薄膜晶体管，所述第二薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第一时钟信号，源极连接所述第一薄膜晶体管的栅极；
第三薄膜晶体管，所述第三薄膜晶体管的漏极连接所述第二薄膜晶体管的源极，且栅极连接预充点电位信号，源极连接直流低压信号；
第四薄膜晶体管，所述第四薄膜晶体管的漏极连接所述第一电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第五薄膜晶体管，所述第五薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第一电路点，源极连接第一反向时钟信号；
第六薄膜晶体管，所述第六薄膜晶体管的漏极连接所述预充点电位信 号，且栅极连接所述第一电路点，源极连接所述第一反向时钟信号；
其中，所述第一反向时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异；
所述第二下拉维持子电路包括：
第七薄膜晶体管，所述第七薄膜晶体管的漏极连接第二时钟信号，且源极连接第二电路点；
第八薄膜晶体管，所述第八薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第二时钟信号，源极连接所述第七薄膜晶体管的栅极；
第九薄膜晶体管，所述第九薄膜晶体管的漏极连接所述第八薄膜晶体管的源极，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第十薄膜晶体管，所述第十薄膜晶体管的漏极连接所述第二电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第十一薄膜晶体管，所述第十一薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第二电路点，源极连接第二反向时钟信号；
第十二薄膜晶体管，所述第十二薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第二电路点，源极连接所述第二反向时钟信号；
其中，所述第二时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异，且所述第二时钟信号与所述第二反向时钟信号在各个相同时刻上的电位均应相对设置为相异。
其中，所述第一反向时钟信号与所述第二时钟信号具有相同的频率及电位。
其中，所述第一反向时钟信号与所述第二时钟信号来自同一信号源。
其中，所述第二反向时钟信号与所述第一时钟信号具有相同的频率及电位。
其中，所述第二反向时钟信号与所述第一时钟信号来自同一信号源。
其中，当所述第一时钟信号与所述第二反向时钟信号的电位均为28V或 8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为-8V；或
当所述第一时钟信号与所述第二反向时钟信号的电位均为-8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为28V或8V。
其中，所述第N级GOA结构单元的上拉电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的漏极连接第N级时钟信号，且栅极连接所述预充点电位信号，源极连接所述栅极输出信号。
其中，所述第N级GOA结构单元的下拉电路包括第十四薄膜晶体管和第十五晶体管；其中，
所述第十四薄膜晶体管的漏极连接所述栅极输出信号，且栅极连接第N+1级GOA结构单元的栅极输出信号，源极连接所述直流低压信号；
所述第十五薄膜晶体管的漏极连接所述预充点电位信号，且栅极同时连接所述第N+1级GOA结构单元的栅极输出信号及所述第十四薄膜晶体管的栅极，源极连接所述直流低压信号。
相应的，本发明实施例还提供了一种液晶面板，其中，包括GOA电路；
所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括上拉控制电路、上拉电路、下传电路、下拉电路、下拉维持电路和自举电容，且N为正整数；其中，
所述下拉维持电路包括交替工作的第一下拉维持子电路和第二下拉维持子电路：其中，
所述第一下拉维持子电路包括：
第一薄膜晶体管，所述第一薄膜晶体管的漏极连接第一时钟信号，且源极连接第一电路点；
第二薄膜晶体管，所述第二薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第一时钟信号，源极连接所述第一薄膜晶体管的栅极；
第三薄膜晶体管，所述第三薄膜晶体管的漏极连接所述第二薄膜晶体管的源极，且栅极连接预充点电位信号，源极连接直流低压信号；
第四薄膜晶体管，所述第四薄膜晶体管的漏极连接所述第一电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第五薄膜晶体管，所述第五薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第一电路点，源极连接第一反向时钟信号；
第六薄膜晶体管，所述第六薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第一电路点，源极连接所述第一反向时钟信号；
其中，所述第一反向时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异；
所述第二下拉维持子电路包括：
第七薄膜晶体管，所述第七薄膜晶体管的漏极连接第二时钟信号，且源极连接第二电路点；
第八薄膜晶体管，所述第八薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第二时钟信号，源极连接所述第七薄膜晶体管的栅极；
第九薄膜晶体管，所述第九薄膜晶体管的漏极连接所述第八薄膜晶体管的源极，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第十薄膜晶体管，所述第十薄膜晶体管的漏极连接所述第二电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第十一薄膜晶体管，所述第十一薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第二电路点，源极连接第二反向时钟信号；
第十二薄膜晶体管，所述第十二薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第二电路点，源极连接所述第二反向时钟信号；
其中，所述第二时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异，且所述第二时钟信号与所述第二反向时钟信号在各个相同时刻上的电位均应相对设置为相异。
其中，所述第一反向时钟信号与所述第二时钟信号具有相同的频率及电位，所述第一反向时钟信号与所述第二时钟信号来自同一信号源。
其中，所述第二反向时钟信号与所述第一时钟信号具有相同的频率及电位，所述第二反向时钟信号与所述第一时钟信号来自同一信号源。
其中，当所述第一时钟信号与所述第二反向时钟信号的电位均为28V或8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为-8V；或
当所述第一时钟信号与所述第二反向时钟信号的电位均为-8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为28V或8V。
相应的，本发明实施例还提供了一种显示装置，其中，包括液晶面板，且所述液晶面板包括GOA电路；其中，
所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括上拉控制电路、上拉电路、下传电路、下拉电路、下拉维持电路和自举电容，且N为正整数；其中，
所述下拉维持电路包括交替工作的第一下拉维持子电路和第二下拉维持子电路：其中，
所述第一下拉维持子电路包括：
第一薄膜晶体管，所述第一薄膜晶体管的漏极连接第一时钟信号，且源极连接第一电路点；
第二薄膜晶体管，所述第二薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第一时钟信号，源极连接所述第一薄膜晶体管的栅极；
第三薄膜晶体管，所述第三薄膜晶体管的漏极连接所述第二薄膜晶体管的源极，且栅极连接预充点电位信号，源极连接直流低压信号；
第四薄膜晶体管，所述第四薄膜晶体管的漏极连接所述第一电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第五薄膜晶体管，所述第五薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第一电路点，源极连接第一反向时钟信号；
第六薄膜晶体管，所述第六薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第一电路点，源极连接所述第一反向时钟信号；
其中，所述第一反向时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异；
所述第二下拉维持子电路包括：
第七薄膜晶体管，所述第七薄膜晶体管的漏极连接第二时钟信号，且源极连接第二电路点；
第八薄膜晶体管，所述第八薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第二时钟信号，源极连接所述第七薄膜晶体管的栅极；
第九薄膜晶体管，所述第九薄膜晶体管的漏极连接所述第八薄膜晶体管的源极，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第十薄膜晶体管，所述第十薄膜晶体管的漏极连接所述第二电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
第十一薄膜晶体管，所述第十一薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第二电路点，源极连接第二反向时钟信号；
第十二薄膜晶体管，所述第十二薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第二电路点，源极连接所述第二反向时钟信号；
其中，所述第二时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异，且所述第二时钟信号与所述第二反向时钟信号在各个相同时刻上的电位均应相对设置为相异。
其中，所述第一反向时钟信号与所述第二时钟信号具有相同的频率及电位。
其中，所述第一反向时钟信号与所述第二时钟信号来自同一信号源。
其中，所述第二反向时钟信号与所述第一时钟信号具有相同的频率及电 位。
其中，所述第二反向时钟信号与所述第一时钟信号来自同一信号源。
其中，当所述第一时钟信号与所述第二反向时钟信号的电位均为28V或8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为-8V；或
当所述第一时钟信号与所述第二反向时钟信号的电位均为-8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为28V或8V。
其中，所述第N级GOA结构单元的上拉电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的漏极连接第N级时钟信号，且栅极连接所述预充点电位信号，源极连接所述栅极输出信号。
其中，所述第N级GOA结构单元的下拉电路包括第十四薄膜晶体管和第十五晶体管；其中，
所述第十四薄膜晶体管的漏极连接所述栅极输出信号，且栅极连接第N+1级GOA结构单元的栅极输出信号，源极连接所述直流低压信号；
所述第十五薄膜晶体管的漏极连接所述预充点电位信号，且栅极同时连接所述第N+1级GOA结构单元的栅极输出信号及所述第十四薄膜晶体管的栅极，源极连接所述直流低压信号。
实施本发明实施例，具有如下有益效果：
在本发明实施例中，通过在GOA电路中，将每一个单级GOA结构单元的下拉维持电路中一下拉维持子电路上所对应薄膜晶体管T32和T42的源极连接由直流低压信号转换成压力效应更小的第一反向时钟信号，并将另一下拉维持子电路上所对应薄膜晶体管T33和T43的源极连接由直流低压信号转换成压力效应更小的第二反向时钟信号，使得每一个单级GOA结构单元能够交替纠正不工作状态时所对应下拉维持子电路上薄膜晶体管的阈值电压出现正向偏转的问题，减少了下拉维持电路的整体压力效应，因此能够有效纠正单级GOA结构单元中下拉维持电路内薄膜晶体管的阈值电压出现正向偏转问题，从而提高GOA电路的可靠性和稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，根据这些附图获得其他的附图仍属于本发明的范畴。
图1为现有技术中单级GOA结构单元的一电路图；
图2为现有技术中单级GOA结构单元的另一电路图；
图3为本发明实施例一提供的GOA电路中单级GOA结构单元的电路图；
图4为图3中单级GOA结构单元中下拉维持电路上各信号的输出波形图。
具体实施方式
下面参考附图对本发明的优选实施例进行描述。
在本发明实施例一中，提供一种GOA电路，包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号，为了叙述方便，以第N级GOA结构单元进行详细说明。
如图3所示，第N级GOA结构单元包括上拉控制电路1、上拉电路2、下传电路3、下拉电路4、下拉维持电路5和自举电容6，且N为正整数；其中，
下拉维持电路5包括交替工作的第一下拉维持子电路和第二下拉维持子电路：其中，
该第一下拉维持子电路包括：
第一薄膜晶体管T53，第一薄膜晶体管T53的漏极连接第一时钟信号LC1，且源极连接第一电路点P(N)；
第二薄膜晶体管T51，第二薄膜晶体管T51的漏极与栅极相连通，且漏极和栅极均连接第一时钟信号LC1，源极连接第一薄膜晶体管T53的栅极；
第三薄膜晶体管T52，第三薄膜晶体管T52的漏极连接第二薄膜晶体管T51的源极，且栅极连接预充点电位信号Q(N)，源极连接直流低压信号VSS；
第四薄膜晶体管T54，第四薄膜晶体管T54的漏极连接第一电路点P(N)，且栅极连接预充点电位信号Q(N)，源极连接直流低压信号VSS；
第五薄膜晶体管(T32)，第五薄膜晶体管T32的漏极连接栅极输出信号G(N)，且栅极连接第一电路点P(N)，源极连接第一反向时钟信号M1；
第六薄膜晶体管T42，第六薄膜晶体管T42的漏极连接预充点电位信号Q(N)，且栅极连接第一电路点P(N)，源极连接第一反向时钟信号M1；
其中，第一反向时钟信号M1与第一时钟信号LC1在各个相同时刻上的电位均应相对设置为相异；
第二下拉维持子电路包括：
第七薄膜晶体管T63，第七薄膜晶体管T63的漏极连接第二时钟信号LC2，且源极连接第二电路点K(N)；
第八薄膜晶体管T61，第八薄膜晶体管T61的漏极与栅极相连通，且漏极和栅极均连接第二时钟信号LC2，源极连接第七薄膜晶体管T63的栅极；
第九薄膜晶体管T62，第九薄膜晶体管T62的漏极连接第八薄膜晶体管T61的源极，且栅极连接预充点电位信号Q(N)，源极连接直流低压信号VSS；
第十薄膜晶体管T64，第十薄膜晶体管T64的漏极连接第二电路点K(N)，且栅极连接预充点电位信号Q(N)，源极连接直流低压信号VSS；
第十一薄膜晶体管T33，第十一薄膜晶体管T33的漏极连接栅极输出信 号G(N)，且栅极连接第二电路点K(N)，源极连接第二反向时钟信号M2；
第十二薄膜晶体管T43，第十二薄膜晶体管T43的漏极连接预充点电位信号Q(N)，且栅极连接第二电路点K(N)，源极连接第二反向时钟信号M2；
其中，第二时钟信号LC2与第一时钟信号LC1在各个相同时刻上的电位均应相对设置为相异，且第二时钟信号LC2与第二反向时钟信号M2在各个相同时刻上的电位均应相对设置为相异。
在本发明实施例一中，虽然传统的下拉维持电路5引入两个交替工作的下拉维持子电路(即第一下拉维持子电路和第二下拉维持子电路)，并采用相应反向的第一时钟信号LC1与第二时钟信号LC2(即在同一时刻上第一时钟信号LC1的输出电压波形为电位时，则第二时钟信号LC1的输出电压波形为负电位，反之亦然)，用来降低下拉维持电路5上对应薄膜晶体管的正向偏转问题，但是却无法反向纠正下拉维持电路5上对应薄膜晶体管的正向偏转，因此通过分别在下拉维持子电路上引入第一反向时钟信号M1和第二反向时钟信号M2来进行反向纠正。此时，下拉维持电路5上对应薄膜晶体管不再连接直流低压信号，而是连接相应的反向时钟信号，使得工作的拉维持子电路继续保持工作状态，而不工作的另一拉维持子电路能够同时减少其对应薄膜晶体管的压力效应，反向纠正正向偏转。
如图4所示，为第N级GOA结构单元中下拉维持电路5上各信号的波形输出图，某一时段上第一下拉维持子电路上第一时钟信号LC1为高电位时(此时第一下拉维持子电路工作，而第二下拉维持子电路不工作)，对应同一时段上的第一反向时钟信号M1为低电位，而第二时钟信号LC2也为低电位，第二反向时钟信号M2为高电位(此时对第二下拉维持子电路的正向偏转问题就行反向纠正)；同理，另一时段上第一下拉维持子电路上第一时钟信号LC1为低电位时，对应同一时段上的第一反向时钟信号M1为高电位(此时对第一下拉维持子电路的正向偏转问题就行反向纠正)，而第二时钟信号 LC2也为高电位(此时第一下拉维持子电路不工作，而第二下拉维持子电路工作)，第二反向时钟信号M2为低电位。
在本发明实施例一中，第一反向时钟信号M1与第二时钟信号LC2设置成同频率同电位或同频率不同电位(但电位不能相异)，同样第二反向时钟信号M2与第一时钟信号LC1也可以设置成同频率同电位或同频率不同电位(但电位不能相异)。
若GOA电路空间有限，则第一反向时钟信号M1与第二时钟信号LC2设置成同频率同电位，且来自同一信号源，即第一反向时钟信号M1可以直接采用第二时钟信号LC2；第二反向时钟信号M2与第一时钟信号LC1也设置成同频率同电位，且来自同一信号源，即第二反向时钟信号M2可以直接采用第一时钟信号LC1。作为一个例子，第一时钟信号LC1与第二反向时钟信号M2的电位相同，采用28V或8V时，则第二时钟信号LC2与第一反向时钟信号M1的电位相同，采用-8V；或者第一时钟信号LC1与第二反向时钟信号M2的电位相同，采用-8V时，则第二时钟信号LC2与第一反向时钟信号M1的电位相同，采用28V或8V。
若GOA电路空间够大，则第一反向时钟信号M1与第二时钟信号LC2设置成同频率不同电位；第二反向时钟信号M2与第一时钟信号LC1也设置成同频率不同电位。作为一个例子，第一时钟信号LC1采用28V或8V时，第一反向时钟信号采用-5V，第二时钟信号LC2采用-8V，第二反向时钟信号采用+10V；或者第一时钟信号LC1采用-8V时，则第一反向时钟信号采用+5V，第二时钟信号LC2采用28V或8V，第二反向时钟信号采用-10V。
在本发明实施例一中，第N级GOA结构单元的上拉电路2包括第十三薄膜晶体管T21，第十三薄膜晶体管T21的漏极连接第N级时钟信号CK(N)，且栅极连接预充点电位信号Q(N)，源极连接栅极输出信号G(N)。
在本发明实施例一中，第N级GOA结构单元的下拉电路包括第十四薄膜晶体管T31和第十五晶体管T41；其中，
第十四薄膜晶体管T31的漏极连接栅极输出信号G(N)，且栅极连接第N+1级GOA结构单元的栅极输出信号G(N+1)，源极连接直流低压信号VSS；
第十五薄膜晶体管T41的漏极连接预充点电位信号Q(N)，且栅极同时连接第N+1级GOA结构单元的栅极输出信号G(N+1)及第十四薄膜晶体管T31的栅极，源极连接直流低压信号VSS。
相应于本发明实施例一的GOA电路，本发明实施例二提供了一种液晶面板，包括本发明实施例一的GOA电路，与本发明实施例一的GOA电路具有相同的结构和连接关系，具体请参见本发明实施例一中的相关内容，在此不再一一赘述。
相应于本发明实施例二的液晶面板，本发明实施例三又提供了一种显示装置，包括本发明实施例二中的液晶面板，与本发明实施例二中的液晶面板具有相同的结构和连接关系，具体请参见本发明实施例二中的相关内容，在此不再一一赘述。
综上，在本发明实施例中，通过在GOA电路中，将每一个单级GOA结构单元的下拉维持电路中一下拉维持子电路上所对应薄膜晶体管T32和T42的源极连接由直流低压信号转换成压力效应更小的第一反向时钟信号，并将另一下拉维持子电路上所对应薄膜晶体管T33和T43的源极连接由直流低压信号转换成压力效应更小的第二反向时钟信号，使得每一个单级GOA结构单元能够交替纠正不工作状态时所对应下拉维持子电路上薄膜晶体管的阈值电压出现正向偏转的问题，减少了下拉维持电路的整体压力效应，因此能够有效纠正单级GOA结构单元中下拉维持电路内薄膜晶体管的阈值电压出现正向偏转问题，从而提高GOA电路的可靠性和稳定性。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (20)

  1. 一种GOA电路，其中，包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括上拉控制电路、上拉电路、下传电路、下拉电路、下拉维持电路和自举电容，且N为正整数；其中，
    所述下拉维持电路包括交替工作的第一下拉维持子电路和第二下拉维持子电路：其中，
    所述第一下拉维持子电路包括：
    第一薄膜晶体管，所述第一薄膜晶体管的漏极连接第一时钟信号，且源极连接第一电路点；
    第二薄膜晶体管，所述第二薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第一时钟信号，源极连接所述第一薄膜晶体管的栅极；
    第三薄膜晶体管，所述第三薄膜晶体管的漏极连接所述第二薄膜晶体管的源极，且栅极连接预充点电位信号，源极连接直流低压信号；
    第四薄膜晶体管，所述第四薄膜晶体管的漏极连接所述第一电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第五薄膜晶体管，所述第五薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第一电路点，源极连接第一反向时钟信号；
    第六薄膜晶体管，所述第六薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第一电路点，源极连接所述第一反向时钟信号；
    其中，所述第一反向时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异；
    所述第二下拉维持子电路包括：
    第七薄膜晶体管，所述第七薄膜晶体管的漏极连接第二时钟信号，且源 极连接第二电路点；
    第八薄膜晶体管，所述第八薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第二时钟信号，源极连接所述第七薄膜晶体管的栅极；
    第九薄膜晶体管，所述第九薄膜晶体管的漏极连接所述第八薄膜晶体管的源极，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第十薄膜晶体管，所述第十薄膜晶体管的漏极连接所述第二电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第十一薄膜晶体管，所述第十一薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第二电路点，源极连接第二反向时钟信号；
    第十二薄膜晶体管，所述第十二薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第二电路点，源极连接所述第二反向时钟信号；
    其中，所述第二时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异，且所述第二时钟信号与所述第二反向时钟信号在各个相同时刻上的电位均应相对设置为相异。
  2. 如权利要求1所述的GOA电路，其中，所述第一反向时钟信号与所述第二时钟信号具有相同的频率及电位。
  3. 如权利要求2所述的GOA电路，其中，所述第一反向时钟信号与所述第二时钟信号来自同一信号源。
  4. 如权利要求3所述的GOA电路，其中，所述第二反向时钟信号与所述第一时钟信号具有相同的频率及电位。
  5. 如权利要求4所述的GOA电路，其中，所述第二反向时钟信号与所述第一时钟信号来自同一信号源。
  6. 如权利要求5所述的GOA电路，其中，当所述第一时钟信号与所述第二反向时钟信号的电位均为28V或8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为-8V；或
    当所述第一时钟信号与所述第二反向时钟信号的电位均为-8V时，则所 述第二时钟信号与所述第一反向时钟信号的电位均为28V或8V。
  7. 如权利要求6所述的GOA电路，其中，所述第N级GOA结构单元的上拉电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的漏极连接第N级时钟信号，且栅极连接所述预充点电位信号，源极连接所述栅极输出信号。
  8. 如权利要求7所述的GOA电路，其中，所述第N级GOA结构单元的下拉电路包括第十四薄膜晶体管和第十五晶体管；其中，
    所述第十四薄膜晶体管的漏极连接所述栅极输出信号，且栅极连接第N+1级GOA结构单元的栅极输出信号，源极连接所述直流低压信号；
    所述第十五薄膜晶体管的漏极连接所述预充点电位信号，且栅极同时连接所述第N+1级GOA结构单元的栅极输出信号及所述第十四薄膜晶体管的栅极，源极连接所述直流低压信号。
  9. 一种液晶面板，其中，包括GOA电路；其中，
    所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括上拉控制电路、上拉电路、下传电路、下拉电路、下拉维持电路和自举电容，且N为正整数；其中，
    所述下拉维持电路包括交替工作的第一下拉维持子电路和第二下拉维持子电路：其中，
    所述第一下拉维持子电路包括：
    第一薄膜晶体管，所述第一薄膜晶体管的漏极连接第一时钟信号，且源极连接第一电路点；
    第二薄膜晶体管，所述第二薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第一时钟信号，源极连接所述第一薄膜晶体管的栅极；
    第三薄膜晶体管，所述第三薄膜晶体管的漏极连接所述第二薄膜晶体管的源极，且栅极连接预充点电位信号，源极连接直流低压信号；
    第四薄膜晶体管，所述第四薄膜晶体管的漏极连接所述第一电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第五薄膜晶体管，所述第五薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第一电路点，源极连接第一反向时钟信号；
    第六薄膜晶体管，所述第六薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第一电路点，源极连接所述第一反向时钟信号；
    其中，所述第一反向时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异；
    所述第二下拉维持子电路包括：
    第七薄膜晶体管，所述第七薄膜晶体管的漏极连接第二时钟信号，且源极连接第二电路点；
    第八薄膜晶体管，所述第八薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第二时钟信号，源极连接所述第七薄膜晶体管的栅极；
    第九薄膜晶体管，所述第九薄膜晶体管的漏极连接所述第八薄膜晶体管的源极，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第十薄膜晶体管，所述第十薄膜晶体管的漏极连接所述第二电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第十一薄膜晶体管，所述第十一薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第二电路点，源极连接第二反向时钟信号；
    第十二薄膜晶体管，所述第十二薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第二电路点，源极连接所述第二反向时钟信号；
    其中，所述第二时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异，且所述第二时钟信号与所述第二反向时钟信号在各个相同时刻上的电位均应相对设置为相异。
  10. 如权利要求9所述的液晶面板，其中，所述第一反向时钟信号与所述第二时钟信号具有相同的频率及电位，所述第一反向时钟信号与所述第二 时钟信号来自同一信号源。
  11. 如权利要求10所述的液晶面板，其中，所述第二反向时钟信号与所述第一时钟信号具有相同的频率及电位，所述第二反向时钟信号与所述第一时钟信号来自同一信号源。
  12. 如权利要求11所述的GOA电路，其中，当所述第一时钟信号与所述第二反向时钟信号的电位均为28V或8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为-8V；或
    当所述第一时钟信号与所述第二反向时钟信号的电位均为-8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为28V或8V。
  13. 一种显示装置，其中，包括液晶面板，且所述液晶面板包括GOA电路；其中，
    所述GOA电路包括多个级联的GOA结构单元，每一个单级GOA结构单元均依照第N级GOA结构单元向显示面板的显示区域内相应的一行像素单元输出行扫描信号；所述第N级GOA结构单元包括上拉控制电路、上拉电路、下传电路、下拉电路、下拉维持电路和自举电容，且N为正整数；其中，
    所述下拉维持电路包括交替工作的第一下拉维持子电路和第二下拉维持子电路：其中，
    所述第一下拉维持子电路包括：
    第一薄膜晶体管，所述第一薄膜晶体管的漏极连接第一时钟信号，且源极连接第一电路点；
    第二薄膜晶体管，所述第二薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第一时钟信号，源极连接所述第一薄膜晶体管的栅极；
    第三薄膜晶体管，所述第三薄膜晶体管的漏极连接所述第二薄膜晶体管的源极，且栅极连接预充点电位信号，源极连接直流低压信号；
    第四薄膜晶体管，所述第四薄膜晶体管的漏极连接所述第一电路点，且 栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第五薄膜晶体管，所述第五薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第一电路点，源极连接第一反向时钟信号；
    第六薄膜晶体管，所述第六薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第一电路点，源极连接所述第一反向时钟信号；
    其中，所述第一反向时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异；
    所述第二下拉维持子电路包括：
    第七薄膜晶体管，所述第七薄膜晶体管的漏极连接第二时钟信号，且源极连接第二电路点；
    第八薄膜晶体管，所述第八薄膜晶体管的漏极与栅极相连通，且漏极和栅极均连接所述第二时钟信号，源极连接所述第七薄膜晶体管的栅极；
    第九薄膜晶体管，所述第九薄膜晶体管的漏极连接所述第八薄膜晶体管的源极，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第十薄膜晶体管，所述第十薄膜晶体管的漏极连接所述第二电路点，且栅极连接所述预充点电位信号，源极连接所述直流低压信号；
    第十一薄膜晶体管，所述第十一薄膜晶体管的漏极连接栅极输出信号，且栅极连接所述第二电路点，源极连接第二反向时钟信号；
    第十二薄膜晶体管，所述第十二薄膜晶体管的漏极连接所述预充点电位信号，且栅极连接所述第二电路点，源极连接所述第二反向时钟信号；
    其中，所述第二时钟信号与所述第一时钟信号在各个相同时刻上的电位均应相对设置为相异，且所述第二时钟信号与所述第二反向时钟信号在各个相同时刻上的电位均应相对设置为相异。
  14. 如权利要求13所述的显示装置，其中，所述第一反向时钟信号与所述第二时钟信号具有相同的频率及电位。
  15. 如权利要求14所述的显示装置，其中，所述第一反向时钟信号与 所述第二时钟信号来自同一信号源。
  16. 如权利要求15所述的显示装置，其中，所述第二反向时钟信号与所述第一时钟信号具有相同的频率及电位。
  17. 如权利要求16所述的显示装置，其中，所述第二反向时钟信号与所述第一时钟信号来自同一信号源。
  18. 如权利要求17所述的显示装置，其中，当所述第一时钟信号与所述第二反向时钟信号的电位均为28V或8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为-8V；或
    当所述第一时钟信号与所述第二反向时钟信号的电位均为-8V时，则所述第二时钟信号与所述第一反向时钟信号的电位均为28V或8V。
  19. 如权利要求18所述的显示装置，其中，所述第N级GOA结构单元的上拉电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的漏极连接第N级时钟信号，且栅极连接所述预充点电位信号，源极连接所述栅极输出信号。
  20. 如权利要求19所述的显示装置，其中，所述第N级GOA结构单元的下拉电路包括第十四薄膜晶体管和第十五晶体管；其中，
    所述第十四薄膜晶体管的漏极连接所述栅极输出信号，且栅极连接第N+1级GOA结构单元的栅极输出信号，源极连接所述直流低压信号；
    所述第十五薄膜晶体管的漏极连接所述预充点电位信号，且栅极同时连接所述第N+1级GOA结构单元的栅极输出信号及所述第十四薄膜晶体管的栅极，源极连接所述直流低压信号。
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US10810923B2 (en) 2018-07-18 2020-10-20 Shenzhen China Star Optoelectronics Technology Co., Ltd. GOA circuit and display panel and display device including the same
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