WO2021203472A1 - Goa 电路和显示面板 - Google Patents

Goa 电路和显示面板 Download PDF

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Publication number
WO2021203472A1
WO2021203472A1 PCT/CN2020/085804 CN2020085804W WO2021203472A1 WO 2021203472 A1 WO2021203472 A1 WO 2021203472A1 CN 2020085804 W CN2020085804 W CN 2020085804W WO 2021203472 A1 WO2021203472 A1 WO 2021203472A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
node
pull
reverse
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Application number
PCT/CN2020/085804
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English (en)
French (fr)
Inventor
徐志达
姚晓慧
金一坤
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/960,601 priority Critical patent/US20210319763A1/en
Publication of WO2021203472A1 publication Critical patent/WO2021203472A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of display technology, and in particular to a GOA circuit and a display panel.
  • the structure of the existing 8K product is shown in Figure 1, including m cascaded GOA modules.
  • the n-th GOA module includes a pull-up control module 101, a pull-up module 102, a signal download module 103, and a first pull-down module.
  • the pull-up control module 101 includes a transistor T11
  • the pull-up module 102 includes a transistor T21
  • the signal download module 103 includes a transistor T22
  • the first pull-down module 104 includes a transistor T31
  • the second pull-down module 105 includes a transistor T41.
  • the pull-down sustaining module 106 includes transistors T51, T52, T53, T54, T32, and T42.
  • the second pull-down sustaining module 107 includes transistors T61, T62, T63, T64, T33, and T43.
  • the connection mode of each transistor is shown in the figure.
  • CK is a clock signal
  • ST(n-6), G(n+6), and G(n+8) are all input signals
  • G(n) and ST(n) are all output signals.
  • Both VSSQ and VSSG are power low-level signals.
  • the first pull-down sustaining module 106 and the second pull-down sustaining module 107 have exactly the same structure, and both are composed of an inverter and two transistors.
  • the first pull-down sustaining module 106 When driving, the first pull-down sustaining module 106 inputs a low-frequency clock signal input terminal. Is LC1, the input signal of the low-frequency clock signal input terminal of the second pull-down sustaining module 107 is LC2, and LC1 and LC2 are a set of low-frequency clock signals with a phase difference of 1/2 period to drive the first pull-down sustaining module 106 and the second pull-down
  • the sustaining module 107 works alternately. Therefore, when the first pull-down sustaining module 106 or the second pull-down sustaining module 107 is working, the signal input from the corresponding low-frequency clock signal input terminal is high.
  • FIG. 2 is a schematic diagram of the structure of the first pull-down sustaining module 106, including an inverter 10 and transistors T32 and T42.
  • the inverter 10 is composed of 4 transistors. Its working principle is: when the potential at point Q(n) is When the potential is low, T52 and T54 are closed, T51 is opened, so that the potential of point A is high, and then T53 is opened, and the potential of point P(n) is high; when the potential of point Q(n) is high, T52 and T54 Turn on, VSSQ inputs a low potential to point A, T51 turns on, and a high potential to point A. The two work together to make the potential of point A low, and T53 cannot be turned on normally, so point P(n) is low.
  • the inverter 10 always reverses the potentials of the Q(n) point and the P(n) point.
  • the space for the GOA circuit is relatively tight.
  • both inverters require 4 transistors. Realizing that the potentials of Q(n) point and P(n) point are opposite, the GOA circuit takes up too much space and cannot meet the requirements of 8K products.
  • the existing GOA circuit has the technical problem of occupying too much space and needs to be improved.
  • the embodiments of the present application provide a GOA circuit and a display panel to alleviate the technical problem that the existing GOA circuit occupies too much space.
  • the embodiment of the present application provides a GOA circuit, including m cascaded GOA units, wherein the nth level GOA unit includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node according to the previous stage transmission signal
  • a pull-up module connected to the first node, and configured to pull up the potential of the gate drive signal of the current level according to the clock signal of the current level;
  • the signal download module is connected to the first node, and is used to control the output of the transmission signal of the current level according to the clock signal of the current level;
  • the first pull-down module is used to pull down the potential of the gate drive signal of the current stage according to the first subsequent stage gate drive signal
  • a second pull-down module connected to the first node, and configured to pull down the potential of the first node according to a second rear-stage gate drive signal
  • a first pull-down maintenance module connected to the first node, and configured to maintain the low potential of the first node and the gate drive signal of the current stage according to the first low-frequency clock signal;
  • the second pull-down maintenance module connected to the first node, is used to maintain the low potentials of the first node and the gate drive signal of the current stage according to the second low-frequency clock signal, the first low-frequency clock signal and The second low-frequency clock signal has an opposite potential at the same time;
  • the first pull-down maintaining module and the second pull-down maintaining module both include an inverting unit and a maintaining unit, the output terminal of the inverting unit is connected to the input terminal of the maintaining unit, and at least one of the inverters is
  • the reverse unit is a first reverse unit;
  • the first reverse unit includes a first reverse transistor, a second reverse transistor, and a third reverse transistor, and the gate of the first reverse transistor is connected to the first electrode Low-frequency clock signal input terminal, the second electrode of the first reverse transistor and the first electrode of the second reverse transistor are connected to a second node, and the gate of the second reverse transistor is connected to the first node ,
  • the second electrode of the second reverse transistor is connected to the first power supply low potential signal, the gate and the first electrode of the third reverse transistor are connected to the second node, and the second electrode of the third reverse transistor is connected to the second node.
  • the two electrodes are connected to the input end of the sustain unit.
  • the inverting units in the first pull-down sustaining module and the second pull-down sustaining module are both first inverting units.
  • one of the inverting unit of the first pull-down sustaining module and the second pull-down sustaining module is a first inverting unit
  • the other inverting unit is a second inverting unit
  • the second inversion unit includes a fourth inversion transistor, a fifth inversion transistor, a sixth inversion transistor, and a seventh inversion transistor, and the gate and the first electrode of the fourth inversion transistor are connected to a low-frequency clock signal
  • the second electrode of the fourth reverse transistor and the first electrode of the fifth reverse transistor are connected to the third node
  • the gate of the fifth reverse transistor is connected to the first node
  • the The second electrode of the fifth reverse transistor is connected to the first power supply low potential signal
  • the gate of the sixth reverse transistor is connected to the third node
  • the first electrode of the sixth reverse transistor is connected to the fourth
  • the first electrode of the reverse transistor, the second electrode of the sixth reverse transistor and the first electrode of the seventh reverse transistor are connected to the input terminal of the sustain unit, and the gate of the seventh
  • the sustain unit includes a first sustain transistor and a second sustain transistor, and the gate of the first sustain transistor and the gate of the second sustain transistor are connected to the input terminal of the sustain unit ,
  • the first electrode of the first sustain transistor is connected to the first power supply low potential signal
  • the second electrode of the first sustain transistor is connected to the first node
  • the first electrode of the second sustain transistor is connected to the first node.
  • Two power supply low-potential signals, and the second electrode of the second sustain transistor is connected to the gate drive signal of the current stage.
  • the pull-up control module includes a first transistor, the gate and the first electrode of the first transistor are connected to the previous stage signal transmission, and the second electrode is connected to the first node.
  • the pull-up module includes a second transistor, the gate of the second transistor is connected to the first node, the first electrode is connected to the clock signal of the current stage, and the second electrode is connected to the This level of gate drive signal.
  • the signal download module includes a third transistor, the gate of the third transistor is connected to the first node, the first electrode is connected to the clock signal of the current stage, and the second electrode is connected to the Describe the transmission signal at this level.
  • the first pull-down module includes a fourth transistor, the gate of the fourth transistor is connected to the first rear-stage gate drive signal, and the first electrode is connected to the second power supply low-potential signal , The second electrode is connected to the gate drive signal of the current stage.
  • the second pull-down module includes a fifth transistor, the gate of the fifth transistor is connected to the second back-stage gate drive signal, and the first electrode is connected to the first power supply low potential Signal, the second electrode is connected to the first node.
  • the first low-frequency clock signal, the second low-frequency clock signal, the first power supply low-potential signal, and the second power supply low-potential signal are all provided by an external timing controller.
  • the present application also provides a display panel, including a plurality of sub-pixels and a GOA circuit for driving the sub-pixels.
  • the GOA circuit includes m cascaded GOA units, wherein the nth-level GOA unit includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node according to the previous stage transmission signal
  • a pull-up module connected to the first node, and configured to pull up the potential of the gate drive signal of the current level according to the clock signal of the current level;
  • the signal download module is connected to the first node, and is used to control the output of the transmission signal of the current level according to the clock signal of the current level;
  • the first pull-down module is used to pull down the potential of the gate drive signal of the current stage according to the first subsequent stage gate drive signal
  • a second pull-down module connected to the first node, and configured to pull down the potential of the first node according to a second rear-stage gate drive signal
  • a first pull-down maintenance module connected to the first node, and configured to maintain the low potential of the first node and the gate drive signal of the current stage according to the first low-frequency clock signal;
  • the second pull-down maintenance module connected to the first node, is used to maintain the low potentials of the first node and the gate drive signal of the current stage according to the second low-frequency clock signal, the first low-frequency clock signal and The second low-frequency clock signal has an opposite potential at the same time;
  • the first pull-down maintaining module and the second pull-down maintaining module both include an inverting unit and a maintaining unit, the output terminal of the inverting unit is connected to the input terminal of the maintaining unit, and at least one of the inverters is
  • the reverse unit is a first reverse unit;
  • the first reverse unit includes a first reverse transistor, a second reverse transistor, and a third reverse transistor, and the gate of the first reverse transistor is connected to the first electrode Low-frequency clock signal input terminal, the second electrode of the first reverse transistor and the first electrode of the second reverse transistor are connected to a second node, and the gate of the second reverse transistor is connected to the first node ,
  • the second electrode of the second reverse transistor is connected to the first power supply low potential signal, the gate and the first electrode of the third reverse transistor are connected to the second node, and the second electrode of the third reverse transistor is connected to the second node.
  • the two electrodes are connected to the input end of the sustain unit.
  • the inversion units in the first pull-down maintenance module and the second pull-down maintenance module are both first inversion units.
  • one of the inverting unit of the first pull-down maintaining module and the second pull-down maintaining module is a first inverting unit
  • the other inverting unit is a second inverting unit
  • the second inversion unit includes a fourth inversion transistor, a fifth inversion transistor, a sixth inversion transistor, and a seventh inversion transistor, and the gate and the first electrode of the fourth inversion transistor are connected to a low-frequency clock signal
  • the second electrode of the fourth reverse transistor and the first electrode of the fifth reverse transistor are connected to the third node
  • the gate of the fifth reverse transistor is connected to the first node
  • the The second electrode of the fifth reverse transistor is connected to the first power supply low potential signal
  • the gate of the sixth reverse transistor is connected to the third node
  • the first electrode of the sixth reverse transistor is connected to the fourth
  • the first electrode of the reverse transistor, the second electrode of the sixth reverse transistor and the first electrode of the seventh reverse transistor are connected to the input terminal of the sustain unit, and the gate of the seventh reverse transistor
  • the sustain unit includes a first sustain transistor and a second sustain transistor, and the gate of the first sustain transistor and the gate of the second sustain transistor are connected to the input terminal of the sustain unit ,
  • the first electrode of the first sustain transistor is connected to the first power supply low potential signal
  • the second electrode of the first sustain transistor is connected to the first node
  • the first electrode of the second sustain transistor is connected to the first node.
  • Two power supply low-potential signals, and the second electrode of the second sustain transistor is connected to the gate drive signal of the current stage.
  • the pull-up control module includes a first transistor, the gate and the first electrode of the first transistor are connected to the previous stage signal transmission, and the second electrode is connected to the first node.
  • the pull-up module includes a second transistor, the gate of the second transistor is connected to the first node, the first electrode is connected to the clock signal of the current stage, and the second electrode is connected to the This level of gate drive signal.
  • the signal download module includes a third transistor, the gate of the third transistor is connected to the first node, the first electrode is connected to the clock signal of the current stage, and the second electrode is connected to the Describe the transmission signal at this level.
  • the first pull-down module includes a fourth transistor, the gate of the fourth transistor is connected to the first rear-stage gate driving signal, and the first electrode is connected to the second power source. Potential signal, the second electrode is connected to the gate drive signal of the current stage.
  • the second pull-down module includes a fifth transistor, the gate of the fifth transistor is connected to the second rear-stage gate driving signal, and the first electrode is connected to the first power supply low potential Signal, the second electrode is connected to the first node.
  • the first low-frequency clock signal, the second low-frequency clock signal, the first power supply low-potential signal, and the second power supply low-potential signal are all provided by an external timing controller.
  • the beneficial effects of the present application provides a GOA circuit and a display panel.
  • the GOA circuit includes m cascaded GOA units, wherein the nth level GOA unit includes a pull-up control module, a pull-up module, a signal download module, and a A pull-down module, a second pull-down module, a first pull-down maintenance module, and a second pull-down maintenance module;
  • the pull-up control module is connected to the first node, and is used to pull up the potential of the first node according to the signal transmitted by the previous stage;
  • the pull-up module is connected to the first node and is used to pull up the potential of the gate drive signal of the current level according to the clock signal of the current level;
  • the signal download module is connected to the first node and is used to control the current level according to the clock signal of the current level
  • the first pull-down module is used to pull down the potential of the gate drive signal of the current stage according to the first rear-stage gate drive
  • the pole drive signal pulls down the potential of the first node;
  • the first pull-down maintenance module is connected to the first node and is used to maintain the low potential of the first node and the gate drive signal of the current stage according to the first low-frequency clock signal;
  • the second pull-down The maintaining module is connected to the first node for maintaining the low potential of the first node and the gate drive signal of the current stage according to the second low-frequency clock signal.
  • Both the first pull-down maintenance module and the second pull-down maintenance module include a reverse unit and a sustain unit, the output terminal of the reverse unit is connected to the input terminal of the sustain unit, and at least one reverse unit is the first reverse unit;
  • the reverse unit includes a first reverse transistor, a second reverse transistor, and a third reverse transistor.
  • the gate and first electrode of the first reverse transistor are connected to the low-frequency clock signal input terminal, and the second electrode of the first reverse transistor
  • the first electrode of the second reverse transistor is connected to the second node
  • the gate of the second reverse transistor is connected to the first node
  • the second electrode of the second reverse transistor is connected to the first power supply low potential signal
  • the third reverse transistor The gate and the first electrode are connected to the second node
  • the second electrode of the third reverse transistor is connected to the input terminal of the sustain unit.
  • at least one inversion unit of the first pull-down maintenance module and the second pull-down maintenance module is set as the first inversion unit.
  • a high-potential low-frequency clock is input to the low-frequency clock signal input terminal Signal, when the potential of the first node is low, the second inverting transistor is turned off, the second node receives the high potential input by the first inverting transistor, and the third inverting transistor is turned on, so that the potential of the input terminal of the sustain unit is High potential.
  • the first node is at high potential
  • the second node simultaneously receives the high potential input by the first reverse transistor and the low potential input by the second reverse transistor.
  • the second node has a low potential and cannot open the third reverse. Transistor, so that the input terminal potential of the sustain unit is low.
  • only three transistors can realize the opposite of the signal potential of the first node and the input terminal of the sustain unit, thereby simplifying the GOA circuit structure and saving It takes up space.
  • Fig. 1 is a schematic diagram of the structure of a GOA circuit in the prior art.
  • FIG. 2 is a schematic diagram of the structure of the first pull-down sustaining module in the GOA circuit of the prior art.
  • FIG. 3 is a schematic diagram of the first structure of the GOA circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of the first pull-down sustain module in the GOA circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of the film layer stacking structure of the reverse unit in the first pull-down sustaining module and the second pull-down sustaining module in the GOA circuit of the prior art.
  • FIG. 6 is a schematic diagram of the film layer stacking structure of the reverse unit in the first pull-down sustaining module and the second pull-down sustaining module in the GOA circuit provided by the embodiment of the application.
  • FIG. 7 is a schematic diagram of the second structure of the GOA circuit provided by an embodiment of the application.
  • the embodiments of the present application provide a GOA circuit and a display panel to alleviate the technical problem that the existing GOA circuit occupies too much space.
  • FIG. 3 it is a schematic structural diagram of a GOA circuit provided by an embodiment of this application.
  • the GOA circuit includes m cascaded GOA units, where the nth level GOA unit includes:
  • the pull-up control module 201 is connected to the first node Q(n), and is used to pull up the potential of the first node Q(n) according to the signal transmitted by the previous stage;
  • the pull-up module 202 is connected to the first node Q(n), and is used to pull up the potential of the gate drive signal G(n) of the current stage according to the clock signal CK of the current stage;
  • the signal download module 203 is connected to the first node Q(n), and is used to control the output of the current level transmission signal ST(n) according to the current level clock signal CK;
  • the first pull-down module 204 is configured to pull down the potential of the gate drive signal G(n) of the current stage according to the first subsequent-stage gate drive signal;
  • the second pull-down module 205 is connected to the first node Q(n), and is configured to pull down the potential of the first node Q(n) according to the second subsequent gate drive signal;
  • the first pull-down maintenance module 206 connected to the first node Q(n), is used to maintain the low potential of the first node Q(n) and the gate drive signal G(n) of the current stage according to the first low-frequency clock signal LC1 ;
  • the second pull-down maintenance module 207 connected to the first node Q(n), is used to maintain the low level of the first node Q(n) and the gate drive signal G(n) of the current stage according to the second low-frequency clock signal LC2,
  • the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 have opposite potentials at the same time;
  • the first pull-down maintaining module 206 and the second pull-down maintaining module 207 both include an inverting unit and a maintaining unit, the output terminal of the inverting unit is connected to the input terminal of the maintaining unit, and at least one inverting unit is the first inverting unit ;
  • the first inversion unit includes a first inversion transistor, a second inversion transistor and a third inversion transistor, the gate and first electrode of the first inversion transistor are connected to the low-frequency clock signal input terminal, and the The second electrode and the first electrode of the second reverse transistor are connected to the second node A(n), the gate of the second reverse transistor is connected to the first node Q(n), and the second electrode of the second reverse transistor is connected to the second node A(n).
  • a power supply low potential signal VSSQ, the gate and the first electrode of the third reverse transistor are connected to the second node A(n), and the second electrode of the third reverse transistor is connected to the input terminal of the sustain unit.
  • the stage transmission signal output by the nth stage GOA unit is the nth stage transmission signal ST(n)
  • the output gate drive signal is the nth stage For the gate drive signal G(n), 6 ⁇ n ⁇ m
  • n is an integer.
  • the previous stage transmission signal is the stage transmission signal of other GOA units before the nth stage GOA unit, which can be the first stage, the first two stages, or the previous multiple stages, the first and the second back gate drive signal and the second back gate
  • the driving signals are all the gate driving signals of other GOA units after the nth-stage GOA unit, and can be the last one stage, the last two stages, or the last multiple stages.
  • the GOA circuit of the 8K product in this application is taken as an example.
  • the transmission signal of the front stage is ST(n-6)
  • the gate drive signal of the first back stage is G(n+6)
  • the gate drive signal of the second back stage is Is G(n+8)
  • ST(n-6) is the stage transmission signal before and six stages away from the nth stage gate drive signal G(n)
  • the second subsequent stage gate drive signal G(n+8) is the nth stage gate drive signal G( n)
  • the gate drive signal after and eight levels away from it.
  • the pull-up control module 201 includes a first transistor T11, the gate and the first electrode of the first transistor T11 are connected to the previous stage transmission signal ST(n-6), and the second electrode is connected to the first node Q (n).
  • the pull-up module 202 includes a second transistor T21, the gate of the second transistor T21 is connected to the first node Q(n), the first electrode is connected to the clock signal CK of the current stage, and the second electrode is connected to the gate of the current stage. Pole drive signal G(n).
  • the signal download module 203 includes a third transistor T22, the gate of the third transistor T22 is connected to the first node Q(n), the first electrode is connected to the clock signal CK of the current stage, and the second electrode is connected to the current stage The level transmission signal ST(n).
  • the first pull-down module 204 includes a fourth transistor T31, the gate of the fourth transistor T31 is connected to the first back-end gate drive signal G(n+6), and the first electrode is connected to the second power source.
  • the potential signal VSSG, and the second electrode is connected to the gate drive signal G(n) of the current stage.
  • the second pull-down module 205 includes a fifth transistor T41, the gate of the fifth transistor T41 is connected to the second back-stage gate drive signal G(n+8), and the first electrode is connected to the low potential of the first power supply.
  • the signal VSSQ, the second electrode is connected to the first node Q(n).
  • the first low-frequency clock signal LC1, the second low-frequency clock signal LC2, the first power supply low potential signal VSSQ, and the second power supply low potential signal VSSG are all provided by an external timing controller.
  • both the first pull-down sustaining module 206 and the second pull-down sustaining module 207 are used to maintain the low potentials of the first node Q(n) and the gate drive signal G(n) of the current stage, so the functions of both same.
  • the low-frequency clock signal input terminal of the first pull-down maintenance module 206 inputs the first low-frequency clock signal LC1
  • the low-frequency clock signal input terminal of the second pull-down maintenance module 207 inputs the second low-frequency clock signal LC2.
  • a low-frequency clock signal LC1 and a second low-frequency clock signal LC2 are both low-frequency clock signals with 200 times the frame period and a duty ratio of 1/2, and the phase difference between the two is 1/2 period.
  • the first low-frequency clock signal LC1 The phase of the second low-frequency clock signal LC2 is opposite, so the first pull-down maintenance module 206 and the second pull-down maintenance module 207 can be driven to work alternately, that is, the working time of the two is staggered, and only one pull-down maintenance module is working at the same time. Due to the input characteristics of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2, for a certain pull-down maintenance module that is currently working, its low-frequency clock signal input terminal is equivalent to receiving a DC signal, which is high Potential, the value is 28V.
  • Both the first pull-down maintenance module 206 and the second pull-down maintenance module 207 include an inversion unit and a maintenance unit, the output terminal of the inversion unit is connected to the input terminal of the maintenance unit, and at least one inversion unit is the first inversion unit.
  • the inversion units in the first pull-down maintenance module 206 and the second pull-down maintenance module 207 are both the first inversion unit, that is, the structure of the first pull-down maintenance module 206 and the second pull-down maintenance module 207
  • FIG. 4 uses the first pull-down sustaining module 206 as an example to describe the structure of the first inversion unit and the sustaining unit, and the specific working principle is also applicable to the second pull-down sustaining module 207.
  • the first pull-down sustaining module 206 includes a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, a ninth transistor T42, and a tenth transistor T32
  • the second pull-down sustaining module 207 includes an eleventh transistor.
  • the first pull-down sustaining module 206 includes a first inverting unit 20 and a sustaining unit 30.
  • the sixth transistor T51 is the first inverting transistor
  • the seventh transistor T52 is the first inverting transistor.
  • the eighth transistor T53 is a third reverse transistor
  • the ninth transistor T42 is a first sustain transistor
  • the tenth transistor T32 is a second sustain transistor.
  • the eleventh transistor T61 is the first inverting transistor
  • the twelfth transistor T62 is the second inverting transistor
  • the thirteenth transistor T63 is the third.
  • the fourteenth transistor T43 is the first sustain transistor
  • the fifteenth transistor T33 is the second sustain transistor.
  • one of the first electrode and the second electrode of each transistor is the source and the other is the drain.
  • the first reverse transistor, the second reverse transistor, the third reverse transistor, the first sustain transistor, the second sustain transistor, and the other transistors are all N-type or P-type transistors.
  • the gate and first electrode of the sixth transistor T51 are connected to the low-frequency clock signal input terminal, the second electrode of the sixth transistor T51 and the first electrode of the seventh transistor T52 are connected to the second node A(n),
  • the gate of the seventh transistor T52 is connected to the first node Q(n)
  • the second electrode of the seventh transistor T52 is connected to the first power supply low potential signal VSSQ
  • the gate and the first electrode of the eighth transistor T53 are connected to the second node A(n)
  • the second electrode of the eighth transistor T53 is connected to the input terminal of the sustain unit 30.
  • the gate of the ninth transistor T42 and the gate of the tenth transistor T32 are connected to the input terminal of the sustain unit 30, the first electrode of the ninth transistor T42 is connected to the first power supply low potential signal VSSQ, and the second electrode of the ninth transistor T42 is connected to the A node Q(n), the first electrode of the tenth transistor T32 is connected to the second power low potential signal VSSG, and the second electrode of the tenth transistor T32 is connected to the gate drive signal G(n) of the current stage.
  • the low-frequency clock signal input terminal inputs the first low-frequency clock signal LC1
  • the input terminal of the sustain unit 30 is connected to the fourth node P(n).
  • the signal input from the low-frequency clock signal input terminal of the first inversion unit 20 is equivalent to a DC signal with a value of 28v, that is, the first low-frequency clock signal LC1 is always at a high level during the working period.
  • the sixth transistor T51 is always in the on state, and pulls the potential of the second node A(n) high.
  • the seventh transistor T52 is turned on, and the first power supply low potential signal VSSQ pulls the potential of the second node A(n) low, so the second node A(n) simultaneously receives the sixth node A(n).
  • the high potential input by the transistor T51 and the low potential input by the seventh transistor T52 make the potential of the second node A(n) low, which is not enough to turn on the eighth transistor T53. Therefore, the potential of the fourth node P(n) is low, that is The input terminal potential of the sustain unit is low, and the ninth transistor T42 and the tenth transistor T32 are turned off.
  • the seventh transistor T52 is turned off, and the second node A(n) only receives the high potential input by the sixth transistor T51.
  • the potential of the second node A(n) is high, so that The eighth transistor T53 is turned on, the potential of the fourth node P(n) is high, that is, the potential of the input terminal of the sustain unit 30 is high, the ninth transistor T42 and the tenth transistor T32 are turned on, and the first power supply low potential signal VSSQ and The second power supply low potential signal VSSG is input to the first node Q(n) and the gate drive signal G(n) of the current stage, and the potentials of both are maintained at a low potential.
  • Each film layer includes a first pull-down sustaining module.
  • the overlapping portion of the first metal layer 11 and the active layer forms the gate of each transistor, and also forms the first node Q(n)
  • the source and drain layer 12 forms the source and drain of each transistor, the first power supply low-potential signal line VSSQ, and the low-frequency clock signal line LC.
  • connection member 13 covers the source and drain layer 12, and the other end is connected to the first
  • the via hole connection in the metal layer 11 realizes the connection between the gate of one transistor and the source or drain of another transistor, and the material of the connection member 13 is indium tin oxide.
  • each inverting unit needs to be provided with four transistors, and the connection requires three connecting members, the structure is relatively complicated, and it takes up more space. Only three transistors need to be provided, and only two connecting members are needed for connection, the structure is relatively simple, the space is less, the manufacturing process is simplified, and the cost is saved.
  • the inverting units are both the first inverting unit 20, and each first inverting unit 20 can be realized by only three transistors.
  • the first node and the voltage of the signal at the input terminal of the sustain unit are opposite, so the n-th GOA unit in the GOA circuit only needs 16 transistors.
  • two transistors are reduced, so that the structure of the GOA circuit is simplified and saved.
  • the space occupied by the GOA circuit is reduced.
  • the same settings as the nth level of GOA unit can be used.
  • the reverse units in the first pull-down maintaining module 206 and the second pull-down maintaining module 207 are both the first reverse unit 20, but the present application is not limited to this.
  • the first pull-down maintaining module 206 and the second pull-down maintaining module 207 One of the pull-down sustaining module 206 and the second pull-down sustaining module 207 is a first inverting unit, the other is a second inverting unit, and the second inverting unit includes a fourth inverting transistor and a second inverting unit.
  • the gate and first electrode of the fourth reverse transistor are connected to the low-frequency clock signal input terminal, and the second electrode of the fourth reverse transistor and the fifth reverse transistor
  • the first electrode of the transistor is connected to the third node
  • the gate of the fifth reverse transistor is connected to the first node
  • the second electrode of the fifth reverse transistor is connected to the first power supply low potential signal
  • the gate of the sixth reverse transistor is connected to the first node.
  • the first electrode of the sixth reverse transistor is connected to the first electrode of the fourth reverse transistor, the second electrode of the sixth reverse transistor and the first electrode of the seventh reverse transistor are connected to the input end of the sustain unit,
  • the gate of the seventh reverse transistor is connected to the first node, and the second electrode of the seventh reverse transistor is connected to the first power low potential signal.
  • the inversion unit in the first pull-down maintenance module 206 is the first inversion unit 20, and the structure is the same as that in FIG. 4, and the inversion unit in the second pull-down maintenance module 207 is the second inversion unit 40.
  • the second inverting unit 40 includes an eleventh transistor T61, a twelfth transistor T62, a thirteenth transistor T63, and a sixteenth transistor T64, wherein the eleventh transistor T61 is a fourth inverting transistor, and the twelfth transistor T62 is the fifth reverse transistor, the thirteenth transistor T63 is the sixth reverse transistor, and the sixteenth transistor T64 is the seventh reverse transistor.
  • the gate and first electrode of the eleventh transistor T61 are connected to the low-frequency clock signal input terminal, the second electrode of the eleventh transistor T61 and the first electrode of the twelfth transistor T62 are connected to the third node B(n), and the twelfth transistor T61 is connected to the third node B(n).
  • the gate of the transistor T62 is connected to the first node Q(n), the second electrode of the twelfth transistor T62 is connected to the first power supply low potential signal VSSQ, the gate of the thirteenth transistor T63 is connected to the third node B(n), The first electrode of the thirteenth transistor T63 is connected to the first electrode of the eleventh transistor T61, the second electrode of the thirteenth transistor T63 and the first electrode of the sixteenth transistor T64 are connected to the input end of the sustain unit 30, and the sixteenth transistor The gate of T64 is connected to the first node Q(n), and the second electrode of the sixteenth transistor T64 is connected to the first power supply low potential signal VSSQ.
  • the low-frequency clock signal input terminal inputs the second low-frequency clock signal LC2, and the input terminal of the sustain unit 30 is connected to the fifth node R(n).
  • the structure of the second inversion unit 40 is the same as that in the prior art, so it can also play the role of making the first node Q(n) and the input terminal potential of the sustaining unit 30 opposite.
  • the reverse unit in the first pull-down maintaining module 206 is designed as the first reverse unit 20
  • the reverse unit in the second pull-down maintaining module 207 is designed as the second reverse unit 40
  • the first pull-down maintaining module 207 is designed as the second reverse unit 40.
  • the inverting unit in the sustaining module 206 is designed as the second inverting unit 40
  • the inverting unit in the second pull-down sustaining module 207 is designed as the first inverting unit 20, both of which can make the total number of transistors in the n-th GOA unit be 16.
  • one transistor is reduced, so the GOA circuit structure is simplified and the occupied space is saved.
  • the present application also provides a display panel, which may be a liquid crystal display panel or an OLED display panel.
  • the display panel includes a plurality of sub-pixels and a GOA circuit for driving the sub-pixels.
  • the GOA circuit is the GOA circuit described in any of the above embodiments, which can be applied In 8K products with a display panel resolution of 7680*4320.
  • the GOA circuit in the display panel of the present application reduces the number of transistors without affecting the existing functions, so that the occupied space of the GOA circuit is reduced, and therefore, it is more conducive to realizing a narrow frame design.
  • the present application provides a GOA circuit and a display panel.
  • the GOA circuit includes m cascaded GOA units.
  • the nth level GOA unit includes a pull-up control module, a pull-up module, a signal download module, a first pull-down module, and a first pull-down module.
  • the second pull-down module, the first pull-down maintenance module, and the second pull-down maintenance module; the pull-up control module is connected to the first node, and is used to pull up the potential of the first node according to the previous stage transmission signal; the pull-up module is connected to the first node.
  • the node connection is used to pull up the potential of the gate drive signal of the current level according to the clock signal of the current level;
  • the signal download module is connected to the first node, and is used to control the output of the transmission signal of the current level according to the clock signal of the current level;
  • a pull-down module is used to pull down the potential of the gate drive signal of the current stage according to the first subsequent stage gate drive signal;
  • the second pull-down module is connected to the first node and is used to pull down the second stage gate drive signal according to the second subsequent stage gate drive signal.
  • the potential of a node is connected to the first node, and is used to maintain the low potential of the first node and the gate drive signal of the current stage according to the first low-frequency clock signal;
  • the second pull-down maintenance module is connected to the first node Connection, used to maintain the low potential of the first node and the gate drive signal of this stage according to the second low-frequency clock signal, the first low-frequency clock signal and the second low-frequency clock signal have opposite potentials at the same time; wherein, the first pull-down maintains
  • the module and the second pull-down sustaining module both include an inverting unit and a sustaining unit. The output terminal of the inverting unit is connected to the input terminal of the sustaining unit.
  • At least one inverting unit is a first inverting unit
  • the first inverting unit includes a first Inverting transistor, second inverting transistor and third inverting transistor, the gate and first electrode of the first inverting transistor are connected to the low-frequency clock signal input terminal, the second electrode of the first inverting transistor and the second inverting transistor
  • the first electrode of the second reverse transistor is connected to the second node
  • the gate of the second reverse transistor is connected to the first node
  • the second electrode of the second reverse transistor is connected to the first power low potential signal
  • the gate of the third reverse transistor is connected to the first node.
  • the electrode is connected to the second node
  • the second electrode of the third reverse transistor is connected to the input terminal of the sustain unit.
  • At least one inversion unit of the first pull-down maintenance module and the second pull-down maintenance module is set as the first inversion unit.
  • a high-potential low-frequency clock is input to the low-frequency clock signal input terminal Signal
  • the second inverting transistor is turned off, the second node receives the high potential input by the first inverting transistor, and the third inverting transistor is turned on, so that the potential of the input terminal of the sustain unit is High potential.
  • the second node simultaneously receives the high potential input by the first reverse transistor and the low potential input by the second reverse transistor.
  • the second node has a low potential and cannot open the third reverse.

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Abstract

一种GOA电路和显示面板，GOA电路的第n级GOA单元中至少一个反向单元为第一反向单元，其包括三个反向晶体管，在工作阶段，当第一节点电位为低电位时，维持单元输入端为高电位，当第一节点为高电位时，维持单元的输入端为低电位。本电路仅通过三个晶体管实现第一节点和维持单元输入端信号的电位相反，节省了占用空间。

Description

GOA电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种GOA电路和显示面板。
 背景技术
现有8K产品中的结构如图1所示，包括m个级联的GOA模块，其中第n级GOA模块包括上拉控制模块101、上拉模块102、信号下传模块103、第一下拉模块104、第二下拉模块105、第一下拉维持模块106和第二下拉维持模块107。其中，上拉控制模块101包括晶体管T11，上拉模块102包括晶体管T21，信号下传模块103包括晶体管T22，第一下拉模块104包括晶体管T31，第二下拉模块105包括晶体管T41，第一下拉维持模块106包括晶体管T51、T52、T53、T54、T32、T42，第二下拉维持模块107包括晶体管T61、T62、T63、T64、T33、T43，各晶体管的连接方式如图。各信号中，CK为时钟信号，ST(n-6)、G(n+6)、G(n+8)均为的输入信号，G(n)和ST(n)均为的输出信号，VSSQ和VSSG均为电源低电位信号。第一下拉维持模块106和第二下拉维持模块107为完全相同的结构，均由一个反相器和两颗晶体管组成，在驱动时第一下拉维持模块106的低频时钟信号输入端输入信号为LC1，第二下拉维持模块107的低频时钟信号输入端输入信号为LC2，LC1和LC2为位相差1/2周期的一组低频时钟信号，以驱动第一下拉维持模块106和第二下拉维持模块107交替工作，因此在第一下拉维持模块106或第二下拉维持模块107工作时，对应的低频时钟信号输入端输入的信号为高电位。
图2为第一下拉维持模块106的结构示意图，包括反相器10和晶体管T32、T42，反相器10由4颗晶体管组成，它的工作原理为：当Q(n)点的电位为低电位时，T52和T54关闭，T51打开，使得A点的电位为高，进而使T53打开，P(n)点为高电位；当Q(n)点的电位为高电位时，T52和T54打开，VSSQ向A点输入低电位，T51打开，向A点输入高电位，两者共同作用使得A点电位偏低，T53不能正常打开，因此P(n)点为低电位。即，反相器10总是使Q(n)点和P(n)点的电位相反。然而，8K产品由于窄边框限制，且负载较大，对于GOA电路的空间较为紧张，现有的第一下拉维持模块106和第二下拉维持模块107中，反相器均需要4颗晶体管才能实现Q(n)点和P(n)点的电位相反，造成GOA电路空间占用过大，不能满足8K产品的需求。
因此，现有的GOA电路存在空间占用过大的技术问题，需要改进。
 技术问题
本申请实施例提供一种GOA电路和显示面板，用以缓解现有GOA电路占用空间过大的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种GOA电路，包括m个级联的GOA单元，其中第n级GOA单元包括：
上拉控制模块，与第一节点连接，用于根据前级级传信号，上拉所述第一节点的电位；
上拉模块，与所述第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；
信号下传模块，与所述第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；
第一下拉模块，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；
第二下拉模块，与所述第一节点连接，用于根据第二后级栅极驱动信号，下拉所述第一节点的电位；
第一下拉维持模块，与所述第一节点连接，用于根据第一低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位；
第二下拉维持模块，与所述第一节点连接，用于根据第二低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位，所述第一低频时钟信号和所述第二低频时钟信号在相同时刻电位相反；
其中，所述第一下拉维持模块和所述第二下拉维持模块中均包括反向单元和维持单元，所述反向单元的输出端连接所述维持单元的输入端，至少一个所述反向单元为第一反向单元；所述第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，所述第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第一反向晶体管的第二电极和所述第二反向晶体管的第一电极连接第二节点，所述第二反向晶体管的栅极连接所述第一节点，所述第二反向晶体管的第二电极连接第一电源低电位信号，所述第三反向晶体管的栅极和第一电极连接所述第二节点，所述第三反向晶体管的第二电极连接所述维持单元的输入端。
在本申请的GOA电路中，所述第一下拉维持模块和所述第二下拉维持模块中的反向单元均为第一反向单元。
在本申请的GOA电路中，所述第一下拉维持模块和所述第二下拉维持模块中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，所述第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，所述第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第四反向晶体管的第二电极和所述第五反向晶体管的第一电极连接第三节点，所述第五反向晶体管的栅极连接所述第一节点，所述第五反向晶体管的第二电极连接第一电源低电位信号，所述第六反向晶体管的栅极连接所述第三节点，所述第六反向晶体管的第一电极连接所述第四反向晶体管的第一电极，所述第六反向晶体管的第二电极与所述第七反向晶体管的第一电极连接所述维持单元的输入端，所述第七反向晶体管的栅极连接所述第一节点，所述第七反向晶体管的第二电极连接所述第一电源低电位信号。
在本申请的GOA电路中，所述维持单元包括第一维持晶体管和第二维持晶体管，所述第一维持晶体管的栅极和所述第二维持晶体管的栅极连接所述维持单元的输入端，所述第一维持晶体管的第一电极连接所述第一电源低电位信号，所述第一维持晶体管的第二电极连接所述第一节点，所述第二维持晶体管的第一电极连接第二电源低电位信号，所述第二维持晶体管的第二电极连接所述本级栅极驱动信号。
在本申请的GOA电路中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极和第一电极连接所述前级级传信号，第二电极连接所述第一节点。
在本申请的GOA电路中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级栅极驱动信号。
在本申请的GOA电路中，所述信号下传模块包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级级传信号。
在本申请的GOA电路中，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极连接第一后级栅极驱动信号，第一电极连接所述第二电源低电位信号，第二电极连接所述本级栅极驱动信号。
在本申请的GOA电路中，所述第二下拉模块包括第五晶体管，所述第五晶体管的栅极连接所述第二后级栅极驱动信号，第一电极连接所述第一电源低电位信号，第二电极连接所述第一节点。
在本申请的GOA电路中，所述第一低频时钟信号、所述第二低频时钟信号、所述第一电源低电位信号和所述第二电源低电位信号均由外部时序控制器提供。
本申请还提供一种显示面板，包括多个子像素和驱动所述子像素的GOA电路，所述GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括：
上拉控制模块，与第一节点连接，用于根据前级级传信号，上拉所述第一节点的电位；
上拉模块，与所述第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；
信号下传模块，与所述第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；
第一下拉模块，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；
第二下拉模块，与所述第一节点连接，用于根据第二后级栅极驱动信号，下拉所述第一节点的电位；
第一下拉维持模块，与所述第一节点连接，用于根据第一低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位；
第二下拉维持模块，与所述第一节点连接，用于根据第二低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位，所述第一低频时钟信号和所述第二低频时钟信号在相同时刻电位相反；
其中，所述第一下拉维持模块和所述第二下拉维持模块中均包括反向单元和维持单元，所述反向单元的输出端连接所述维持单元的输入端，至少一个所述反向单元为第一反向单元；所述第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，所述第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第一反向晶体管的第二电极和所述第二反向晶体管的第一电极连接第二节点，所述第二反向晶体管的栅极连接所述第一节点，所述第二反向晶体管的第二电极连接第一电源低电位信号，所述第三反向晶体管的栅极和第一电极连接所述第二节点，所述第三反向晶体管的第二电极连接所述维持单元的输入端。
在本申请的显示面板中，所述第一下拉维持模块和所述第二下拉维持模块中的反向单元均为第一反向单元。
在本申请的显示面板中，所述第一下拉维持模块和所述第二下拉维持模块中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，所述第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，所述第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第四反向晶体管的第二电极和所述第五反向晶体管的第一电极连接第三节点，所述第五反向晶体管的栅极连接所述第一节点，所述第五反向晶体管的第二电极连接第一电源低电位信号，所述第六反向晶体管的栅极连接所述第三节点，所述第六反向晶体管的第一电极连接所述第四反向晶体管的第一电极，所述第六反向晶体管的第二电极与所述第七反向晶体管的第一电极连接所述维持单元的输入端，所述第七反向晶体管的栅极连接所述第一节点，所述第七反向晶体管的第二电极连接所述第一电源低电位信号。
在本申请的显示面板中，所述维持单元包括第一维持晶体管和第二维持晶体管，所述第一维持晶体管的栅极和所述第二维持晶体管的栅极连接所述维持单元的输入端，所述第一维持晶体管的第一电极连接所述第一电源低电位信号，所述第一维持晶体管的第二电极连接所述第一节点，所述第二维持晶体管的第一电极连接第二电源低电位信号，所述第二维持晶体管的第二电极连接所述本级栅极驱动信号。
在本申请的显示面板中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极和第一电极连接所述前级级传信号，第二电极连接所述第一节点。
在本申请的显示面板中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级栅极驱动信号。
在本申请的显示面板中，所述信号下传模块包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级级传信号。
在本申请的显示面板中，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极连接所述第一后级栅极驱动信号，第一电极连接所述第二电源低电位信号，第二电极连接所述本级栅极驱动信号。
在本申请的显示面板中，所述第二下拉模块包括第五晶体管，所述第五晶体管的栅极连接所述第二后级栅极驱动信号，第一电极连接所述第一电源低电位信号，第二电极连接所述第一节点。
在本申请的显示面板中，所述第一低频时钟信号、所述第二低频时钟信号、所述第一电源低电位信号和所述第二电源低电位信号均由外部时序控制器提供。
 有益效果
本申请的有益效果：本申请提供一种GOA电路和显示面板，GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括上拉控制模块、上拉模块、信号下传模块、第一下拉模块、第二下拉模块、第一下拉维持模块和第二下拉维持模块；上拉控制模块与第一节点连接，用于根据前级级传信号，上拉第一节点的电位；上拉模块与第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；信号下传模块与第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；第一下拉模块用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；第二下拉模块与第一节点连接，用于根据第二后级栅极驱动信号，下拉第一节点的电位；第一下拉维持模块与第一节点连接，用于根据第一低频时钟信号，维持第一节点和本级栅极驱动信号的低电位；第二下拉维持模块与第一节点连接，用于根据第二低频时钟信号，维持第一节点和本级栅极驱动信号的低电位，第一低频时钟信号和第二低频时钟信号在相同时刻电位相反；其中，第一下拉维持模块和第二下拉维持模块中均包括反向单元和维持单元，反向单元的输出端连接维持单元的输入端，至少一个反向单元为第一反向单元；第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，第一反向晶体管的第二电极和第二反向晶体管的第一电极连接第二节点，第二反向晶体管的栅极连接第一节点，第二反向晶体管的第二电极连接第一电源低电位信号，第三反向晶体管的栅极和第一电极连接第二节点，第三反向晶体管的第二电极连接维持单元的输入端。本申请将第一下拉维持模块和第二下拉维持模块中的至少一个反向单元设置为第一反向单元，在第一反向单元工作阶段，低频时钟信号输入端输入高电位的低频时钟信号，当第一节点电位为低电位时，第二反向晶体管关闭，第二节点接收第一反向晶体管输入的高电位，将第三反向晶体管打开，以使维持单元的输入端电位为高电位，当第一节点为高电位时，第二节点同时接收第一反向晶体管输入的高电位和第二反向晶体管输入的低电位，第二节点电位偏低，不能打开第三反向晶体管，以使维持单元的输入端电位为低电位，在第一反向单元中仅通过三个晶体管就能实现第一节点和维持单元输入端信号的电位相反，从而精简了GOA电路结构，节省了占用空间。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中GOA电路的结构示意图。
图2为现有技术的GOA电路中第一下拉维持模块的结构示意图。
图3为本申请实施例提供的GOA电路的第一种结构示意图。
图4为本申请实施例提供的GOA电路中第一下拉维持模块的结构示意图。
图5为现有技术的GOA电路中，第一下拉维持模块和第二下拉维持模块中反向单元的膜层叠加结构示意图。
图6为本申请实施例提供的GOA电路中，第一下拉维持模块和第二下拉维持模块中反向单元的膜层叠加结构示意图。
图7为本申请实施例提供的GOA电路的第二种结构示意图。
本申请的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相近的单元是用以相同标号表示。
本申请实施例提供一种GOA电路和显示面板，用以缓解现有GOA电路占用空间过大的技术问题。
如图3所示，为本申请实施例提供的GOA电路的结构示意图。GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括：
上拉控制模块201，与第一节点Q(n)连接，用于根据前级级传信号，上拉第一节点Q(n)的电位；
上拉模块202，与第一节点Q(n)连接，用于根据本级时钟信号CK，上拉本级栅极驱动信号G(n)的电位；
信号下传模块203，与第一节点Q(n)连接，用于根据本级时钟信号CK，控制本级级传信号ST(n)的输出；
第一下拉模块204，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号G(n)的电位；
第二下拉模块205，与第一节点Q(n)连接，用于根据第二后级栅极驱动信号，下拉第一节点Q(n)的电位；
第一下拉维持模块206，与第一节点Q(n)连接，用于根据第一低频时钟信号LC1，维持第一节点Q(n)和本级栅极驱动信号G(n)的低电位；
第二下拉维持模块207，与第一节点Q(n)连接，用于根据第二低频时钟信号LC2，维持第一节点Q(n)和本级栅极驱动信号G(n)的低电位，第一低频时钟信号LC1和第二低频时钟信号LC2在相同时刻电位相反；
其中，第一下拉维持模块206和第二下拉维持模块207中均包括反向单元和维持单元，反向单元的输出端连接维持单元的输入端，至少一个反向单元为第一反向单元；第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，第一反向晶体管的第二电极和第二反向晶体管的第一电极连接第二节点A(n)，第二反向晶体管的栅极连接第一节点Q(n)，第二反向晶体管的第二电极连接第一电源低电位信号VSSQ，第三反向晶体管的栅极和第一电极连接第二节点A(n)，第三反向晶体管的第二电极连接维持单元的输入端。
在本申请的GOA电路中，包括m个级联的GOA单元，其中第n级GOA单元输出的级传信号为第n级级传信号ST(n)，输出的栅极驱动信号为第n级栅极驱动信号G(n)，6≤n≤m，且n为整数。前级级传信号为第n级GOA单元之前的其他GOA单元的级传信号，可以是前1级、前2级或前多级，第一后级栅极驱动信号和第二后级栅极驱动信号均为第n级GOA单元之后的其他GOA单元的栅极驱动信号，可以是后1级、后2级或后多级。本申请的以8K产品的GOA电路为例，取前级级传信号为ST(n-6)，第一后级栅极驱动信号为G(n+6)，第二后级栅极驱动信号为G(n+8)，其中ST(n-6)为第n级栅极驱动信号G(n)之前且与其相隔六级的级传信号，第一后级栅极驱动信号G(n+6)为第n级栅极驱动信号G(n)之后且与其相隔六级的栅极驱动信号，第二后级栅极驱动信号G(n+8)为第n级栅极驱动信号G(n)之后且与其相隔八级的栅极驱动信号。
在一种实施例中，上拉控制模块201包括第一晶体管T11，第一晶体管T11的栅极和第一电极连接前级级传信号ST(n-6)，第二电极连接第一节点Q(n)。
在一种实施例中，上拉模块202包括第二晶体管T21，第二晶体管T21的栅极连接第一节点Q(n)，第一电极连接本级时钟信号CK，第二电极连接本级栅极驱动信号G(n)。
在一种实施例中，信号下传模块203包括第三晶体管T22，第三晶体管T22的栅极连接第一节点Q(n)，第一电极连接本级时钟信号CK，第二电极连接本级级传信号ST(n)。
在一种实施例中，第一下拉模块204包括第四晶体管T31，第四晶体管T31的栅极连接第一后级栅极驱动信号G(n+6)，第一电极连接第二电源低电位信号VSSG，第二电极连接本级栅极驱动信号G(n)。
在一种实施例中，第二下拉模块205包括第五晶体管T41，第五晶体管T41的栅极连接第二后级栅极驱动信号G(n+8)，第一电极连接第一电源低电位信号VSSQ，第二电极连接第一节点Q(n)。
在一种实施例中，第一低频时钟信号LC1、第二低频时钟信号LC2、第一电源低电位信号VSSQ和第二电源低电位信号VSSG均由外部时序控制器提供。
在本申请中，第一下拉维持模块206和第二下拉维持模块207均用于维持第一节点Q(n)和本级栅极驱动信号G(n)的低电位，因此两者的作用相同。在GOA电路进行驱动时，第一下拉维持模块206的低频时钟信号输入端输入第一低频时钟信号LC1，第二下拉维持模块207的低频时钟信号输入端输入第二低频时钟信号LC2，其中第一低频时钟信号LC1和第二低频时钟信号LC2均为200倍帧周期，占空比1/2的低频时钟信号，且两者相位差1/2周期，在相同时刻，第一低频时钟信号LC1和第二低频时钟信号LC2的相位相反，因此可以驱动第一下拉维持模块206和第二下拉维持模块207交替进行工作，即两者工作时间错开，同一时刻只有一个下拉维持模块在工作。由于第一低频时钟信号LC1和第二低频时钟信号LC2的输入特性，对于此刻正在工作的某个下拉维持模块，其低频时钟信号输入端相当于接收到的是一个直流信号，该直流信号为高电位，数值为28V。
第一下拉维持模块206和第二下拉维持模块207中均包括反向单元和维持单元，反向单元的输出端连接维持单元的输入端，至少一个反向单元为第一反向单元。在本实施例中，第一下拉维持模块206和第二下拉维持模块207中的反向单元均为第一反向单元，即第一下拉维持模块206和第二下拉维持模块207的结构相同，因此图4以第一下拉维持模块206为例，对第一反向单元和维持单元结构进行说明，具体工作原理对第二下拉维持模块207也适用。
如图3所示，第一下拉维持模块206包括第六晶体管T51、第七晶体管T52、第八晶体管T53、第九晶体管T42和第十晶体管T32，第二下拉维持模块207包括第十一晶体管T61、第十二晶体管T62、第十三晶体管T63、第十四晶体管T43和第十五晶体管T33。如图4所示，第一下拉维持模块206包括第一反向单元20和维持单元30，第一反向单元20中，第六晶体管T51为第一反向晶体管，第七晶体管T52为第二反向晶体管，第八晶体管T53为第三反向晶体管，维持单元30中，第九晶体管T42为第一维持晶体管，第十晶体管T32为第二维持晶体管。同样地，第二下拉维持模块207的第一反向单元20中，第十一晶体管T61为第一反向晶体管，第十二晶体管T62为第二反向晶体管，第十三晶体管T63为第三反向晶体管，第二下拉维持模块207的维持单元30中，第十四晶体管T43为第一维持晶体管，第十五晶体管T33为第二维持晶体管。
在本申请中，各晶体管的第一电极和第二电极，其中一个为源极，另一个为漏极。第一反向晶体管、第二反向晶体管、第三反向晶体管、第一维持晶体管、第二维持晶体管以及其他各晶体管均为N型或P型晶体管。
在图4中，第六晶体管T51的栅极和第一电极连接低频时钟信号输入端，第六晶体管T51的第二电极和第七晶体管T52的第一电极连接第二节点A(n)，第七晶体管T52的栅极连接第一节点Q(n)，第七晶体管T52的第二电极连接第一电源低电位信号VSSQ，第八晶体管T53的栅极和第一电极连接第二节点A(n)，第八晶体管T53的第二电极连接维持单元30的输入端。第九晶体管T42的栅极和第十晶体管T32的栅极连接维持单元30的输入端，第九晶体管T42的第一电极连接第一电源低电位信号VSSQ，第九晶体管T42的第二电极连接第一节点Q(n)，第十晶体管T32的第一电极连接第二电源低电位信号VSSG，第十晶体管T32的第二电极连接本级栅极驱动信号G(n)。其中，低频时钟信号输入端输入第一低频时钟信号LC1，维持单元30的输入端与第四节点P(n)连接。
在第一下拉维持模块206工作时，第一反向单元20的低频时钟信号输入端输入的信号等同于直流信号，数值为28v，即工作期间第一低频时钟信号LC1一直为高电位，因此第六晶体管T51始终处于打开状态，将第二节点A(n)电位拉高。在第一节点Q(n)为高电位时，第七晶体管T52打开，第一电源低电位信号VSSQ将第二节点A(n)电位拉低，因此第二节点A(n)同时接收第六晶体管T51输入的高电位和第七晶体管T52输入的低电位，使得第二节点A(n)电位偏低，不足以打开第八晶体管T53，因此第四节点P(n)电位为低，也即维持单元的输入端电位为低，第九晶体管T42和第十晶体管T32关闭。在第一节点Q(n)为低电位时，第七晶体管T52关闭，第二节点A(n)仅接收第六晶体管T51输入的高电位，因此第二节点A(n)电位为高，使得第八晶体管T53打开，第四节点P(n)电位为高，也即维持单元30的输入端电位为高，第九晶体管T42和第十晶体管T32打开，分别将第一电源低电位信号VSSQ和第二电源低电位信号VSSG输入给第一节点Q(n)和本级栅极驱动信号G(n)，将两者的电位维持在低电位。
图5和图6分别示出了现有技术和本申请实施例提供的GOA电路中，第一下拉维持模块和第二下拉维持模块中反向单元的膜层叠加结构，各膜层包括第一金属层11、源漏极层12和连接构件13，第一金属层11与有源层（图未示出）重叠的部分形成各晶体管的栅极，此外还形成第一节点Q(n)，源漏极层12形成各晶体管的源极和漏极、第一电源低电位信号线VSSQ、以及低频时钟信号线LC，连接构件13一端覆盖在源漏极层12上，另一端与第一金属层11中的过孔连接，实现一个晶体管的栅极和另一个晶体管的源极或漏极连接，连接构件13的材料为氧化铟锡。
由图5和图6对比可知，现有技术中每个反向单元需要设置四个晶体管，且连接需要三个连接构件，结构较为复杂，占用空间较多，而本申请中每个反向单元仅需要设置三个晶体管，连接仅需要两个连接构件，结构较为简单，占用空间较少，且简化了制作工艺，节省了成本。
本实施例中的第一下拉维持模块206和第二下拉维持模块207中，反向单元均为第一反向单元20，每个第一反向单元20仅需通过三个晶体管就能实现第一节点和维持单元输入端信号的电位相反，因此GOA电路中第n级GOA单元仅需16个晶体管，相对于现有技术，减少了两个晶体管，从而使得GOA电路的结构得到精简，节省了GOA电路的占用空间。对于GOA电路中每级GOA单元，均可采用与第n级GOA单元相同的设置。
在上述实施例中，第一下拉维持模块206和第二下拉维持模块207中反向单元均为第一反向单元20，但本申请不限于此，在一种实施例中，第一下拉维持模块206和第二下拉维持模块207中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，第四反向晶体管的第二电极和第五反向晶体管的第一电极连接第三节点，第五反向晶体管的栅极连接第一节点，第五反向晶体管的第二电极连接第一电源低电位信号，第六反向晶体管的栅极连接第三节点，第六反向晶体管的第一电极连接第四反向晶体管的第一电极，第六反向晶体管的第二电极与第七反向晶体管的第一电极连接维持单元的输入端，第七反向晶体管的栅极连接第一节点，第七反向晶体管的第二电极连接第一电源低电位信号。
如图7所示，为本申请实施例提供的GOA电路的第二种结构示意图。在本实施例中，第一下拉维持模块206中反向单元为第一反向单元20，结构与图4中相同，第二下拉维持模块207中反向单元为第二反向单元40，第二反向单元40中包括第十一晶体管T61、第十二晶体管T62、第十三晶体管T63、第十六晶体管T64，其中，第十一晶体管T61为第四反向晶体管，第十二晶体管T62为第五反向晶体管，第十三晶体管T63为第六反向晶体管，第十六晶体管T64为第七反向晶体管。
第十一晶体管T61的栅极和第一电极连接低频时钟信号输入端，第十一晶体管T61的第二电极和第十二晶体管T62的第一电极连接第三节点B(n)，第十二晶体管T62的栅极连接第一节点Q(n)，第十二晶体管T62的第二电极连接第一电源低电位信号VSSQ，第十三晶体管T63的栅极连接第三节点B(n)，第十三晶体管T63的第一电极连接第十一晶体管T61的第一电极，第十三晶体管T63的第二电极与第十六晶体管T64的第一电极连接维持单元30的输入端，第十六晶体管T64的栅极连接第一节点Q(n)，第十六晶体管T64的第二电极连接第一电源低电位信号VSSQ。其中，低频时钟信号输入端输入第二低频时钟信号LC2，维持单元30的输入端与第五节点R(n)连接。
第二反向单元40中结构与现有技术中结构相同，因此也能起到使第一节点Q(n)与维持单元30的输入端电位相反的作用。本实施例中将第一下拉维持模块206中反向单元设计为第一反向单元20，第二下拉维持模块207中反向单元设计为第二反向单元40，或将第一下拉维持模块206中反向单元设计为第二反向单元40，第二下拉维持模块207中反向单元设计为第一反向单元20，均可以使得第n级GOA单元中晶体管总数为16个，相对于现有技术，减少了一个晶体管，因此精简了GOA电路结构，节省了占用空间。
本申请还提供一种显示面板，可以是液晶显示面板或OLED显示面板，显示面板包括多个子像素和驱动子像素的GOA电路，其中GOA电路为上述任一实施例所述的GOA电路，可应用于显示面板分辨率为7680*4320的8K产品中。本申请的显示面板中GOA电路相对于现有技术，在不影响现有功能的前提下减少了晶体管的数量，使得GOA电路的占用空间减少，因此更利于实现窄边框设计。
根据以上实施例可知：
本申请提供一种GOA电路和显示面板，GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括上拉控制模块、上拉模块、信号下传模块、第一下拉模块、第二下拉模块、第一下拉维持模块和第二下拉维持模块；上拉控制模块与第一节点连接，用于根据前级级传信号，上拉第一节点的电位；上拉模块与第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；信号下传模块与第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；第一下拉模块用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；第二下拉模块与第一节点连接，用于根据第二后级栅极驱动信号，下拉第一节点的电位；第一下拉维持模块与第一节点连接，用于根据第一低频时钟信号，维持第一节点和本级栅极驱动信号的低电位；第二下拉维持模块与第一节点连接，用于根据第二低频时钟信号，维持第一节点和本级栅极驱动信号的低电位，第一低频时钟信号和第二低频时钟信号在相同时刻电位相反；其中，第一下拉维持模块和第二下拉维持模块中均包括反向单元和维持单元，反向单元的输出端连接维持单元的输入端，至少一个反向单元为第一反向单元，第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，第一反向晶体管的第二电极和第二反向晶体管的第一电极连接第二节点，第二反向晶体管的栅极连接第一节点，第二反向晶体管的第二电极连接第一电源低电位信号，第三反向晶体管的栅极和第一电极连接第二节点，第三反向晶体管的第二电极连接维持单元的输入端。本申请将第一下拉维持模块和第二下拉维持模块中的至少一个反向单元设置为第一反向单元，在第一反向单元工作阶段，低频时钟信号输入端输入高电位的低频时钟信号，当第一节点电位为低电位时，第二反向晶体管关闭，第二节点接收第一反向晶体管输入的高电位，将第三反向晶体管打开，以使维持单元的输入端电位为高电位，当第一节点为高电位时，第二节点同时接收第一反向晶体管输入的高电位和第二反向晶体管输入的低电位，第二节点电位偏低，不能打开第三反向晶体管，以使维持单元的输入端电位为低电位，在第一反向单元中仅通过三个晶体管就能实现第一节点和维持单元输入端信号的电位相反，从而精简了GOA电路结构，节省了占用空间。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种GOA电路和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种GOA电路，其包括m个级联的GOA单元，其中第n级GOA单元包括：
    上拉控制模块，与第一节点连接，用于根据前级级传信号，上拉所述第一节点的电位；
    上拉模块，与所述第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；
    信号下传模块，与所述第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；
    第一下拉模块，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；
    第二下拉模块，与所述第一节点连接，用于根据第二后级栅极驱动信号，下拉所述第一节点的电位；
    第一下拉维持模块，与所述第一节点连接，用于根据第一低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位；
    第二下拉维持模块，与所述第一节点连接，用于根据第二低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位，所述第一低频时钟信号和所述第二低频时钟信号在相同时刻电位相反；
    其中，所述第一下拉维持模块和所述第二下拉维持模块中均包括反向单元和维持单元，所述反向单元的输出端连接所述维持单元的输入端，至少一个所述反向单元为第一反向单元；所述第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，所述第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第一反向晶体管的第二电极和所述第二反向晶体管的第一电极连接第二节点，所述第二反向晶体管的栅极连接所述第一节点，所述第二反向晶体管的第二电极连接第一电源低电位信号，所述第三反向晶体管的栅极和第一电极连接所述第二节点，所述第三反向晶体管的第二电极连接所述维持单元的输入端。
  2. 如权利要求1所述的GOA电路，其中，所述第一下拉维持模块和所述第二下拉维持模块中的反向单元均为第一反向单元。
  3. 如权利要求1所述的GOA电路，其中，所述第一下拉维持模块和所述第二下拉维持模块中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，所述第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，所述第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第四反向晶体管的第二电极和所述第五反向晶体管的第一电极连接第三节点，所述第五反向晶体管的栅极连接所述第一节点，所述第五反向晶体管的第二电极连接第一电源低电位信号，所述第六反向晶体管的栅极连接所述第三节点，所述第六反向晶体管的第一电极连接所述第四反向晶体管的第一电极，所述第六反向晶体管的第二电极与所述第七反向晶体管的第一电极连接所述维持单元的输入端，所述第七反向晶体管的栅极连接所述第一节点，所述第七反向晶体管的第二电极连接所述第一电源低电位信号。
  4. 如权利要求1所述的GOA电路，其中，所述维持单元包括第一维持晶体管和第二维持晶体管，所述第一维持晶体管的栅极和所述第二维持晶体管的栅极连接所述维持单元的输入端，所述第一维持晶体管的第一电极连接所述第一电源低电位信号，所述第一维持晶体管的第二电极连接所述第一节点，所述第二维持晶体管的第一电极连接第二电源低电位信号，所述第二维持晶体管的第二电极连接所述本级栅极驱动信号。
  5. 如权利要求4所述的GOA电路，其中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极和第一电极连接所述前级级传信号，第二电极连接所述第一节点。
  6. 如权利要求5所述的GOA电路，其中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级栅极驱动信号。
  7. 如权利要求6所述的GOA电路，其中，所述信号下传模块包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级级传信号。
  8. 如权利要求7所述的GOA电路，其中，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极连接所述第一后级栅极驱动信号，第一电极连接所述第二电源低电位信号，第二电极连接所述本级栅极驱动信号。
  9. 如权利要求8所述的GOA电路，其中，所述第二下拉模块包括第五晶体管，所述第五晶体管的栅极连接所述第二后级栅极驱动信号，第一电极连接所述第一电源低电位信号，第二电极连接所述第一节点。
  10. 如权利要求9所述的GOA电路，其中，所述第一低频时钟信号、所述第二低频时钟信号、所述第一电源低电位信号和所述第二电源低电位信号均由外部时序控制器提供。
  11. 一种显示面板，其包括多个子像素和驱动所述子像素的GOA电路，所述GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括：
    上拉控制模块，与第一节点连接，用于根据前级级传信号，上拉所述第一节点的电位；
    上拉模块，与所述第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；
    信号下传模块，与所述第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；
    第一下拉模块，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；
    第二下拉模块，与所述第一节点连接，用于根据第二后级栅极驱动信号，下拉所述第一节点的电位；
    第一下拉维持模块，与所述第一节点连接，用于根据第一低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位；
    第二下拉维持模块，与所述第一节点连接，用于根据第二低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位，所述第一低频时钟信号和所述第二低频时钟信号在相同时刻电位相反；
    其中，所述第一下拉维持模块和所述第二下拉维持模块中均包括反向单元和维持单元，所述反向单元的输出端连接所述维持单元的输入端，至少一个所述反向单元为第一反向单元；所述第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，所述第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第一反向晶体管的第二电极和所述第二反向晶体管的第一电极连接第二节点，所述第二反向晶体管的栅极连接所述第一节点，所述第二反向晶体管的第二电极连接第一电源低电位信号，所述第三反向晶体管的栅极和第一电极连接所述第二节点，所述第三反向晶体管的第二电极连接所述维持单元的输入端。
  12. 如权利要求11所述的显示面板，其中，所述第一下拉维持模块和所述第二下拉维持模块中的反向单元均为第一反向单元。
  13. 如权利要求11所述的显示面板，其中，所述第一下拉维持模块和所述第二下拉维持模块中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，所述第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，所述第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第四反向晶体管的第二电极和所述第五反向晶体管的第一电极连接第三节点，所述第五反向晶体管的栅极连接所述第一节点，所述第五反向晶体管的第二电极连接第一电源低电位信号，所述第六反向晶体管的栅极连接所述第三节点，所述第六反向晶体管的第一电极连接所述第四反向晶体管的第一电极，所述第六反向晶体管的第二电极与所述第七反向晶体管的第一电极连接所述维持单元的输入端，所述第七反向晶体管的栅极连接所述第一节点，所述第七反向晶体管的第二电极连接所述第一电源低电位信号。
  14. 如权利要求11所述的显示面板，其中，所述维持单元包括第一维持晶体管和第二维持晶体管，所述第一维持晶体管的栅极和所述第二维持晶体管的栅极连接所述维持单元的输入端，所述第一维持晶体管的第一电极连接所述第一电源低电位信号，所述第一维持晶体管的第二电极连接所述第一节点，所述第二维持晶体管的第一电极连接第二电源低电位信号，所述第二维持晶体管的第二电极连接所述本级栅极驱动信号。
  15. 如权利要求14所述的显示面板，其中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极和第一电极连接所述前级级传信号，第二电极连接所述第一节点。
  16. 如权利要求15所述的显示面板，其中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级栅极驱动信号。
  17. 如权利要求16所述的显示面板，其中，所述信号下传模块包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级级传信号。
  18. 如权利要求17所述的显示面板，其中，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极连接所述第一后级栅极驱动信号，第一电极连接所述第二电源低电位信号，第二电极连接所述本级栅极驱动信号。
  19. 如权利要求18所述的显示面板，其中，所述第二下拉模块包括第五晶体管，所述第五晶体管的栅极连接所述第二后级栅极驱动信号，第一电极连接所述第一电源低电位信号，第二电极连接所述第一节点。
  20. 如权利要求19所述的显示面板，其中，所述第一低频时钟信号、所述第二低频时钟信号、所述第一电源低电位信号和所述第二电源低电位信号均由外部时序控制器提供。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115862511A (zh) * 2022-11-30 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862514A (zh) * 2022-12-16 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080100333A1 (en) * 2006-10-31 2008-05-01 Hynix Semiconductor Inc. Impedance matching circuit of semiconductor memory device
US20090289499A1 (en) * 2008-05-22 2009-11-26 Elpida Memory, Inc. Prevention of the propagation of power supply noise from one output circuit to another in a semiconductor device
CN107424575A (zh) * 2017-08-01 2017-12-01 深圳市华星光电半导体显示技术有限公司 Goa驱动电路及液晶面板
CN107507555A (zh) * 2017-08-15 2017-12-22 友达光电股份有限公司 栅极驱动电路
CN108962178A (zh) * 2018-09-03 2018-12-07 深圳市华星光电技术有限公司 Goa电路及液晶面板
CN109509459A (zh) * 2019-01-25 2019-03-22 深圳市华星光电技术有限公司 Goa电路及显示装置
CN110619856A (zh) * 2019-08-23 2019-12-27 深圳市华星光电半导体显示技术有限公司 一种goa电路
CN110827776A (zh) * 2019-10-16 2020-02-21 深圳市华星光电技术有限公司 Goa器件及栅极驱动电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104715730B (zh) * 2015-03-04 2017-07-18 昆山龙腾光电有限公司 一种栅极驱动电路及显示装置
CN106997753B (zh) * 2017-04-07 2019-07-12 深圳市华星光电技术有限公司 一种goa驱动电路
CN107358931B (zh) * 2017-09-04 2019-12-24 深圳市华星光电半导体显示技术有限公司 Goa电路
CN108320717B (zh) * 2018-02-06 2020-12-22 深圳市华星光电技术有限公司 一种goa驱动电路及其制备的液晶显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080100333A1 (en) * 2006-10-31 2008-05-01 Hynix Semiconductor Inc. Impedance matching circuit of semiconductor memory device
US20090289499A1 (en) * 2008-05-22 2009-11-26 Elpida Memory, Inc. Prevention of the propagation of power supply noise from one output circuit to another in a semiconductor device
CN107424575A (zh) * 2017-08-01 2017-12-01 深圳市华星光电半导体显示技术有限公司 Goa驱动电路及液晶面板
CN107507555A (zh) * 2017-08-15 2017-12-22 友达光电股份有限公司 栅极驱动电路
CN108962178A (zh) * 2018-09-03 2018-12-07 深圳市华星光电技术有限公司 Goa电路及液晶面板
CN109509459A (zh) * 2019-01-25 2019-03-22 深圳市华星光电技术有限公司 Goa电路及显示装置
CN110619856A (zh) * 2019-08-23 2019-12-27 深圳市华星光电半导体显示技术有限公司 一种goa电路
CN110827776A (zh) * 2019-10-16 2020-02-21 深圳市华星光电技术有限公司 Goa器件及栅极驱动电路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115862511A (zh) * 2022-11-30 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862511B (zh) * 2022-11-30 2024-04-12 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862514A (zh) * 2022-12-16 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862514B (zh) * 2022-12-16 2024-03-15 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

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