WO2021196283A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2021196283A1
WO2021196283A1 PCT/CN2020/084770 CN2020084770W WO2021196283A1 WO 2021196283 A1 WO2021196283 A1 WO 2021196283A1 CN 2020084770 W CN2020084770 W CN 2020084770W WO 2021196283 A1 WO2021196283 A1 WO 2021196283A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
signal
level
Prior art date
Application number
PCT/CN2020/084770
Other languages
English (en)
French (fr)
Inventor
朱静
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/050,847 priority Critical patent/US11854461B2/en
Publication of WO2021196283A1 publication Critical patent/WO2021196283A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • This application relates to the field of mobile communication technology, in particular to the field of mobile device technology, and in particular to a GOA circuit and a display panel.
  • GOA full name in English: Gate Driver on Array, full name in Chinese: integrated gate drive circuit
  • GOA full name in English: Gate Driver on Array, full name in Chinese: integrated gate drive circuit
  • the embodiments of the present application provide a GOA circuit and a display panel, which can solve the technical problems of serious GOA circuit leakage and insufficient high temperature limit during product reliability testing of existing GOA circuits.
  • a GOA circuit in the embodiment of the present application includes: multi-stage cascaded GOA units, each level of GOA unit includes: a node control module, a stage transfer module, a pull-up module, a pull-down module, a pull-down maintenance module, and a bootstrap capacitor;
  • the node control module is connected to the power signal and the upper-level transmission signal, and is electrically connected to the first node, and the node control module is configured to transmit the signal according to the upper-level scanning signal and the upper-level transmission signal Controlling the potential of the first node;
  • the stage transmission module is connected to the clock signal of the current stage and is electrically connected to the first node, and the stage transmission module is configured to output the stage transmission signal of the current stage under the control of the potential of the first node;
  • the pull-up module is connected to the clock signal of the current level and is electrically connected to the first node, and the pull-up module is configured to output the scan signal of the current level under the control of the potential of the first node;
  • the pull-down module is connected to a next-level scan signal, a first reference low-level signal, and a second reference low-level signal, and is electrically connected to the first node and the current-level scan signal, and the pull-down module It is used to pull down the potential of the first node to the potential of the first reference low level signal under the control of the next-level transmission signal, and to pull down the potential of the first reference low-level signal under the control of the next-level transmission signal
  • the current-level scanning signal is pulled down to the potential of the second reference low-level signal;
  • the pull-down maintaining module is connected to a power signal, the first reference low level signal, and the second reference low level signal, and is electrically connected to the first node, and the pull-down maintaining module is configured to The first control signal, the first reference low-level signal, and the second reference low-level signal maintain the potential of the first node and the potential of the current-level scanning signal; wherein, the pull-down maintaining module It is also used to suppress the leakage of the first node when the first node is at a high potential;
  • the first end of the bootstrap capacitor is electrically connected to the first node, and the second end of the bootstrap capacitor is electrically connected to the scan signal of the current stage.
  • the node control module includes a first transistor; the gate of the first transistor is electrically connected to the upper-level transmission signal, and the source of the first transistor is electrically connected to the For the power signal, the drain of the first transistor is electrically connected to the first node.
  • the stage transfer module includes a second transistor; the gate of the second transistor is electrically connected to the first node, and the source of the second transistor is electrically connected to the current stage For a clock signal, the drain of the second transistor is electrically connected to the current-level transmission signal.
  • the pull-up module includes a third transistor; the gate of the third transistor is electrically connected to the first node, and the source of the third transistor is electrically connected to the current stage For a clock signal, the drain of the third transistor is electrically connected to the scan signal of the current level.
  • the gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the next stage signal, and the source of the fourth transistor is electrically connected to all For the first reference low-level signal, the drain of the fourth transistor is electrically connected to the first node, and the source of the fifth transistor is electrically connected to the second reference low-level signal, so The drain of the fifth transistor is electrically connected to the scan signal of the current stage.
  • the pull-down sustaining module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the gate and source of the sixth transistor, and the source of the seventh transistor are all electrically connected to the power signal, the drain of the sixth transistor, the gate of the seventh transistor, and the The drain of the eighth transistor is electrically connected, the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, the gate of the eleventh transistor, and the The gates of the twelve transistors are all electrically connected to the second node, the gate of the eighth transistor, the gate of the ninth transistor, the drain of the eleventh transistor, and the thirteenth transistor.
  • the gate and source of the transistor are electrically connected to the first node, the drain of the tenth transistor is electrically connected to the scan signal of the current stage, and the source of the eighth transistor and the source of the ninth transistor are And the source of the twelfth transistor are electrically connected to the first reference low voltage signal, and the source of the tenth transistor is electrically connected to the second reference low voltage signal, the tenth transistor.
  • the source of a transistor, the drain of the twelfth transistor, and the drain of the thirteenth transistor are electrically connected to a third node.
  • the thirteenth transistor when the first node is at a high potential, the thirteenth transistor is turned on to reduce the voltage difference between the source and the drain of the eleventh transistor and suppress the first node Leakage.
  • the pull-down sustaining module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor;
  • the gate and source of the fourteenth transistor and the source of the fifteenth transistor are all electrically connected to the power signal.
  • the drain of the fourteenth transistor and the gate of the fifteenth transistor are all electrically connected to the power signal.
  • the drain of the sixteenth transistor are electrically connected, the drain of the fifteenth transistor, the drain of the seventeenth transistor, the gate of the eighteenth transistor, the nineteenth transistor.
  • the gate of the transistor and the drain of the twentieth transistor are electrically connected to the second node, the gate of the sixteenth transistor, the gate of the seventeenth transistor, and the nineteenth transistor are electrically connected to the second node.
  • the drains of the transistors are all electrically connected to the first node, the source of the sixteenth transistor, the source of the seventeenth transistor, the source of the nineteenth transistor, and the twentieth transistor
  • the sources of the eighteenth transistor are electrically connected to the first reference low voltage signal
  • the source of the eighteenth transistor is electrically connected to the second reference low voltage signal
  • the drain of the eighteenth transistor is electrically connected Connected to the scanning signal of the current stage
  • the gate of the twentieth transistor is electrically connected to the signal transmitting of the current stage.
  • the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the The seventeenth transistor and the twentieth transistor are turned on to reduce the voltage difference between the gate and the source of the nineteenth transistor and suppress the leakage of the first node.
  • An embodiment of the present application also provides a display panel including a GOA circuit, and the GOA circuit includes: multi-level cascaded GOA units, each level of GOA unit includes: a node control module, a level transmission module, a pull-up module, Pull-down module, pull-down maintenance module and bootstrap capacitor;
  • the node control module is connected to the power signal and the upper-level transmission signal, and is electrically connected to the first node, and the node control module is configured to transmit the signal according to the upper-level scanning signal and the upper-level transmission signal Controlling the potential of the first node;
  • the stage transmission module is connected to the clock signal of the current stage and is electrically connected to the first node, and the stage transmission module is configured to output the stage transmission signal of the current stage under the control of the potential of the first node;
  • the pull-up module is connected to the clock signal of the current level and is electrically connected to the first node, and the pull-up module is configured to output the scan signal of the current level under the control of the potential of the first node;
  • the pull-down module is connected to a next-level scan signal, a first reference low-level signal, and a second reference low-level signal, and is electrically connected to the first node and the current-level scan signal, and the pull-down module It is used to pull down the potential of the first node to the potential of the first reference low level signal under the control of the next-level transmission signal, and to pull down the potential of the first reference low-level signal under the control of the next-level transmission signal
  • the current-level scanning signal is pulled down to the potential of the second reference low-level signal;
  • the pull-down maintaining module is connected to a power signal, the first reference low level signal, and the second reference low level signal, and is electrically connected to the first node, and the pull-down maintaining module is configured to The first control signal, the first reference low-level signal, and the second reference low-level signal maintain the potential of the first node and the potential of the current-level scanning signal; wherein, the pull-down maintaining module It is also used to suppress the leakage of the first node when the first node is at a high potential;
  • the first end of the bootstrap capacitor is electrically connected to the first node, and the second end of the bootstrap capacitor is electrically connected to the scan signal of the current stage.
  • the node control module includes a first transistor; the gate of the first transistor is electrically connected to the upper-level transmission signal, and the source of the first transistor is electrically connected to the For the power signal, the drain of the first transistor is electrically connected to the first node.
  • the stage transfer module includes a second transistor; the gate of the second transistor is electrically connected to the first node, and the source of the second transistor is electrically connected to the current stage For a clock signal, the drain of the second transistor is electrically connected to the current-level transmission signal.
  • the pull-up module includes a third transistor; the gate of the third transistor is electrically connected to the first node, and the source of the third transistor is electrically connected to the current stage For a clock signal, the drain of the third transistor is electrically connected to the scan signal of the current level.
  • the gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the next stage signal, and the source of the fourth transistor is electrically connected to all For the first reference low-level signal, the drain of the fourth transistor is electrically connected to the first node, and the source of the fifth transistor is electrically connected to the second reference low-level signal, so The drain of the fifth transistor is electrically connected to the scan signal of the current stage.
  • the pull-down sustaining module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the gate and source of the sixth transistor, and the source of the seventh transistor are all electrically connected to the power signal, the drain of the sixth transistor, the gate of the seventh transistor, and the The drain of the eighth transistor is electrically connected, the drain of the seventh transistor, the drain of the ninth transistor, the gate of the tenth transistor, the gate of the eleventh transistor, and the The gates of the twelve transistors are all electrically connected to the second node, the gate of the eighth transistor, the gate of the ninth transistor, the drain of the eleventh transistor, and the thirteenth transistor.
  • the gate and source of the transistor are electrically connected to the first node, the drain of the tenth transistor is electrically connected to the scan signal of the current stage, and the source of the eighth transistor and the source of the ninth transistor are And the source of the twelfth transistor are electrically connected to the first reference low voltage signal, and the source of the tenth transistor is electrically connected to the second reference low voltage signal, the tenth transistor.
  • the source of a transistor, the drain of the twelfth transistor, and the drain of the thirteenth transistor are electrically connected to a third node.
  • the thirteenth transistor when the first node is at a high potential, the thirteenth transistor is turned on to reduce the voltage difference between the source and the drain of the eleventh transistor and suppress the first node Leakage.
  • the pull-down sustaining module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor;
  • the gate and source of the fourteenth transistor and the source of the fifteenth transistor are all electrically connected to the power signal.
  • the drain of the fourteenth transistor and the gate of the fifteenth transistor are all electrically connected to the power signal.
  • the drain of the sixteenth transistor are electrically connected, the drain of the fifteenth transistor, the drain of the seventeenth transistor, the gate of the eighteenth transistor, the nineteenth transistor.
  • the gate of the transistor and the drain of the twentieth transistor are electrically connected to the second node, the gate of the sixteenth transistor, the gate of the seventeenth transistor, and the nineteenth transistor are electrically connected to the second node.
  • the drains of the transistors are all electrically connected to the first node, the source of the sixteenth transistor, the source of the seventeenth transistor, the source of the nineteenth transistor, and the twentieth transistor
  • the sources of the eighteenth transistor are electrically connected to the first reference low voltage signal
  • the source of the eighteenth transistor is electrically connected to the second reference low voltage signal
  • the drain of the eighteenth transistor is electrically connected Connected to the scanning signal of the current stage
  • the gate of the twentieth transistor is electrically connected to the signal transmitting of the current stage.
  • the GOA circuit and display panel provided by the embodiments of the present application can not only add a thirteenth transistor to the pull-down sustaining module, thereby reducing the voltage difference between the source and drain of the eleventh transistor, thereby suppressing the leakage of the first node
  • a twentieth transistor to the pull-down maintenance module to reduce the voltage difference between the gate and source of the nineteenth transistor, thereby suppressing the leakage of the first node and increasing the first node.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a first circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a second circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a third circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • FIG. 5 is a signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the "on" or “under” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other pole is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application are all N-type transistors or P-type transistors, where the N-type transistor is turned on when the gate is high and turned off when the gate is low; and the P-type transistor is low when the gate is low. Turn on when the level is high, and turn off when the gate is high.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • the GOA circuit 10 provided by the embodiment of the present application includes a multi-stage cascaded GOA unit 20.
  • Each GOA unit 20 is used to output a scanning signal and a first-stage transmission signal.
  • the first-level GOA unit 20 is connected to the start signal STV, and then the second-level GOA unit 20, the third-level GOA unit 20, ..., the last-level GOA unit 20 are sequentially Pass start.
  • FIG. 2 is a schematic diagram of a first circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the GOA unit 20 includes: a node control module, a stage transfer module, a pull-up module, a pull-down module, a pull-down maintenance module, and a bootstrap capacitor Cbt.
  • the node control module is connected to the power signal VDD and the upper level transmission signal ST(n-1), and is electrically connected to the first node Q(n) for transmitting the signal according to the power signal VDD and the upper level ST(n-1) controls the potential of the first node Q(n).
  • the level transmission module is connected to the clock signal CK of the current level, and is electrically connected to the first node Q(n), for outputting the level transmission signal ST(n) of the current level under the control of the potential of the first node Q(n) .
  • the pull-up module is connected to the clock signal CK of the current level and is electrically connected to the first node Q(n) for outputting the scan signal G(n) of the current level under the control of the potential of the first node Q(n).
  • the pull-down module is connected to the next level transmission signal ST(n+1), the first reference low level signal VSSQ, and the second reference low level signal VSSG, and is electrically connected to the first node Q(n) and
  • the scanning signal G(n) of the current stage is used to pull down the potential of the first node Q(n) to the potential of the first reference low level signal VSSQ under the control of the next stage transmission signal ST(n+1), and
  • the scan signal G(n) of the current level is pulled down to the potential of the second reference low level signal VSSG under the control of the next level transfer signal ST(n+1).
  • the pull-down maintenance module is connected to the power supply signal VDD, the first reference low level signal VSSQ, and the second reference low level signal VSSG, and is electrically connected to the first node Q(n),
  • the pull-down maintaining module 105 is configured to maintain the potential of the first node Q(n) and the voltage of the first node Q(n) according to the power signal VDD, the first reference low level signal VSSQ, and the second reference low level signal VSSG.
  • the first end of the bootstrap capacitor Cbt is electrically connected to the first node Q(n), and the second end of the bootstrap capacitor Cbt is electrically connected to the scan signal G(n) of the current stage.
  • FIG. 3 is a schematic diagram of a second circuit of a GOA unit in the GOA circuit provided by the embodiment of the application.
  • the GOA unit 20 includes: a node control module 101, a stage transfer module 102, a pull-up module 103, a pull-down module 104, a pull-down maintenance module 105, and a bootstrap capacitor Cbt.
  • the node control module 101 includes a first transistor T1; the gate of the first transistor T1 is electrically connected to the upper-level transmission signal ST(n-1), and the source of the first transistor T1 is electrically connected In response to the power signal VDD, the drain of the first transistor T1 is electrically connected to the first node Q(n).
  • the stage transfer module 102 includes a second transistor T2; the gate of the second transistor T2 is electrically connected to the first node Q(n), and the source of the second transistor T2 is electrically connected to the clock signal of the current stage CK, the drain of the second transistor T2 is electrically connected to the transmission signal ST(n) of the current stage.
  • the pull-up module 103 includes a third transistor T3; the gate of the third transistor T3 is electrically connected to the first node Q(n), and the source of the third transistor T3 is electrically connected to the clock signal of the current stage CK, the drain of the third transistor T3 is electrically connected to the scan signal G(n) of the current level.
  • the pull-down module 104 includes a fourth transistor T4 and a fifth transistor T5; the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are both electrically connected to the next stage transmission signal ST(n+ 1)
  • the source of the fourth transistor T4 is electrically connected to the first reference low level signal VSSQ
  • the drain of the fourth transistor T4 is electrically connected to the first node Q(n)
  • the source of the fifth transistor T5 is electrically connected It is electrically connected to the second reference low level signal VSSG
  • the drain of the fifth transistor T5 is electrically connected to the current level scanning signal G(n).
  • the pull-down sustain module 105 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and The thirteenth transistor T13; the gate and source of the sixth transistor T6 and the source of the seventh transistor T7 are electrically connected to the power signal VDD, the drain of the sixth transistor T6 and the gate of the seventh transistor T7 And the drain of the eighth transistor T8 is electrically connected, the drain of the seventh transistor T7, the drain of the ninth transistor T9, the gate of the tenth transistor T10, the gate of the eleventh transistor T11, and the twelfth transistor T12 The gates of each are electrically connected to the second node P(n), the gate of the eighth transistor T8, the gate of the ninth transistor T9, the drain of the eleventh transistor T11, and the gate of the thirteenth transistor T13 Both the electrode and the source are electrically connected to the first node Q(
  • FIG. 4 is a schematic diagram of a third circuit of a GOA unit in the GOA circuit provided by the embodiment of the application.
  • the GOA unit 20 includes: a node control module 201, a stage transfer module 202, a pull-up module 203, a pull-down module 204, a pull-down maintenance module 205, and a bootstrap capacitor Cbt.
  • the node control module 201 and the node control module 101 have the same structure and have the same function;
  • the cascade transmission module 202 and the cascade transmission module 102 have the same structure and play the same role; the pull-up module 203 and the pull-up module 103 have the same structure and play the same role; the pull-down module 204 and the pull-down module 104 have the same structure and play the same role.
  • the functions obtained are the same; therefore, the specific structures of the node control module 201, the grade transfer module 202, the pull-up module 203, and the pull-down module 204 are not described here, and you can refer to the above-mentioned embodiment.
  • the pull-down maintenance module 205 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, and a Twenty transistor T20;
  • the gate and source of the fourteenth transistor T14 and the source of the fifteenth transistor T15 are electrically connected to the power signal, the drain of the fourteenth transistor T14, the gate of the fifteenth transistor T15, and the tenth transistor T15 are electrically connected to the power signal.
  • the drain of the six transistor T16 is electrically connected, the drain of the fifteenth transistor T15, the drain of the seventeenth transistor T17, the gate of the eighteenth transistor T18, the gate of the nineteenth transistor T19, and the twentieth transistor
  • the drains of T20 are all electrically connected to the second node P(n)
  • the gates of the sixteenth transistor T16, the gates of the seventeenth transistor T17, and the drains of the nineteenth transistor T19 are all electrically connected to all
  • the source of the sixteenth transistor T16, the source of the seventeenth transistor T17, the source of the nineteenth transistor T19, and the source of the twentieth transistor T20 are all electrically connected to all
  • the source of the eighteenth transistor T18 is electrically connected to the second reference low voltage signal VSSG
  • the drain of the eighteenth transistor T18 is electrically connected to the scan signal G of the current level (N)
  • the gate of the twentieth transistor T20 is electrically
  • FIG. 5 is a signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the first transistor T1 When the upper level transmission signal ST(n-1) is high and the power signal VDD is high, the first transistor T1 is turned on, and the power signal VDD charges the bootstrap capacitor Cbt through the first transistor T1, so that the first transistor T1 is used to charge the bootstrap capacitor Cbt.
  • the potential of a node Q(n) rises to a higher potential.
  • the upper-level transmission signal ST(n-1) turns to a low level
  • the first transistor T1 is turned off
  • the potential of the first node Q(n) is maintained at a higher potential through the bootstrap capacitor Cbt.
  • the potential of the clock signal CK of the current stage turns to a high potential
  • the clock signal CK of the current stage continues to charge the bootstrap capacitor Cbt through the second transistor T2, so that the potential of the first node Q(n) reaches a higher potential.
  • the scanning signal G(n) and the transfer signal ST(n) of this stage are also turned to high potential, and the power supply signal VDD is also high, so that the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the first The nine transistor T9 is turned on to maintain the potential of the second node P(n) at the potential of the first reference low level signal VSSQ.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the first reference low level signal VSSQ pulls the potential of the first node Q(n) Low, the second reference low level signal VSSG pulls the scan signal G(n) of the current level low.
  • the eighth transistor T8 and the ninth transistor T9 are turned off, and at the same time, the power signal VDD is at a high potential, so that the sixth transistor T6 and the seventh transistor T7 are turned on.
  • the potential of the second node P(n) is pulled up to a high potential, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the first reference low-level signal VSSQ maintains the first node Q(n)
  • the potential reaches the potential of the first reference low-level signal VSSQ, and then maintains the potential of the scan signal G(n) of the current level to the potential of the second reference low-level signal VSSG.
  • a thirteenth transistor T13 is added to the pull-down sustaining module 105, so that when the first node Q(n) is at a high potential, the thirteenth transistor T13 can be turned on, so that the third node A charges, pulls the third node A to a high potential, reduces the voltage difference between the source and drain of the eleventh transistor T11; because the leakage of the transistor mainly depends on the voltage difference between the source and drain of the transistor and The voltage difference between the gate and the source of the transistor. When the voltage difference between the gate and the source of the transistor is fixed, the greater the voltage difference between the source and the drain of the transistor, the more serious the leakage.
  • the voltage difference between the electrodes is fixed, the smaller the voltage difference between the gate and the source of the transistor, the smaller the leakage, and it is the best in a certain area; so reduce the difference between the source and drain of the eleventh transistor T11
  • the voltage difference can achieve the effect of suppressing the leakage of the eleventh transistor T11, thereby suppressing the leakage of the first node Q(n), and improving the high temperature limit of the first node Q(n).
  • the upper-level transmission signal ST(n-1) turns to a low level
  • the first transistor T1 is turned off
  • the potential of the first node Q(n) is maintained at a higher potential through the bootstrap capacitor Cbt.
  • the potential of the clock signal CK of the current stage turns to a high potential
  • the clock signal CK of the current stage continues to charge the bootstrap capacitor Cbt through the second transistor T2, so that the potential of the first node Q(n) reaches a higher potential.
  • the level scanning signal G(n) and the level transmission signal ST(n) of this level are also turned to high potential, and the power supply signal VDD is also high, so that the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16, the seventeenth transistor T17, and the twentieth transistor T20 are turned on to maintain the potential of the second node P(n) at the potential of the first reference low level signal VSSQ.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the first reference low level signal VSSQ pulls the potential of the first node Q(n) Low, the second reference low level signal VSSG pulls the scan signal G(n) of the current level low.
  • the sixteenth transistor T16 and the seventeenth transistor T17 are turned off.
  • the power signal VDD is at a high potential, so that the fourteenth transistor T14 and the fifteenth transistor T14 are turned off.
  • the transistor T15 is turned on to pull the potential of the second node P(n) to a high potential, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, and the first reference low level signal VSS1 maintains the potential of the first node Q(n) To the potential of the first reference low-level signal VSSQ, and then maintain the potential of the scan signal G(n) of the current level to the potential of the second reference low-level signal VSSG.
  • the twentieth transistor T20 can be made when the first node Q(n) and the current stage transmission signal ST(n) are at a high potential.
  • the transistor T20 is turned on, so that the second node P(n) can be better maintained at the potential of the first reference low level signal VSSQ, thereby reducing the voltage difference between the source and the gate of the nineteenth transistor T19;
  • the leakage of the transistor mainly depends on the voltage difference between the source and drain of the transistor and the voltage difference between the gate and source of the transistor.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes a display area 100 and a GOA circuit 200 integratedly arranged on the edge of the display area 100; wherein the structure and principle of the GOA circuit 200 are similar to the GOA circuit 10 described above, and will not be repeated here.

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Abstract

一种GOA电路及显示面板，不仅通过在下拉维持模块(105)加入第十三晶体管(T13)，降低第十一晶体管(T11)源极与漏极之间的压差，抑制第一节点(Q(n))漏电，提高第一节点(Q(n))的高温界限；还通过在下拉维持模块(205)加入第二十晶体管(T20)，降低第十九晶体管(T19)栅极与源极之间的压差，抑制第一节点(Q(n))漏电，提高第一节点(Q(n))的高温界限。

Description

GOA电路及显示面板 技术领域
本申请涉及移动通信技术领域，尤其涉及移动设备技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
由于现有产品均需要经过产品可靠性测试，而产品可靠性测试时间较长，而且在产品可靠性测试的时候需要保持高温。而GOA电路在高温条件，某些晶体管就会出现严重的漏电现象，从而造成GOA电路漏电现象严重，高温界限不足。
 技术问题
本申请实施例提供一种GOA电路及显示面板，可以解决现有GOA电路在进行产品可靠性测试时GOA电路漏电现象严重，高温界限不足的技术问题。
 技术解决方案
本申请实施例一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、下拉维持模块以及自举电容；
所述节点控制模块接入电源信号以及上一级级传信号，并电性连接于第一节点，所述节点控制模块用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
所述级传模块接入本级时钟信号，并电性连接于所述第一节点，所述级传模块用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，所述下拉模块用于在所述下一级级传信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级级传信号的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
所述下拉维持模块接入电源信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点，所述下拉维持模块用于根据所述第一控制信号、所述第一参考低电平信号以及所述第二参考低电平信号维持所述第一节点的电位以及所述本级扫描信号的电位；其中，所述下拉维持模块还用于当所述第一节点处于高电位时，抑制所述第一节点漏电；
所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
在一些实施例中，所述节点控制模块包括第一晶体管；所述第一晶体管的栅极电性连接于所述上一级级传信号，所述第一晶体管的源极电性连接于所述电源信号，所述第一晶体管的漏极电性连接于所述第一节点。
在一些实施例中，所述级传模块包括第二晶体管；所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
在一些实施例中，所述上拉模块包括第三晶体管；所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
在一些实施例中，所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级级传信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在一些实施例中，所述下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述电源信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极电性连接，所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极、所述第十一晶体管的漏极以及所述第十三晶体管的栅极、源极均电连接于所述第一节点，所述第十晶体管的漏极电性连接于本级扫描信号，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电压信号、所述第十晶体管的源极电性连接于所述第二参考低电压信号、所述第十一晶体管的源极、所述第十二晶体管的漏极以及所述第十三晶体管的漏极电性连接于第三节点。
在一些实施例中，当所述第一节点处于高电位时，所述第十三晶体管打开，以降低所述第十一晶体管源极与漏极之间的压差，抑制所述第一节点漏电。
在一些实施例中，所述下拉维持模块包括第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管以及第二十晶体管；
所述第十四晶体管的栅极、源极以及所述第十五晶体管的源极均电性连接于所述电源信号，所述第十四晶体管的漏极、所述第十五晶体管的栅极以及所述第十六晶体管的漏极电性连接，所述第十五晶体管的漏极、所述第十七晶体管的漏极、所述第十八晶体管的栅极、所述第十九晶体管的栅极以及所述第二十晶体管的漏极均电性连接于所述第二节点，所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十九晶体管的漏极均电连接于所述第一节点，所述第十六晶体管的源极、所述第十七晶体管的源极、所述第十九晶体管的源极以及所述第二十晶体管的源极均电性连接于所述第一参考低电压信号，所述第十八晶体管的源极电性连接于所述第二参考低电压信号，所述第十八晶体管的漏极电性连接于所述本级扫描信号，所述第二十晶体管的栅极电连接于所述本级级传信号。
在一些实施例中，当所述本级扫描信号和所述本级级传信号处于高电位时，所述第十四晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管以及所述第二十晶体管打开，以降低所述第十九晶体管栅极与源极之间的压差，抑制所述第一节点漏电。
本申请实施例还提供一种显示面板，包括GOA电路，且所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、下拉维持模块以及自举电容；
所述节点控制模块接入电源信号以及上一级级传信号，并电性连接于第一节点，所述节点控制模块用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
所述级传模块接入本级时钟信号，并电性连接于所述第一节点，所述级传模块用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，所述下拉模块用于在所述下一级级传信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级级传信号的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
所述下拉维持模块接入电源信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点，所述下拉维持模块用于根据所述第一控制信号、所述第一参考低电平信号以及所述第二参考低电平信号维持所述第一节点的电位以及所述本级扫描信号的电位；其中，所述下拉维持模块还用于当所述第一节点处于高电位时，抑制所述第一节点漏电；
所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
在一些实施例中，所述节点控制模块包括第一晶体管；所述第一晶体管的栅极电性连接于所述上一级级传信号，所述第一晶体管的源极电性连接于所述电源信号，所述第一晶体管的漏极电性连接于所述第一节点。
在一些实施例中，所述级传模块包括第二晶体管；所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
在一些实施例中，所述上拉模块包括第三晶体管；所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
在一些实施例中，所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级级传信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在一些实施例中，所述下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述电源信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极电性连接，所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极、所述第十一晶体管的漏极以及所述第十三晶体管的栅极、源极均电连接于所述第一节点，所述第十晶体管的漏极电性连接于本级扫描信号，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电压信号、所述第十晶体管的源极电性连接于所述第二参考低电压信号、所述第十一晶体管的源极、所述第十二晶体管的漏极以及所述第十三晶体管的漏极电性连接于第三节点。
在一些实施例中，当所述第一节点处于高电位时，所述第十三晶体管打开，以降低所述第十一晶体管源极与漏极之间的压差，抑制所述第一节点漏电。
在一些实施例中，所述下拉维持模块包括第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管以及第二十晶体管；
所述第十四晶体管的栅极、源极以及所述第十五晶体管的源极均电性连接于所述电源信号，所述第十四晶体管的漏极、所述第十五晶体管的栅极以及所述第十六晶体管的漏极电性连接，所述第十五晶体管的漏极、所述第十七晶体管的漏极、所述第十八晶体管的栅极、所述第十九晶体管的栅极以及所述第二十晶体管的漏极均电性连接于所述第二节点，所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十九晶体管的漏极均电连接于所述第一节点，所述第十六晶体管的源极、所述第十七晶体管的源极、所述第十九晶体管的源极以及所述第二十晶体管的源极均电性连接于所述第一参考低电压信号，所述第十八晶体管的源极电性连接于所述第二参考低电压信号，所述第十八晶体管的漏极电性连接于所述本级扫描信号，所述第二十晶体管的栅极电连接于所述本级级传信号。
 有益效果
本申请实施例提供的GOA电路及显示面板，不仅可以通过在下拉维持模块加入第十三晶体管，从而降低第十一晶体管源极与漏极之间的压差，进而抑制所述第一节点漏电，提高第一节点的高温界限，还可以通过在下拉维持模块加入第二十晶体管，从而降低第十九晶体管栅极与源极之间的压差，进而抑制所述第一节点漏电，提高第一节点的高温界限。
对附图的简要说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的GOA电路的结构示意图。
图2为本申请实施例提供的GOA电路中一GOA单元的第一电路示意图。
图3为本申请实施例提供的GOA电路中一GOA单元的第二电路示意图。
图4为本申请实施例提供的GOA电路中一GOA单元的第三电路示意图。
图5为本申请实施例提供的GOA电路中一GOA单元的信号时序图。
图6为本申请实施例提供的显示面板的结构示意图。
发明实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管均为N 型晶体管或P型晶体管，其中，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止；P 型晶体管为在栅极为低电平时导通，在栅极为高电平时截止。
请参阅图1，图1为本申请实施例提供的GOA电路的结构示意图。如图1所示，本申请实施例提供的GOA电路10包括多级级联的GOA单元20。每一级GOA单元20均用于输出一扫描信号以及一级传信号。其中，当该GOA电路10工作时，第一级GOA单元20接入起始信号STV，随后，第二级GOA单元20、第三级GOA单元20，……，最后一级GOA单元20依次级传启动。
进一步的，请参阅图2，图2为本申请实施例提供的GOA电路中一GOA单元的第一电路示意图。如图2所示，该GOA单元20包括：节点控制模块、级传模块、上拉模块、下拉模块、下拉维持模块以及自举电容Cbt。
其中，节点控制模块接入电源信号VDD以及上一级级传信号ST（n-1），并电性连接于第一节点Q(n)，用于根据电源信号VDD以及上一级级传信号ST（n-1）控制第一节点Q(n)的电位。
其中，级传模块接入本级时钟信号CK，并电性连接于第一节点Q(n)，用于在第一节点Q(n)的电位控制下输出本级级传信号ST（n）。
其中，上拉模块接入本级时钟信号CK，并电性连接于第一节点Q(n)，用于在第一节点Q(n)的电位控制下输出本级扫描信号G（n）。
其中，下拉模块接入下一级级传信号ST（n+1）、第一参考低电平信号VSSQ以及第二参考低电平信号VSSG，并电性连接于第一节点Q(n)以及本级扫描信号G（n），用于在下一级级传信号ST（n+1）的控制下将第一节点Q(n)的电位下拉至第一参考低电平信号VSSQ的电位，以及在下一级级传信号ST（n+1）的控制下将本级扫描信号G（n）下拉至第二参考低电平信号VSSG的电位。
其中，所述下拉维持模块接入电源信号VDD、所述第一参考低电平信号VSSQ以及所述第二参考低电平信号VSSG，并电性连接于所述第一节点Q(n)，所述下拉维持模块105用于根据所述电源信号VDD、所述第一参考低电平信号VSSQ以及所述第二参考低电平信号VSSG维持所述第一节点Q(n)的电位以及所述本级扫描信号G（n）的电位；其中，所述下拉维持模块还用于当所述第一节点Q(n)处于高电位时，抑制所述第一节点Q(n)漏电。
其中，自举电容Cbt的第一端电性连接于第一节点Q(n)，自举电容Cbt的第二端电性连接于本级扫描信号G（n）。
进一步的，请参阅图2、图3，图3为本申请实施例提供的GOA电路中一GOA单元的第二电路示意图。如图3所示，该GOA单元20包括：节点控制模块101、级传模块102、上拉模块103、下拉模块104、下拉维持模块105以及自举电容Cbt。
在一些实施例中，节点控制模块101包括第一晶体管T1；第一晶体管T1的栅极电性连接于上一级级传信号ST（n-1），第一晶体管T1的源极电性连接于电源信号VDD，第一晶体管T1的漏极电性连接于第一节点Q(n)。
在一些实施例中，级传模块102包括第二晶体管T2；第二晶体管T2的栅极电性连接于第一节点Q(n)，第二晶体管T2的源极电性连接于本级时钟信号CK，第二晶体管T2的漏极电性连接于本级级传信号ST（n）。
在一些实施例中，上拉模块103包括第三晶体管T3；第三晶体管T3的栅极电性连接于第一节点Q(n)，第三晶体管T3的源极电性连接于本级时钟信号CK，第三晶体管T3的漏极电性连接于本级扫描信号G（n）。
在一些实施例中，下拉模块104包括第四晶体管T4以及第五晶体管T5；第四晶体管T4的栅极以及第五晶体管T5的栅极均电性连接于下一级级传信号ST（n+1），第四晶体管T4的源极电性连接于第一参考低电平信号VSSQ，第四晶体管T4的漏极电性连接于第一节点Q(n)，第五晶体管T5的源极电性连接于第二参考低电平信号VSSG，第五晶体管T5的漏极电性连接于本级扫描信号G（n）。
在一些实施例中，所述下拉维持模块105包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12以及第十三晶体管T13；第六晶体管T6的栅极、源极以及第七晶体管T7的源极均电性连接于所述电源信号VDD，第六晶体管T6的漏极、第七晶体管T7的栅极以及第八晶体管T8的漏极电性连接，第七晶体管T7的漏极、第九晶体管T9的漏极、第十晶体管T10的栅极、第十一晶体管T11的栅极以及第十二晶体管T12的栅极均电性连接于所述第二节点P（n），第八晶体管T8的栅极、第九晶体管T9的栅极、第十一晶体管T11的漏极以及第十三晶体管T13的栅极、源极均电连接于所述第一节点Q(n)，第十晶体管T10的漏极电性连接于本级扫描信号G(n)，第八晶体管T8、第九晶体管T9的源极以及第十二晶体管T12的源极均电性连接于所述第一参考低电压信号VSSQ、第十晶体管T10的源极电性连接于所述第二参考低电压信号VSSG、第十一晶体管T11的源极、第十二晶体管T12的漏极以及第十三晶体管T13的漏极电性连接于第三节点A。
进一步的，请参阅图2、图4，图4为本申请实施例提供的GOA电路中一GOA单元的第三电路示意图。如图4所示，该GOA单元20包括：节点控制模块201、级传模块202、上拉模块203、下拉模块204、下拉维持模块205以及自举电容Cbt。
其中，节点控制模块201与节点控制模块101结构一致，所起到的作用一致；
级传模块202与级传模块102结构一致，所起到的作用一致；上拉模块203与上拉模块103结构一致，所起到的作用一致；下拉模块204与下拉模块104结构一致，所起到的作用一致；所以节点控制模块201、级传模块202、上拉模块203以及下拉模块204的具体结构就不在此一一赘述，参考上述实施例即可。
在一些实施例中，所述下拉维持模块205包括第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17、第十八晶体管T18、第十九晶体管T19以及第二十晶体管T20；
第十四晶体管T14的栅极、源极以及第十五晶体管T15的源极均电性连接于所述电源信号，第十四晶体管T14的漏极、第十五晶体管T15的栅极以及第十六晶体管T16的漏极电性连接，第十五晶体管T15的漏极、第十七晶体管T17的漏极、第十八晶体管T18的栅极、第十九晶体管T19的栅极以及第二十晶体管T20的漏极均电性连接于所述第二节点P（n），第十六晶体管T16的栅极、第十七晶体管T17的栅极以及第十九晶体管T19的漏极均电连接于所述第一节点Q（n），第十六晶体管T16的源极、第十七晶体管T17的源极、第十九晶体管T19的源极以及第二十晶体管T20的源极均电性连接于所述第一参考低电压信号VSSQ，第十八晶体管T18的源极电性连接于所述第二参考低电压信号VSSG，第十八晶体管T18的漏极电性连接于所述本级扫描信号G（n），第二十晶体管T20的栅极电连接于所述本级级传信号ST（n）。
具体的，请结合图3、图5，图5为本申请实施例提供的GOA电路中一GOA单元的信号时序图。当上一级级传信号ST（n-1）为高电平，电源信号VDD为高电位时，第一晶体管T1导通，电源信号VDD通过第一晶体管T1给自举电容Cbt充电，使得第一节点Q(n)的电位上升到一较高的电位。
随后，上一级级传信号ST（n-1）转为低电平，第一晶体管T1关闭，第一节点Q(n)的电位通过自举电容Cbt维持一较高的电位。同时，本级时钟信号CK的电位转为高电位，本级时钟信号CK通过第二晶体管T2继续给自举电容Cbt充电，使得第一节点Q(n)的电位达到一更高的电位，本级扫描信号G（n）和本级级传信号ST（n）也转为高电位，而电源信号VDD也为高电位，从而使第六晶体管T6、第七晶体管T7、第八晶体管T8以及第九晶体管T9打开，使第二节点P(n)的电位维持在第一参考低电平信号VSSQ的电位。
接着，当下一级级传信号ST（n+1）转为高电平时，第四晶体管T4和第五晶体管T5打开，第一参考低电平信号VSSQ将第一节点Q(n)的电位拉低，第二参考低电平信号VSSG将本级扫描信号G（n）拉低。
最后，由于第一节点Q(n)的电位转为低电位，使得第八晶体管T8和第九晶体管T9关闭，同时，电源信号VDD为高电位，使得第六晶体管T6和第七晶体管T7打开，使第二节点P(n)的电位拉升至高电位，第十晶体管T10、第十一晶体管T11以及第十二晶体管T12打开，第一参考低电平信号VSSQ维持第一节点Q(n)的电位至第一参考低电平信号VSSQ的电位，进而维持本级扫描信号G（n）的电位至第二参考低电平信号VSSG的电位。
特别的，本申请实施例通过在下拉维持模块105中增加第十三晶体管T13，从而可以在第一节点Q（n）处于高电位时，使第十三晶体管T13打开，从而可以对第三节点A充电，使第三节点A拉升至高电位，降低第十一晶体管T11源极与漏极之间的压差；因晶体管的漏电大小主要取决于晶体管源极与漏极之间的压差和晶体管栅极与源极之间的压差，当晶体管栅极与源极之间的压差固定时，晶体管源极与漏极之间的压差越大，漏电越严重，晶体管源极与漏极之间的压差固定时，晶体管栅极与源极之间的压差越小，漏电越小，且在一定的区域内最佳；所以降低第十一晶体管T11源极与漏极之间的压差，可以达到抑制第十一晶体管T11漏电的效果，进而可以抑制第一节点Q（n）漏电，提高第一节点Q（n）的高温界限。
具体的，请结合图4、图5。当上一级级传信号ST（n-1）为高电平，电源信号VDD为高电位时，第一晶体管T1导通，电源信号VDD通过第一晶体管T1给自举电容Cbt充电，使得第一节点Q(n)的电位上升到一较高的电位。
随后，上一级级传信号ST（n-1）转为低电平，第一晶体管T1关闭，第一节点Q(n)的电位通过自举电容Cbt维持一较高的电位。同时，本级时钟信号CK的电位转为高电位，本级时钟信号CK通过第二晶体管T2继续给自举电容Cbt充电，使得第一节点Q(n)的电位达到一更高的电位，本级扫描信号G（n）和本级级传信号ST（n）也转为高电位，而电源信号VDD也为高电位，从而使第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17以及第二十晶体管T20打开，使第二节点P(n)的电位维持在第一参考低电平信号VSSQ的电位。
接着，当下一级级传信号ST（n+1）转为高电平时，第四晶体管T4和第五晶体管T5打开，第一参考低电平信号VSSQ将第一节点Q(n)的电位拉低，第二参考低电平信号VSSG将本级扫描信号G（n）拉低。
最后，由于第一节点Q(n)的电位转为低电位，使得第十六晶体管T16和第十七晶体管T17关闭，同时，电源信号VDD为高电位，使得第十四晶体管T14和第十五晶体管T15打开，使第二节点P(n)的电位拉升至高电位，第十八晶体管T18以及第十九晶体管T19打开，第一参考低电平信号VSS1维持第一节点Q(n)的电位至第一参考低电平信号VSSQ的电位，进而维持本级扫描信号G（n）的电位至第二参考低电平信号VSSG的电位。
特别的，本申请实施例通过在下拉维持模块205中增加第二十晶体管T20，从而可以在第一节点Q（n）和本级级传信号ST（n）处于高电位时，使第二十晶体管T20打开，从而可以使第二节点P（n）更好的维持在第一参考低电平信号VSSQ的电位，进而降低第十九晶体管T19源极与栅极之间的压差；因晶体管的漏电大小主要取决于晶体管源极与漏极之间的压差和晶体管栅极与源极之间的压差，当晶体管栅极与源极之间的压差固定时，晶体管源极与漏极之间的压差越大，漏电越严重，晶体管源极与漏极之间的压差固定时，晶体管栅极与源极之间的压差越小，漏电越小，且在一定的区域内最佳；所以降低第十九晶体管T19源极与栅极之间的压差，可以达到抑制第十九晶体管T19漏电的效果，进而可以抑制第一节点Q（n）漏电，提高第一节点Q（n）的高温界限。
请参阅图6，图6为本申请实施例提供的显示面板的结构示意图。如图5所示，该显示面板包括显示区域100以及集成设置在显示区域100边缘上的GOA电路200；其中，该GOA电路200与上述的GOA电路10的结构和原理类似，这里不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种电子装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、下拉维持模块以及自举电容；
    所述节点控制模块接入电源信号以及上一级级传信号，并电性连接于第一节点，所述节点控制模块用于根据所述电源信号以及所述上一级级传信号控制所述第一节点的电位；
    所述级传模块接入本级时钟信号，并电性连接于所述第一节点，所述级传模块用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级级传信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，所述下拉模块用于在所述下一级级传信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级级传信号的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
    所述下拉维持模块接入电源信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点，所述下拉维持模块用于根据所述电源信号、所述第一参考低电平信号以及所述第二参考低电平信号维持所述第一节点的电位以及所述本级扫描信号的电位；其中，所述下拉维持模块还用于当所述第一节点处于高电位时，抑制所述第一节点漏电；
    所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
  2. 根据权利要求1所述的GOA电路，其中，所述节点控制模块包括第一晶体管；
    所述第一晶体管的栅极电性连接于所述上一级级传信号，所述第一晶体管的源极电性连接于所述电源信号，所述第一晶体管的漏极电性连接于所述第一节点。
  3. 根据权利要求1所述的GOA电路，其中，所述级传模块包括第二晶体管；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
  4. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括第四晶体管以及第五晶体管；
    所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级级传信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  6. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
    所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述电源信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极电性连接，所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极、所述第十一晶体管的漏极以及所述第十三晶体管的栅极、源极均电连接于所述第一节点，所述第十晶体管的漏极电性连接于本级扫描信号，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电压信号、所述第十晶体管的源极电性连接于所述第二参考低电压信号、所述第十一晶体管的源极、所述第十二晶体管的漏极以及所述第十三晶体管的漏极电性连接于第三节点。
  7. 根据权利要求6所述的GOA电路，其中，当所述第一节点处于高电位时，所述第十三晶体管打开，以降低所述第十一晶体管源极与漏极之间的压差，抑制所述第一节点漏电。
  8. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管以及第二十晶体管；
    所述第十四晶体管的栅极、源极以及所述第十五晶体管的源极均电性连接于所述电源信号，所述第十四晶体管的漏极、所述第十五晶体管的栅极以及所述第十六晶体管的漏极电性连接，所述第十五晶体管的漏极、所述第十七晶体管的漏极、所述第十八晶体管的栅极、所述第十九晶体管的栅极以及所述第二十晶体管的漏极均电性连接于所述第二节点，所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十九晶体管的漏极均电连接于所述第一节点，所述第十六晶体管的源极、所述第十七晶体管的源极、所述第十九晶体管的源极以及所述第二十晶体管的源极均电性连接于所述第一参考低电压信号，所述第十八晶体管的源极电性连接于所述第二参考低电压信号，所述第十八晶体管的漏极电性连接于所述本级扫描信号，所述第二十晶体管的栅极电连接于所述本级级传信号。
  9. 根据权利要求8所述的GOA电路，其中，当所述本级扫描信号和所述本级级传信号处于高电位时，所述第十四晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管以及所述第二十晶体管打开，以降低所述第十九晶体管栅极与源极之间的压差，抑制所述第一节点漏电。
  10. 一种显示面板，其包括GOA电路，且所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、下拉维持模块以及自举电容；
    所述节点控制模块接入电源信号以及上一级级传信号，并电性连接于第一节点，所述节点控制模块用于根据所述电源信号以及所述上一级级传信号控制所述第一节点的电位；
    所述级传模块接入本级时钟信号，并电性连接于所述第一节点，所述级传模块用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，所述上拉模块用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级级传信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，所述下拉模块用于在所述下一级级传信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级级传信号的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
    所述下拉维持模块接入电源信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点，所述下拉维持模块用于根据所述电源信号、所述第一参考低电平信号以及所述第二参考低电平信号维持所述第一节点的电位以及所述本级扫描信号的电位；其中，所述下拉维持模块还用于当所述第一节点处于高电位时，抑制所述第一节点漏电；
    所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
  11. 根据权利要求10所述的GOA电路，其中，所述节点控制模块包括第一晶体管；
    所述第一晶体管的栅极电性连接于所述上一级级传信号，所述第一晶体管的源极电性连接于所述电源信号，所述第一晶体管的漏极电性连接于所述第一节点。
  12. 根据权利要求10所述的GOA电路，其中，所述级传模块包括第二晶体管；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
  13. 根据权利要求10所述的GOA电路，其中，所述上拉模块包括第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
  14. 根据权利要求10所述的GOA电路，其中，所述下拉模块包括第四晶体管以及第五晶体管；
    所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级级传信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  15. 根据权利要求10所述的GOA电路，其中，所述下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
    所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述电源信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极电性连接，所述第七晶体管的漏极、所述第九晶体管的漏极、所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极、所述第十一晶体管的漏极以及所述第十三晶体管的栅极、源极均电连接于所述第一节点，所述第十晶体管的漏极电性连接于本级扫描信号，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电压信号、所述第十晶体管的源极电性连接于所述第二参考低电压信号、所述第十一晶体管的源极、所述第十二晶体管的漏极以及所述第十三晶体管的漏极电性连接于第三节点。
  16. 根据权利要求15所述的GOA电路，其中，当所述第一节点处于高电位时，所述第十三晶体管打开，以降低所述第十一晶体管源极与漏极之间的压差，抑制所述第一节点漏电。
  17. 根据权利要求10所述的GOA电路，其中，所述下拉维持模块包括第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管以及第二十晶体管；
    所述第十四晶体管的栅极、源极以及所述第十五晶体管的源极均电性连接于所述电源信号，所述第十四晶体管的漏极、所述第十五晶体管的栅极以及所述第十六晶体管的漏极电性连接，所述第十五晶体管的漏极、所述第十七晶体管的漏极、所述第十八晶体管的栅极、所述第十九晶体管的栅极以及所述第二十晶体管的漏极均电性连接于所述第二节点，所述第十六晶体管的栅极、所述第十七晶体管的栅极以及所述第十九晶体管的漏极均电连接于所述第一节点，所述第十六晶体管的源极、所述第十七晶体管的源极、所述第十九晶体管的源极以及所述第二十晶体管的源极均电性连接于所述第一参考低电压信号，所述第十八晶体管的源极电性连接于所述第二参考低电压信号，所述第十八晶体管的漏极电性连接于所述本级扫描信号，所述第二十晶体管的栅极电连接于所述本级级传信号。
  18. 根据权利要求14所述的GOA电路，其中，当所述本级扫描信号和所述本级级传信号处于高电位时，所述第十四晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管以及所述第二十晶体管打开，以降低所述第十九晶体管栅极与源极之间的压差，抑制所述第一节点漏电。
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CN115862514A (zh) * 2022-12-16 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862514B (zh) * 2022-12-16 2024-03-15 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

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