WO2020206816A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2020206816A1
WO2020206816A1 PCT/CN2019/087626 CN2019087626W WO2020206816A1 WO 2020206816 A1 WO2020206816 A1 WO 2020206816A1 CN 2019087626 W CN2019087626 W CN 2019087626W WO 2020206816 A1 WO2020206816 A1 WO 2020206816A1
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WIPO (PCT)
Prior art keywords
transistor
signal
electrically connected
level
node
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Application number
PCT/CN2019/087626
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English (en)
French (fr)
Inventor
奚苏萍
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深圳市华星光电技术有限公司
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Publication of WO2020206816A1 publication Critical patent/WO2020206816A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA full name in English: Gate Driver on Array, full name in Chinese: integrated gate drive circuit
  • GOA full name in English: Gate Driver on Array, full name in Chinese: integrated gate drive circuit
  • the existing GOA circuit needs to maintain the low level of the horizontal scanning signal for a period of time after outputting the horizontal scanning signal of the current stage GOA unit.
  • the transistor works for a long time, the electrical properties of the transistor are easily damaged, which causes the GOA circuit to fail to work normally.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem of the conventional GOA circuit that the transistor is easily damaged due to long-time operation of the transistor, which causes the GOA circuit to fail to work normally.
  • An embodiment of the present application provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes: a node control module, a level transmission module, a pull-up module, a pull-down module, a first pull-down maintenance module, The second pull-down maintenance module and the bootstrap capacitor;
  • the node control module accesses the upper-level scanning signal and the upper-level transmission signal, and is electrically connected to the first node, and is used to control the station according to the upper-level scanning signal and the upper-level transmission signal The potential of the first node;
  • the level transmission module is connected to the clock signal of the current level, and is electrically connected to the first node, for outputting the level transmission signal of the current level under the control of the potential of the first node;
  • the pull-up module is connected to the clock signal of the current level and is electrically connected to the first node for outputting the scan signal of the current level under the control of the potential of the first node;
  • the pull-down module is connected to the next-level scan signal, the first reference low-level signal, and the second reference low-level signal, and is electrically connected to the first node and the current-level scan signal for Under the control of the next-level scan signal, the potential of the first node is pulled down to the potential of the first reference low-level signal, and the current level is scanned under the control of the next-level scan signal The signal is pulled down to the potential of the second reference low level signal;
  • Both the first pull-down maintenance module and the second pull-down maintenance module are connected to a first control signal, a second control signal, a third reference low level signal, and the first reference low level signal, and are electrically connected Is connected to the first node, and is used to maintain the first control signal, the second control signal, the third reference low level signal, and the first reference low level signal.
  • the potential of the node, and the first pull-down maintenance module and the second pull-down maintenance module work alternately;
  • the first end of the bootstrap capacitor is electrically connected to the first node, and the second end of the bootstrap capacitor is electrically connected to the scan signal of the current level;
  • the potential of the first reference low-level signal is greater than the potential of the third reference low-level signal, and the potential of the second reference low-level signal is greater than the potential of the third reference low-level signal;
  • the phase of the first control signal is opposite to the phase of the second control signal.
  • the node control module includes a first transistor
  • the gate of the first transistor is electrically connected to the upper-level scanning signal, the source of the first transistor is electrically connected to the upper-level transmission signal, and the drain of the first transistor is electrically connected Sexually connected to the first node.
  • the stage transfer module includes a second transistor
  • the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the local clock signal, and the drain of the second transistor is electrically connected to the Describe the transmission signal at this level.
  • the pull-up module includes a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the local clock signal, and the drain of the third transistor is electrically connected to all Describe the scan signal at this level.
  • the pull-down module includes a fourth transistor and a fifth transistor
  • the gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the next-stage scan signal, and the source of the fourth transistor is electrically connected to the first reference low level Signal, the drain of the fourth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the second reference low level signal, and the drain of the fifth transistor It is electrically connected to the scanning signal of the current level.
  • the first pull-down sustaining module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate and source of the sixth transistor and the source of the seventh transistor are all electrically connected to the first control signal, the drain of the sixth transistor, the gate of the seventh transistor, and The drain of the ninth transistor is electrically connected, and the drain of the seventh transistor, the drain of the eighth transistor, the drain of the tenth transistor, and the gate of the eleventh transistor are all electrically connected.
  • the gate of the eighth transistor, the gate of the ninth transistor, and the drain of the eleventh transistor are electrically connected to the first node, and the eighth transistor
  • the source of the ninth transistor and the source of the eleventh transistor are all electrically connected to the first reference low level signal, and the gate of the tenth transistor is electrically connected to all
  • the source of the tenth transistor is electrically connected to the third reference low level signal.
  • the second pull-down sustain module includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;
  • the gate and source of the twelfth transistor and the source of the thirteenth transistor are all electrically connected to the second control signal, and the drain of the twelfth transistor and the thirteenth transistor
  • the gate and the drain of the fifteenth transistor are electrically connected, the drain of the thirteenth transistor, the drain of the fourteenth transistor, the drain of the sixteenth transistor, and the
  • the gates of the seventeenth transistor are electrically connected to the third node, and the gates of the fourteenth transistor, the gate of the fifteenth transistor, and the drain of the seventeenth transistor are all electrically connected to all
  • the first node, the source of the fourteenth transistor, the source of the fifteenth transistor, and the source of the sixteenth transistor are all electrically connected to the first reference low level signal, so
  • the gate of the seventeenth transistor is electrically connected to the first control signal, and the source of the seventeenth transistor is electrically connected to the third reference low level signal.
  • An embodiment of the present application also provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes: a node control module, a stage transfer module, a pull-up module, a pull-down module, and a first pull-down maintenance module , The second pull-down maintenance module and the bootstrap capacitor;
  • the node control module accesses the upper-level scanning signal and the upper-level transmission signal, and is electrically connected to the first node, and is used to control the station according to the upper-level scanning signal and the upper-level transmission signal The potential of the first node;
  • the level transmission module is connected to the clock signal of the current level, and is electrically connected to the first node, for outputting the level transmission signal of the current level under the control of the potential of the first node;
  • the pull-up module is connected to the clock signal of the current level and is electrically connected to the first node for outputting the scan signal of the current level under the control of the potential of the first node;
  • the pull-down module is connected to the next-level scan signal, the first reference low-level signal, and the second reference low-level signal, and is electrically connected to the first node and the current-level scan signal for Under the control of the next-level scan signal, the potential of the first node is pulled down to the potential of the first reference low-level signal, and the current level is scanned under the control of the next-level scan signal The signal is pulled down to the potential of the second reference low level signal;
  • Both the first pull-down maintenance module and the second pull-down maintenance module are connected to a first control signal, a second control signal, a third reference low level signal, and the first reference low level signal, and are electrically connected Is connected to the first node, and is used to maintain the first control signal, the second control signal, the third reference low level signal, and the first reference low level signal.
  • the potential of the node, and the first pull-down maintenance module and the second pull-down maintenance module work alternately;
  • the first end of the bootstrap capacitor is electrically connected to the first node, and the second end of the bootstrap capacitor is electrically connected to the scan signal of the current level.
  • the node control module includes a first transistor
  • the gate of the first transistor is electrically connected to the upper-level scanning signal, the source of the first transistor is electrically connected to the upper-level transmission signal, and the drain of the first transistor is electrically connected Sexually connected to the first node.
  • the stage transfer module includes a second transistor
  • the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the local clock signal, and the drain of the second transistor is electrically connected to the Describe the transmission signal at this level.
  • the pull-up module includes a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the local clock signal, and the drain of the third transistor is electrically connected to all Describe the scan signal at this level.
  • the pull-down module includes a fourth transistor and a fifth transistor
  • the gate of the fourth transistor and the gate of the fifth transistor are both electrically connected to the next-stage scan signal, and the source of the fourth transistor is electrically connected to the first reference low level Signal, the drain of the fourth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the second reference low level signal, and the drain of the fifth transistor It is electrically connected to the scanning signal of the current level.
  • the first pull-down sustaining module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
  • the gate and source of the sixth transistor and the source of the seventh transistor are all electrically connected to the first control signal, the drain of the sixth transistor, the gate of the seventh transistor, and The drain of the ninth transistor is electrically connected, and the drain of the seventh transistor, the drain of the eighth transistor, the drain of the tenth transistor, and the gate of the eleventh transistor are all electrically connected.
  • the gate of the eighth transistor, the gate of the ninth transistor, and the drain of the eleventh transistor are electrically connected to the first node, and the eighth transistor
  • the source of the ninth transistor and the source of the eleventh transistor are all electrically connected to the first reference low level signal, and the gate of the tenth transistor is electrically connected to all
  • the source of the tenth transistor is electrically connected to the third reference low level signal.
  • the second pull-down sustain module includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;
  • the gate and source of the twelfth transistor and the source of the thirteenth transistor are all electrically connected to the second control signal, and the drain of the twelfth transistor and the thirteenth transistor
  • the gate and the drain of the fifteenth transistor are electrically connected, the drain of the thirteenth transistor, the drain of the fourteenth transistor, the drain of the sixteenth transistor, and the
  • the gates of the seventeenth transistor are electrically connected to the third node, and the gates of the fourteenth transistor, the gate of the fifteenth transistor, and the drain of the seventeenth transistor are all electrically connected to all
  • the first node, the source of the fourteenth transistor, the source of the fifteenth transistor, and the source of the sixteenth transistor are all electrically connected to the first reference low level signal, so
  • the gate of the seventeenth transistor is electrically connected to the first control signal, and the source of the seventeenth transistor is electrically connected to the third reference low level signal.
  • the potential of the first reference low-level signal is greater than the potential of the third reference low-level signal
  • the potential of the second reference low-level signal is greater than that of the third reference low-level signal. Refer to the potential of the low-level signal.
  • the phase of the first control signal is opposite to the phase of the second control signal.
  • An embodiment of the present application also provides a display panel including a GOA circuit
  • the GOA circuit includes: multi-level cascaded GOA units, each level of GOA unit includes: node control module, level transmission module, pull-up module, pull-down module Module, first pull-down maintenance module, second pull-down maintenance module, and bootstrap capacitor;
  • the node control module accesses the upper-level scanning signal and the upper-level transmission signal, and is electrically connected to the first node, and is used to control the station according to the upper-level scanning signal and the upper-level transmission signal The potential of the first node;
  • the level transmission module is connected to the clock signal of the current level, and is electrically connected to the first node, for outputting the level transmission signal of the current level under the control of the potential of the first node;
  • the pull-up module is connected to the clock signal of the current level and is electrically connected to the first node for outputting the scan signal of the current level under the control of the potential of the first node;
  • the pull-down module is connected to the next-level scan signal, the first reference low-level signal, and the second reference low-level signal, and is electrically connected to the first node and the current-level scan signal for Under the control of the next-level scan signal, the potential of the first node is pulled down to the potential of the first reference low-level signal, and the current level is scanned under the control of the next-level scan signal The signal is pulled down to the potential of the second reference low level signal;
  • Both the first pull-down maintenance module and the second pull-down maintenance module are connected to a first control signal, a second control signal, a third reference low level signal, and the first reference low level signal, and are electrically connected Is connected to the first node, and is used to maintain the first control signal, the second control signal, the third reference low level signal, and the first reference low level signal.
  • the potential of the node, and the first pull-down maintenance module and the second pull-down maintenance module work alternately;
  • the first end of the bootstrap capacitor is electrically connected to the first node, and the second end of the bootstrap capacitor is electrically connected to the scan signal of the current level.
  • the node control module includes a first transistor
  • the gate of the first transistor is electrically connected to the upper-level scanning signal, the source of the first transistor is electrically connected to the upper-level transmission signal, and the drain of the first transistor is electrically connected Sexually connected to the first node.
  • the stage transfer module includes a second transistor
  • the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the local clock signal, and the drain of the second transistor is electrically connected to the Describe the transmission signal at this level.
  • the pull-up module includes a third transistor
  • the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the local clock signal, and the drain of the third transistor is electrically connected to all Describe the scan signal at this level.
  • the tenth transistor is added to the first pull-down sustaining module and the sixteenth transistor is added to the second pull-down sustaining module, so that the tenth and sixteenth transistors can be passed through
  • the transistor pulls down the second node and the third node to a lower potential, thereby improving the stability of the GOA circuit.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic circuit diagram of a GOA unit in the GOA circuit provided by an embodiment of this application;
  • FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application are all N-type transistors or P-type transistors, where the N-type transistor is turned on when the gate is high and turned off when the gate is low; and the P-type transistor is low when the gate is low. Turns on when the level is high, and turns off when the gate is high.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • the GOA circuit 10 provided by the embodiment of the present application includes multi-stage cascaded GOA units 20.
  • Each GOA unit 20 is used to output a scanning signal and a first-stage transmission signal.
  • the first-level GOA unit 20 is connected to the start signal STV, and then the second-level GOA unit 20, the third-level GOA unit 20, ..., the last-level GOA unit 20 are sequentially Pass start.
  • FIG. 2 is a schematic circuit diagram of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the GOA unit 20 includes: a node control module 101, a stage transfer module 102, a pull-up module 103, a pull-down module 104, a first pull-down maintenance module 105, a second pull-down maintenance module 106, and a bootstrap capacitor Cbt .
  • the node control module 101 is connected to the upper level scanning signal G(n-1) and the upper level transmission signal ST(n-1), and is electrically connected to the first node Q(n), which is used to follow the upper The first level scanning signal G(n-1) and the upper level transmission signal ST(n-1) control the potential of the first node Q(n).
  • the stage transmission module 102 is connected to the clock signal CK of the current stage and is electrically connected to the first node Q(n) for outputting the stage transmission signal ST(n) under the control of the potential of the first node Q(n). ).
  • the pull-up module 103 is connected to the clock signal CK of the current level and is electrically connected to the first node Q(n) for outputting the scan signal G(n) of the current level under the control of the potential of the first node Q(n) .
  • the pull-down module 104 is connected to the next level scan signal G(n+1), the first reference low level signal VSS1 and the second reference low level signal VSS2, and is electrically connected to the first node Q(n) and
  • the scan signal G(n) of the current stage is used to pull down the potential of the first node Q(n) to the potential of the first reference low level signal VSS1 under the control of the scan signal G(n+1) of the next stage, and Under the control of the first level scan signal G(n+1), the current level scan signal G(n) is pulled down to the potential of the second reference low level signal VSS2.
  • the first pull-down maintaining module 105 and the second pull-down maintaining module 106 are both connected to the first control signal LC1, the second control signal LC2, the third reference low level signal VSS3, and the first reference low level signal VSS1, and It is electrically connected to the first node Q(n), and is used to maintain the first node Q according to the first control signal LC1, the second control signal LC2, the third reference low level signal VSS3, and the first reference low level signal VSS1 (n), and the first pull-down maintaining module 105 and the second pull-down maintaining module 106 work alternately.
  • the first end of the bootstrap capacitor Cbt is electrically connected to the first node Q(n), and the second end of the bootstrap capacitor Cbt is electrically connected to the scan signal G(n) of the current stage.
  • the node control module 101 includes a first transistor T1; the gate of the first transistor T1 is electrically connected to the previous scan signal G(n-1), and the source of the first transistor T1 is electrically connected to The upper stage transmits the signal ST(n-1), and the drain of the first transistor T1 is electrically connected to the first node Q(n).
  • the stage transfer module 102 includes a second transistor T2; the gate of the second transistor T2 is electrically connected to the first node Q(n), and the source of the second transistor T2 is electrically connected to the clock signal of the current stage CK, the drain of the second transistor T2 is electrically connected to the transmission signal ST(n) of the current stage.
  • the pull-up module 103 includes a third transistor T3; the gate of the third transistor T3 is electrically connected to the first node Q(n), and the source of the third transistor T3 is electrically connected to the clock signal of this stage CK, the drain of the third transistor T3 is electrically connected to the scan signal G(n) of the current level.
  • the pull-down module 104 includes a fourth transistor T4 and a fifth transistor T5; the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are both electrically connected to the next-stage scanning signal G(n+1 ), the source of the fourth transistor T4 is electrically connected to the first reference low level signal VSS1, the drain of the fourth transistor T4 is electrically connected to the first node Q(n), and the source of the fifth transistor T5 is electrically connected Connected to the second reference low level signal VSS2, the drain of the fifth transistor T5 is electrically connected to the scanning signal G(n) of the current level.
  • the first pull-down sustain module 105 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11;
  • the gate, the source, and the source of the seventh transistor T7 are all electrically connected to the first control signal LC1, the drain of the sixth transistor T6, the gate of the seventh transistor T7, and the drain of the ninth transistor T9 are electrically connected ,
  • the drain of the seventh transistor T7, the drain of the eighth transistor T8, the drain of the tenth transistor T10, and the gate of the eleventh transistor T11 are all electrically connected to the second node a, and the gate of the eighth transistor T8 ,
  • the gate of the ninth transistor T9 and the drain of the eleventh transistor T11 are electrically connected to the first node Q(n), the source of the eighth transistor T8, the source of the ninth transistor T9, and the eleventh transistor
  • the sources of T11 are electrically connected to the first reference low level signal VSS1,
  • the second pull-down sustain module 106 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17;
  • the gate and source of the twelfth transistor T12 and the source of the thirteenth transistor T13 are electrically connected to the second control signal LC2, the drain of the twelfth transistor T12, the gate of the thirteenth transistor T13, and the tenth transistor T13 are electrically connected to the second control signal LC2.
  • the drain of the fifth transistor T15 is electrically connected, the drain of the thirteenth transistor T13, the drain of the fourteenth transistor T14, the drain of the sixteenth transistor T16, and the gate of the seventeenth transistor T17 are all electrically connected to The third node b, the gate of the fourteenth transistor T14, the gate of the fifteenth transistor T15, and the drain of the seventeenth transistor T17 are all electrically connected to the first node Q(n), and the gate of the fourteenth transistor T14
  • the source, the source of the fifteenth transistor T15, and the source of the sixteenth transistor T16 are all electrically connected to the first reference low level signal VSS1
  • the gate of the seventeenth transistor T17 is electrically connected to the first control signal LC1
  • the source of the seventeenth transistor T17 is electrically connected to the third reference low level signal VSS3.
  • the potential of the first reference low level signal VSS1 is greater than the potential of the third reference low level signal VSS3, and the potential of the second reference low level signal VSS2 is greater than the potential of the third reference low level.
  • the phase of the first control signal LC1 is opposite to the phase of the second control signal LC2.
  • FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by the embodiment of the application.
  • the first transistor T1 When the upper level transmission signal ST(n-1) is at high level and the upper level scanning signal G(n-1) is high level, the first transistor T1 is turned on, and the upper level transmission signal ST(n -1) The bootstrap capacitor Cbt is charged through the first transistor T1, so that the potential of the first node Q(n) rises to a higher potential.
  • the previous scan signal G(n-1) turns to a low level
  • the first transistor T1 is turned off
  • the potential of the first node Q(n) is maintained at a higher potential through the bootstrap capacitor Cbt.
  • the potential of the clock signal CK of this stage turns to a high potential
  • the clock signal CK of this stage continues to charge the bootstrap capacitor Cbt through the second transistor T2, so that the potential of the first node Q(n) reaches a higher potential.
  • the level scan signal G(n) and the current level transmission signal ST(n) also turn to high potential.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the first reference low level signal VSS1 pulls the potential of the first node Q(n) low ,
  • the second reference low level signal VSS2 pulls the scan signal G(n) of the current level low.
  • the eighth transistor T8 and the ninth transistor T9 are turned off.
  • the potential of the first control signal LC1 is high, so that the sixth transistor T6 and the seventh transistor T6 are turned off.
  • the transistor T7 is turned on, the first control signal LC1 is transmitted to the second node a, so that the eleventh transistor T11 is turned on, and the first reference low level signal VSS1 maintains the potential of the first node Q(n) to the first reference low level signal
  • the potential of VSS1 in turn maintains the potential of the scanning signal G(n) of this level.
  • the tenth transistor T10 is added to the first pull-down sustaining module 105, and the sixteenth transistor T16 is added to the second pull-down sustaining module 106, so that the tenth transistor T10 and the sixteenth transistor T10 can be used.
  • the transistor T16 pulls down the second node a and the third node b to a lower potential, thereby improving the stability of the GOA circuit.
  • the first pull-down sustain module 105 because the first control signal LC1 is at a high potential, the sixth transistor T6 and the seventh transistor T7 are turned on, the tenth transistor T10 is turned off, and the first control signal LC1 is transmitted to the second node a, The eleventh transistor T11 is turned on, and the first reference low-level signal VSS1 maintains the potential of the first node Q(n) to the potential of the first reference low-level signal VSS1, thereby maintaining the potential of the scanning signal G(n) of the current level . That is, the first pull-down maintenance module 105 works normally.
  • the sixteenth transistor T16 is turned on, and the third reference low level signal VSS3 is transmitted to the third node b. That is, the potential of the third node b is pulled down to a potential lower than the potential of the first reference low level signal VSS1, effectively reducing the leakage of the first node Q(n). Furthermore, when the second pull-down sustaining module 106 is not working, the twelfth transistor T12 and the thirteenth transistor T13 are in the off state, and it is easy to retain charge.
  • Turning on the sixteenth transistor T16 can release the charge, which is effective Reducing the current pressure of the twelfth transistor T12 and the thirteenth transistor T13 during operation is to increase the life of the transistor in the second pull-down maintenance module 106, thereby improving the stability of the GOA circuit.
  • the second pull-down sustain module 106 because the second control signal LC2 is at a high potential, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, the sixteenth transistor T16 is turned off, and the second control signal LC2 is transmitted to the third node b.
  • the seventeenth transistor T17 is turned on, and the first reference low level signal VSS1 maintains the potential of the first node Q(n) to the potential of the first reference low level signal VSS1, thereby maintaining the current level scanning signal G(n) The potential. That is, the second pull-down maintenance module 106 works normally.
  • the first pull-down sustain module 105 because the potential of the second control signal LC2 is high, the tenth transistor T10 is turned on, and the third reference low level signal VSS3 is transmitted to the second node a. That is, the potential of the second node a is pulled down to a potential lower than the potential of the first reference low level signal VSS1, effectively reducing the leakage of the first node Q(n). Furthermore, when the first pull-down sustaining module 105 is not working, the sixth transistor T6 and the seventh transistor T7 are in the off state, and it is easy to retain charge.
  • the current pressure of the sixth transistor T6 and the seventh transistor T7 during operation increases the life of the transistors in the first pull-down maintenance module 105, thereby improving the stability of the GOA circuit.
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes a display area 100 and a GOA circuit 200 integratedly arranged on the edge of the display area 100; wherein the structure and principle of the GOA circuit 200 are similar to the GOA circuit 10 described above, and will not be repeated here.

Abstract

一种GOA电路（10、200）及显示面板，通过在第一下拉维持模块（105）中增加第十晶体管（T10），以及在第二下拉维持模块（106）中增加第十六晶体管（T16），从而可以通过第十晶体管（T10）以及第十六晶体管（T16）将第二节点（a）以及第三节点（b）下拉至更低电位，进而提高GOA电路（10、200）的稳定性。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
现有的GOA电路在输出当前级GOA单元的行扫描信号后，需在一段时间内维持行扫描信号的低电平。然而，由于晶体管长时间工作，晶体管的电性容易受到破坏，从而导致GOA电路不能正常工作。
 技术问题
本申请实施例的目的在于提供一种GOA电路及显示面板，能够解决现有的GOA电路由于晶体管长时间工作，晶体管的电性容易受到破坏，从而导致GOA电路不能正常工作的技术问题。
 技术解决方案
本申请实施例提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、第一下拉维持模块、第二下拉维持模块以及自举电容；
所述节点控制模块接入上一级扫描信号以及上一级级传信号，并电性连接于第一节点，用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
所述级传模块接入本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下一级扫描信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级扫描信号的的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
所述第一下拉维持模块以及所述第二下拉维持模块均接入第一控制信号、第二控制信号、第三参考低电平信号以及所述第一参考低电平信号，并电性连接于所述第一节点，均用于根据所述第一控制信号、所述第二控制信号、所述第三参考低电平信号以及所述第一参考低电平信号维持所述第一节点的电位，且所述第一下拉维持模块以及所述第二下拉维持模块交替工作；
所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号；
所述第一参考低电平信号的电位大于所述第三参考低电平信号的电位，所述第二参考低电平信号的电位大于所述第三参考低电平信号的电位；
所述第一控制信号的相位和所述第二控制信号的相位相反。
在本申请所述的GOA电路中，所述节点控制模块包括第一晶体管；
所述第一晶体管的栅极电性连接于所述上一级扫描信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述级传模块包括第二晶体管；
所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述上拉模块包括第三晶体管；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉模块包括第四晶体管以及第五晶体管；
所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述第一下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述第一控制信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第九晶体管的漏极电性连接，所述第七晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的漏极以及所述第十一晶体管的栅极均电性连接于第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十一晶体管的漏极均电性连接于所述第一节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十一晶体管的源极均电性连接于所述第一参考低电平信号，所述第十晶体管的栅极电性连接于所述第二控制信号，所述第十晶体管的源极电性连接于所述第三参考低电平信号。
在本申请所述的GOA电路中，所述第二下拉维持模块包括第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管以及第十七晶体管；
所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均电性连接于所述第二控制信号，所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的漏极电性连接，所述第十三晶体管的漏极、所述第十四晶体管的漏极、所述第十六晶体管的漏极以及所述第十七晶体管的栅极均电性连接于第三节点，所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十七晶体管的漏极均电性连接于所述第一节点，所述第十四晶体管的源极、所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一参考低电平信号，所述第十七晶体管的栅极电性连接于所述第一控制信号，所述第十七晶体管的源极电性连接于所述第三参考低电平信号。
本申请实施例还提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、第一下拉维持模块、第二下拉维持模块以及自举电容；
所述节点控制模块接入上一级扫描信号以及上一级级传信号，并电性连接于第一节点，用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
所述级传模块接入本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下一级扫描信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级扫描信号的的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
所述第一下拉维持模块以及所述第二下拉维持模块均接入第一控制信号、第二控制信号、第三参考低电平信号以及所述第一参考低电平信号，并电性连接于所述第一节点，均用于根据所述第一控制信号、所述第二控制信号、所述第三参考低电平信号以及所述第一参考低电平信号维持所述第一节点的电位，且所述第一下拉维持模块以及所述第二下拉维持模块交替工作；
所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述节点控制模块包括第一晶体管；
所述第一晶体管的栅极电性连接于所述上一级扫描信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述级传模块包括第二晶体管；
所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述上拉模块包括第三晶体管；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉模块包括第四晶体管以及第五晶体管；
所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述第一下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述第一控制信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第九晶体管的漏极电性连接，所述第七晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的漏极以及所述第十一晶体管的栅极均电性连接于第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十一晶体管的漏极均电性连接于所述第一节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十一晶体管的源极均电性连接于所述第一参考低电平信号，所述第十晶体管的栅极电性连接于所述第二控制信号，所述第十晶体管的源极电性连接于所述第三参考低电平信号。
在本申请所述的GOA电路中，所述第二下拉维持模块包括第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管以及第十七晶体管；
所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均电性连接于所述第二控制信号，所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的漏极电性连接，所述第十三晶体管的漏极、所述第十四晶体管的漏极、所述第十六晶体管的漏极以及所述第十七晶体管的栅极均电性连接于第三节点，所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十七晶体管的漏极均电性连接于所述第一节点，所述第十四晶体管的源极、所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一参考低电平信号，所述第十七晶体管的栅极电性连接于所述第一控制信号，所述第十七晶体管的源极电性连接于所述第三参考低电平信号。
在本申请所述的GOA电路中，所述第一参考低电平信号的电位大于所述第三参考低电平信号的电位，所述第二参考低电平信号的电位大于所述第三参考低电平信号的电位。
在本申请所述的GOA电路中，所述第一控制信号的相位和所述第二控制信号的相位相反。
本申请实施例还提供一种显示面板，包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、第一下拉维持模块、第二下拉维持模块以及自举电容；
所述节点控制模块接入上一级扫描信号以及上一级级传信号，并电性连接于第一节点，用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
所述级传模块接入本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下一级扫描信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级扫描信号的的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
所述第一下拉维持模块以及所述第二下拉维持模块均接入第一控制信号、第二控制信号、第三参考低电平信号以及所述第一参考低电平信号，并电性连接于所述第一节点，均用于根据所述第一控制信号、所述第二控制信号、所述第三参考低电平信号以及所述第一参考低电平信号维持所述第一节点的电位，且所述第一下拉维持模块以及所述第二下拉维持模块交替工作；
所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
在本申请所述的显示面板中，所述节点控制模块包括第一晶体管；
所述第一晶体管的栅极电性连接于所述上一级扫描信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极电性连接于所述第一节点。
在本申请所述的显示面板中，所述级传模块包括第二晶体管；
所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的显示面板中，所述上拉模块包括第三晶体管；
所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
 有益效果
本申请实施例提供的GOA电路及显示面板，通过在第一下拉维持模块中增加第十晶体管，以及在第二下拉维持模块中增加第十六晶体管，从而可以通过第十晶体管以及第十六晶体管将第二节点以及第三节点下拉至更低电位，进而提高GOA电路的稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA电路的结构示意图；
图2为本申请实施例提供的GOA电路中一GOA单元的电路示意图；
图3为本申请实施例提供的GOA电路中一GOA单元的信号时序图；以及
图4为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管均为N 型晶体管或P型晶体管，其中，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止；P 型晶体管为在栅极为低电平时导通，在栅极为高电平时截止。
请参阅图1，图1为本申请实施例提供的GOA电路的结构示意图。如图1所示，本申请实施例提供的GOA电路10包括多级级联的GOA单元20。每一级GOA单元20均用于输出一扫描信号以及一级传信号。其中，当该GOA电路10工作时，第一级GOA单元20接入起始信号STV，随后，第二级GOA单元20、第三级GOA单元20，……，最后一级GOA单元20依次级传启动。
进一步的，请参阅图2，图2为本申请实施例提供的GOA电路中一GOA单元的电路示意图。如图2所示，该GOA单元20包括：节点控制模块101、级传模块102、上拉模块103、下拉模块104、第一下拉维持模块105、第二下拉维持模块106以及自举电容Cbt。
其中，节点控制模块101接入上一级扫描信号G（n-1）以及上一级级传信号ST（n-1），并电性连接于第一节点Q(n)，用于根据上一级扫描信号G（n-1）以及上一级级传信号ST（n-1）控制第一节点Q(n)的电位。
其中，级传模块102接入本级时钟信号CK，并电性连接于第一节点Q(n)，用于在第一节点Q(n)的电位控制下输出本级级传信号ST（n）。
其中，上拉模块103接入本级时钟信号CK，并电性连接于第一节点Q(n)，用于在第一节点Q(n)的电位控制下输出本级扫描信号G（n）。
其中，下拉模块104接入下一级扫描信号G（n+1）、第一参考低电平信号VSS1以及第二参考低电平信号VSS2，并电性连接于第一节点Q(n)以及本级扫描信号G（n），用于在下一级扫描信号G（n+1）的控制下将第一节点Q(n)的电位下拉至第一参考低电平信号VSS1的电位，以及在下一级扫描信号G（n+1）的的控制下将本级扫描信号G（n）下拉至第二参考低电平信号VSS2的电位。
其中，第一下拉维持模块105以及第二下拉维持模块106均接入第一控制信号LC1、第二控制信号LC2、第三参考低电平信号VSS3以及第一参考低电平信号VSS1，并电性连接于第一节点Q(n)，均用于根据第一控制信号LC1、第二控制信号LC2、第三参考低电平信号VSS3以及第一参考低电平信号VSS1维持第一节点Q(n)的电位，且第一下拉维持模块105以及第二下拉维持模块106交替工作。
其中，自举电容Cbt的第一端电性连接于第一节点Q(n)，自举电容Cbt的第二端电性连接于本级扫描信号G（n）。
在一些实施例中，节点控制模块101包括第一晶体管T1；第一晶体管T1的栅极电性连接于上一级扫描信号G（n-1），第一晶体管T1的源极电性连接于上一级级传信号ST（n-1），第一晶体管T1的漏极电性连接于第一节点Q(n)。
在一些实施例中，级传模块102包括第二晶体管T2；第二晶体管T2的栅极电性连接于第一节点Q(n)，第二晶体管T2的源极电性连接于本级时钟信号CK，第二晶体管T2的漏极电性连接于本级级传信号ST（n）。
在一些实施例中，上拉模块103包括第三晶体管T3；第三晶体管T3的栅极电性连接于第一节点Q(n)，第三晶体管T3的源极电性连接于本级时钟信号CK，第三晶体管T3的漏极电性连接于本级扫描信号G（n）。
在一些实施例中，下拉模块104包括第四晶体管T4以及第五晶体管T5；第四晶体管T4的栅极以及第五晶体管T5的栅极均电性连接于下一级扫描信号G（n+1），第四晶体管T4的源极电性连接于第一参考低电平信号VSS1，第四晶体管T4的漏极电性连接于第一节点Q(n)，第五晶体管T5的源极电性连接于第二参考低电平信号VSS2，第五晶体管T5的漏极电性连接于本级扫描信号G（n）。
在一些实施例中，第一下拉维持模块105包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10以及第十一晶体管T11；第六晶体管T6的栅极、源极以及第七晶体管T7的源极均电性连接于第一控制信号LC1，第六晶体管T6的漏极、第七晶体管T7的栅极以及第九晶体管T9的漏极电性连接，第七晶体管T7的漏极、第八晶体管T8的漏极、第十晶体管T10的漏极以及第十一晶体管T11的栅极均电性连接于第二节点a，第八晶体管T8的栅极、第九晶体管T9的栅极以及第十一晶体管T11的漏极均电性连接于第一节点Q(n)，第八晶体管T8的源极、第九晶体管T9的源极以及第十一晶体管T11的源极均电性连接于第一参考低电平信号VSS1，第十晶体管T10的栅极电性连接于第二控制信号LC2，第十晶体管T10的源极电性连接于第三参考低电平信号VSS3。
在一些实施例中，第二下拉维持模块106包括第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16以及第十七晶体管T17；第十二晶体管T12的栅极、源极以及第十三晶体管T13的源极均电性连接于第二控制信号LC2，第十二晶体管T12的漏极、第十三晶体管T13的栅极以及第十五晶体管T15的漏极电性连接，第十三晶体管T13的漏极、第十四晶体管T14的漏极、第十六晶体管T16的漏极以及第十七晶体管T17的栅极均电性连接于第三节点b，第十四晶体管T14的栅极、第十五晶体管T15的栅极以及第十七晶体管T17的漏极均电性连接于第一节点Q(n)，第十四晶体管T14的源极、第十五晶体管T15的源极以及第十六晶体管T16的源极均电性连接于第一参考低电平信号VSS1，第十七晶体管T17的栅极电性连接于第一控制信号LC1，第十七晶体管T17的源极电性连接于第三参考低电平信号VSS3。
进一步的，本申请实施例提供的GOA电路，第一参考低电平信号VSS1的电位大于第三参考低电平信号VSS3的电位，第二参考低电平信号VSS2的电位大于第三参考低电平信号VSS3的电位。第一控制信号LC1的相位和第二控制信号LC2的相位相反。
具体的，请结合图2、图3，图3为本申请实施例提供的GOA电路中一GOA单元的信号时序图。当上一级级传信号ST（n-1）为高电平，上一级扫描信号G（n-1）为高电平时，第一晶体管T1导通，上一级级传信号ST（n-1）通过第一晶体管T1给自举电容Cbt充电，使得第一节点Q(n)的电位上升到一较高的电位。
随后，上一级扫描信号G（n-1）转为低电平，第一晶体管T1关闭，第一节点Q(n)的电位通过自举电容Cbt维持一较高的电位。同时，本级时钟信号CK的电位转为高电位，本级时钟信号CK通过第二晶体管T2继续给自举电容Cbt充电，使得第一节点Q(n)的电位达到一更高的电位，本级扫描信号G（n）和本级级传信号ST（n）也转为高电位。
接着，当下一级扫描信号G（n+1）转为高电平时，第四晶体管T4和第五晶体管T5打开，第一参考低电平信号VSS1将第一节点Q(n)的电位拉低，第二参考低电平信号VSS2将本级扫描信号G（n）拉低。
最后，由于第一节点Q(n)的电位转为低电位，使得第八晶体管T8和第九晶体管T9关闭，同时，第一控制信号LC1的电位为高电位，使得第六晶体管T6和第七晶体管T7打开，第一控制信号LC1传至第二节点a，使得第十一晶体管T11打开，第一参考低电平信号VSS1维持第一节点Q(n)的电位至第一参考低电平信号VSS1的电位，进而维持本级扫描信号G（n）的电位。
特别的，本申请实施例通过在第一下拉维持模块105中增加第十晶体管T10，以及在第二下拉维持模块106中增加第十六晶体管T16，从而可以通过第十晶体管T10以及第十六晶体管T16将第二节点a以及第三节点b下拉至更低电位，进而提高GOA电路的稳定性。
例如，当第一控制信号LC1的电位为高电位，第二控制信号LC2的电位为低电位时，此时，第一节点Q(n)的电位为低电位。在第一下拉维持模块105中，由于第一控制信号LC1为高电位，使得第六晶体管T6和第七晶体管T7打开，第十晶体管T10关闭，第一控制信号LC1传至第二节点a，使得第十一晶体管T11打开，第一参考低电平信号VSS1维持第一节点Q(n)的电位至第一参考低电平信号VSS1的电位，进而维持本级扫描信号G（n）的电位。也即，第一下拉维持模块105正常工作。
与此同时，在第二下拉维持模块106中，由于第一控制信号LC1的电位为高电位，使得第十六晶体管T16打开，第三参考低电平信号VSS3传至第三节点b。也即，第三节点b的电位被拉倒比第一参考低电平信号VSS1的电位更低的电位，有效减小第一节点Q(n)漏电。再一个，由于第二下拉维持模块106不工作时，第十二晶体管T12以及第十三晶体管T13处于关闭状态，容易残存电荷，第十六晶体管T16的打开，可以使得电荷释放掉，这样可以有效减小第十二晶体管T12以及第十三晶体管T13在工作时受到的电流压力, 即提高了第二下拉维持模块106中晶体管的寿命，从而提高了GOA电路的稳定性。
同样，例如，当第二控制信号LC2的电位为高电位，第一控制信号LC1的电位为低电位时，此时，第一节点Q(n)的电位为低电位。在第二下拉维持模块106中，由于第二控制信号LC2为高电位，使得第十二晶体管T12和第十三晶体管T13打开，第十六晶体管T16关闭，第二控制信号LC2传至第三节点b，使得第十七晶体管T17打开，第一参考低电平信号VSS1维持第一节点Q(n)的电位至第一参考低电平信号VSS1的电位，进而维持本级扫描信号G（n）的电位。也即，第二下拉维持模块106正常工作。
与此同时，在第一下拉维持模块105中，由于第二控制信号LC2的电位为高电位，使得第十晶体管T10打开，第三参考低电平信号VSS3传至第二节点a。也即，第二节点a的电位被拉倒比第一参考低电平信号VSS1的电位更低的电位，有效减小第一节点Q(n)漏电。再一个，由于第一下拉维持模块105不工作时，第六晶体管T6以及第七晶体管T7处于关闭状态，容易残存电荷，第十晶体管T10的打开，可以使得电荷释放掉，这样可以有效减小第六晶体管T6以及第七晶体管T7在工作时受到的电流压力, 即提高了第一下拉维持模块105中晶体管的寿命，从而提高了GOA电路的稳定性。
请参阅图4，图4为本申请实施例提供的显示面板的结构示意图。如图4所示，该显示面板包括显示区域100以及集成设置在显示区域100边缘上的GOA电路200；其中，该GOA电路200与上述的GOA电路10的结构和原理类似，这里不再赘述。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、第一下拉维持模块、第二下拉维持模块以及自举电容；
    所述节点控制模块接入上一级扫描信号以及上一级级传信号，并电性连接于第一节点，用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
    所述级传模块接入本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下一级扫描信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级扫描信号的的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
    所述第一下拉维持模块以及所述第二下拉维持模块均接入第一控制信号、第二控制信号、第三参考低电平信号以及所述第一参考低电平信号，并电性连接于所述第一节点，均用于根据所述第一控制信号、所述第二控制信号、所述第三参考低电平信号以及所述第一参考低电平信号维持所述第一节点的电位，且所述第一下拉维持模块以及所述第二下拉维持模块交替工作；
    所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号；
    所述第一参考低电平信号的电位大于所述第三参考低电平信号的电位，所述第二参考低电平信号的电位大于所述第三参考低电平信号的电位；
    所述第一控制信号的相位和所述第二控制信号的相位相反。
  2. 根据权利要求1所述的GOA电路，其中，所述节点控制模块包括第一晶体管；
    所述第一晶体管的栅极电性连接于所述上一级扫描信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极电性连接于所述第一节点。
  3. 根据权利要求1所述的GOA电路，其中，所述级传模块包括第二晶体管；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
  4. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括第四晶体管以及第五晶体管；
    所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  6. 根据权利要求1所述的GOA电路，其中，所述第一下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
    所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述第一控制信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第九晶体管的漏极电性连接，所述第七晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的漏极以及所述第十一晶体管的栅极均电性连接于第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十一晶体管的漏极均电性连接于所述第一节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十一晶体管的源极均电性连接于所述第一参考低电平信号，所述第十晶体管的栅极电性连接于所述第二控制信号，所述第十晶体管的源极电性连接于所述第三参考低电平信号。
  7. 根据权利要求1所述的GOA电路，其中，所述第二下拉维持模块包括第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管以及第十七晶体管；
    所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均电性连接于所述第二控制信号，所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的漏极电性连接，所述第十三晶体管的漏极、所述第十四晶体管的漏极、所述第十六晶体管的漏极以及所述第十七晶体管的栅极均电性连接于第三节点，所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十七晶体管的漏极均电性连接于所述第一节点，所述第十四晶体管的源极、所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一参考低电平信号，所述第十七晶体管的栅极电性连接于所述第一控制信号，所述第十七晶体管的源极电性连接于所述第三参考低电平信号。
  8. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、第一下拉维持模块、第二下拉维持模块以及自举电容；
    所述节点控制模块接入上一级扫描信号以及上一级级传信号，并电性连接于第一节点，用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
    所述级传模块接入本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下一级扫描信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级扫描信号的的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
    所述第一下拉维持模块以及所述第二下拉维持模块均接入第一控制信号、第二控制信号、第三参考低电平信号以及所述第一参考低电平信号，并电性连接于所述第一节点，均用于根据所述第一控制信号、所述第二控制信号、所述第三参考低电平信号以及所述第一参考低电平信号维持所述第一节点的电位，且所述第一下拉维持模块以及所述第二下拉维持模块交替工作；
    所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
  9. 根据权利要求8所述的GOA电路，其中，所述节点控制模块包括第一晶体管；
    所述第一晶体管的栅极电性连接于所述上一级扫描信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极电性连接于所述第一节点。
  10. 根据权利要求8所述的GOA电路，其中，所述级传模块包括第二晶体管；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
  11. 根据权利要求8所述的GOA电路，其中，所述上拉模块包括第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
  12. 根据权利要求8所述的GOA电路，其中，所述下拉模块包括第四晶体管以及第五晶体管；
    所述第四晶体管的栅极以及所述第五晶体管的栅极均电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第一参考低电平信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第二参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  13. 根据权利要求8所述的GOA电路，其中，所述第一下拉维持模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第十一晶体管；
    所述第六晶体管的栅极、源极以及所述第七晶体管的源极均电性连接于所述第一控制信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第九晶体管的漏极电性连接，所述第七晶体管的漏极、所述第八晶体管的漏极、所述第十晶体管的漏极以及所述第十一晶体管的栅极均电性连接于第二节点，所述第八晶体管的栅极、所述第九晶体管的栅极以及所述第十一晶体管的漏极均电性连接于所述第一节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十一晶体管的源极均电性连接于所述第一参考低电平信号，所述第十晶体管的栅极电性连接于所述第二控制信号，所述第十晶体管的源极电性连接于所述第三参考低电平信号。
  14. 根据权利要求8所述的GOA电路，其中，所述第二下拉维持模块包括第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管以及第十七晶体管；
    所述第十二晶体管的栅极、源极以及所述第十三晶体管的源极均电性连接于所述第二控制信号，所述第十二晶体管的漏极、所述第十三晶体管的栅极以及所述第十五晶体管的漏极电性连接，所述第十三晶体管的漏极、所述第十四晶体管的漏极、所述第十六晶体管的漏极以及所述第十七晶体管的栅极均电性连接于第三节点，所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十七晶体管的漏极均电性连接于所述第一节点，所述第十四晶体管的源极、所述第十五晶体管的源极以及所述第十六晶体管的源极均电性连接于所述第一参考低电平信号，所述第十七晶体管的栅极电性连接于所述第一控制信号，所述第十七晶体管的源极电性连接于所述第三参考低电平信号。
  15. 根据权利要求8所述的GOA电路，其中，所述第一参考低电平信号的电位大于所述第三参考低电平信号的电位，所述第二参考低电平信号的电位大于所述第三参考低电平信号的电位。
  16. 根据权利要求8所述的GOA电路，其中，所述第一控制信号的相位和所述第二控制信号的相位相反。
  17. 一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：节点控制模块、级传模块、上拉模块、下拉模块、第一下拉维持模块、第二下拉维持模块以及自举电容；
    所述节点控制模块接入上一级扫描信号以及上一级级传信号，并电性连接于第一节点，用于根据所述上一级扫描信号以及所述上一级级传信号控制所述第一节点的电位；
    所述级传模块接入本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述本级时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下一级扫描信号的控制下将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及在所述下一级扫描信号的的控制下将所述本级扫描信号下拉至所述第二参考低电平信号的电位；
    所述第一下拉维持模块以及所述第二下拉维持模块均接入第一控制信号、第二控制信号、第三参考低电平信号以及所述第一参考低电平信号，并电性连接于所述第一节点，均用于根据所述第一控制信号、所述第二控制信号、所述第三参考低电平信号以及所述第一参考低电平信号维持所述第一节点的电位，且所述第一下拉维持模块以及所述第二下拉维持模块交替工作；
    所述自举电容的第一端电性连接于所述第一节点，所述自举电容的第二端电性连接于所述本级扫描信号。
  18. 根据权利要求17所述的显示面板，其中，所述节点控制模块包括第一晶体管；
    所述第一晶体管的栅极电性连接于所述上一级扫描信号，所述第一晶体管的源极电性连接于所述上一级级传信号，所述第一晶体管的漏极电性连接于所述第一节点。
  19. 根据权利要求17所述的显示面板，其中，所述级传模块包括第二晶体管；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极电性连接于所述本级时钟信号，所述第二晶体管的漏极电性连接于所述本级级传信号。
  20. 根据权利要求17所述的显示面板，其中，所述上拉模块包括第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的源极电性连接于所述本级时钟信号，所述第三晶体管的漏极电性连接于所述本级扫描信号。
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