WO2018176577A1 - 一种goa驱动电路 - Google Patents

一种goa驱动电路 Download PDF

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Publication number
WO2018176577A1
WO2018176577A1 PCT/CN2017/083451 CN2017083451W WO2018176577A1 WO 2018176577 A1 WO2018176577 A1 WO 2018176577A1 CN 2017083451 W CN2017083451 W CN 2017083451W WO 2018176577 A1 WO2018176577 A1 WO 2018176577A1
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Prior art keywords
transistor
signal
goa driving
unit
gate
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PCT/CN2017/083451
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English (en)
French (fr)
Inventor
吕晓文
廖聪维
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深圳市华星光电技术有限公司
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Priority to US15/539,738 priority Critical patent/US10699658B2/en
Publication of WO2018176577A1 publication Critical patent/WO2018176577A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the invention belongs to the technical field of display, and in particular relates to a GOA driving circuit.
  • GOA Gate On Array
  • the GOA driver circuit has many advantages. For example, since the GOA driver circuit is formed directly on the array substrate, the use of the gate driver chip (Gate IC) can be saved, the borderless design of the display screen can be realized, and the product can be improved. Yield. Reduce production costs, etc.
  • the GOA driving circuit is directly disposed on the array substrate, it is not convenient to replace the components in the circuit. As the component's electrical drift or leakage increases, the voltage of some key nodes in the circuit will change. In severe cases, the timing of the operation of the GOA driver circuit will be wrong, causing display failure.
  • One of the technical problems to be solved by the present invention is to provide a GOA driving circuit that maintains a stable node voltage and reliable operation timing.
  • an embodiment of the present application first provides a GOA driving circuit, including a multi-level GOA driving unit, each level of the GOA driving unit is configured to output a row scanning signal to a row of pixel units, and the GOA driving unit further includes a pull-up unit, a pull-up control unit, a downlink unit, a pull-down unit, and a pull-down maintaining unit; the pull-up control unit outputs a first voltage signal; the GOA driving unit further includes a pre-charge pull-down unit, the pre-charge pull-down unit Is configured to: turn off the first voltage signal via the pull-down maintaining unit before the first voltage signal transitions from a low potential to a high potential The path of the discharge.
  • the pull-down maintaining unit includes a first transistor, a gate of the first transistor is connected to the first voltage signal, a source thereof is connected to the first power signal, and a drain thereof is outputting a second voltage signal, the first The two voltage signals are configured to turn the path on or off.
  • the precharge down pull-down unit includes a second transistor, a source of the second transistor is connected to the first power signal, a drain thereof is connected to the second voltage signal, and a gate thereof is connected to a precharge pull-down signal.
  • the rising edge of the precharge pull-down signal leads the rising edge of the first voltage signal
  • the falling edge of the precharge pull-down signal leads the falling edge of the first voltage signal and lags behind the first The rising edge of the voltage signal.
  • the downlink transmitting unit outputs a first downlink signal as the precharge down-down signal.
  • the downlink unit outputs the second as the precharge down signal Send the signal.
  • the pull-up control unit includes a third transistor, and the gate of the third transistor is connected to the first downlink signal output by the downlink unit of the previous stage GOA driving unit cascaded with the GOA driving unit of the current stage.
  • the source is connected to the first voltage signal, and the drain thereof is connected to the second power signal.
  • the pull-down maintaining unit further includes: a fourth transistor having a gate connected to the second voltage signal, a source connected to the first power signal, a drain connected to the first voltage signal, and a fifth a transistor having a gate and a source connected to a gate and a source of the fourth transistor, a drain connected to a row scan signal of a GOA driving unit to which the gate is associated, and a sixth transistor having a gate and a drain
  • the third power signal is connected in common, and the source is connected to the second voltage signal.
  • the downlink unit comprises a seventh transistor, the gate of the seventh transistor is connected to the first voltage signal, the drain thereof is connected to the clock signal, and the source thereof is outputting the third downlink signal.
  • the pull-up unit includes: an eighth transistor having a gate connected to the first voltage signal, a drain connected to the clock signal, and a source output corresponding to the row scan signal of the GOA driving unit to which it belongs; A capacitor is connected in parallel between the gate and the source of the eighth transistor.
  • the pull-down unit includes a ninth transistor and a tenth transistor, a gate and a source of the ninth transistor are respectively connected to a gate and a source of the tenth transistor, and a drain of the ninth transistor
  • the first voltage signal is connected to the pole, and the drain of the tenth transistor is connected to a row scan signal corresponding to the GOA driving unit to which it belongs.
  • the discharge path of the Q point voltage is turned off before the voltage at the Q point changes from a low potential to a high potential, thus ensuring the stability of the critical node voltage in the circuit.
  • the overall performance of the GOA driving circuit is improved, which is advantageous for extending the life of the liquid crystal display device.
  • FIG. 1 is a schematic structural view of a GOA driving unit in the prior art
  • FIG. 2 is a schematic structural diagram of a primary GOA driving unit according to an embodiment of the invention.
  • FIG. 3 is a schematic structural diagram of a primary GOA driving unit according to another embodiment of the present invention.
  • FIG. 4 is a timing chart showing the operation of a GOA driving circuit according to still another embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a GOA driving unit in the prior art.
  • the actual GOA driving circuit is generally composed of multiple stages of GOA driving units as shown in the figure, and the primary GOA driving unit is used to output lines to a row of pixel units. Scan the signal.
  • the conventional GOA driving circuit is generally provided with a pull-up control unit 11, a pull-up unit 12, a pull-down unit 13, a pull-down maintaining unit 14, and the like.
  • the pull-up control unit 11 and the pull-up unit The 12-phase connection can output a control signal to the pull-up unit 12 in a specific timing, which is represented by the voltage at the Q point in FIG. 1, and the control signal is used to turn on the pull-up unit 12 to output a line scan signal.
  • the pull-down unit 13 is configured to pull down the row scan signal and the Q-point voltage of the GOA driving unit of the current stage to a low potential
  • the pull-down maintaining unit 14 is configured to maintain the line scan signal and the Q-point voltage during the scanning period of the non-negative row of pixel units. Low potential.
  • the value of the Q-point voltage and the timing of the action are critical to the implementation of the GOA drive circuit function. In actual use, when the voltage at the Q point is changed from a low potential to a high potential, it is prone to cause a failure to drive.
  • the embodiment of the present invention provides a GOA driving unit for the above problem, and its structure is as shown in FIG. 2 .
  • the GOA driving unit of the embodiment of the present invention further includes a pre-charge pull-down unit 25 and a downlink transmission unit 26 in addition to the pull-up control unit 21, the pull-up unit 22, the pull-down unit 23, and the pull-down maintaining unit 24.
  • the precharge pull-down unit 25 is connected to the pull-down maintaining unit 24, and the pre-charge pull-down unit 25 is configured to maintain the Q-point voltage off via the pull-down before the Q-point voltage (the first voltage signal) transitions from the low potential to the high potential.
  • Unit 24 performs the path of the discharge.
  • FIG. 3 is a schematic structural diagram of a primary GOA driving unit according to another embodiment of the present invention.
  • the source of t11 is connected to Q point, and the drain of t11 is connected to a fixed high voltage signal Vdd (second power signal).
  • the downlink signal STn 1 is generated by the downlink unit 26 of the n1th stage GOA driving unit.
  • the downlink unit 26 mainly includes a transistor t22 (seventh transistor), the gate of t22 is connected to the Q point, the drain of t22 is connected to the clock signal CK, and the source of the t22 is outputting the downlink signal STn (corresponding to this The third downstream signal of the stage GOA drive unit).
  • the setting of the downlink unit 26 can also reduce the leakage of the Q point of the GOA driving unit of the current stage through the pull-up unit 22 during the voltage maintaining phase thereof to some extent.
  • the pull-up unit 22 in this embodiment includes a transistor t21 (eighth transistor) and a bootstrap capacitor Cb.
  • the bootstrap capacitor Cb is connected in parallel between the gate and the source of t21.
  • the drain of t21 is connected to the clock signal CK, the source of t21 is used as the line scan signal output terminal of the GOA driving unit of the present stage, and the corresponding line scan signal Gn is output, and the gate of t21 is connected at the Q point.
  • the pull-down unit 23 in this embodiment includes a transistor t31 (tenth transistor) and a transistor t41 (ninth transistor).
  • the gate and the source of t31 are respectively connected to the gate and the source of t41, and the drain of t31 is connected to the row scan signal of the GOA driving unit of the current stage, which can be used to pull down the corresponding line scan signal, and the drain of t41 Extremely connected at point Q.
  • the gates of t31 and t41 are controlled by the pull-down signal Gn 2 (Gn 2 is a line scan signal corresponding to the n-th stage GOA driving unit, and the value of n 2 is greater than the value of n).
  • the source of t31 and t41 is connected to a fixed low level signal Vss.
  • the Q point is the convergence point of many branches, so the voltage of Q point and the working timing are crucial for the realization of the circuit driving function.
  • the pull-up control unit 21 When STn 1 is a high level signal, the transistor t11 is turned on, and the Q point receives the high level of the power supply Vdd, and jumps from a low potential to a high potential.
  • the source of the transistor t11 is also connected to the gate of the transistor t52 (first transistor), the source of t52 is connected to the fixed low voltage signal Vss (first power signal), and the voltage of the drain of t52 is output (second voltage signal). ) is expressed by the voltage at point P.
  • the drain of t52 is connected to the gate of transistor t42 (fourth transistor), the source of t42 is connected to a fixed low voltage signal Vss, and the drain of t42 is connected to point Q. Then, when the voltage at point P is high, the transistor t42 is turned on, and the voltage at the Q point is pulled from the high potential to the low potential, that is, the Q point is discharged via the transistor t42. When the voltage at point P is low, transistor t42 is turned off and the voltage at point Q can be kept at a high potential. Therefore, the discharge path at the Q point can be turned on or off by controlling the value of the voltage at point P.
  • the pull-down maintaining unit 24 in this embodiment includes a transistor t32 (fifth transistor) and a transistor t51 (sixth transistor) in addition to the transistors t52 and t42.
  • the gate and source of t32 are connected to the gate and source of transistor t42, respectively, and the drain of t32 is connected to the row scan signal for pulling the row scan signal low to a low level in an appropriate timing.
  • the gate and the drain of t51 are connected in common to the fixed high voltage signal LC (third power signal), and the source of t51 is connected to the P point, and t51 can make the P point be at a high potential, thereby maintaining the transistor t42 in an on state.
  • the precharge pull-down unit 25 includes a transistor t61 (second transistor).
  • the gate of t61 is connected to the precharge pull-down signal Con
  • the source of t61 is connected to the fixed low voltage signal Vss
  • the drain of t61 is connected to point P to control the voltage of point P.
  • the precharge pull-down signal Con is a high voltage signal
  • the transistor t61 is turned on, and the voltage at the point P is pulled low to a low level, thereby causing the transistor t42 to be turned off.
  • the precharge pull-down signal Con is a low voltage signal
  • the transistor t61 is turned off, and the voltage at the point P jumps to a high potential under the control of the transistor t51, as shown in FIG.
  • the rising edge of Con leads the rising edge of Q, and the falling edge of Con exceeds It is before the falling edge of Q and lags behind the rising edge of Q.
  • Con can turn on transistor t61, and then pull the voltage at point P low to low potential.
  • the transistor 42 is turned off, that is, the discharge path of the Q point is turned off before the Q point changes from the low potential to the high potential to ensure that the voltage at the Q point can be reliably pulled high.
  • the transistor t52 is turned on under the control of the voltage at the Q point, and the potential at the point P is pulled down by t52.
  • the GOA driving circuit in the prior art does not have the transistor t61, it may cause the Q point voltage to be unacceptable. Specifically, as shown in FIG. 3, when the voltage at the Q point starts to jump from a low potential to a high potential, since the transistor t42 is in an on state at this time, and only the voltage at the Q point is at a high potential, the transistor can be made. T42 is off. If the voltage at point P is not pulled down in time, it will cause leakage of Q point in the pre-charging stage, then the Q point may not be lifted. That is to say, there is a competitive relationship between the jump of the voltage at the Q point and the jump of the voltage at the P point.
  • timing between the Q point and the P point meets the corresponding timing relationship in the design stage or the initial use phase of the product, the reliability of the timing is caused by the electrical drift or leakage of the component. It will gradually decrease, and it may be further intensified with the use of the product. Eventually, timing errors will occur, resulting in failure of the function of the drive circuit, which is a dangerous and weak link in the circuit.
  • the P point is turned off by turning off the discharge path of the Q point before the voltage jumps at the Q point, and when the next jump occurs at the Q point (when the high potential jumps to the low potential)
  • the control of the voltage is returned to the Q point, which fully guarantees the reliability of the working sequence. Improve the reliability of the entire GOA drive circuit work, and help to extend the life of the product.
  • the same signal as the control signal of the control terminal of the pull-up control unit 21 may be employed as the precharge pull-down signal Con.
  • the control signal STn 1 of the pull-up control unit 21 is the output signal STn 1 (first down-going signal) of the downstream unit 26 in the previous stage GOA driving unit cascaded with the GOA driving unit of the present stage. .
  • the precharge down-down signal Con of the nth stage GOA driving unit is ST(n-1).
  • the control unit 21 receives the downlink signal ST(n-1) generated by the n-1th stage GOA driving unit. As shown in FIG. 4, the n-1th stage GOA driving unit outputs the down signal ST(n-1) when XCK is at a high level.
  • the transistor t11 and the transistor t61 are simultaneously turned on, the voltage at the P point is pulled low to a low potential, and the Q point receives the action of the fixed high voltage signal Vdd, which occurs from a low potential to a high potential.
  • the Q point is controlled by Vdd to reach the corresponding set potential, as shown by the first step rising edge of Qn in Figure 4.
  • the following signal may also be used as the precharge pull-down signal Con.
  • the GOA is in front of the GOA drive unit.
  • the downlink unit 26 generates a downlink signal ST(n 1 -1) (second downlink signal) with ST(n 1 -1) as the precharge pull-down signal Con.
  • the precharge down-down signal Con of the nth stage GOA driving unit is ST(n-2).
  • the timing relationship between ST(n-2) and Q satisfies the rising edge of ST(n-2) and the rising edge of Q, and the falling edge of ST(n-2) leads the falling edge of Q. And lags behind the rising edge of Q.
  • the GOA driving circuit driven by two clock signals (2CK) as an example, as shown in FIG. 4, when there is a certain width overlapping portion between the CK clock signal and the high level of the XCK clock signal, that is, the CK clock
  • the above condition can be satisfied by the falling edge of the signal lags the rising edge of the XCK clock signal.
  • the GOA driving circuit operating in the 2CK mode is only used to describe the specific embodiments of the present invention, and does not constitute a limitation of the present invention.
  • the GOA driving circuit of the embodiment of the present invention can be applied to various operating modes. For example, when the circuit is driven in the 8CK mode, the CK terminal is sequentially connected to CK1, CK3, CK5, and CK7, and the XCK terminal is sequentially connected to CK2, CK4, CK6, and CK8, and all GOA driving units are divided into four groups.
  • the downlink signal ST(n-4) corresponding to the n-4th-level GOA driving unit may be used as the pre-charge pull-down signal, or may be adopted corresponding to the n-5th-level GOA driver.
  • the unit's downlink signal ST(n-5) is used as a precharge down-down signal. It is easy to understand that in the latter case, there is a certain width overlap between the high levels of the respective clock signals. A person skilled in the art can select the working mode of the GOA driving circuit as needed, and details are not described herein again.
  • the GOA driving circuit in the embodiment of the present invention has a pre-charge pull-down unit, so that the Q point is electrically
  • the discharge path of the voltage is turned off before the voltage at the Q point changes from the low potential to the high potential, thus ensuring the stability of the Q point voltage and the reliability of the timing, improving the overall performance of the GOA driving circuit, and facilitating the extension of the liquid crystal. Shows the life of the device.

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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
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Abstract

一种GOA驱动电路，包括多级GOA驱动单元，GOA驱动单元包括预充下拉单元（25），预充下拉单元（25）被配置为：在第一电压信号（Q点电压）由低电位跳变为高电位之前，关闭第一电压信号（Q点电压）经由下拉维持单元（24）进行放电的路径。GOA驱动电路保证了电路中关键节点电压的稳定性以及时序的可靠性，提升了GOA驱动电路的整体性能，有利于延长显示设备的寿命。

Description

一种GOA驱动电路
相关申请的交叉引用
本申请要求享有2017年03月31日提交的名称为“一种GOA驱动电路”的中国专利申请CN201710206223.7的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于显示技术领域，尤其涉及一种GOA驱动电路。
背景技术
随着液晶显示技术的发展以及薄膜晶体管(TFT)性能的提升，GOA(Gate On Array)驱动电路已日渐普遍地应用于液晶显示设备中。
GOA驱动电路具有很多的优点，例如由于GOA驱动电路是直接在阵列基板上制作形成的，因此可以节省栅极驱动芯片(Gate IC)的使用，实现显示屏的无边框设计，且有利于提高产品的良率。降低生产成本等。
但另一方面，由于GOA驱动电路是直接设置在阵列基板上的，因此不便于对电路中的元器件进行更换。随着元器件的电性漂移或漏电增加等原因，将导致电路中一些关键节点的电压发生变化，严重时将使GOA驱动电路的动作时序发生错误，造成显示故障。
发明内容
本发明所要解决的技术问题之一是需要提供一种维持节点电压稳定且工作时序可靠的GOA驱动电路。
为了解决上述技术问题，本申请的实施例首先提供了一种GOA驱动电路，包括多级GOA驱动单元，每级GOA驱动单元用于向一行像素单元输出行扫描信号，所述GOA驱动单元进一步包括上拉单元、上拉控制单元、下传单元、下拉单元以及下拉维持单元；所述上拉控制单元输出第一电压信号；所述GOA驱动单元还包括预充下拉单元，所述预充下拉单元被配置为：在所述第一电压信号由低电位跳变为高电位之前，关闭所述第一电压信号经由所述下拉维持单元进行 放电的路径。
优选地，所述下拉维持单元包括第一晶体管，所述第一晶体管的栅极连接所述第一电压信号，其源极连接第一电源信号，其漏极输出第二电压信号，所述第二电压信号被配置为开启或关闭所述路径。
优选地，所述预充下拉单元包括第二晶体管，所述第二晶体管的源极连接所述第一电源信号，其漏极连接所述第二电压信号，其栅极连接预充下拉信号，所述预充下拉信号的上升沿超前于所述第一电压信号的上升沿，所述预充下拉信号的下降沿超前于所述第一电压信号的下降沿且滞后于所述所述第一电压信号的上升沿。
优选地，在与本级GOA驱动单元级联的前一级GOA驱动单元中，下传单元输出作为所述预充下拉信号的第一下传信号。
优选地，对于与本级GOA驱动单元级联的前一级GOA驱动单元来说，在该GOA驱动单元的前面一级GOA驱动单元中，下传单元输出作为所述预充下拉信号的第二下传信号。
优选地，所述上拉控制单元包括第三晶体管，所述第三晶体管的栅极连接与本级GOA驱动单元级联的前一级GOA驱动单元的下传单元所输出的第一下传信号，其源极连接所述第一电压信号，其漏极连接第二电源信号。
优选地，所述下拉维持单元还包括：第四晶体管，其栅极连接所述第二电压信号，其源极连接所述第一电源信号，其漏极连接所述第一电压信号；第五晶体管，其栅极与源极分别与所述第四晶体管的栅极与源极相连接，其漏极连接对应于其所属的GOA驱动单元的行扫描信号；第六晶体管，其栅极与漏极共同连接第三电源信号，其源极连接所述第二电压信号。
优选地，所述下传单元包括第七晶体管，所述第七晶体管的栅极连接所述第一电压信号，其漏极连接时钟信号，其源极输出第三下传信号。
优选地，所述上拉单元包括：第八晶体管，其栅极连接所述第一电压信号，其漏极连接时钟信号，其源极输出对应于其所属的GOA驱动单元的行扫描信号；自举电容，其并联连接于所述第八晶体管的栅极与源极之间。
优选地，所述下拉单元包括第九晶体管与第十晶体管，所述第九晶体管的栅极和源极分别与所述第十晶体管的栅极和源极相连接，所述第九晶体管的漏极连接所述第一电压信号，所述第十晶体管的漏极连接对应于其所属的GOA驱动单元的行扫描信号。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
通过在各级GOA驱动单元内设置预充下拉单元，使得Q点电压的放电路径在Q点电压由低电位跳变为高电位之前就已经被关闭，因此保证了电路中关键节点电压的稳定性以及时序的可靠性，提升了GOA驱动电路的整体性能，有利于延长液晶显示设备的寿命。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1为现有技术中一种GOA驱动单元的结构示意图；
图2为根据本发明一实施例的一级GOA驱动单元的结构示意图；
图3为根据本发明另一实施例的一级GOA驱动单元的结构示意图；
图4为根据本发明又一实施例的GOA驱动电路的工作时序图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
图1为现有技术中一种GOA驱动单元的结构示意图，实际的GOA驱动电路一般由多级如图所示的GOA驱动单元相互连接构成，一级GOA驱动单元用于向一行像素单元输出行扫描信号。
如图1所示，现有GOA驱动电路一般设置有上拉控制单元11、上拉单元12、下拉单元13以及下拉维持单元14等。其中，上拉控制单元11与上拉单元 12相连接，可以在特定的时序中向上拉单元12输出一个控制信号，以图1中的Q点电压来表示，该控制信号用于开启上拉单元12输出行扫描信号。下拉单元13用于将本级GOA驱动单元的行扫描信号和Q点电压下拉至低电位，下拉维持单元14则用于在非本行像素单元的扫描期间内，维持行扫描信号和Q点电压的低电位。
可以看出，Q点电压的数值以及动作的时序是否符合要求对GOA驱动电路功能的实现至关重要。而在实际使用中，当Q点电压从低电位跳变为高电位时，容易发生驱动(Boost)不起来的情况。
本发明实施例针对上述问题提出一种GOA驱动单元，其结构如图2所示。本发明实施例的GOA驱动单元除包括上拉控制单元21、上拉单元22、下拉单元23以及下拉维持单元24之外，还设置有预充下拉单元25与下传单元26。
预充下拉单元25与下拉维持单元24相连接，该预充下拉单元25被配置为，在Q点电压(第一电压信号)由低电位跳变为高电位之前，关闭Q点电压经由下拉维持单元24进行放电的路径。下面结合另一个具体的实施例对本发明进行说明。
图3为根据本发明另一实施例的一级GOA驱动单元的结构示意图。如图3所示，晶体管t11(第三晶体管)构成上拉控制单元21，晶体管t11的栅极连接与本级GOA驱动单元级联的前一级GOA驱动单元所输出的下传信号STn1(n1的值小于n的值)。t11的源极连接Q点，t11的漏极连接连接固定的高电压信号Vdd(第二电源信号)。其中，下传信号STn1由第n1级GOA驱动单元的下传单元26产生。
如图3所示，下传单元26主要包括晶体管t22(第七晶体管)，t22的栅极连接Q点，t22的漏极连接时钟信号CK，t22的源极输出下传信号STn(对应于本级GOA驱动单元的第三下传信号)。在本发明实施例中，设置下传单元26也可在一定程度上减少本级GOA驱动单元的Q点在其电压维持阶段经由上拉单元22发生漏电。
本实施例中的上拉单元22包括晶体管t21(第八晶体管)和自举电容Cb。其中，自举电容Cb并联连接在t21的栅极与源极之间。t21的漏极连接时钟信号CK，t21的源极作为本级GOA驱动单元的行扫描信号输出端，输出相应的行扫描信号Gn，而t21的栅极连接在Q点。
本实施例中的下拉单元23包括晶体管t31(第十晶体管)和晶体管t41(第 九晶体管)。其中，t31的栅极和源极分别与t41的栅极和源极相连接，t31的漏极连接本级GOA驱动单元的行扫描信号，可用于拉低相应的行扫描信号，而t41的漏极同样连接在Q点。t31与t41的栅极由下拉信号Gn2控制(Gn2为对应于第n2级GOA驱动单元的行扫描信号，n2的值大于n的值)。t31与t41的源极连接固定的低电平信号Vss。
通过上述连接关系也可以看出，Q点为众多支路的汇聚点，因此Q点的电压以及工作时序对电路驱动功能的实现至关重要。
进一步地请参见上拉控制单元21，当STn1为高电平信号时，晶体管t11开启，Q点接收到电源Vdd的高电平，由低电位跳变为高电位。
晶体管t11的源极还同时连接晶体管t52(第一晶体管)的栅极，t52的源极连接固定的低电压信号Vss(第一电源信号)，t52的漏极输出的电压信号(第二电压信号)以P点的电压来表示。t52的漏极连接晶体管t42(第四晶体管)的栅极，t42的源极连接固定的低电压信号Vss，t42的漏极连接Q点。则当P点电压为高电位时，晶体管t42开启，Q点电压将从高电位被拉低至低电位，即Q点会经由晶体管t42进行放电。当P点电压为低电位时，晶体管t42关闭，Q点电压可以保持在高电位。因此，通过控制P点电压的数值就可以开启或关闭Q点的放电路径。
另外，本实施例中的下拉维持单元24除包括晶体管t52以及t42外，还包括晶体管t32(第五晶体管)与晶体管t51(第六晶体管)。t32的栅极和源极分别与晶体管t42的栅极和源极相连接，t32的漏极连接行扫描信号，用于在适当的时序中将行扫描信号拉低至低电位。t51的栅极与漏极共同连接固定的高电压信号LC(第三电源信号)，t51的源极连接P点，t51可以使得P点电时处于高电位，进而维持晶体管t42处于开启的状态。
在本发明实施例中，预充下拉单元25包括一个晶体管t61(第二晶体管)。t61的栅极连接预充下拉信号Con，t61的源极连接固定的低电压信号Vss，t61的漏极连接P点，以控制P点电压。具体的，当预充下拉信号Con为高电压信号时，晶体管t61开启，P点电压被拉低至低电位，进而使得晶体管t42关闭。当预充下拉信号Con为低电压信号时，晶体管t61关闭，P点电压在晶体管t51的控制下跳变为高电位，如图3所示。
进一步地，在本发明实施例中，预充下拉信号Con与电压信号Q之间需满足一定的时序关系，具体为，Con的上升沿超前于Q的上升沿，Con的下降沿超 前于Q的下降沿且滞后于Q的上升沿。
由于Con的上升沿超前于Q的上升沿到来，因此在Q点电压尚未从低电位跳变为高电位之前，Con就可以将晶体管t61开启，进而将P点的电压拉低至低电位，使得晶体管42关闭，即在Q点由低电位跳变为高电位之前就关闭Q点的放电路径，以保证Q点的电压可以可靠地被拉高。当Q点电压跳变为高电位后，晶体管t52在Q点电压的控制下开启，利用t52来拉低P点电位。
由于Con的下降沿超前于Q的下降沿(且同时滞后于Q的上升沿)，因此，当Con电压跳变为低电位后，晶体管t61关闭，不再对P点电压形成钳制，P点的电压完全由Q点电压以及LC来进行控制。
现有技术中的GOA驱动电路由于不具有晶体管t61，可能导致Q点电压出现提升不起来的情况。具体的，如图3所示，当Q点电压开始从低电位向高电位跳变的起始阶段，由于此时晶体管t42是处于开启状态的，而只有Q点电压处于高电位时才能使晶体管t42关闭。如果P点电压未能被及时拉低，则将导致Q点在预充电阶段发生漏电，那么Q点就有可能提升不起来。也就是说，Q点电压的跳变与P点电压的跳变之间存在一个竞争的关系。
即使Q点与P点之间的时序在设计阶段，或产品的初期使用阶段都能满足对应的时序关系，但随着元器件的电性漂移或漏电增加等原因，这种时序上的可靠度会逐渐降低，并有可能随着产品的使用进一步加剧，最终出现时序错误，导致驱动电路的功能失效，是电路中较危险薄弱的一个环节。
而在本发明的实施例中，通过在Q点电压发生跳变前关闭Q点的放电路径，同时在Q点发生下一次跳变时(由高电位跳变为低电位时)将对P点电压的控制权交还给Q点，充分保证了工作时序的可靠性。提高了整个GOA驱动电路工作的可靠性，有利于延长产品的使用寿命。
在本发明的一个实施例中，可以采用与上拉控制单元21的控制端的控制信号相同的信号来作为预充下拉信号Con。如图3所示，上拉控制单元21的控制信号STn1为与本级GOA驱动单元级联的前一级GOA驱动单元中，下传单元26的输出信号STn1(第一下传信号)。
举例而言，如果GOA驱动电路采用前后级逐级级联的形式，第n级GOA驱动单元的预充下拉信号Con为ST(n-1)。下面结合图4所示的时序图进行说明。
假设以采用2个时钟信号(2CK)进行驱动的GOA驱动电路为例，时钟信号CK和XCK分别间隔接入各级GOA驱动单元，第n级GOA驱动单元的上拉 控制单元21接收第n-1级GOA驱动单元所产生的下传信号ST(n-1)。如图4所示，第n-1级GOA驱动单元在XCK为高电平时输出下传信号ST(n-1)。在ST(n-1)的作用下，晶体管t11与晶体管t61同时开启，P点电压被拉低至低电位，而Q点接收固定的高电压信号Vdd的作用，发生从低电位到高电位的第一次跳变，Q点受Vdd控制达到相应的设定电位，如图4中Qn的第一级阶梯式上升沿所示。
在接下来的时序中，CK变为高电平，此时Q点电压受CK的影响发生第二次跳变，如图4中Qn的第二级阶梯式上升沿所示。而P点仍在Q点的控制下保持为低电位。至于图4中STn、G(n-1)以及Gn等信号的输出波形可以根据现有技术得出，此处不再赘述。
在本发明的其他实施例中，还可以采用如下信号作为预充下拉信号Con，对于与本级GOA驱动单元级联的前一级GOA驱动单元来说，在该GOA驱动单元的前面一级GOA驱动单元中，下传单元26会产生下传信号ST(n1-1)(第二下传信号)，以ST(n1-1)作为预充下拉信号Con。
举例而言，如果GOA驱动电路采用前后级逐级级联的形式，第n级GOA驱动单元的预充下拉信号Con为ST(n-2)。但此时应保证ST(n-2)与Q之间的时序关系满足ST(n-2)的上升沿超前于Q的上升沿，ST(n-2)的下降沿超前于Q的下降沿且滞后于Q的上升沿。仍以采用2个时钟信号(2CK)进行驱动的GOA驱动电路为例，如图4所示，当CK时钟信号与XCK时钟信号的高电平之间存在一定宽度的交叠部分，即CK时钟信号的下降沿滞后于XCK时钟信号的上升沿，就可以满足上述条件。
另外，需要说明的是，上述工作于2CK模式的GOA驱动电路仅用于对本发明的具体实施例方式进行说明，并不构成对本发明的限定。实际上，本发明实施例的GOA驱动电路可以适用于多种工作模式。例如，当采用8CK模式对电路进行驱动时，CK端依次连接CK1、CK3、CK5以及CK7，XCK端依次连接CK2、CK4、CK6以及CK8，同时将全部GOA驱动单元分为四组。那么对于第n级GOA驱动单元，可以采用对应于第n-4级GOA驱动单元的下传信号ST(n-4)来作为预充下拉信号，也可以采用对应于第n-5级GOA驱动单元的下传信号ST(n-5)来作为预充下拉信号。容易理解的是，在后面一种情况中，各时钟信号的高电平之间存在一定宽度的交叠。本领域技术人员可以根据需要对GOA驱动电路的工作模式进行选择，此处不再赘述。
本发明实施例中的GOA驱动电路，由于设置了预充下拉单元，使得Q点电 压的放电路径在Q点电压由低电位跳变为高电位之前就已经被关闭，因此保证了Q点电压的稳定性以及时序的可靠性，提升了GOA驱动电路的整体性能，有利于延长液晶显示设备的寿命。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种GOA驱动电路，包括多级GOA驱动单元，每级GOA驱动单元用于向一行像素单元输出行扫描信号，所述GOA驱动单元进一步包括上拉单元、上拉控制单元、下传单元、下拉单元以及下拉维持单元；所述上拉控制单元输出第一电压信号；
    所述GOA驱动单元还包括预充下拉单元，所述预充下拉单元被配置为：在所述第一电压信号由低电位跳变为高电位之前，关闭所述第一电压信号经由所述下拉维持单元进行放电的路径。
  2. 根据权利要求1所述的GOA驱动电路，其中，所述下拉维持单元包括第一晶体管，所述第一晶体管的栅极连接所述第一电压信号，其源极连接第一电源信号，其漏极输出第二电压信号，所述第二电压信号被配置为开启或关闭所述路径。
  3. 根据权利要求2所述的GOA驱动电路，其中，所述预充下拉单元包括第二晶体管，所述第二晶体管的源极连接所述第一电源信号，其漏极连接所述第二电压信号，其栅极连接预充下拉信号，所述预充下拉信号的上升沿超前于所述第一电压信号的上升沿，所述预充下拉信号的下降沿超前于所述第一电压信号的下降沿且滞后于所述所述第一电压信号的上升沿。
  4. 根据权利要求3所述的GOA驱动电路，其中，在与本级GOA驱动单元级联的前一级GOA驱动单元中，下传单元输出作为所述预充下拉信号的第一下传信号。
  5. 根据权利要求4所述的GOA驱动电路，其中，所述上拉控制单元包括第三晶体管，所述第三晶体管的栅极连接与本级GOA驱动单元级联的前一级GOA驱动单元的下传单元所输出的第一下传信号，其源极连接所述第一电压信号，其漏极连接第二电源信号。
  6. 根据权利要求4所述的GOA驱动电路，其中，所述下拉维持单元还包括：
    第四晶体管，其栅极连接所述第二电压信号，其源极连接所述第一电源信号，其漏极连接所述第一电压信号；
    第五晶体管，其栅极与源极分别与所述第四晶体管的栅极与源极相连接，其漏极连接对应于其所属的GOA驱动单元的行扫描信号；
    第六晶体管，其栅极与漏极共同连接第三电源信号，其源极连接所述第二电 压信号。
  7. 根据权利要求4所述的GOA驱动电路，其中，所述下传单元包括第七晶体管，所述第七晶体管的栅极连接所述第一电压信号，其漏极连接时钟信号，其源极输出第三下传信号。
  8. 根据权利要求4所述的GOA驱动电路，其中，所述上拉单元包括：
    第八晶体管，其栅极连接所述第一电压信号，其漏极连接时钟信号，其源极输出对应于其所属的GOA驱动单元的行扫描信号；
    自举电容，其并联连接于所述第八晶体管的栅极与源极之间。
  9. 根据权利要求4所述的GOA驱动电路，其中，所述下拉单元包括第九晶体管与第十晶体管，所述第九晶体管的栅极和源极分别与所述第十晶体管的栅极和源极相连接，所述第九晶体管的漏极连接所述第一电压信号，所述第十晶体管的漏极连接对应于其所属的GOA驱动单元的行扫描信号。
  10. 根据权利要求3所述的GOA驱动电路，其中，对于与本级GOA驱动单元级联的前一级GOA驱动单元来说，在该GOA驱动单元的前面一级GOA驱动单元中，下传单元输出作为所述预充下拉信号的第二下传信号。
  11. 根据权利要求10所述的GOA驱动电路，其中，所述上拉控制单元包括第三晶体管，所述第三晶体管的栅极连接与本级GOA驱动单元级联的前一级GOA驱动单元的下传单元所输出的第一下传信号，其源极连接所述第一电压信号，其漏极连接第二电源信号。
  12. 根据权利要求10所述的GOA驱动电路，其中，所述下拉维持单元还包括：
    第四晶体管，其栅极连接所述第二电压信号，其源极连接所述第一电源信号，其漏极连接所述第一电压信号；
    第五晶体管，其栅极与源极分别与所述第四晶体管的栅极与源极相连接，其漏极连接对应于其所属的GOA驱动单元的行扫描信号；
    第六晶体管，其栅极与漏极共同连接第三电源信号，其源极连接所述第二电压信号。
  13. 根据权利要求10所述的GOA驱动电路，其中，所述下传单元包括第七晶体管，所述第七晶体管的栅极连接所述第一电压信号，其漏极连接时钟信号，其源极输出第三下传信号。
  14. 根据权利要求10所述的GOA驱动电路，其中，所述上拉单元包括：
    第八晶体管，其栅极连接所述第一电压信号，其漏极连接时钟信号，其源极输出对应于其所属的GOA驱动单元的行扫描信号；
    自举电容，其并联连接于所述第八晶体管的栅极与源极之间。
  15. 根据权利要求10所述的GOA驱动电路，其中，所述下拉单元包括第九晶体管与第十晶体管，所述第九晶体管的栅极和源极分别与所述第十晶体管的栅极和源极相连接，所述第九晶体管的漏极连接所述第一电压信号，所述第十晶体管的漏极连接对应于其所属的GOA驱动单元的行扫描信号。
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