WO2020118971A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2020118971A1
WO2020118971A1 PCT/CN2019/080230 CN2019080230W WO2020118971A1 WO 2020118971 A1 WO2020118971 A1 WO 2020118971A1 CN 2019080230 W CN2019080230 W CN 2019080230W WO 2020118971 A1 WO2020118971 A1 WO 2020118971A1
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WO
WIPO (PCT)
Prior art keywords
transistor
signal
level
electrically connected
node
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Application number
PCT/CN2019/080230
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English (en)
French (fr)
Inventor
陈帅
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020118971A1 publication Critical patent/WO2020118971A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA Gate Driver on Array
  • integrated gate drive circuit integrates the gate drive circuit on the array substrate of the display panel, so that the gate drive integrated circuit part can be omitted, from the material cost and The production process reduces the product cost in two aspects.
  • Such a gate switch circuit integrated on an array substrate using GOA technology is also called a GOA circuit or a shift register circuit, where each shift register in the gate switch circuit is also called a GOA unit.
  • stage transmission structure of the existing GOA circuit is complete and continuous, that is, each stage GOA unit is sequentially turned on and off in the order of stage transmission, and the GOA circuit cannot realize the suspension and opening of stage transmission.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can realize the pause and start of the stage transmission.
  • An embodiment of the present application provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes: cascade control module, pull-up control module, download module, pull-up module, pull-down module, pull-down Maintenance module and energy storage module;
  • the cascade control module accesses the first control signal, the second control signal, the upper-level scan signal and the low-level signal, and is electrically connected to the pull-up control module for use in the first control signal And output the upper-level scan signal or the low-level signal to the pull-up control module under the control of the second control signal;
  • the pull-up control module connects to the upper-level transmission signal and is electrically connected to the first node, and is used to control the upper-level scanning signal or the low level under the control of the upper-level transmission signal.
  • the level signal is output to the first node;
  • the download module is connected to a first clock signal and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;
  • the pull-up module is connected to the first clock signal and is electrically connected to the first node, and is used to output a scan signal at the current level under the control of the potential of the first node;
  • the pull-down module accesses the next-level scan signal and the low-level signal, and is electrically connected to the first node and the current-level scan signal, and is used to pull-down the scan signal according to the next-level scan signal The potential of the first node and the potential of the scanning signal at this level;
  • the pull-down maintenance module accesses the low-level signal and is electrically connected to the first node and the current-level scan signal for pulling down the potential of the first node and the Maintaining the potential of the first node and the potential of the scan signal of the current level at the potential of the low-level signal after the potential of the scan signal of the current level;
  • the energy storage module is electrically connected to the first node and the current-level scan signal, and is used for storing the potential of the first node and the potential of the first node and the potential of the current-level scan signal Equipotential jump occurs;
  • the cascade control module includes: a first transistor and a second transistor;
  • the source of the first transistor is electrically connected to the scan signal of the previous stage, the gate of the first transistor is electrically connected to the first control signal; the source of the second transistor is electrically connected For the low-level signal, the gate of the second transistor is electrically connected to the second control signal; the drain of the first transistor and the drain of the second transistor are electrically connected to the Pull-up control module;
  • the pull-up control module includes: a third transistor
  • the source of the third transistor is electrically connected to the cascade control module, the gate of the third transistor is electrically connected to the signal of the previous stage, and the drain of the third transistor is electrically Connected to the first node.
  • the polarity of the first control signal and the polarity of the second control signal Same sex
  • the polarities of the first control signal and the second control signal are the same.
  • the download module includes: a fourth transistor
  • the source of the fourth transistor is electrically connected to the first clock signal, the gate of the fourth transistor is electrically connected to the first node, and the drain of the fourth transistor is electrically connected to the Describe the signal at this level.
  • the pull-up module includes: a fifth transistor
  • the source of the fifth transistor is electrically connected to the first clock signal, the gate of the fifth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the Describe the scanning signal at this level.
  • the pull-down module includes: a sixth transistor and a seventh transistor;
  • the source of the sixth transistor and the source of the seventh transistor are both electrically connected to the low-level signal; the gate of the sixth transistor and the gate of the seventh transistor are both electrically connected At the next-level scan signal; the drain of the sixth transistor is electrically connected to the first node, and the drain of the seventh transistor is electrically connected to the current-level scan signal.
  • the pull-down sustaining module includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the source and gate of the eighth transistor and the source of the ninth transistor are all electrically connected to the second clock signal; the drain of the eighth transistor is electrically connected to the gate of the ninth transistor And the source of the twelfth transistor; the drain of the ninth transistor is electrically connected to the gate of the tenth transistor, the gate of the eleventh transistor, and the source of the thirteenth transistor Level; the drain of the tenth transistor, the drain of the eleventh transistor, the source of the twelfth transistor, and the source of the thirteenth transistor are all electrically connected to the low level Signal; the drain of the tenth transistor is electrically connected to the current scan signal, the drain of the eleventh transistor, the gate of the twelfth transistor, and the gate of the thirteenth transistor It is electrically connected to the first node.
  • the energy storage module includes: a capacitor
  • One end of the capacitor is electrically connected to the first node, and the other end of the capacitor is electrically connected to the current scan signal.
  • An embodiment of the present application further provides a GOA circuit, including: a multi-level cascaded GOA unit, each level of GOA unit includes: a cascade control module, a pull-up control module, a download module, a pull-up module, a pull-down module, Pull-down maintenance module and energy storage module;
  • the cascade control module accesses the first control signal, the second control signal, the upper-level scan signal and the low-level signal, and is electrically connected to the pull-up control module for use in the first control signal And output the upper-level scan signal or the low-level signal to the pull-up control module under the control of the second control signal;
  • the pull-up control module connects to the upper-level transmission signal and is electrically connected to the first node, and is used to control the upper-level scanning signal or the low level under the control of the upper-level transmission signal.
  • the level signal is output to the first node;
  • the download module is connected to a first clock signal and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;
  • the pull-up module is connected to the first clock signal and is electrically connected to the first node, and is used to output a scan signal at the current level under the control of the potential of the first node;
  • the pull-down module accesses the next-level scan signal and the low-level signal, and is electrically connected to the first node and the current-level scan signal, and is used to pull-down the scan signal according to the next-level scan signal The potential of the first node and the potential of the scanning signal at this level;
  • the pull-down maintenance module accesses the low-level signal and is electrically connected to the first node and the current-level scan signal for pulling down the potential of the first node and the Maintaining the potential of the first node and the potential of the scan signal of the current level at the potential of the low-level signal after the potential of the scan signal of the current level;
  • the energy storage module is electrically connected to the first node and the current-level scan signal, and is used for storing the potential of the first node and the potential of the first node and the potential of the current-level scan signal Equipotential jump occurs.
  • the cascade control module includes: a first transistor and a second transistor;
  • the source of the first transistor is electrically connected to the scan signal of the previous stage, the gate of the first transistor is electrically connected to the first control signal; the source of the second transistor is electrically connected For the low-level signal, the gate of the second transistor is electrically connected to the second control signal; the drain of the first transistor and the drain of the second transistor are electrically connected to the Pull up the control module.
  • the polarity of the first control signal and the polarity of the second control signal Same sex
  • the polarities of the first control signal and the second control signal are the same.
  • the pull-up control module includes: a third transistor
  • the source of the third transistor is electrically connected to the cascade control module, the gate of the third transistor is electrically connected to the signal of the previous stage, and the drain of the third transistor is electrically Connected to the first node.
  • the download module includes: a fourth transistor
  • the source of the fourth transistor is electrically connected to the first clock signal, the gate of the fourth transistor is electrically connected to the first node, and the drain of the fourth transistor is electrically connected to the Describe the signal at this level.
  • the pull-up module includes: a fifth transistor
  • the source of the fifth transistor is electrically connected to the first clock signal, the gate of the fifth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the Describe the scanning signal at this level.
  • the pull-down module includes: a sixth transistor and a seventh transistor;
  • the source of the sixth transistor and the source of the seventh transistor are both electrically connected to the low-level signal; the gate of the sixth transistor and the gate of the seventh transistor are both electrically connected At the next-level scan signal; the drain of the sixth transistor is electrically connected to the first node, and the drain of the seventh transistor is electrically connected to the current-level scan signal.
  • the pull-down sustaining module includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the source and gate of the eighth transistor and the source of the ninth transistor are all electrically connected to the second clock signal; the drain of the eighth transistor is electrically connected to the gate of the ninth transistor And the source of the twelfth transistor; the drain of the ninth transistor is electrically connected to the gate of the tenth transistor, the gate of the eleventh transistor, and the source of the thirteenth transistor Level; the drain of the tenth transistor, the drain of the eleventh transistor, the source of the twelfth transistor, and the source of the thirteenth transistor are all electrically connected to the low level Signal; the drain of the tenth transistor is electrically connected to the current scan signal, the drain of the eleventh transistor, the gate of the twelfth transistor, and the gate of the thirteenth transistor It is electrically connected to the first node.
  • the energy storage module includes: a capacitor
  • One end of the capacitor is electrically connected to the first node, and the other end of the capacitor is electrically connected to the current scan signal.
  • An embodiment of the present application further provides a display panel, which includes a GOA circuit.
  • the GOA circuit includes: a multi-stage cascaded GOA unit, and each stage of the GOA unit includes: a cascade control module, a pull-up control module, and a download Module, pull-up module, pull-down module, pull-down maintenance module and energy storage module;
  • the cascade control module accesses the first control signal, the second control signal, the upper-level scan signal and the low-level signal, and is electrically connected to the pull-up control module for use in the first control signal And output the upper-level scan signal or the low-level signal to the pull-up control module under the control of the second control signal;
  • the pull-up control module connects to the upper-level transmission signal and is electrically connected to the first node, and is used to control the upper-level scanning signal or the low level under the control of the upper-level transmission signal.
  • the level signal is output to the first node;
  • the download module is connected to a first clock signal and is electrically connected to the first node, and is used to output a local transmission signal under the potential control of the first node;
  • the pull-up module is connected to the first clock signal and is electrically connected to the first node, and is used to output a scan signal at the current level under the control of the potential of the first node;
  • the pull-down module accesses the next-level scan signal and the low-level signal, and is electrically connected to the first node and the current-level scan signal, and is used to pull-down the scan signal according to the next-level scan signal The potential of the first node and the potential of the scanning signal at this level;
  • the pull-down maintenance module accesses the low-level signal and is electrically connected to the first node and the current-level scan signal for pulling down the potential of the first node and the Maintaining the potential of the first node and the potential of the scan signal of the current level at the potential of the low-level signal after the potential of the scan signal of the current level;
  • the energy storage module is electrically connected to the first node and the current-level scan signal, and is used for storing the potential of the first node and the potential of the first node and the potential of the current-level scan signal Equipotential jump occurs;
  • the cascade control module when the display panel is in a working state, the cascade control module outputs the upper-level scan signal to the pull-up control module; when the display panel is in a suspended state, the cascade control The module outputs the low-level signal to the pull-up control module.
  • the cascade control module includes: a first transistor and a second transistor;
  • the source of the first transistor is electrically connected to the scan signal of the previous stage, the gate of the first transistor is electrically connected to the first control signal; the source of the second transistor is electrically connected For the low-level signal, the gate of the second transistor is electrically connected to the second control signal; the drain of the first transistor and the drain of the second transistor are electrically connected to the Pull up the control module.
  • the cascade control module by adding a cascade control module to each stage of the GOA unit, when the display panel is in a normal working state, the cascade control module outputs the scan signal of the previous stage to the pull-up control The module, the GOA circuit stage transmission is normally opened; when the display panel is in an abnormal pause state, the cascade control module outputs a low-level signal to the pull-up control module, the GOA circuit stage transmission is suspended, thereby achieving the suspension and opening of the GOA circuit stage transmission, Furthermore, it enriches the control functions of the GOA circuit and improves the reliability of the display panel.
  • FIG. 1 is a schematic structural diagram of a GOA unit provided by an embodiment of this application.
  • FIG. 2 is a first circuit diagram of a GOA unit provided by an embodiment of this application.
  • FIG. 3 is a second circuit diagram of the GOA unit provided by the embodiment of the present application.
  • FIG. 5 is a fourth circuit diagram of the GOA unit provided by the embodiment of the present application.
  • FIG. 6 is a timing diagram corresponding to the GOA unit shown in FIG. 2 in a suspended state.
  • the transistors used in all the embodiments of this application may be thin film transistors, field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called a source electrode, and the other electrode is called a drain electrode. According to the form in the drawing, the middle end of the switching transistor is a gate, the signal input end is a drain, and the output end is a source.
  • the transistors used in the embodiments of the present application may include two types of P-type transistors and/or N-type transistors, where the P-type transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type transistor is at The gate turns on when the gate is high, and turns off when the gate is low.
  • the GOA circuit of the embodiment of the present application includes a multi-level cascaded GOA unit.
  • each level of GOA unit in the GOA circuit of the embodiment of the present application can be turned on and off in turn according to the order of level transmission; and, the GOA circuit of the embodiment of the present application can also realize the suspension and opening of the level transmission to enrich Control function of GOA circuit.
  • FIG. 1 is a schematic structural diagram of a GOA unit provided by an embodiment of the present application.
  • the GOA unit provided by the embodiment of the present application includes: a cascade control module 101, a pull-up control module 102, a download module 103, a pull-up module 104, a pull-down module 105, a pull-down maintenance module 106, and an energy storage module 107.
  • the cascade control module 101 is connected to the first control signal C12, the second control signal C13, the upper-level scan signal G(N-1) and the low-level signal VSS, and is electrically connected to the pull-up control module 102, Under the control of the first control signal C12 and the second control signal C13, the upper-level scan signal G(N-1) or the low-level signal VSS is output to the pull-up control module 102.
  • the pull-up control module 102 accesses the upper-level transmission signal ST(N-1) and is electrically connected to the first node Q(N) for controlling the transmission of the upper-level signal ST(N-1) Next, the upper-level scan signal G(N-1) or the low-level signal VSS is output to the first node Q(N).
  • the download module 103 is connected to the first clock signal CK, and is electrically connected to the first node Q(N), and is used for outputting the stage transmission signal ST(N) under the control of the potential of the first node Q(N).
  • the pull-up module 104 is connected to the first clock signal CK and is electrically connected to the first node Q(N), and is used to output the current scan signal G(N) under the control of the potential of the first node Q(N).
  • the pull-down module 105 is connected to the next-level scan signal and the low-level signal VSS, and is electrically connected to the first node Q(N) and the current-level scan signal G(N) to pull down the first according to the next-level scan signal The potential of the node Q(N) and the potential of the scanning signal G(N) of this stage.
  • the pull-down sustaining module 106 is connected to the low-level signal VSS, and is electrically connected to the first node Q(N) and the current scan signal G(N) for pulling down the potential of the first node Q(N) at the pull-down module 105 And the potential of the scanning signal G(N) of the current stage, and then maintain the potential of the first node Q(N) and the potential of the scanning signal G(N) of the current stage at the potential of the low-level signal VSS;
  • the energy storage module 107 is electrically connected to the first node Q(N) and the current scan signal G(N), and is used to store the potential of the first node Q(N) and make the potential of the first node Q(N) The potential of the stage scanning signal G(N) jumps equipotentially.
  • the GOA unit includes: a cascade control module 101, a pull-up control module 102, a download module 103, a pull-up module 104, a pull-down module 105, a pull-down maintenance module 106, and an energy storage module 107, wherein
  • the cascade control module 101 can output the upper-level scan signal G(N-1) or the low-level signal VSS to the pull-up control module 102 under the control of the first control signal C12 and the second control signal C13, so the cascade control module 101 can make the GOA circuit in a working state or a suspended state.
  • the cascade control module 101 can output the upper-level scan signal G(N-1) to the pull-up control module 102; when the GOA circuit is in the suspended state, the cascade control module 101 can turn off the power The level signal VSS is output to the pull-up control module 102, thereby suspending the operation of the GOA circuit.
  • FIG. 2 is a first circuit diagram of a GOA unit provided by an embodiment of the present application
  • FIG. 3 is a second circuit diagram of a GOA unit provided by an embodiment of the present application
  • FIG. 5 is the fourth circuit diagram of the GOA unit provided by the embodiment of the application.
  • FIG. 2 is a first circuit diagram of a GOA unit provided by an embodiment of the present application
  • FIG. 3 is a second circuit diagram of a GOA unit provided by an embodiment of the present application
  • FIG. 5 is the fourth circuit diagram of the GOA unit provided by the embodiment of the application.
  • FIG. 2 is a first circuit diagram of a GOA unit provided by an embodiment of the present application
  • FIG. 3 is a second circuit diagram of a GOA unit provided by an embodiment of the present application
  • FIG. 5 is the fourth circuit
  • the cascade control module 101 includes: a first transistor T12 and a second transistor T13; the source of the first transistor T12 is electrically connected to the scan signal G ( N-1), the gate of the first transistor T12 is electrically connected to the first control signal C12; the source of the second transistor T13 is electrically connected to the low-level signal VSS, and the gate of the second transistor T13 is electrically connected to The second control signal C13; the drain of the first transistor T12 and the drain of the second transistor T13 are electrically connected to the pull-up control module 102.
  • both the first transistor T12 and the second transistor T13 are N-type transistors, and the polarities of the first control signal C12 and the second control signal C13 are opposite. That is, when the GOA circuit is in the working state, the first control signal C12 is at a high level, the second control signal C13 is at a low level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the upper-level scanning signal G(N-1) is output to the pull-up control module 102 via the first transistor T12; when the GOA circuit is in the suspended state, the first control signal C12 is low, the second control signal C13 is high, and the first transistor T12 Turning off, the second transistor T13 is turned on, so that the low-level signal VSS is output to the pull-up control module 102 via the second transistor T13.
  • both the first transistor T12 and the second transistor T13 are P-type transistors, and the polarities of the first control signal C12 and the second control signal C13 are opposite. That is, when the GOA circuit is in the working state, the first control signal C12 is at a low level, the second control signal C13 is at a high level, the first transistor T12 is turned on, and the second transistor T13 is turned off, thereby making the upper-level scanning signal G(N-1) is output to the pull-up control module 102 via the first transistor T12; when the GOA circuit is in the suspended state, the first control signal C12 is high, the second control signal C13 is low, and the first transistor T12 Turning off, the second transistor T13 is turned on, so that the low-level signal VSS is output to the pull-up control module 102 via the second transistor T13.
  • the first transistor T12 is an N-type transistor
  • the second transistor T13 is a P-type transistor
  • the polarities of the first control signal C12 and the second control signal C13 are the same. That is, when the GOA circuit is in the working state, the first control signal C12 is at a high level, the second control signal C13 is at a high level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the upper-level scanning signal G(N-1) is output to the pull-up control module 102 via the first transistor T12; when the GOA circuit is in the suspended state, the first control signal C12 is low, the second control signal C13 is low, and the first transistor T12 Turning off, the second transistor T13 is turned on, so that the low-level signal VSS is output to the pull-up control module 102 via the second transistor T13.
  • the first transistor T12 is a P-type transistor
  • the second transistor T13 is an N-type transistor
  • the polarities of the first control signal C12 and the second control signal C13 are the same. That is, when the GOA circuit is in the working state, the first control signal C12 is at a low level, the second control signal C13 is at a low level, the first transistor T12 is turned on, and the second transistor T13 is turned off, thereby making the upper-level scan signal G(N-1) is output to the pull-up control module 102 via the first transistor T12; when the GOA circuit is in the suspended state, the first control signal C12 is high, the second control signal C13 is high, and the first transistor T12 Turning off, the second transistor T13 is turned on, so that the low-level signal VSS is output to the pull-up control module 102 via the second transistor T13.
  • the pull-up control module 102 includes: a third transistor T11; the source of the third transistor T11 is electrically connected to the cascade control module 101, and the gate of the third transistor T11 It is electrically connected to the upper stage signal ST(N-1), and the drain of the third transistor T11 is electrically connected to the first node Q(N).
  • the download module 103 includes: a fourth transistor T22; a source of the fourth transistor T22 is electrically connected to the first clock signal CK, a gate of the fourth transistor T22 is electrically connected to the first node Q(N), and a fourth transistor The drain of T22 is electrically connected to the signal ST(N) of the current stage.
  • the pull-up module 104 includes: a fifth transistor T21; a source of the fifth transistor T21 is electrically connected to the first clock signal CK, a gate of the fifth transistor T21 is electrically connected to the first node Q(N), a fifth transistor The drain of T21 is electrically connected to the current scan signal G(N).
  • the pull-down module 105 includes: a sixth transistor T41 and a seventh transistor T31; the source of the sixth transistor T41 and the source of the seventh transistor T31 are electrically connected to the low-level signal VSS; the gate of the sixth transistor T41 and the first The gates of the seven transistors T31 are electrically connected to the scan signal of the next stage; the drain of the sixth transistor T41 is electrically connected to the first node Q(N), and the drain of the seventh transistor T31 is electrically connected to the current scan Signal G(N).
  • the pull-down sustaining module 106 includes: an eighth transistor T51, a ninth transistor T53, a tenth transistor T32, an eleventh transistor T42, a twelfth transistor T52 and a thirteenth transistor T54; the source and gate of the eighth transistor T51 and The source of the ninth transistor T53 is electrically connected to the second clock signal LC; the drain of the eighth transistor T51 is electrically connected to the gate of the ninth transistor T53 and the source of the twelfth transistor T52; the ninth transistor T53 Is electrically connected to the gate of the tenth transistor T32, the gate of the eleventh transistor T42, and the source of the thirteenth transistor T54; the drain of the tenth transistor T32, the drain of the eleventh transistor T42, The source of the twelfth transistor T52 and the source of the thirteenth transistor T54 are both electrically connected to the low-level signal VSS; the drain of the tenth transistor T32 is electrically connected to the current scan signal G(N), the tenth The drain
  • the energy storage module 107 includes: a capacitor Cbt; one end of the capacitor Cbt is electrically connected to the first node Q(N), and the other end of the capacitor Cbt is electrically connected to the current scanning signal G(N).
  • the third transistor T11, the fourth transistor T22, the fifth transistor T21, the sixth transistor T41, the seventh transistor T31, the eighth transistor T51, the ninth transistor T53, the tenth transistor T32, the eleventh transistor T42, the twelfth transistor T52 and the thirteenth transistor T54 are all N-type transistors.
  • those skilled in the art can change the third transistor T11, fourth transistor T22, fifth transistor T21, sixth transistor T41, seventh transistor T31, eighth transistor T51, ninth transistor T53, tenth transistor T32,
  • the eleventh transistor T42, the twelfth transistor T52, and the thirteenth transistor T54 are configured as P-type transistors, and are not limited herein.
  • FIG. 6 is a timing diagram corresponding to the GOA unit shown in FIG. 2 in a suspended state. 2 and 6, when the GOA unit is in the suspended state, the first control signal C12 is low, the second control signal C13 is high, the first transistor T12 is turned off, and the second transistor T13 is turned on, thereby The low-level signal VSS is output to the first node Q(N) through the second transistor T13, and then the fourth transistor T22, the fifth transistor T21, the twelfth transistor T52 and the thirteenth transistor T54 are turned off. The G(N) output is low, and the GOA unit stops working.
  • the GOA unit When the GOA unit is in the working state, the first control signal C12 is at a high level, the second control signal C13 is at a high and low level, the first transistor T12 is turned on, and the second transistor T13 is turned off, so that the previous scanning signal G(N -1) Output to the first node Q(N) via the first transistor T12, the GOA unit works normally. It should be noted that the processes corresponding to the working state of the GOA unit are consistent with the prior art, and will not be repeated here.
  • the cascade control module 101 converts the previous stage scan signal G(N-1 ) Output to the pull-up control module 102, the GOA circuit stage transmission is normally turned on; when the display panel is in an abnormal pause state, the cascade control module 101 outputs a low-level signal VSS to the pull-up control module 102, the GOA circuit stage transmission is suspended, thereby achieving The pause and start of the GOA circuit cascade transfer, thereby enriching the control function of the GOA circuit and improving the reliability of the display panel.
  • An embodiment of the present application further provides a display panel, which includes the above GOA circuit, and details are not described herein.
  • the cascade control module 101 When the display panel is in the working state, the cascade control module 101 outputs the upper-level scan signal G(N-1) to the pull-up control module 102; when the display panel is in the suspended state, the cascade control module 101 will turn off The level signal VSS is output to the pull-up control module 102.

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Abstract

一种GOA电路及显示面板，通过在每一级GOA单元中增加一级联控制模块（101），当显示面板处于正常工作状态时，级联控制模块（101）将上一级扫描信号（G(N-1)）输出至上拉控制模块（102），GOA电路级传正常开启；当显示面板处于异常暂停状态时，级联控制模块（101）将低电平信号（VSS）输出至上拉控制模块（102），GOA电路级传暂停，从而实现GOA电路级传的暂停和开启。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。这种利用GOA 技术集成在阵列基板上的栅极开关电路也称为GOA电路或移位寄存器电路，其中该栅极开关电路中的每个移位寄存器也称GOA 单元。
现有的GOA电路的级传结构是完整连续的，即每一级GOA单元均按照级传的顺序依次打开和关闭，GOA电路不能实现级传的暂停和开启。
 技术问题
本申请实施例的目的在于提供一种GOA电路及显示面板，能够实现级传的暂停和开启。
 技术解决方案
本申请实施例提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：级联控制模块、上拉控制模块、下传模块、上拉模块、下拉模块、下拉维持模块以及储能模块；
所述级联控制模块接入第一控制信号、第二控制信号、上一级扫描信号以及低电平信号，并电性连接于所述上拉控制模块，用于在所述第一控制信号和所述第二控制信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述上拉控制模块；
所述上拉控制模块接入上一级级传信号，并电性连接于第一节点，用于在所述上一级级传信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述第一节点；
所述下传模块接入第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号以及所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于根据所述下一级扫描信号下拉所述第一节点的电位以及所述本级扫描信号的电位；
所述下拉维持模块接入所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下拉模块下拉所述第一节点的电位以及所述本级扫描信号的电位后将所述第一节点的电位以及所述本级扫描信号的电位维持在所述低电平信号的电位；
所述储能模块电性连接于所述第一节点以及所述本级扫描信号，用于存储所述第一节点的电位以及使所述第一节点的电位与所述本级扫描信号的电位发生等势跳变；
所述级联控制模块包括：第一晶体管以及第二晶体管；
所述第一晶体管的源极电性连接于所述上一级扫描信号，所述第一晶体管的栅极电性连接于所述第一控制信号；所述第二晶体管的源极电性连接于所述低电平信号，所述第二晶体管的栅极电性连接于所述第二控制信号；所述第一晶体管的漏极以及所述第二晶体管的漏极电性连接于所述上拉控制模块；
所述上拉控制模块包括：第三晶体管；
所述第三晶体管的源极电性连接于所述级联控制模块，所述第三晶体管的栅极电性连接于所述上一级级传信号，所述第三晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，当所述第一晶体管和所述第二晶体管均为N型晶体管或P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相反。
在本申请所述的GOA电路中，当所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同；
或者，当所述第一晶体管为P型晶体管，述第二晶体管为N型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同。
在本申请所述的GOA电路中，所述下传模块包括：第四晶体管；
所述第四晶体管的源极电性连接于所述第一时钟信号，所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述上拉模块包括：第五晶体管；
所述第五晶体管的源极电性连接于所述第一时钟信号，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉模块包括：第六晶体管以及第七晶体管；
所述第六晶体管的源极以及所述第七晶体管的源极均电性连接与所述低电平信号；所述第六晶体管的栅极以及所述第七晶体管的栅极均电性连接于所述下一级扫描信号；所述第六晶体管的漏极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉维持模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
所述第八晶体管的源极、栅极以及所述第九晶体管的源极均电性连接于第二时钟信号；所述第八晶体管的漏极电性连接于所述第九晶体管的栅极以及所述第十二晶体管的源级；所述第九晶体管的漏极电性连接于所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十三晶体管的源级；所述第十晶体管的漏极、所述第十一晶体管的漏极、所述第十二晶体管的源极以及所述第十三晶体管的源极均电性连接于所述低电平信号；所述第十晶体管的漏极电性连接于所述本级扫描信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的栅极均电性连接于所述第一节点。
在本申请所述的GOA电路中，所述储能模块包括：电容；
所述电容的一端电性连接于所述第一节点，所述电容的另一端电性连接于所述本级扫描信号。
本申请实施例还提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：级联控制模块、上拉控制模块、下传模块、上拉模块、下拉模块、下拉维持模块以及储能模块；
所述级联控制模块接入第一控制信号、第二控制信号、上一级扫描信号以及低电平信号，并电性连接于所述上拉控制模块，用于在所述第一控制信号和所述第二控制信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述上拉控制模块；
所述上拉控制模块接入上一级级传信号，并电性连接于第一节点，用于在所述上一级级传信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述第一节点；
所述下传模块接入第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号以及所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于根据所述下一级扫描信号下拉所述第一节点的电位以及所述本级扫描信号的电位；
所述下拉维持模块接入所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下拉模块下拉所述第一节点的电位以及所述本级扫描信号的电位后将所述第一节点的电位以及所述本级扫描信号的电位维持在所述低电平信号的电位；
所述储能模块电性连接于所述第一节点以及所述本级扫描信号，用于存储所述第一节点的电位以及使所述第一节点的电位与所述本级扫描信号的电位发生等势跳变。
在本申请所述的GOA电路中，所述级联控制模块包括：第一晶体管以及第二晶体管；
所述第一晶体管的源极电性连接于所述上一级扫描信号，所述第一晶体管的栅极电性连接于所述第一控制信号；所述第二晶体管的源极电性连接于所述低电平信号，所述第二晶体管的栅极电性连接于所述第二控制信号；所述第一晶体管的漏极以及所述第二晶体管的漏极电性连接于所述上拉控制模块。
在本申请所述的GOA电路中，当所述第一晶体管和所述第二晶体管均为N型晶体管或P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相反。
在本申请所述的GOA电路中，当所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同；
或者，当所述第一晶体管为P型晶体管，述第二晶体管为N型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同。
在本申请所述的GOA电路中，所述上拉控制模块包括：第三晶体管；
所述第三晶体管的源极电性连接于所述级联控制模块，所述第三晶体管的栅极电性连接于所述上一级级传信号，所述第三晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述下传模块包括：第四晶体管；
所述第四晶体管的源极电性连接于所述第一时钟信号，所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述上拉模块包括：第五晶体管；
所述第五晶体管的源极电性连接于所述第一时钟信号，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉模块包括：第六晶体管以及第七晶体管；
所述第六晶体管的源极以及所述第七晶体管的源极均电性连接与所述低电平信号；所述第六晶体管的栅极以及所述第七晶体管的栅极均电性连接于所述下一级扫描信号；所述第六晶体管的漏极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉维持模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
所述第八晶体管的源极、栅极以及所述第九晶体管的源极均电性连接于第二时钟信号；所述第八晶体管的漏极电性连接于所述第九晶体管的栅极以及所述第十二晶体管的源级；所述第九晶体管的漏极电性连接于所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十三晶体管的源级；所述第十晶体管的漏极、所述第十一晶体管的漏极、所述第十二晶体管的源极以及所述第十三晶体管的源极均电性连接于所述低电平信号；所述第十晶体管的漏极电性连接于所述本级扫描信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的栅极均电性连接于所述第一节点。
在本申请所述的GOA电路中，所述储能模块包括：电容；
所述电容的一端电性连接于所述第一节点，所述电容的另一端电性连接于所述本级扫描信号。
本申请实施例还提供一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：级联控制模块、上拉控制模块、下传模块、上拉模块、下拉模块、下拉维持模块以及储能模块；
所述级联控制模块接入第一控制信号、第二控制信号、上一级扫描信号以及低电平信号，并电性连接于所述上拉控制模块，用于在所述第一控制信号和所述第二控制信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述上拉控制模块；
所述上拉控制模块接入上一级级传信号，并电性连接于第一节点，用于在所述上一级级传信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述第一节点；
所述下传模块接入第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述上拉模块接入所述第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级扫描信号以及所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于根据所述下一级扫描信号下拉所述第一节点的电位以及所述本级扫描信号的电位；
所述下拉维持模块接入所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下拉模块下拉所述第一节点的电位以及所述本级扫描信号的电位后将所述第一节点的电位以及所述本级扫描信号的电位维持在所述低电平信号的电位；
所述储能模块电性连接于所述第一节点以及所述本级扫描信号，用于存储所述第一节点的电位以及使所述第一节点的电位与所述本级扫描信号的电位发生等势跳变；
其中，当所述显示面板处于工作状态时，所述级联控制模块将所述上一级扫描信号输出至所述上拉控制模块；当所述显示面板处于暂停状态时，所述级联控制模块将所述低电平信号输出至所述上拉控制模块。
在本申请所述的显示面板中，所述级联控制模块包括：第一晶体管以及第二晶体管；
所述第一晶体管的源极电性连接于所述上一级扫描信号，所述第一晶体管的栅极电性连接于所述第一控制信号；所述第二晶体管的源极电性连接于所述低电平信号，所述第二晶体管的栅极电性连接于所述第二控制信号；所述第一晶体管的漏极以及所述第二晶体管的漏极电性连接于所述上拉控制模块。
 有益效果
本申请实施例提供的GOA电路及显示面板，通过在每一级GOA单元中增加一级联控制模块，当显示面板处于正常工作状态时，级联控制模块将上一级扫描信号输出至上拉控制模块，GOA电路级传正常开启；当显示面板处于异常暂停状态时，级联控制模块将低电平信号输出至上拉控制模块，GOA电路级传暂停，从而实现GOA电路级传的暂停和开启，进而丰富GOA电路的控制功能，提高显示面板的信赖性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA单元的结构示意图；
图2为本申请实施例提供的GOA单元的第一电路图；
图3为本申请实施例提供的GOA单元的第二电路图；
图4为本申请实施例提供的GOA单元的第三电路图；
图5为本申请实施例提供的GOA单元的第四电路图；
图6为图2所示的GOA单元处于暂停状态下对应的时序示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为漏极、输出端为源极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
此外，需要说明的是，本申请实施例的GOA电路包括多级级联的GOA单元。其中，本申请实施例的GOA电路中的每一级GOA单元均可按照级传的顺序依次打开和关闭；并且，本申请实施例的GOA电路还可以实现级传的暂停和开启，以此丰富GOA电路的控制功能。
请参阅图1，图1为本申请实施例提供的GOA单元的结构示意图。如图1所示，本申请实施例提供的GOA单元包括：级联控制模块101、上拉控制模块102、下传模块103、上拉模块104、下拉模块105、下拉维持模块106以及储能模块107。
其中，级联控制模块101接入第一控制信号C12、第二控制信号C13、上一级扫描信号G(N-1)以及低电平信号VSS，并电性连接于上拉控制模块102，用于在第一控制信号C12和第二控制信号C13的控制下将上一级扫描信号G(N-1)或低电平信号VSS输出至上拉控制模块102。
上拉控制模块102接入上一级级传信号ST(N-1)，并电性连接于第一节点Q(N)，用于在上一级级传信号ST(N-1)的控制下将上一级扫描信号G(N-1)或低电平信号VSS输出至第一节点Q(N)。
下传模块103接入第一时钟信号CK，并电性连接于第一节点Q(N)，用于在第一节点Q(N)的电位控制下输出本级级传信号ST(N)。
上拉模块104接入第一时钟信号CK，并电性连接于第一节点Q(N)，用于在第一节点Q(N)的电位控制下输出本级扫描信号G(N)。
下拉模块105接入下一级扫描信号以及低电平信号VSS，并电性连接于第一节点Q(N)以及本级扫描信号G(N)，用于根据下一级扫描信号下拉第一节点Q(N)的电位以及本级扫描信号G(N)的电位。
下拉维持模块106接入低电平信号VSS，并电性连接于第一节点Q(N)以及本级扫描信号G(N)，用于在下拉模块105下拉第一节点Q(N)的电位以及本级扫描信号G(N)的电位后将第一节点Q(N)的电位以及本级扫描信号G(N)的电位维持在低电平信号VSS的电位；
储能模块107电性连接于第一节点Q(N)以及本级扫描信号G(N)，用于存储第一节点Q(N)的电位以及使第一节点Q(N)的电位与本级扫描信号G(N)的电位发生等势跳变。
本申请实施例提供的GOA单元，包括：级联控制模块101、上拉控制模块102、下传模块103、上拉模块104、下拉模块105、下拉维持模块106以及储能模块107，其中，级联控制模块101能够在第一控制信号C12和第二控制信号C13的控制下将上一级扫描信号G(N-1)或低电平信号VSS输出至上拉控制模块102，所以级联控制模块101可以使得GOA电路处于工作状态或暂停状态。当GOA电路处于工作状态时，级联控制模块101可以将上一级扫描信号G(N-1)输出至上拉控制模块102；当GOA电路处于暂停状态时，级联控制模块101可以将低电平信号VSS输出至上拉控制模块102，进而使得GOA电路暂停工作。
请参阅图2、图3、图4或图5，图2为本申请实施例提供的GOA单元的第一电路图；图3为本申请实施例提供的GOA单元的第二电路图；图4为本申请实施例提供的GOA单元的第三电路图；图5为本申请实施例提供的GOA单元的第四电路图。如图2、图3、图4或图5所示，级联控制模块101包括：第一晶体管T12以及第二晶体管T13；第一晶体管T12的源极电性连接于上一级扫描信号G(N-1)，第一晶体管T12的栅极电性连接于第一控制信号C12；第二晶体管T13的源极电性连接于低电平信号VSS，第二晶体管T13的栅极电性连接于第二控制信号C13；第一晶体管T12的漏极以及第二晶体管T13的漏极电性连接于上拉控制模块102。
在一些实施例中，如图2所示，第一晶体管T12和第二晶体管T13均为N型晶体管，第一控制信号C12的极性和第二控制信号C13的极性相反。也即，当GOA 电路处于工作状态时，第一控制信号C12为高电平，第二控制信号C13为低电平，第一晶体管T12打开，第二晶体管T13关闭，从而使得上一级扫描信号G(N-1)经第一晶体管T12输出至上拉控制模块102；当GOA电路处于暂停状态时，第一控制信号C12为低电平，第二控制信号C13为高电平，第一晶体管T12关闭，第二晶体管T13打开，从而使得低电平信号VSS经第二晶体管T13输出至上拉控制模块102。
在一些实施例中，如图3所示，第一晶体管T12和第二晶体管T13均为P型晶体管，第一控制信号C12的极性和第二控制信号C13的极性相反。也即，当GOA 电路处于工作状态时，第一控制信号C12为低电平，第二控制信号C13为高电平，第一晶体管T12打开，第二晶体管T13关闭，从而使得上一级扫描信号G(N-1)经第一晶体管T12输出至上拉控制模块102；当GOA电路处于暂停状态时，第一控制信号C12为高电平，第二控制信号C13为低电平，第一晶体管T12关闭，第二晶体管T13打开，从而使得低电平信号VSS经第二晶体管T13输出至上拉控制模块102。
在一些实施例中，如图4所示，第一晶体管T12为N型晶体管，第二晶体管T13为P型晶体管，第一控制信号C12的极性和第二控制信号C13的极性相同。也即，当GOA 电路处于工作状态时，第一控制信号C12为高电平，第二控制信号C13为高电平，第一晶体管T12打开，第二晶体管T13关闭，从而使得上一级扫描信号G(N-1)经第一晶体管T12输出至上拉控制模块102；当GOA电路处于暂停状态时，第一控制信号C12为低电平，第二控制信号C13为低电平，第一晶体管T12关闭，第二晶体管T13打开，从而使得低电平信号VSS经第二晶体管T13输出至上拉控制模块102。
在一些实施例中，如图5所示，第一晶体管T12为P型晶体管，第二晶体管T13为N型晶体管，第一控制信号C12的极性和第二控制信号C13的极性相同。也即，当GOA 电路处于工作状态时，第一控制信号C12为低电平，第二控制信号C13为低电平，第一晶体管T12打开，第二晶体管T13关闭，从而使得上一级扫描信号G(N-1)经第一晶体管T12输出至上拉控制模块102；当GOA电路处于暂停状态时，第一控制信号C12为高电平，第二控制信号C13为高电平，第一晶体管T12关闭，第二晶体管T13打开，从而使得低电平信号VSS经第二晶体管T13输出至上拉控制模块102。
请参阅图2、图3、图4或图5，上拉控制模块102包括：第三晶体管T11；第三晶体管T11的源极电性连接于级联控制模块101，第三晶体管T11的栅极电性连接于上一级级传信号ST(N-1)，第三晶体管T11的漏极电性连接于第一节点Q(N)。
下传模块103包括：第四晶体管T22；第四晶体管T22的源极电性连接于第一时钟信号CK，第四晶体管T22的栅极电性连接于第一节点Q(N)，第四晶体管T22的漏极电性连接于本级级传信号ST(N)。
上拉模块104包括：第五晶体管T21；第五晶体管T21的源极电性连接于第一时钟信号CK，第五晶体管T21的栅极电性连接于第一节点Q(N)，第五晶体管T21的漏极电性连接于本级扫描信号G(N)。
下拉模块105包括：第六晶体管T41以及第七晶体管T31；第六晶体管T41的源极以及第七晶体管T31的源极均电性连接与低电平信号VSS；第六晶体管T41的栅极以及第七晶体管T31的栅极均电性连接于下一级扫描信号；第六晶体管T41的漏极电性连接于第一节点Q(N)，第七晶体管T31的漏极电性连接于本级扫描信号G(N)。
下拉维持模块106包括：第八晶体管T51、第九晶体管T53、第十晶体管T32、第十一晶体管T42、第十二晶体管T52以及第十三晶体管T54；第八晶体管T51的源极、栅极以及第九晶体管T53的源极均电性连接于第二时钟信号LC；第八晶体管T51的漏极电性连接于第九晶体管T53的栅极以及第十二晶体管T52的源级；第九晶体管T53的漏极电性连接于第十晶体管T32的栅极、第十一晶体管T42的栅极以及第十三晶体管T54的源级；第十晶体管T32的漏极、第十一晶体管T42的漏极、第十二晶体管T52的源极以及第十三晶体管T54的源极均电性连接于低电平信号VSS；第十晶体管T32的漏极电性连接于本级扫描信号G(N)，第十一晶体管T42的漏极、第十二晶体管T52的栅极以及第十三晶体管T54的栅极均电性连接于第一节点Q(N)。
储能模块107包括：电容Cbt；电容Cbt的一端电性连接于第一节点Q(N)，电容Cbt的另一端电性连接于本级扫描信号G(N)。
在一些实施例中，第三晶体管T11、第四晶体管T22、第五晶体管T21、第六晶体管T41、第七晶体管T31、第八晶体管T51、第九晶体管T53、第十晶体管T32、第十一晶体管T42、第十二晶体管T52以及第十三晶体管T54均为N型晶体管。当然，本领域技术人员可以根据需要将第三晶体管T11、第四晶体管T22、第五晶体管T21、第六晶体管T41、第七晶体管T31、第八晶体管T51、第九晶体管T53、第十晶体管T32、第十一晶体管T42、第十二晶体管T52以及第十三晶体管T54设置为P型晶体管，在此不做限制。
请参阅图6，图6为图2所示的GOA单元处于暂停状态下对应的时序示意图。结合图2、图6所示，当GOA单元处于暂停状态时，第一控制信号C12为低电平，第二控制信号C13为高电平，第一晶体管T12关闭，第二晶体管T13打开，从而使得低电平信号VSS经第二晶体管T13输出至第一节点Q(N)，进而使得第四晶体管T22、第五晶体管T21、第十二晶体管T52以及第十三晶体管T54关闭，本级扫描信号G(N)输出为低电平，该GOA单元停止工作。
当GOA单元处于工作状态时，第一控制信号C12为高电平，第二控制信号C13为高低电平，第一晶体管T12打开，第二晶体管T13关闭，从而使得上一级扫描信号G(N-1)经第一晶体管T12输出至第一节点Q(N)，该GOA单元正常工作。需要说明的是，该GOA单元处于工作状态对应的各个过程与现有技术一致，在此不做赘述。
本申请实施例提供的GOA电路，通过在每一级GOA单元中增加一级联控制模块101，当显示面板处于正常工作状态时，级联控制模块101将上一级扫描信号G(N-1)输出至上拉控制模块102，GOA电路级传正常开启；当显示面板处于异常暂停状态时，级联控制模块101将低电平信号VSS输出至上拉控制模块102，GOA电路级传暂停，从而实现GOA电路级传的暂停和开启，进而丰富GOA电路的控制功能，提高显示面板的信赖性。
本申请实施例还提供一种显示面板，其包括以上的GOA电路，在此不做赘述。其中，当显示面板处于工作状态时，级联控制模块101将上一级扫描信号G(N-1)输出至上拉控制模块102；当显示面板处于暂停状态时，级联控制模块101将低电平信号VSS输出至上拉控制模块102。
以上对本申请实施例提供的GOA电路及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：级联控制模块、上拉控制模块、下传模块、上拉模块、下拉模块、下拉维持模块以及储能模块；
    所述级联控制模块接入第一控制信号、第二控制信号、上一级扫描信号以及低电平信号，并电性连接于所述上拉控制模块，用于在所述第一控制信号和所述第二控制信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述上拉控制模块；
    所述上拉控制模块接入上一级级传信号，并电性连接于第一节点，用于在所述上一级级传信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述第一节点；
    所述下传模块接入第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级扫描信号以及所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于根据所述下一级扫描信号下拉所述第一节点的电位以及所述本级扫描信号的电位；
    所述下拉维持模块接入所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下拉模块下拉所述第一节点的电位以及所述本级扫描信号的电位后将所述第一节点的电位以及所述本级扫描信号的电位维持在所述低电平信号的电位；
    所述储能模块电性连接于所述第一节点以及所述本级扫描信号，用于存储所述第一节点的电位以及使所述第一节点的电位与所述本级扫描信号的电位发生等势跳变；
    所述级联控制模块包括：第一晶体管以及第二晶体管；
    所述第一晶体管的源极电性连接于所述上一级扫描信号，所述第一晶体管的栅极电性连接于所述第一控制信号；所述第二晶体管的源极电性连接于所述低电平信号，所述第二晶体管的栅极电性连接于所述第二控制信号；所述第一晶体管的漏极以及所述第二晶体管的漏极电性连接于所述上拉控制模块；
    所述上拉控制模块包括：第三晶体管；
    所述第三晶体管的源极电性连接于所述级联控制模块，所述第三晶体管的栅极电性连接于所述上一级级传信号，所述第三晶体管的漏极电性连接于所述第一节点。
  2. 根据权利要求1所述的GOA电路，其中，当所述第一晶体管和所述第二晶体管均为N型晶体管或P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相反。
  3. 根据权利要求1所述的GOA电路，其中，当所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同；
    或者，当所述第一晶体管为P型晶体管，述第二晶体管为N型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同。
  4. 根据权利要求1所述的GOA电路，其中，所述下传模块包括：第四晶体管；
    所述第四晶体管的源极电性连接于所述第一时钟信号，所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的漏极电性连接于所述本级级传信号。
  5. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括：第五晶体管；
    所述第五晶体管的源极电性连接于所述第一时钟信号，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  6. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括：第六晶体管以及第七晶体管；
    所述第六晶体管的源极以及所述第七晶体管的源极均电性连接与所述低电平信号；所述第六晶体管的栅极以及所述第七晶体管的栅极均电性连接于所述下一级扫描信号；所述第六晶体管的漏极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述本级扫描信号。
  7. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
    所述第八晶体管的源极、栅极以及所述第九晶体管的源极均电性连接于第二时钟信号；所述第八晶体管的漏极电性连接于所述第九晶体管的栅极以及所述第十二晶体管的源级；所述第九晶体管的漏极电性连接于所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十三晶体管的源级；所述第十晶体管的漏极、所述第十一晶体管的漏极、所述第十二晶体管的源极以及所述第十三晶体管的源极均电性连接于所述低电平信号；所述第十晶体管的漏极电性连接于所述本级扫描信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的栅极均电性连接于所述第一节点。
  8. 根据权利要求1所述的GOA电路，其中，所述储能模块包括：电容；
    所述电容的一端电性连接于所述第一节点，所述电容的另一端电性连接于所述本级扫描信号。
  9. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：级联控制模块、上拉控制模块、下传模块、上拉模块、下拉模块、下拉维持模块以及储能模块；
    所述级联控制模块接入第一控制信号、第二控制信号、上一级扫描信号以及低电平信号，并电性连接于所述上拉控制模块，用于在所述第一控制信号和所述第二控制信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述上拉控制模块；
    所述上拉控制模块接入上一级级传信号，并电性连接于第一节点，用于在所述上一级级传信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述第一节点；
    所述下传模块接入第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级扫描信号以及所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于根据所述下一级扫描信号下拉所述第一节点的电位以及所述本级扫描信号的电位；
    所述下拉维持模块接入所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下拉模块下拉所述第一节点的电位以及所述本级扫描信号的电位后将所述第一节点的电位以及所述本级扫描信号的电位维持在所述低电平信号的电位；
    所述储能模块电性连接于所述第一节点以及所述本级扫描信号，用于存储所述第一节点的电位以及使所述第一节点的电位与所述本级扫描信号的电位发生等势跳变。
  10. 根据权利要求9所述的GOA电路，其中，所述级联控制模块包括：第一晶体管以及第二晶体管；
    所述第一晶体管的源极电性连接于所述上一级扫描信号，所述第一晶体管的栅极电性连接于所述第一控制信号；所述第二晶体管的源极电性连接于所述低电平信号，所述第二晶体管的栅极电性连接于所述第二控制信号；所述第一晶体管的漏极以及所述第二晶体管的漏极电性连接于所述上拉控制模块。
  11. 根据权利要求10所述的GOA电路，其中，当所述第一晶体管和所述第二晶体管均为N型晶体管或P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相反。
  12. 根据权利要求10所述的GOA电路，其中，当所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同；
    或者，当所述第一晶体管为P型晶体管，述第二晶体管为N型晶体管时，所述第一控制信号的极性和所述第二控制信号的极性相同。
  13. 根据权利要求9所述的GOA电路，其中，所述上拉控制模块包括：第三晶体管；
    所述第三晶体管的源极电性连接于所述级联控制模块，所述第三晶体管的栅极电性连接于所述上一级级传信号，所述第三晶体管的漏极电性连接于所述第一节点。
  14. 根据权利要求9所述的GOA电路，其中，所述下传模块包括：第四晶体管；
    所述第四晶体管的源极电性连接于所述第一时钟信号，所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的漏极电性连接于所述本级级传信号。
  15. 根据权利要求9所述的GOA电路，其中，所述上拉模块包括：第五晶体管；
    所述第五晶体管的源极电性连接于所述第一时钟信号，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  16. 根据权利要求9所述的GOA电路，其中，所述下拉模块包括：第六晶体管以及第七晶体管；
    所述第六晶体管的源极以及所述第七晶体管的源极均电性连接与所述低电平信号；所述第六晶体管的栅极以及所述第七晶体管的栅极均电性连接于所述下一级扫描信号；所述第六晶体管的漏极电性连接于所述第一节点，所述第七晶体管的漏极电性连接于所述本级扫描信号。
  17. 根据权利要求9所述的GOA电路，其中，所述下拉维持模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第十三晶体管；
    所述第八晶体管的源极、栅极以及所述第九晶体管的源极均电性连接于第二时钟信号；所述第八晶体管的漏极电性连接于所述第九晶体管的栅极以及所述第十二晶体管的源级；所述第九晶体管的漏极电性连接于所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十三晶体管的源级；所述第十晶体管的漏极、所述第十一晶体管的漏极、所述第十二晶体管的源极以及所述第十三晶体管的源极均电性连接于所述低电平信号；所述第十晶体管的漏极电性连接于所述本级扫描信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的栅极均电性连接于所述第一节点。
  18. 根据权利要求9所述的GOA电路，其中，所述储能模块包括：电容；
    所述电容的一端电性连接于所述第一节点，所述电容的另一端电性连接于所述本级扫描信号。
  19. 一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：级联控制模块、上拉控制模块、下传模块、上拉模块、下拉模块、下拉维持模块以及储能模块；
    所述级联控制模块接入第一控制信号、第二控制信号、上一级扫描信号以及低电平信号，并电性连接于所述上拉控制模块，用于在所述第一控制信号和所述第二控制信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述上拉控制模块；
    所述上拉控制模块接入上一级级传信号，并电性连接于第一节点，用于在所述上一级级传信号的控制下将所述上一级扫描信号或所述低电平信号输出至所述第一节点；
    所述下传模块接入第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述上拉模块接入所述第一时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级扫描信号以及所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于根据所述下一级扫描信号下拉所述第一节点的电位以及所述本级扫描信号的电位；
    所述下拉维持模块接入所述低电平信号，并电性连接于所述第一节点以及所述本级扫描信号，用于在所述下拉模块下拉所述第一节点的电位以及所述本级扫描信号的电位后将所述第一节点的电位以及所述本级扫描信号的电位维持在所述低电平信号的电位；
    所述储能模块电性连接于所述第一节点以及所述本级扫描信号，用于存储所述第一节点的电位以及使所述第一节点的电位与所述本级扫描信号的电位发生等势跳变；
    其中，当所述显示面板处于工作状态时，所述级联控制模块将所述上一级扫描信号输出至所述上拉控制模块；当所述显示面板处于暂停状态时，所述级联控制模块将所述低电平信号输出至所述上拉控制模块。
  20. 根据权利要求19所述的显示面板，其中，所述级联控制模块包括：第一晶体管以及第二晶体管；
    所述第一晶体管的源极电性连接于所述上一级扫描信号，所述第一晶体管的栅极电性连接于所述第一控制信号；所述第二晶体管的源极电性连接于所述低电平信号，所述第二晶体管的栅极电性连接于所述第二控制信号；所述第一晶体管的漏极以及所述第二晶体管的漏极电性连接于所述上拉控制模块。
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