WO2020077924A1 - 栅极驱动电路以及使用该栅极驱动电路的液晶显示器 - Google Patents

栅极驱动电路以及使用该栅极驱动电路的液晶显示器 Download PDF

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WO2020077924A1
WO2020077924A1 PCT/CN2019/075545 CN2019075545W WO2020077924A1 WO 2020077924 A1 WO2020077924 A1 WO 2020077924A1 CN 2019075545 W CN2019075545 W CN 2019075545W WO 2020077924 A1 WO2020077924 A1 WO 2020077924A1
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control node
transistor
source
gate
drain
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PCT/CN2019/075545
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English (en)
French (fr)
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宋乔乔
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020077924A1 publication Critical patent/WO2020077924A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the invention relates to the field of a liquid crystal display, in particular to a liquid crystal display using a gate driver (GOA) circuit.
  • GOA gate driver
  • the GOA circuit uses a transistor liquid crystal display Array manufacturing process to fabricate a gate driver on a substrate with a thin film transistor (TFT) array to realize a progressive scanning driving method.
  • TFT thin film transistor
  • the GOA circuit contains several GOA circuit units.
  • the conventional GOA circuit unit outputs the scan signal by controlling the gate voltage (ie, Q point voltage) of the output transistor.
  • the traditional GOA circuit unit uses the clock signal as the input source of the pull-down sustain module, so the pull-down sustain module will only operate during the pulse generation of the clock signal. During the period when the clock signal does not generate a pulse, the pull-down sustain module will not function, so that the scan signal at the output cannot maintain a low potential.
  • the frames on both sides of the liquid crystal display are mainly composed of a common voltage source, a GOA circuit, and a GOA signal area.
  • the GOA signal area includes multiple sets of clock (CK) signals and low-potential DC signals.
  • CK clock
  • the number of clock signals gradually increases. This directly leads to the widening of the borders on both sides of the liquid crystal display so that more clock signal pads (Pad) can be added.
  • Increasing the frame does not meet the needs of existing users. At the same time, the increase in the clock signal will also increase the complexity of designing the driving circuit and will increase the cost.
  • an object of the present invention is to provide a gate driving circuit that uses fewer clock signals to drive several GOA circuit units to solve the problems of the prior art.
  • the technical solution of the present invention provides a gate driving circuit, which includes a plurality of GOA circuit units, and a plurality of the GOA circuit units are coupled in series.
  • the N-th stage GOA circuit unit is used to comply with the N-3th stage GOA Scan signal output by the circuit unit, N-3 stage start signal, N + 3 stage GOA circuit unit output scan signal, N + 3 stage start signal, first clock signal, second clock signal, and third clock signal , Output scan signal at the output.
  • the N-th stage GOA circuit unit includes: an input control module for controlling the first control node according to the signal of the N-3th stage start signal terminal and the scan signal at the output end of the N-3th stage GOA circuit unit Level; the output module, electrically connected to the first control node and the second control node, for receiving the voltage applied to the first control node, the second control node voltage is turned to The output terminal; the output control module, electrically connected to the second control node, for controlling the voltage applied to the second control node according to the first clock signal or the second clock signal; the pull-down module , Electrically connected to the output module and the fixed voltage source, for receiving the scan signal at the output end of the N-3th stage GOA circuit unit, to pull down the voltage of the scan signal at the output end and pull down to the first The voltage of the control node; and the first pull-down maintenance module, which is electrically connected to the output terminal, the first control node and the first clock signal, and is used for depending on the power applied to the first control node Voltage to maintain
  • the input control module includes: a first transistor whose gate is connected to the N-3 stage start signal terminal, its source is connected to the N-3 stage gate signal terminal, and its drain Connect to the first control node.
  • the output module includes: a second transistor whose gate is connected to the first control node, whose source is connected to the second control node, and whose drain is connected to the output terminal; A transistor, a gate of which is connected to the first control node, a source of which is connected to the second control node, and a drain of which is connected to the Nth stage start signal terminal; and a capacitor, which is connected to the first control node and the Between outputs.
  • the output control module includes: a fourth transistor whose gate is connected to the third clock signal, whose source is connected to the second control node, and whose drain is connected to the first clock signal Or the second clock signal; and the fifth transistor, its gate is connected to the third clock signal, its source is connected to the second control node, and its drain is connected to the fixed voltage source.
  • the pull-down module includes: a sixth transistor whose gate is connected to the output of the N-3th stage GOA circuit unit, whose source is connected to the output, and whose drain is connected to the A fixed voltage source; a seventh transistor, the gate of which is connected to the output of the N-3th stage GOA circuit unit, the source of which is connected to the first control node, and the drain of which is connected to the fixed voltage source.
  • the first pull-down sustaining module includes: an eighth transistor whose gate and source are connected to the first clock signal; a ninth transistor whose gate is connected to the drain of the eighth transistor , Its source is connected to the first clock signal, its drain is connected to the third control node; the tenth transistor, its gate is connected to the first control node, and its source is connected to the drain of the eighth transistor, The drain is connected to the fixed voltage source; the eleventh transistor, the gate is connected to the first control node, the source is connected to the third control node, and the drain is connected to the fixed voltage source; the twelfth transistor , Its gate is connected to the third control node, its source is connected to the output terminal, and its drain is connected to the fixed voltage source; and the thirteenth transistor, its gate is connected to the third control node, its source The pole is connected to the first control node, and the drain is connected to the fixed voltage source.
  • the second pull-down sustaining module includes: a fourteenth transistor whose gate and source are connected to the second clock signal; a fifteenth transistor whose gate is connected to the fourteenth transistor The drain, the source of which is connected to the second clock signal, the drain of which is connected to the fourth control node; the sixteenth transistor, the gate of which is connected to the first control node, and the source of which is connected to the fourteenth transistor A drain whose drain is connected to the fixed voltage source; a seventeenth transistor whose gate is connected to the first control node, whose source is connected to the fourth control node and whose drain is connected to the fixed voltage source; The eighteenth transistor has its gate connected to the fourth control node, its source connected to the output terminal, and its drain connected to the fixed voltage source; the nineteenth transistor has its gate connected to the fourth control node , Its source is connected to the first control node, and its drain is connected to the fixed voltage source.
  • the first clock signal and the second clock signal are inverse to each other.
  • the frequency of the third clock signal is greater than that of the first clock signal.
  • the technical solution of the present invention further provides a liquid crystal display including the above-mentioned gate driving circuit.
  • the output control module of the gate driving circuit of the present invention includes a fourth transistor and a fifth transistor. Since the third clock signal becomes an inverted clock signal after being input to the output control module, another high-frequency clock signal can be formed by a single output control module. Compared with the gate drive circuit that requires four high-frequency clock signals to drive in the prior art, the clock signal reduced by half can be used to drive the GOA circuit in this case, which greatly saves layout space and has the beneficial effect of achieving a narrow-frame LCD.
  • FIG. 1 is a functional block diagram of the liquid crystal display of the present invention.
  • FIG. 2 is a circuit diagram of the GOA circuit unit of the preferred embodiment of the present invention.
  • FIG. 3 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2.
  • FIG. 1 is a functional block diagram of the liquid crystal display 10 of the present invention.
  • the liquid crystal display 10 includes a glass substrate 14, a timing controller 30 and a source driver 16.
  • the glass substrate 14 is provided with a plurality of pixels and gate drive (GOA) circuits 12 arranged in a matrix, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB).
  • the timing controller 30 is used to generate the clock signals CK1-CK2 and the start signal ST.
  • the GOA circuit 12 outputs scan signals at regular intervals so that the transistors 22 in each row are sequentially turned on, and at the same time, the source driver 16 outputs corresponding data signals to a whole column of pixel units 20 to charge them to their respective required voltages.
  • the GOA circuit 12 controls to include N GOA circuit units SR (1), ..., SR (N), where N is equal to 1080.
  • the odd-numbered GOA circuit units SR (1), SR (3), SR (N-1) of the N GOA circuit units SR (1),..., SR (N) receive the third clock signal CK (N) Driven, the even-numbered GOA circuit units SR (2), SR (4), ..., SR (N) of the N GOA circuit units SR (1), ..., SR (N) receive the fourth clock signal XCK ( N) driven.
  • the phases of the third clock signal CK (N) and the fourth clock signal XCK (N) differ by 90 degrees.
  • N GOA circuit units SR (1), ..., SR (N) are divided into a first group of GOA circuit units and a second group of GOA circuit units, of which the first group of GOA circuit units SR (1), SR (2) , SR (5), SR (6), ..., SR (4m-3), SR (4m-2) have the same circuit structure, and the second group of GOA circuit units SR (3), SR (4), SR (7), SR (8), ..., SR (4m-1), SR (4m) have the same circuit structure, but the circuit structures of the first group of GOA circuit units and the second group of GOA circuit units are not the same.
  • FIG. 2 is a circuit diagram of the GOA circuit unit SR (n) of the preferred embodiment of the present invention.
  • the GOA circuit 12 is directly disposed on the glass substrate 14.
  • the GOA circuit unit SR (n) shown in FIG. 2 belongs to the second group of GOA circuit units SR (3), SR (4), ..., SR (4m-1), SR (4m).
  • the Nth stage GOA circuit unit is used for scanning signals output by the N-3th stage GOA circuit unit, the N-3 stage start signal, the N + 3 stage GOA circuit unit output scan signal, the N + 3 stage start signal ,
  • the first clock signal LC1, the second clock signal LC2, and the third clock signal CK (N) output scan signals at the output terminal G (N), where N is a positive integer greater than 3.
  • the first clock signal LC1 and the second clock signal LC2 are inverse to each other.
  • the frequency of the third clock signal CK (N) is greater than the first clock signal LC1 and the second clock signal LC2.
  • the GOA circuit unit SR (n) includes an input control module 100, an output module 200, an output control module 300, a pull-down module 400, a first pull-down maintaining module 510, and a second pull-down maintaining module 520.
  • the input control module 100 is used to control the scan signal of the output terminal G (N-3) of the GOA circuit unit of the N-3 stage according to the signal of the start signal terminal ST (N-3) of the N-3 stage and to control The level of the first control node Q (N).
  • the output module 200 is electrically connected to the first control node Q (N) and the second control node K (N), for receiving the voltage applied to the first control node Q (N) The voltage of the two control nodes K (N) is turned on to the output terminal G (N).
  • the output control module 300 is electrically connected to the second control node K (N), and is used to control the application to the second control node K (N) according to the first clock signal LC1 or the second clock signal LC2 The voltage.
  • the pull-down module 400 is electrically connected to the output module 200 and a fixed voltage source (Vss), and is used to pull down the output when receiving the scan signal from the output terminal G (N + 3) of the N-3 stage GOA circuit unit The voltage of the scan signal at the terminal G (N) and the voltage applied to the first control node Q (N) are pulled down.
  • the first pull-down maintenance module 510 is electrically connected to the output terminal G (N), the first control node Q (N), and the first clock signal LC1, and is used to apply to the first control node Q The voltage of (N) maintains the low level of the scan signal at the output terminal G (N).
  • the second pull-down maintenance module 520 is electrically connected to the output terminal, the first control node Q (N) and the second clock signal LC2, and is used for depending on the voltage applied to the first control node Q (N) To maintain the low level of the scan signal at the output terminal G (N).
  • the first group of GOA circuit units SR (1), SR (2), ... , SR (4m-3), SR (4m-2) does not have the design of the output control module 300.
  • the input control module 100 includes a first transistor T1 whose gate is connected to the N-3 stage start signal terminal ST (N-3) and whose source is connected to the N-3 stage gate signal terminal G (N- 3) Its drain is connected to the first control node Q (N).
  • the output module 200 includes a second transistor T2, a third transistor T3, and a capacitor C bt .
  • the gate of the second transistor T2 is connected to the first control node Q (N), the source thereof is connected to the second control node K (N), and the drain thereof is connected to the output terminal G (N).
  • the gate of the third transistor T3 is connected to the first control node Q (N), the source thereof is connected to the second control node K (N), and the drain thereof is connected to the Nth stage start signal terminal ST (N).
  • the capacitor C bt is connected between the first control node Q (N) and the output terminal G (N).
  • the output control module 300 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is connected to the third clock signal CK (N), its source is connected to the second control node K (N), and its drain is connected to the first clock signal LC1 or the first Two clock signal LC2.
  • the gate of the fifth transistor T5 is connected to the third clock signal CK (N), the source thereof is connected to the second control node K (N), and the drain thereof is connected to the fixed voltage source (Vss).
  • the pull-down module 400 includes a sixth transistor T6 and a seventh transistor T7.
  • the gate of the sixth transistor T6 is connected to the output terminal G (N + 3) of the N-3th stage GOA circuit unit, its source is connected to the output terminal G (N), and its drain is connected to the fixed voltage source (Vss).
  • the gate of the seventh transistor T7 is connected to the output terminal G (N + 3) of the N-3th stage GOA circuit unit, its source is connected to the first control node Q (N), and its drain is connected to the fixed Voltage source (Vss).
  • the first pull-down sustaining module 510 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.
  • the gate and source of the eighth transistor T8 are connected to the first clock signal LC1.
  • the gate of the ninth transistor T9 is connected to the drain of the eighth transistor T8, the source is connected to the first clock signal LC1, and the drain is connected to the third control node P (N).
  • the gate of the tenth transistor T10 is connected to the first control node Q (N), the source thereof is connected to the drain of the eighth transistor T8, and the drain thereof is connected to the fixed voltage source (Vss).
  • the gate of the eleventh transistor T11 is connected to the first control node Q (N), the source thereof is connected to the third control node P (N), and the drain thereof is connected to the fixed voltage source (Vss).
  • the gate of the twelfth transistor T12 is connected to the third control node P (N), the source thereof is connected to the output terminal G (N), and the drain thereof is connected to the fixed voltage source (Vss).
  • the gate of the thirteenth transistor T13 is connected to the third control node P (N), the source thereof is connected to the first control node Q (N), and the drain thereof is connected to the fixed voltage source (Vss).
  • the second pull-down sustaining module 520 includes a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18 and a nineteenth transistor T19.
  • the gate and source of the fourteenth transistor T14 are connected to the second clock signal LC2.
  • the gate of the fifteenth transistor T15 is connected to the drain of the fourteenth transistor T14, the source thereof is connected to the second clock signal LC2, and the drain thereof is connected to the fourth control node O (N).
  • the gate of the sixteenth transistor T16 is connected to the first control node Q (N), the source thereof is connected to the drain of the fourteenth transistor T14, and the drain thereof is connected to the fixed voltage source (Vss).
  • the gate of the seventeenth transistor T17 is connected to the first control node Q (N), the source thereof is connected to the fourth control node O (N), and the drain thereof is connected to the fixed voltage source (Vss).
  • the gate of the eighteenth transistor T18 is connected to the fourth control node O (N), the source thereof is connected to the output terminal G (N), and the drain thereof is connected to the fixed voltage source (Vss).
  • the gate of the nineteenth transistor T19 is connected to the fourth control node O (N), the source thereof is connected to the first control node Q (N), and the drain thereof is connected to the fixed voltage source (Vss).
  • the fourth transistor T4 is a P-type metal oxide semiconductor (PMOS) transistor
  • all the transistors of the GOA circuit unit SR (n) of FIG. 2 are N-type metal oxide semiconductor (N-type metal oxide semiconductor) oxide semiconductor (NMOS) transistor.
  • FIG. 3 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2.
  • the output control module 300 of the GOA circuit unit SR (3) includes The fourth transistor T4 and the fifth transistor T5. After the third clock signal CK (N) is input and output to the control module 100, an inverted clock signal is output at the second control node K (N).
  • the output module 200 of the first-stage GOA circuit unit SR (1) is driven by the third clock signal CK (N), and the output module 200 of the third-stage GOA circuit unit SR (3) is substantially inverted by The third clock signal CK (N) is driven by the clock signal.
  • the output module 200 of the second stage GOA circuit unit SR (2) is driven by the fourth clock signal XCK (N), and the output module 200 of the fourth stage GOA circuit unit SR (4) is essentially The clock signal relative to the fourth clock signal XCK (N) is driven.
  • a person skilled in the art can replace all or part of the NMOS transistors with PMOS transistors according to the circuit of the present invention to realize the GOA circuit unit with the same function.
  • the output control module of the gate drive circuit of the present invention includes a fourth transistor and a fifth transistor. Since the third clock signal becomes an inverted clock signal after being input to the output control module, another high-frequency clock signal can be formed by a single output control module. Compared with the gate drive circuit that requires four high-frequency clock signals to drive in the prior art, the clock signal reduced by half can be used to drive the GOA circuit in this case, which greatly saves layout space and has the beneficial effect of achieving a narrow-frame LCD.

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Abstract

一种栅极驱动电路，其包含数个GOA电路单元。GOA电路单元包含输入控制模块、输出模块、输出控制模块、下拉模块、第一下拉维持模块和第二下拉维持模块。该输出控制模块包含第四晶体管和第五晶体管。由于第三时钟信号输入该输出控制模块之后会变成反相的时钟信号，因此只要通过单一输出控制模块就可形成另一个高频的时钟信号。

Description

栅极驱动电路以及使用该栅极驱动电路的液晶显示器 技术领域
本发明是有关于一种液晶显示器领域，尤指一种使用栅极驱动(Gate driver on array，GOA)电路的液晶显示器。
 背景技术
GOA电路是利用晶体管液晶显示器Array制程将栅极驱动器制作在具有晶体管(Thin film transistor，TFT)阵列的基板上，以实现逐行扫描的驱动方式。
GOA电路包含数个GOA电路单元。传统的GOA电路单元通过控制输出晶体管的栅极电压(亦即Q点电压)来输出扫描信号。传统GOA 电路单元是使用时钟信号作为下拉维持模块的输入源，因此下拉维持模块只有在时钟信号产生脉冲期间才会运作。在时钟信号没有产生脉冲期间，下拉维持模块将没有发挥作用，使得输出端的扫描信号不能维持低电位。
现有使用GOA电路的液晶显示器(Liquid crystal display，LCD)，在液晶显示器两侧的边框主要是由公共电压源、GOA电路及GOA信号区组成。GOA信号区包括多组时钟（CK）信号以及低电位直流信号。随着更新频率和面板分辨越来越高，为了提高每一GOA电路单元的充电能力和扫描信号传递速度，时钟信号的数量逐渐增加。这就直接导致液晶显示器两侧的边框变宽才得以加入容纳更多的时钟信号垫(Pad)。增加边框并不符合现有使用者的的需求，同时，时钟信号增加也会增加设计驱动电路的复杂度，更会提高成本。
 技术问题
有鉴于此，本发明的目的是提供一种栅极驱动电路，通过使用较少的时钟信号来驱动数个GOA电路单元，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种栅极驱动电路，其包含数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，第N级GOA电路单元用来依据第N-3级GOA电路单元输出的扫描信号、第N-3级启动信号、第N+3级GOA电路单元输出的扫描信号、第N+3级启动信号、第一时钟信号、第二时钟信号以及第三时钟信号，在输出端输出扫描信号。所述第N级GOA电路单元包含：输入控制模块，用来依据所述第N-3级启动信号端的信号和所述第N-3级GOA电路单元输出端的扫描信号，以控制第一控制节点的电平；输出模块，电性连接所述第一控制节点以及第二控制节点，用来于接收施加于所述第一控制节点的电压时，将所述第二控制节点的电压导通至所述输出端；输出控制模块，电性连接所述第二控制节点，用来依据所述第一时钟信号或所述第二时钟信号，控制施加于所述第二控制节点的电压；下拉模块，电性连接所述输出模块以及固定电压源，用来于接收所述第N-3级GOA电路单元输出端的扫描信号时，下拉所述输出端的扫描信号的电压以及下拉施加于所述第一控制节点的电压；及第一下拉维持模块，电性连接所述输出端、所述第一控制节点和所述第一时钟信号，用来依据施加于所述第一控制节点的电压，维持所述输出端的所述扫描信号的低电平；第二下拉维持模块，电性连接所述输出端、所述第一控制节点和所述第二时钟信号，用来依据施加于所述第一控制节点的电压，维持所述输出端的所述扫描信号的低电平。
依据本发明的实施例，所述输入控制模块包含：第一晶体管，其栅极连接所述第N-3级启动信号端，其源极连接第N-3级栅极信号端，其漏极连接所述第一控制节点。
依据本发明的实施例，所述输出模块包含：第二晶体管，其栅极连接所述第一控制节点，其源极连接所述第二控制节点，其漏极连接所述输出端；第三晶体管，其栅极连接所述第一控制节点，其源极连接所述第二控制节点，其漏极连接第N级启动信号端；及电容，其连接于所述第一控制节点和所述输出端之间。
依据本发明的实施例，所述输出控制模块包含：第四晶体管，其栅极连接所述第三时钟信号，其源极连接所述第二控制节点，其漏极连接所述第一时钟信号或是所述第二时钟信号；及第五晶体管，其栅极连接所述第三时钟信号，其源极连接所述第二控制节点，其漏极连接所述固定电压源。
依据本发明的实施例，所述下拉模块包含：第六晶体管，其栅极连接所述第N-3级GOA电路单元的输出端，其源极连接所述输出端，其漏极连接所述固定电压源；第七晶体管，其栅极连接所述第N-3级GOA电路单元的输出端，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
依据本发明的实施例，第一下拉维持模块包含：第八晶体管，其栅极和其源极连接所述第一时钟信号；第九晶体管，其栅极连接所述第八晶体管的漏极，其源极连接所述第一时钟信号，其漏极连接第三控制节点；第十晶体管，其栅极连接所述第一控制节点，其源极连接所述第八晶体管的漏极，其漏极连接所述固定电压源；第十一晶体管，其栅极连接所述第一控制节点，其源极连接所述第三控制节点，其漏极连接所述固定电压源；第十二晶体管，其栅极连接所述第三控制节点，其源极连接所述输出端，其漏极连接所述固定电压源；及第十三晶体管，其栅极连接所述第三控制节点，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
依据本发明的实施例，第二下拉维持模块包含：第十四晶体管，其栅极和其源极连接所述第二时钟信号；第十五晶体管，其栅极连接所述第十四晶体管的漏极，其源极连接所述第二时钟信号，其漏极连接第四控制节点；第十六晶体管，其栅极连接所述第一控制节点，其源极连接所述第十四晶体管的漏极，其漏极连接所述固定电压源；第十七晶体管，其栅极连接所述第一控制节点，其源极连接所述第四控制节点，其漏极连接所述固定电压源；第十八晶体管，其栅极连接所述第四控制节点，其源极连接所述输出端，其漏极连接所述固定电压源；第十九晶体管，其栅极连接所述第四控制节点，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
依据本发明的实施例，所述第一时钟信号和所述第二时钟信号互为反相。
依据本发明的实施例，所述第三时钟信号的频率大于所述第一时钟信号。
本发明的技术方案另提供一种液晶显示器，其包含上述的栅极驱动电路。
 有益效果
相较于现有技术，本发明的栅极驱动电路的输出控制模块包含第四晶体管和第五晶体管。由于该第三时钟信号输入该输出控制模块之后会变成反相的时钟信号，因此只要通过单一输出控制模块就可形成另一个高频的时钟信号。相较于现有技术需要四个高频时钟信号来驱动的栅极驱动电路，本案可以使用减少一半的时钟信号来驱动GOA电路，大大节省版图空间，具有实现窄边框液晶显示器的有益效果。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的液晶显示器的功能方块图。
图2是本发明较佳实施例的GOA电路单元的电路图。
图3是图2所示各种输入信号、输出信号和节点电压的时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施之特定实施例。本发明所提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”、“水平”、“垂直”等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图1，图1是本发明的液晶显示器10的功能方块图。液晶显示器10包含玻璃基板14、时序控制器30以及源极驱动器(source driver)16。玻璃基板14上设置数个呈矩阵排列的像素(pixel)和栅极驱动(GOA)电路12，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。时序控制器30用来产生时钟信号CK1-CK2以及启动信号ST。GOA电路12每隔一固定间隔输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，GOA电路12便将该行的扫描信号关闭，然后GOA电路12再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到所有像素单元20都充电完成，再从第一行开始充电。图1所示的GOA电路12 控制包含N个GOA电路单元SR(1)、…、SR(N)，N等于1080。
N个GOA电路单元SR(1)、…、SR(N)中的奇数级GOA电路单元SR(1)、SR(3) …、SR(N-1)是接收第三时钟信号CK(N)所驱动，N个GOA电路单元SR(1)、…、SR(N)中的偶数级GOA 电路单元SR(2)、SR(4) 、…、SR(N)是接收第四时钟信号XCK(N)所驱动。第三时钟信号CK(N)和第四时钟信号XCK(N)的相位相差90度。此外，N个GOA电路单元SR(1)、…、SR(N)分为第一组GOA电路单元和第二组GOA电路单元，其中第一组GOA电路单元SR(1)、SR(2)、SR(5)、SR(6)、…、SR(4m-3)、SR(4m-2) 具有相同的电路结构，而第二组GOA电路单元SR(3)、SR(4)、SR(7)、SR(8)、…、SR(4m-1)、SR(4m) 具有相同的电路结构，但第一组GOA电路单元和第二组GOA电路单元的电路结构并不相同。
请参阅图1和图2，图2是本发明较佳实施例的GOA电路单元SR(n)的电路图。为了让液晶显示器10的非显示区(也就是玻璃基板14放置GOA电路12的区域)变窄，GOA电路12直接设置在玻璃基板14上。GOA电路12包含数个串接(cascade-connected)的GOA电路单元SR(n)，n=0~N。为简化说明，图2所示的GOA电路单元SR(n)是属于第二组GOA电路单元SR(3)、SR(4)、…、SR(4m-1)、SR(4m)。第N级GOA电路单元用来依据第N-3级GOA电路单元输出的扫描信号、第N-3级启动信号、第N+3级GOA电路单元输出的扫描信号、第N+3级启动信号、第一时钟信号LC1、第二时钟信号LC2以及第三时钟信号CK(N)，在输出端G(N)输出扫描信号，其中N为大于3的正整数。第一时钟信号LC1和第二时钟信号LC2互为反相。第三时钟信号CK(N)的频率大于第一时钟信号LC1和第二时钟信号LC2。
GOA电路单元SR(n)包含输入控制模块100、输出模块200、输出控制模块300、下拉模块400、第一下拉维持模块510和第二下拉维持模块520。输入控制模块100用来依据所述第N-3级启动信号端ST(N-3)的信号和所述第N-3级GOA电路单元输出端G(N-3)的扫描信号，以控制第一控制节点Q(N)的电平。输出模块200电性连接所述第一控制节点Q(N)以及第二控制节点K(N)，用来于接收施加于所述第一控制节点Q(N)的电压时，将所述第二控制节点K(N)的电压导通至所述输出端G(N)。输出控制模块300电性连接所述第二控制节点K(N)，用来依据所述第一时钟信号LC1或所述第二时钟信号LC2，控制施加于所述第二控制节点K(N)的电压。下拉模块400电性连接所述输出模块200以及固定电压源(Vss)，用来于接收所述第N-3级GOA电路单元输出端G(N+3)的扫描信号时，下拉所述输出端G(N)的扫描信号的电压以及下拉施加于所述第一控制节点Q(N)的电压。第一下拉维持模块510电性连接所述输出端G(N)、所述第一控制节点Q(N) 和所述第一时钟信号LC1，用来依据施加于所述第一控制节点Q(N)的电压，维持所述输出端G(N)的所述扫描信号的低电平。第二下拉维持模块520电性连接所述输出端、所述第一控制节点Q(N)和所述第二时钟信号LC2，用来依据施加于所述第一控制节点Q(N)的电压，维持所述输出端G(N)的所述扫描信号的低电平。相较于第二组GOA电路单元SR(3)、SR(4)、…、SR(4m-1)、SR(4m)，第一组GOA电路单元SR(1)、SR(2)、…、SR(4m-3)、SR(4m-2)并没有输出控制模块300的设计。
所述输入控制模块100包含第一晶体管T1，其栅极连接所述第N-3级启动信号端ST (N-3)，其源极连接第N-3级栅极信号端G (N-3)，其漏极连接所述第一控制节点Q (N)。
所述输出模块200包含第二晶体管T2、第三晶体管T3和电容C bt。第二晶体管T2的栅极连接所述第一控制节点Q (N)，其源极连接所述第二控制节点K(N)，其漏极连接所述输出端G(N)。第三晶体管T3的栅极连接所述第一控制节点Q (N)，其源极连接所述第二控制节点K(N)，其漏极连接第N级启动信号端ST (N)。电容C bt连接于所述第一控制节点Q (N)和所述输出端G(N)之间。
所述输出控制模块300包含第四晶体管T4及第五晶体管T5。第四晶体管T4的栅极连接所述第三时钟信号CK (N)，其源极连接所述第二控制节点K(N)，其漏极连接所述第一时钟信号LC1或是所述第二时钟信号LC2。第五晶体管T5的栅极连接所述第三时钟信号CK(N)，其源极连接所述第二控制节点K(N)，其漏极连接所述固定电压源(Vss)。
所述下拉模块400包含第六晶体管T6和第七晶体管T7。第六晶体管T6的栅极连接所述第N-3级GOA电路单元的输出端G(N+3)，其源极连接所述输出端G(N)，其漏极连接所述固定电压源(Vss)。第七晶体管T7的栅极连接所述第N-3级GOA电路单元的输出端G(N+3)，其源极连接所述第一控制节点Q (N)，其漏极连接所述固定电压源(Vss)。
第一下拉维持模块510包含第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12和第十三晶体管T13。第八晶体管T8的栅极和源极连接所述第一时钟信号LC1。第九晶体管T9的栅极连接所述第八晶体管T8的漏极，其源极连接所述第一时钟信号LC1，其漏极连接第三控制节点P(N)。第十晶体管T10的栅极连接所述第一控制节点Q (N)，其源极连接所述第八晶体管T8的漏极，其漏极连接所述固定电压源(Vss)。第十一晶体管T11的栅极连接所述第一控制节点Q (N)，其源极连接所述第三控制节点P(N)，其漏极连接所述固定电压源(Vss)。第十二晶体管T12的栅极连接所述第三控制节点P(N)，其源极连接所述输出端G(N)，其漏极连接所述固定电压源(Vss)。第十三晶体管T13的栅极连接所述第三控制节点P(N)，其源极连接所述第一控制节点Q (N)，其漏极连接所述固定电压源(Vss)。
第二下拉维持模块520包含第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17、第十八晶体管T18和第十九晶体管T19。第十四晶体管T14的栅极和其源极连接所述第二时钟信号LC2。第十五晶体管T15的栅极连接所述第十四晶体管T14的漏极，其源极连接所述第二时钟信号LC2，其漏极连接第四控制节点O(N)。第十六晶体管T16的栅极连接所述第一控制节点Q (N)，其源极连接所述第十四晶体管T14的漏极，其漏极连接所述固定电压源(Vss)。第十七晶体管T17的栅极连接所述第一控制节点Q (N)，其源极连接所述第四控制节点O(N)，其漏极连接所述固定电压源(Vss)。第十八晶体管T18的栅极连接所述第四控制节点O(N)，其源极连接所述输出端G(N)，其漏极连接所述固定电压源(Vss)。第十九晶体管T19的栅极连接所述第四控制节点O(N)，其源极连接所述第一控制节点Q (N)，其漏极连接所述固定电压源(Vss)。
除了第四晶体管T4为P型金氧半导体(P-type metal oxide semiconductor，PMOS)晶体管之外，图2的GOA电路单元SR(n)的所有晶体管皆为N型金氧半导体(N-type metal oxide semiconductor，NMOS)晶体管。
请一并参阅图3，图3是图2所示各种输入信号、输出信号和节点电压的时序图。虽然奇数级GOA电路单元SR(1)、SR(3) …、SR(N-1)是由第三时钟信号CK(N)所驱动，但是GOA电路单元SR(3)的输出控制模块300包含第四晶体管T4和第五晶体管T5。当第三时钟信号CK(N)输入输出控制模块100之后，会于第二控制节点K(N)会输出反相的时钟信号。因此第一级GOA电路单元SR(1) 的输出模块200是由第三时钟信号CK(N)所驱动，而第三级GOA电路单元SR(3)的输出模块200实质上是由反相于第三时钟信号CK(N)的时钟信号所驱动。同样地，第二级GOA电路单元SR(2)的输出模块200是由第四时钟信号XCK(N)所驱动，而第四级GOA电路单元SR(4)的输出模块200实质上是由反相于第四时钟信号XCK(N)的时钟信号所驱动。
本领域技术人员可以根据本发明的电路将其中全部或是部分NMOS晶体管以PMOS晶体管取代，以实现同样功能的GOA电路单元。
 工业实用性
本发明的栅极驱动电路的输出控制模块包含第四晶体管和第五晶体管。由于该第三时钟信号输入该输出控制模块之后会变成反相的时钟信号，因此只要通过单一输出控制模块就可形成另一个高频的时钟信号。相较于现有技术需要四个高频时钟信号来驱动的栅极驱动电路，本案可以使用减少一半的时钟信号来驱动GOA电路，大大节省版图空间，具有实现窄边框液晶显示器的有益效果。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，第N级GOA电路单元用来依据第N-3级GOA电路单元输出的扫描信号、第N-3级启动信号、第N+3级GOA电路单元输出的扫描信号、第N+3级启动信号、第一时钟信号、第二时钟信号以及第三时钟信号，在输出端输出扫描信号，所述第N级GOA电路单元包含：
    输入控制模块，用来依据所述第N-3级启动信号端的信号和所述第N-3级GOA电路单元输出端的扫描信号，以控制第一控制节点的电平；
    输出模块，电性连接所述第一控制节点以及第二控制节点，用来于接收施加于所述第一控制节点的电压时，将所述第二控制节点的电压导通至所述输出端；
    输出控制模块，电性连接所述第二控制节点，用来依据所述第一时钟信号或所述第二时钟信号，控制施加于所述第二控制节点的电压；
    下拉模块，电性连接所述输出模块以及固定电压源，用来于接收所述第N-3级GOA电路单元输出端的扫描信号时，下拉所述输出端的扫描信号的电压以及下拉施加于所述第一控制节点的电压；及
    第一下拉维持模块，电性连接所述输出端、所述第一控制节点和所述第一时钟信号，用来依据施加于所述第一控制节点的电压，维持所述输出端的所述扫描信号的低电平；
    第二下拉维持模块，电性连接所述输出端、所述第一控制节点和所述第二时钟信号，用来依据施加于所述第一控制节点的电压，维持所述输出端的所述扫描信号的低电平。
  2. 如权利要求1所述的栅极驱动电路，其中所述输入控制模块包含：
    第一晶体管，其栅极连接所述第N-3级启动信号端，其源极连接第N-3级栅极信号端，其漏极连接所述第一控制节点。
  3. 如权利要求1所述的栅极驱动电路，其中所述输出模块包含：
    第二晶体管，其栅极连接所述第一控制节点，其源极连接所述第二控制节点，其漏极连接所述输出端；
    第三晶体管，其栅极连接所述第一控制节点，其源极连接所述第二控制节点，其漏极连接第N级启动信号端；及
    电容，其连接于所述第一控制节点和所述输出端之间。
  4. 如权利要求1所述的栅极驱动电路，其中所述输出控制模块包含：
    第四晶体管，其栅极连接所述第三时钟信号，其源极连接所述第二控制节点，其漏极连接所述第一时钟信号或是所述第二时钟信号；及
    第五晶体管，其栅极连接所述第三时钟信号，其源极连接所述第二控制节点，其漏极连接所述固定电压源。
  5. 如权利要求1所述的栅极驱动电路，其中所述下拉模块包含：
    第六晶体管，其栅极连接所述第N-3级GOA电路单元的输出端，其源极连接所述输出端，其漏极连接所述固定电压源；及
    第七晶体管，其栅极连接所述第N-3级GOA电路单元的输出端，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
  6. 如权利要求1所述的栅极驱动电路，其中第一下拉维持模块包含：
    第八晶体管，其栅极和其源极连接所述第一时钟信号；
    第九晶体管，其栅极连接所述第八晶体管的漏极，其源极连接所述第一时钟信号，其漏极连接第三控制节点；
    第十晶体管，其栅极连接所述第一控制节点，其源极连接所述第八晶体管的漏极，其漏极连接所述固定电压源；
    第十一晶体管，其栅极连接所述第一控制节点，其源极连接所述第三控制节点，其漏极连接所述固定电压源；
    第十二晶体管，其栅极连接所述第三控制节点，其源极连接所述输出端，其漏极连接所述固定电压源；及
    第十三晶体管，其栅极连接所述第三控制节点，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
  7. 如权利要求1所述的栅极驱动电路，其中第二下拉维持模块包含：
    第十四晶体管，其栅极和其源极连接所述第二时钟信号；
    第十五晶体管，其栅极连接所述第十四晶体管的漏极，其源极连接所述第二时钟信号，其漏极连接第四控制节点；
    第十六晶体管，其栅极连接所述第一控制节点，其源极连接所述第十四晶体管的漏极，其漏极连接所述固定电压源；
    第十七晶体管，其栅极连接所述第一控制节点，其源极连接所述第四控制节点，其漏极连接所述固定电压源；
    第十八晶体管，其栅极连接所述第四控制节点，其源极连接所述输出端，其漏极连接所述固定电压源；及
    第十九晶体管，其栅极连接所述第四控制节点，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
  8. 如权利要求1所述的栅极驱动电路，其中所述第一时钟信号和所述第二时钟信号互为反相。
  9. 如权利要求1所述的栅极驱动电路，其中所述第三时钟信号的频率大于所述第一时钟信号。
  10. 一种液晶显示器，包含：
    源极驱动器，用来产生数据信号；
    栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，第N级GOA电路单元用来依据第N-3级GOA电路单元输出的扫描信号、第N-3级启动信号、第N+3级GOA电路单元输出的扫描信号、第N+3级启动信号、第一时钟信号、第二时钟信号以及第三时钟信号，在输出端输出扫描信号，所述第N级GOA电路单元包含：
    输入控制模块，用来依据所述第N-3级启动信号端的信号和所述第N-3级GOA电路单元输出端的扫描信号，以控制第一控制节点的电平；
    输出模块，电性连接所述第一控制节点以及第二控制节点，用来于接收施加于所述第一控制节点的电压时，将所述第二控制节点的电压导通至所述输出端；
    输出控制模块，电性连接所述第二控制节点，用来依据所述第一时钟信号或所述第二时钟信号，控制施加于所述第二控制节点的电压；
    下拉模块，电性连接所述输出模块以及固定电压源，用来于接收所述第N-3级GOA电路单元输出端的扫描信号时，下拉所述输出端的扫描信号的电压以及下拉施加于所述第一控制节点的电压；及
    第一下拉维持模块，电性连接所述输出端、所述第一控制节点和所述第一时钟信号，用来依据施加于所述第一控制节点的电压，维持所述输出端的所述扫描信号的低电平；
    第二下拉维持模块，电性连接所述输出端、所述第一控制节点和所述第二时钟信号，用来依据施加于所述第一控制节点的电压，维持所述输出端的所述扫描信号的低电平。
  11. 如权利要求10所述的液晶显示器，其中所述输入控制模块包含：
    第一晶体管，其栅极连接所述第N-3级启动信号端，其源极连接第N-3级栅极信号端，其漏极连接所述第一控制节点。
  12. 如权利要求10所述的液晶显示器，其中所述输出模块包含：
    第二晶体管，其栅极连接所述第一控制节点，其源极连接所述第二控制节点，其漏极连接所述输出端；
    第三晶体管，其栅极连接所述第一控制节点，其源极连接所述第二控制节点，其漏极连接第N级启动信号端；及
    电容，其连接于所述第一控制节点和所述输出端之间。
  13. 如权利要求10所述的液晶显示器，其中所述输出控制模块包含：
    第四晶体管，其栅极连接所述第三时钟信号，其源极连接所述第二控制节点，其漏极连接所述第一时钟信号或是所述第二时钟信号；及
    第五晶体管，其栅极连接所述第三时钟信号，其源极连接所述第二控制节点，其漏极连接所述固定电压源。
  14. 如权利要求10所述的液晶显示器，其中所述下拉模块包含：
    第六晶体管，其栅极连接所述第N-3级GOA电路单元的输出端，其源极连接所述输出端，其漏极连接所述固定电压源；及
    第七晶体管，其栅极连接所述第N-3级GOA电路单元的输出端，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
  15. 如权利要求10所述的液晶显示器，其中第一下拉维持模块包含：
    第八晶体管，其栅极和其源极连接所述第一时钟信号；
    第九晶体管，其栅极连接所述第八晶体管的漏极，其源极连接所述第一时钟信号，其漏极连接第三控制节点；
    第十晶体管，其栅极连接所述第一控制节点，其源极连接所述第八晶体管的漏极，其漏极连接所述固定电压源；
    第十一晶体管，其栅极连接所述第一控制节点，其源极连接所述第三控制节点，其漏极连接所述固定电压源；
    第十二晶体管，其栅极连接所述第三控制节点，其源极连接所述输出端，其漏极连接所述固定电压源；及
    第十三晶体管，其栅极连接所述第三控制节点，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
  16. 如权利要求10所述的液晶显示器，其中第二下拉维持模块包含：
    第十四晶体管，其栅极和其源极连接所述第二时钟信号；
    第十五晶体管，其栅极连接所述第十四晶体管的漏极，其源极连接所述第二时钟信号，其漏极连接第四控制节点；
    第十六晶体管，其栅极连接所述第一控制节点，其源极连接所述第十四晶体管的漏极，其漏极连接所述固定电压源；
    第十七晶体管，其栅极连接所述第一控制节点，其源极连接所述第四控制节点，其漏极连接所述固定电压源；
    第十八晶体管，其栅极连接所述第四控制节点，其源极连接所述输出端，其漏极连接所述固定电压源；及
    第十九晶体管，其栅极连接所述第四控制节点，其源极连接所述第一控制节点，其漏极连接所述固定电压源。
  17. 如权利要求10所述的液晶显示器，其中所述第一时钟信号和所述第二时钟信号互为反相。
  18. 如权利要求10所述的液晶显示器，其中所述第三时钟信号的频率大于所述第一时钟信号。
PCT/CN2019/075545 2018-10-16 2019-02-20 栅极驱动电路以及使用该栅极驱动电路的液晶显示器 WO2020077924A1 (zh)

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