WO2017113447A1 - 栅极驱动电路及显示装置 - Google Patents

栅极驱动电路及显示装置 Download PDF

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Publication number
WO2017113447A1
WO2017113447A1 PCT/CN2016/071170 CN2016071170W WO2017113447A1 WO 2017113447 A1 WO2017113447 A1 WO 2017113447A1 CN 2016071170 W CN2016071170 W CN 2016071170W WO 2017113447 A1 WO2017113447 A1 WO 2017113447A1
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Prior art keywords
transistor
gate
pole
signal
gate driving
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PCT/CN2016/071170
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English (en)
French (fr)
Inventor
张盛东
胡治晋
廖聪维
曹世杰
李长晔
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/917,942 priority Critical patent/US9972266B2/en
Priority to DE112016004872.6T priority patent/DE112016004872T5/de
Priority to JP2018526666A priority patent/JP6732911B2/ja
Priority to KR1020187015803A priority patent/KR102057824B1/ko
Priority to GB1806445.1A priority patent/GB2557842B/en
Publication of WO2017113447A1 publication Critical patent/WO2017113447A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a display device.
  • Flat panel display (FPD, Flat-Panel-Display) has the advantages of high image clarity, flicker-free picture, energy saving and environmental protection, and thinness. It is currently the mainstream display. In recent years, flat panel displays have been developing in the direction of high frame rate, high resolution, and narrower borders.
  • the conventional driving method is an integrated circuit (IC), and the peripheral driving circuit is passed through a packaging process such as COG (Chip On Glass). Connecting to the liquid crystal panel is not only disadvantageous to the slimness of the display, but also costly. The number of pins of the peripheral driving circuit also affects the mechanical and electrical reliability of the display, especially for high-resolution displays. This kind of defect is more obvious.
  • integrated display driver circuits has solved the above problems well.
  • the integrated display driving circuit refers to a peripheral driving circuit such as a gate driving circuit and a data driving circuit of a display, which is formed on a liquid crystal panel together with a pixel thin film transistor in the form of a thin film transistor (TFT).
  • TFT thin film transistor
  • the Gate Driver on Array has been extensively studied, but as the display progresses toward high frame rates, high resolution, and narrower bezels, the operating frequency of the integrated gate drive circuit, Circuit footprints also place higher demands.
  • a low level sustain transistor is typically required to maintain a low level of the output signal of the gate drive circuit.
  • the control potential of the low-level sustain transistor in the existing circuit design cannot be fully pulled down to low power. Flat, leading to the existence of leakage. The low level maintains the leakage of the transistor, which increases the rise and fall delay of the output pulse of the gate drive circuit, thereby limiting the increase of the operating frequency of the circuit.
  • the technical problem to be solved by the present invention is to provide a gate driving circuit and a display device, which can reduce the leakage of the low level sustaining module, thereby reducing the delay of the gate signal output and improving the operating frequency.
  • a technical solution adopted by the present invention is to provide a gate driving circuit for driving a liquid crystal panel, which includes M cascaded gate driving units, wherein M is an integer greater than 1.
  • Each of the gate driving units includes an input module, an output module, a control module, and a first low level maintenance module;
  • the input module includes a pulse signal input terminal for inputting a first pulse signal, and is used for inputting the first control a first pull-down control terminal of the signal and a control signal output coupled to the first control node, the input module configured to control a potential of the first control node according to the first pulse signal and the first control signal
  • the output module includes a drive control end coupled to the first control node, a clock signal input terminal for inputting a first clock signal, and a gate signal output end, the output module being at the first control node a gate strobe signal or a gate turn-off signal is output through the gate signal output terminal under control of a potential;
  • the control module includes a clock signal input of the clock signal,
  • the input module includes a first transistor and a third transistor, and a gate of the first transistor is coupled to a first electrode of the first transistor for inputting the first pulse signal, the first transistor a second pole and a first pole of the third transistor are coupled to the first control node, a gate of the third transistor is configured to input the first control signal, and a second pole of the third transistor Connected to the low level node or to the first pole of the first transistor, the first control signal is a second pulse signal or a second clock signal, a high level of the first clock signal and the a high level of the second clock signal overlaps by 1/4 clock cycle; the output module includes a second transistor, a gate of the second transistor is coupled to the first control node, and a first of the second transistor The pole is used for inputting the first clock signal, and the second of the second transistor is the gate signal output end; the control module includes a fourth transistor, a fifth transistor, an eighth transistor, and a second capacitor.
  • the fourth crystal a gate connected to the first pole of the eighth transistor and one end of the second capacitor, the other end of the second capacitor for inputting the first clock signal, a gate of the eighth transistor and a gate of the fifth transistor is connected to the first control node, a second electrode of the eighth transistor and a second electrode of the fifth transistor are connected to the low level node, and the fifth transistor a first pole and a second pole of the fourth transistor are coupled to the second control node, a first pole of the fourth transistor is configured to input the first input signal;
  • the first low level maintenance module includes a sixth transistor and a seventh transistor, a gate of the sixth transistor and a gate of the seventh transistor are connected to the second control node, and a first electrode of the sixth transistor is connected to the first control a node, a second pole of the sixth transistor and a second pole of the seventh transistor are connected to the low level node, and a first pole of the seventh transistor is connected to a second pole of the second transistor .
  • the second pole of the third transistor of each stage of the gate driving unit of the first to the M-4th stage driving units is connected to the low level node and the gate input of the third transistor
  • the first control signal is a second pulse signal
  • the second pole of the third transistor of each stage of the M-3th to Mth stage gate driving unit is connected to the The first control signal input to the first pole of a transistor and the gate of the third transistor is a second clock signal.
  • control module further includes a fifteenth transistor, a gate of the fifteenth transistor is connected to a gate of the first transistor, and a first pole of the fifteenth transistor is connected to the second control a node, the second pole of the fifteenth transistor is coupled to the low level node.
  • the method further includes a second low level maintaining module, the control module further includes a ninth transistor and a tenth transistor, the second low level maintaining unit includes an eleventh transistor and a twelfth transistor; a gate of the transistor is connected to a gate of the fourth transistor, a first pole of the ninth transistor is used to input a third clock signal, and a second pole of the ninth transistor and a first one of the tenth transistor a gate, a gate of the eleventh transistor, and a gate of the twelfth transistor, a gate of the tenth transistor and a gate of the eighth transistor being connected to the first control node, a second pole of the tenth transistor is connected to the low level node, a first pole of the eleventh transistor is connected to a second pole of the second transistor, and a second pole of the eleventh transistor is a second pole of the twelfth transistor is connected to the low level node, a first pole of the twelfth transistor is connected to the first control node; and a first
  • the control module further includes a thirteenth transistor and a fourteenth transistor, wherein a gate of the thirteenth transistor is used to input the third clock signal, and a first pole of the thirteenth transistor is connected to the a first pole of the fourth transistor, a second pole of the thirteenth transistor is connected to the second control node, and a gate of the fourteenth transistor is used to input the fourth clock signal, A first pole of the fourteen transistor is coupled to the first pole of the ninth transistor, and a second pole of the fourteenth transistor is coupled to the second pole of the ninth transistor.
  • control unit further includes a sixteenth transistor and a seventeenth transistor, a gate of the sixteenth transistor is connected to a gate of the seventeenth transistor and a gate of the first transistor, a first pole of the sixteenth transistor is connected to the second pole of the ninth transistor, and a second pole of the sixteenth transistor and a second pole of the seventeenth transistor are connected to the low level node, A first pole of the seventeenth transistor is coupled to the second control node.
  • the gate drive unit of each of the first to the M-4th gate drive units is a second pole of the third transistor is coupled to the low level node and the first control signal of the gate input of the third transistor is a second pulse signal;
  • the M-3th to the Mth stage gate driving unit a second pole of the third transistor of each stage of the gate driving unit is connected to a first pole of the first transistor and the first control signal of a gate input of the third transistor is a second clock signal.
  • Each of the gate driving units further includes a second low level maintaining module, wherein the second low level maintaining module includes an eighteenth transistor and a nineteenth transistor; wherein the current stage gate driving unit is a gate of the eighteenth transistor and a gate of the nineteenth transistor are connected to a second control node of the previous stage gate driving unit, and a first pole connection of the eighteenth transistor of the current stage gate driving unit To the first control node of the current stage gate driving unit, the second electrode of the eighteenth transistor of the current stage gate driving unit is connected to the low level node of the current stage gate driving unit, and the current stage gate driving unit The first pole of the nineteenth transistor is connected to the second pole of the second transistor of the current stage gate driving unit, and the second pole of the nineteenth transistor of the current stage gate driving unit is connected to the current level gate a low level node of the pole drive unit; the first input signal of the first pole input of the fourth transistor of the current stage gate drive unit is a fourth clock signal.
  • the second low level maintaining module includes an eighteen
  • the first stage gate driving unit and each of the M-3th to Mth stage gate driving units further include a second low level maintaining module, a first level gate driving unit and a first stage
  • the control module of each of the M-3 to M-th gate drive units further includes a ninth transistor and a tenth transistor, the second low-level sustain unit including an eleventh transistor and a twelfth transistor; a gate of the ninth transistor is connected to a gate of the fourth transistor, a first electrode of the ninth transistor is used to input a third clock signal, and a second pole of the ninth transistor Connecting with a first pole of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor, a gate of the tenth transistor and a gate of the eighth transistor are connected Up to the first control node, a second pole of the tenth transistor is connected to the low level node, and a first pole of the eleventh transistor is connected to a second pole of the second transistor, a second pole of the eleventh transistor
  • a display device including a plurality of scan lines and a gate driving circuit for providing a gate signal to the scan lines, wherein the gate
  • the driving circuit includes M cascaded gate driving units, wherein M is an integer greater than 1, each of the gate driving units includes an input module, an output module, a control module, and a first low level maintaining module;
  • the module includes a pulse signal input for inputting a first pulse signal, a first pull-down control terminal for inputting a first control signal, and a control signal output coupled to the first control node, the input module for The first pulse signal and the first control signal control a potential of the first control node;
  • the output module includes a drive control end coupled to the first control node, a clock signal for inputting a first clock signal An input end and a gate signal output end, the output module being in the first control a gate strobe signal or a gate turn-off signal is output through the gate signal output terminal under control of a potential of the no
  • the input module includes a first transistor and a third transistor, and a gate of the first transistor is coupled to a first electrode of the first transistor for inputting the first pulse signal, the first transistor a second pole and a first pole of the third transistor are coupled to the first control node, a gate of the third transistor is configured to input the first control signal, and a second pole of the third transistor Connected to the low level node or to the first pole of the first transistor, the first control signal is a second pulse signal or a second clock signal, a high level of the first clock signal and the a high level of the second clock signal overlaps by 1/4 clock cycle; the output module includes a second transistor, a gate of the second transistor is coupled to the first control node, and a first of the second transistor The pole is used for inputting the first clock signal, and the second of the second transistor is the gate signal output end; the control module includes a fourth transistor, a fifth transistor, an eighth transistor, and a second capacitor.
  • the fourth crystal A first electrode and a gate of the eighth transistor and the second capacitor is connected to one end of said first The other end of the second capacitor is for inputting the first clock signal, the gate of the eighth transistor and the gate of the fifth transistor are connected to the first control node, and the second pole of the eighth transistor And a second pole of the fifth transistor connected to the low level node, a first pole of the fifth transistor and a second pole of the fourth transistor being connected to the second control node, the fourth transistor a first pole for inputting the first input signal;
  • the first low level maintaining module includes a sixth transistor and a seventh transistor, a gate of the sixth transistor and a gate of the seventh transistor To the second control node, a first pole of the sixth transistor is connected to the first control node, and a second pole of the sixth transistor and a second pole of the seventh transistor are connected to the low a level node, a first pole of the seventh transistor being coupled to a second pole of the second transistor.
  • the second pole of the third transistor of each stage of the gate driving unit of the first to the M-4th stage driving units is connected to the low level node and the gate input of the third transistor
  • the first control signal is a second pulse signal
  • the second electrode of the third transistor of each stage of the M-3th to Mth stage gate driving unit is connected to the first transistor
  • the first control signal of the first pole and the gate of the third transistor is a second clock signal.
  • control module further includes a fifteenth transistor, a gate of the fifteenth transistor is connected to a gate of the first transistor, and a first pole of the fifteenth transistor is connected to the second control a node, the second pole of the fifteenth transistor is coupled to the low level node.
  • Each of the gate driving units further includes a second low level maintaining module
  • the control module further includes a ninth transistor and a tenth transistor
  • the second low level maintaining unit includes an eleventh transistor and a a twelve transistor; a gate of the ninth transistor is connected to a gate of the fourth transistor, a first pole of the ninth transistor is used for inputting a third clock signal, and a second pole of the ninth transistor is a first pole of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor are connected, and a gate of the tenth transistor and a gate of the eighth transistor are connected to The first control node, the second pole of the tenth transistor is connected to the low level node, and the first pole of the eleventh transistor is connected to the second pole of the second transistor, the first a second pole of the eleven transistor and a second pole of the twelfth transistor are connected to the low level node, and a first pole of the twelfth transistor is connected to the first a control
  • the control module further includes a thirteenth transistor and a fourteenth transistor, wherein a gate of the thirteenth transistor is used to input the third clock signal, and a first pole of the thirteenth transistor is connected to the a first pole of the fourth transistor, a second pole of the thirteenth transistor is connected to the second control node, and a gate of the fourteenth transistor is used to input the fourth clock signal, A first pole of the fourteen transistor is coupled to the first pole of the ninth transistor, and a second pole of the fourteenth transistor is coupled to the second pole of the ninth transistor.
  • control unit further includes a sixteenth transistor and a seventeenth transistor, a gate of the sixteenth transistor is connected to a gate of the seventeenth transistor and a gate of the first transistor, a first pole of the sixteenth transistor is connected to the second pole of the ninth transistor, and a second pole of the sixteenth transistor and a second pole of the seventeenth transistor are connected to the low level node, A first pole of the seventeenth transistor is coupled to the second control node.
  • the second pole of the third transistor of each stage of the gate driving unit of the first to the M-4th stage driving units is connected to the low level node and the gate input of the third transistor
  • the first control signal is a second pulse signal
  • the second electrode of the third transistor of each stage of the M-3th to Mth stage gate driving unit is connected to the first transistor
  • the first control signal of the first pole and the gate of the third transistor is a second clock signal.
  • Each of the gate driving units further includes a second low level maintaining module, wherein the second low level maintaining module includes an eighteenth transistor and a nineteenth transistor; wherein the current stage gate driving unit is a gate of the eighteenth transistor and a gate of the nineteenth transistor are connected to a second control node of the previous stage gate driving unit, and a first pole connection of the eighteenth transistor of the current stage gate driving unit To the first control node of the current stage gate driving unit, the second electrode of the eighteenth transistor of the current stage gate driving unit is connected to the low level node of the current stage gate driving unit, and the current stage gate driving unit The first pole of the nineteenth transistor is connected to the second pole of the second transistor of the current stage gate driving unit, and the second pole of the nineteenth transistor of the current stage gate driving unit is connected to the current level gate a low level node of the pole drive unit; the first of the first pole inputs of the fourth transistor of the current stage gate drive unit The input signal is the fourth clock signal.
  • the second low level maintaining module includes an eighte
  • the first stage gate driving unit and each of the M-3th to Mth stage gate driving units further include a second low level maintaining module, a first level gate driving unit and a first stage
  • the control module of each of the M-3 to M-th gate drive units further includes a ninth transistor and a tenth transistor, the second low-level sustain unit including an eleventh transistor and a twelfth transistor; a gate of the ninth transistor is connected to a gate of the fourth transistor, a first pole of the ninth transistor is used to input a third clock signal, and a second pole of the ninth transistor Connecting with a first pole of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor, a gate of the tenth transistor and a gate of the eighth transistor are connected Up to the first control node, a second pole of the tenth transistor is connected to the low level node, and a first pole of the eleventh transistor is connected to a second pole of the second transistor, a second pole of the eleventh transistor
  • the present invention provides a control module for pulling down the potential of the second control node before the output module outputs the gate strobe signal and during the output gate strobe signal.
  • the third pull-down control terminal of the low-level maintenance module can be pulled down to a low level before the output module output gate strobe signal and during the output gate strobe signal, so that the low-level maintenance module It is in the off state, which can reduce the leakage of the low level maintenance module, which is beneficial to reduce the output delay time of the output gate strobe signal of the output module.
  • FIG. 1 is a schematic structural view of an embodiment of a gate driving unit of the present invention
  • FIG. 2 is a schematic structural diagram of a specific circuit of an embodiment of a gate driving unit of the present invention.
  • FIG. 3 is an operational timing diagram of an embodiment of the gate driving unit shown in FIG. 2;
  • FIG. 4 is an operational timing diagram of another embodiment of the gate driving unit shown in FIG. 2;
  • FIG. 5 is a schematic structural diagram of a specific circuit of another embodiment of a gate driving unit of the present invention.
  • FIG. 6 is a schematic structural diagram of a specific circuit of still another embodiment of a gate driving unit of the present invention.
  • FIG. 7 is a timing chart showing an operation of an embodiment of the gate driving unit shown in FIG. 6;
  • FIG. 8 is a timing chart showing an operation of another embodiment of the gate driving unit shown in FIG. 6;
  • FIG. 9 is a schematic structural diagram of a specific circuit of still another embodiment of a gate driving unit of the present invention.
  • FIG. 10 is a schematic structural diagram of a specific circuit of still another embodiment of a gate driving unit of the present invention.
  • FIG. 11 is a schematic structural diagram of a specific circuit of still another embodiment of a gate driving unit of the present invention.
  • Figure 12 is a timing chart showing the operation of an embodiment of the gate driving unit shown in Figure 11;
  • Figure 13 is a timing chart showing the operation of another embodiment of the gate driving unit shown in Figure 11;
  • FIG. 14 is a schematic structural diagram of a specific circuit of still another embodiment of a gate driving unit of the present invention.
  • Figure 15 is a timing chart showing the operation of an embodiment of the gate driving unit shown in Figure 14;
  • 16 is a schematic structural view of an embodiment of a gate driving circuit of the present invention.
  • FIG. 17 is a schematic structural view of another embodiment of a gate driving circuit of the present invention.
  • FIG. 18 is a schematic structural view of still another embodiment of a gate driving circuit of the present invention.
  • Figure 19 is a timing chart showing the operation of an embodiment of the gate driving circuit of the present invention.
  • FIG. 20 is a schematic structural view of an embodiment of a display device of the present invention.
  • 21 is a schematic diagram showing signal waveforms of a third pull-down control terminal of a low-level maintenance module of the present invention and a signal waveform of a control terminal of a low-level maintenance module in a conventional gate driving unit.
  • a gate driving unit for driving a liquid crystal panel is configured to output a scan driving signal to a scan line of a liquid crystal panel, including an input module 11 , an output module 12 , and a control Module 13 and first low level maintenance module 14.
  • the input module 11 comprises an input pulse a first pulse signal V i is the input terminal, for outputting a first control signal input terminal of the first pull-down control signal V c and a control coupled to the first control node Q 1 ' end.
  • the input module is configured to control the potential of the first control node Q 1 according to the first pulse signal V i and the first control signal V c .
  • Output module 12 includes a drive control terminal coupled to the first control node Q 1 ', a clock signal input terminal and a gate signal output terminal of the first input of the clock signal CK A.
  • the gate signal output end is used for connecting to the scan line of the liquid crystal panel.
  • the output module 12 outputs a gate signal V o through the gate signal output terminal under the control of the potential of the first control node Q 1 , wherein the gate signal V o includes a gate strobe signal and a gate turn-off signal.
  • the gate strobe signal refers to a high-level scan signal that turns on the pixel thin film transistor connected to the scan line
  • the gate-off signal refers to a low-level scan signal that turns off the pixel thin film transistor connected to the scan line.
  • the control module 13 includes a clock signal input terminal for inputting the first clock signal CK A , a first input signal terminal for inputting the first input signal V ii , a second pull-down control terminal coupled to the second control node Q 2 , A first control terminal coupled to the first control node Q 1 and a first pull-down terminal coupled to the low level node Q 3 .
  • the control module 13 is configured to at least use the potential of the second control node Q 2 under the high level control of the first control node Q 1 before the output gate 12 outputs the gate strobe signal and during the output gate strobe signal. Pull down to low level.
  • control module 13 is further configured to, after the gate of the output module 12 outputs a strobe signal to the high level to the potential of the second pull-up control node at a first control node Q 1 is low-level control.
  • the first low level maintenance module 14 includes a third pull-down control terminal coupled to the second control node Q 2 , a first end coupled to the first control node Q 1 , and a gate drive signal output coupled to the output module 12 and a second end coupled to the low end of the third node Q 3.
  • the first module 14 is maintained at a low level until the output module 12 outputs the gate strobe signal in an off state, and at least during the gate strobe signal at a low level control of the second control node Q 2.
  • the first low level maintaining module 14 is further configured to be in an on state after the output module 12 outputs the gate strobe signal under the high level control of the second control node Q 2 to connect the gate of the output module 12 The potential at the output of the pole signal is pulled low.
  • the on and off of the first low level maintenance module 14 is determined by the potential of the third pull-down control terminal, and the first low level maintenance module 14 is turned on when the potential of the third pull-down control terminal is high, so that The gate signal output end of the output module 12 is coupled to the low level node Q 3 , thereby maintaining the gate signal output end of the output module 12 in a low state; and the first low power when the potential of the third pull down control terminal is a low level The level maintenance module 14 is turned off.
  • the potential of the second control node Q 2 is controlled by the setting control module 13 to control the potential of the third pull-down control terminal of the first low level maintaining module 14 before the output gate 12 outputs the gate strobe signal and the output gate strobe signal During the period, the potential of the second control node Q 2 is pulled down to a low level, so that the third pull-down control terminal of the first low level maintaining module 14 can output the gate strobe signal before the output module 12 outputs the output gate Pulling down to a low level during the pass signal causes the first low level maintaining module 14 to be in an off state, thereby reducing leakage of the first low level maintaining module 14 and avoiding leakage conduction of the first low level maintaining module 14 The potential of the gate signal output end of the output module 12 is pulled low, thereby reducing the output delay of the output gate strobe signal of the output module 12, and improving the working efficiency of the circuit.
  • the control module 13 controls the potential of the second control node Q 2 to be pulled high after the output gate 12 outputs the gate strobe signal
  • the first low level maintaining module 14 is turned on, thereby outputting the module 12
  • the potential of the gate signal output terminal is pulled down to a low level, thereby maintaining the potential of the output terminal of the output module 12 at a low level, thereby preventing the pixel thin film transistor connected to the gate signal output terminal from being turned on, preventing signal writing errors. .
  • the gate driving unit of the embodiment of the present invention will be described below in conjunction with a specific circuit configuration.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the input module 11 includes a first transistor T1 and a third transistor T3.
  • the gate of the first transistor T1 and the first pole are short-circuited as the pulse signal input end of the input module 11, for inputting the first pulse signal V i , the second pole of the first transistor T1 and the third transistor T3 One pole is connected to the first control node Q 1 , the second pole of the third transistor T3 is connected to the low level node Q 3 , and the gate of the third transistor T3 is used as the first pull-down control terminal of the input module 11 for input The first control signal V c .
  • the output module 12 includes a second transistor T2, and further includes a first capacitor C1.
  • the gate of the second transistor T2 serves as a driving control end of the output module 12 and is connected to the first control node Q 1 .
  • the first pole of the second transistor T2 serves as a clock signal input terminal of the output module 12 for inputting the first clock signal CK A .
  • the second terminal of the second transistor T2 outputs the gate signal output of the module 12. Both ends of the first capacitor C1 are connected to the second poles of the first control node Q 1 and the second transistor T2, respectively.
  • the control module 13 includes a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, and a second capacitor C2.
  • the gate of the fourth transistor T4 is connected to the first pole of the eighth transistor T8 and one end of the second capacitor C2.
  • the other end of the second capacitor C2 serves as a clock signal input terminal of the control module 13 for inputting the first clock signal CK A .
  • the first pole of the fourth transistor T4 serves as a first input signal terminal of the control module 13 for inputting the first input signal.
  • a second electrode of the fourth transistor T4 and the fifth transistor T5 is connected to the second electrode, and is connected to a second control node Q 2 as a second pull-down control terminal 13 of the control module.
  • Gate of the fifth transistor T5 and T8 is connected to the gate of the eighth transistor, and is connected to a first control node Q 1 as a first control terminal 13 of the control module.
  • a second electrode of the fifth transistor T5 and the eighth transistor T8 is connected to the second electrode, and is connected to the low level as the first pull-down node Q 3 end of the control module 13.
  • the first low level maintenance module 14 includes a sixth transistor T6 and a seventh transistor T7.
  • the gate of the sixth transistor T6 is connected to the gate of the seventh transistor T7, and is connected to the second control node Q 2 as a third pull-down control terminal of the first low level maintaining module 14.
  • the first pole of the sixth transistor T6 is connected to the first control node Q 1 as the first end of the first low level maintenance module 14.
  • the first pole of the seventh transistor T7 is connected as the second end of the first low level maintaining module 14 to the second pole of the second transistor T2.
  • a second electrode of the sixth transistor T6 and the seventh transistor T7 is connected to the second electrode, and maintaining a low level as a first end 14 of the third module is connected to the low level node Q 3.
  • the first pulse signal V i is a gate signal output by the front second gate driving unit.
  • the current stage gate driving unit is the third level gate driving unit
  • the first pulse signal of the current stage is V i is a gate signal output by the first-stage gate driving unit.
  • the first pulse signal V i may also be the gate signal output by the previous stage gate driving unit, or the required first pulse signal V i may be input using a separate signal source.
  • the first clock signal CK A is a high frequency clock signal having a high level voltage of V H1 and a low level voltage of V L1 .
  • the first control signal V c is a second pulse signal.
  • the high voltage source V DD is coupled to the first pole of the fourth transistor T4 to provide a first input signal, ie, the first input signal is a high level signal having a voltage magnitude of V H2 .
  • the low voltage source V SS is connected to the low level node Q 3 to provide a low level signal having a voltage of V L . Where V H1 ⁇ V H2 and V L ⁇ V L1 .
  • FIG. 3 is an operational timing diagram of an embodiment of the gate driving unit shown in FIG. 2.
  • the operation process of the gate driving unit can be divided into two phases: a driving phase (time t1 to t4) and a low level sustaining phase (after time t5).
  • the liquid crystal panel is in a progressive scan mode. Therefore, in one frame, the gate driving unit outputs a high-level scan signal only to the scan line connected thereto at the scanning timing, and is gated at other times after the high-level scan signal is output.
  • the output of the pole drive unit needs to be maintained in a low state to avoid turning on the pixel thin film transistor connected to the scan line connected to it, preventing signal writing errors.
  • the first control signal V c to a low level, so that the third transistor T3 is turned off.
  • the potential of the first clock signal CK A is a low level V L1
  • the potential of the first pulse signal V i is a high level V H1 .
  • the first transistor T1 is turned on, and the first pulse signal V i passes through the first transistor T1.
  • the fifth transistor T5 and the eighth transistor T8 are turned on, thereby causing the gate potential of the fourth transistor T4 to be pulled down. Up to the low level V L , so that the fourth transistor T4 is completely turned off, whereby the potential V Q2 of the second control node Q 2 can be completely pulled down to the low level V L by the turned-on fifth transistor T5, so that The sixth transistor T6 and the seventh transistor T7 are turned off, thereby causing the first low level maintaining module 14 to be in an off state.
  • the first control signal V c is still low.
  • the potential of the first pulse signal V i drops to a low level V L1 , causing the first transistor T1 to turn off.
  • the potential V Q1 of the first control node Q 1 remains at a high level, so that the second transistor T2 maintains an on state, and the potential of the first clock signal CK A rises from a low level V L1 to a high level V H1 , the gate signal output terminal is charged by the turned-on second transistor T2, so that the potential of the gate signal output terminal rises rapidly.
  • the first transistor T1 Since the first transistor T1, the third transistor T3 and a sixth transistor T6 is in the off state, resulting in a first control node Q 1 (i.e., the gate of the second transistor T2) in a floating state. Therefore, under the action of the capacitor bootstrap effect, as the voltage at the output of the gate signal increases, the voltage of the first control node Q 1 is raised to a higher voltage than V H1 -V TH1 , thereby the gate signal The output can be quickly charged to a high level V H1 to output a high level gate signal V o .
  • the first clock signal CK A falls from the high level V H1 to the low level V L1 , and since the potential V Q1 of the first control node Q 1 is still at the high level, the second transistor T2 remains turned on. The state, therefore, the gate signal output is discharged through the turned-on second transistor T2, so that the potential of the gate signal V o outputted from the gate signal output can be quickly dropped to a low level V L1 . Due to the capacitor bootstrap effect, the potential V Q1 of the first control node Q 1 drops to V H1 -V TH1 .
  • the first control signal V c rises from the low level to the high level, the third transistor T3 is turned on, whereby the potential of the first control node Q V Q1 1 is pulled down to the low level V L, so that the fifth The transistor T5 and the eighth transistor T8 are turned off. Since the first clock signal CK A is still at the low level V L1 , the fourth transistor T4 is still in the off state, so that the potential V Q2 of the second control node Q 2 is maintained at the low level V L .
  • the first clock signal CK A rises from the low level V L1 to the high level V H1 , and the second capacitor C2 couples the high voltage to the gate of the fourth transistor T4 such that the fourth transistor T4 is turned on.
  • the high voltage source V DD charges the second control node Q 2 through the turned-on fourth transistor T4 such that the potential V Q2 of the second control node Q 2 rises to V H2 -V TH4 , where V TH4 is the fourth transistor T4
  • V TH4 is the fourth transistor T4
  • the sixth transistor T6 and the seventh transistor T7 are turned on.
  • the potential V Q1 of the first control node Q 1 is pulled down to the low level V L by the turned-on sixth transistor T6.
  • the turned-on seventh transistor T7 the potential of the second electrode of the second transistor T2 is pulled down to the low level V L , that is, the gate signal V o outputted from the gate signal output terminal is pulled down to the low level V L .
  • the potential V Q2 of the second control node Q 2 can be pulled down to the low through the turned-on fifth transistor T5.
  • the level V L thereby suppressing the leakage of the sixth transistor T6 and the seventh transistor T7, thereby reducing the rise delay time of the output of the gate signal output, and is advantageous for increasing the operating speed of the circuit.
  • the connected scan line is in a non-strobe state, and the gate signal output end of the gate drive unit needs to be kept at a low level V L to prevent
  • the pixel thin film transistor connected to the scan line is turned on to cause a signal write error.
  • the potential V Q1 of the first control node Q 1 ie, the gate of the second transistor T2
  • the potential V o of the gate signal output terminal ie, the second pole of the second transistor T2
  • the fourth transistor T4 is periodically turned on with the high level pulse of the first clock signal CK A , and the second The potential V Q2 of the control node Q 2 is always kept at a high level, so that the sixth transistor T6 and the seventh transistor T7 are kept in an on state, thereby maintaining the gate signal V o outputted from the gate signal output terminal at a low level. Scan the signal.
  • Fig. 4 is a timing chart showing the operation of another embodiment of the gate driving unit shown in Fig. 2.
  • the high level of the first pulse signal V i and the low level of the first clock signal CK A come simultaneously.
  • the high level of the first pulse signal V i overlaps with the high level of the first clock signal CK A by 1/4 clock. cycle.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 5 is a schematic structural diagram of a specific circuit of another embodiment of a gate driving unit according to the present invention.
  • the control module 13 further includes a fifteenth transistor T15. Wherein a gate of the fifteenth transistor T15 is connected to the first transistor T1, a first fifteenth transistor T15 is connected to the second control node Q 2, the second electrode fifteenth transistor T15 is connected to the low Level node Q 3 .
  • the gate of the fifteenth transistor T15 is controlled by a first pulse signal V i.
  • V i a first pulse signal
  • the fifteenth transistor T15 of the high level control signal of the first pulse signal V i is turned on, whereby the potential V Q2 of the second control node Q 2 can be quickly pulled down
  • the low level V L further suppresses the leakage current that may exist in the seventh transistor T7 at time t1, which is advantageous for further reducing the rise delay time of the output signal of the second transistor T2 and improving the operating speed of the circuit.
  • the operation timing chart of the gate driving unit of the present embodiment is the same as the operation timing chart of the gate driving unit shown in FIG. 2, and the specific working process can be performed by referring to the working mode shown in FIG. 3 or FIG. Do not repeat them one by one.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 6 is a schematic structural diagram of a specific circuit of still another embodiment of a gate driving unit according to the present invention.
  • the control module 13 further includes a ninth transistor T9 and a tenth transistor T10.
  • the gate driving unit further includes a second low level maintaining module 15 , wherein the second low level maintaining module 15 includes the eleventh crystal The tube T11 and the twelfth transistor T12.
  • the gate of the ninth transistor T9 is connected to the gate of the fourth transistor T4, the first pole of the ninth transistor T9 is used to input the third clock signal EXCK, and the second pole of the ninth transistor T9 and the tenth transistor T10 first, a gate of the eleventh transistor T11 and the gate of the twelfth transistor T12 are connected to a fourth control node Q 4.
  • Gate of the tenth transistor T10 and the gate of the eighth transistor T8 is connected to the first control node Q 1, the second electrode of the tenth transistor is connected to the low level of the node Q 3 T10.
  • the first pole of the eleventh transistor T11 is connected to the second pole of the second transistor T2, that is, to the gate signal output terminal.
  • a second electrode of the second pole of the eleventh and the twelfth transistor T11 the transistor T12 is connected to the low level node Q 3.
  • the first pole of the twelfth transistor T12 is coupled to the first control node Q 1 .
  • the first input signal input by the fourth transistor T4 is the fourth clock signal ECK.
  • the third clock signal EXCK and the fourth clock signal ECK are two-phase low frequency clock signals.
  • the sixth transistor T6 and the seventh transistor T7 in the first low level maintaining module 14 are under an approximate DC stress bias, which may occur after a long period of operation. Severe threshold voltage drift. When the threshold voltage drift exceeds a certain level, it will cause the circuit to fail. With the gate driving unit of the present embodiment, the threshold voltage drift of the transistor can be reduced, and the reliability of the circuit can be enhanced.
  • FIG. 7 is an operational timing chart of an embodiment of the gate driving unit shown in FIG. 6.
  • the third clock signal EXCK is at a low level
  • the voltage magnitude is V L
  • the fourth clock signal ECK is at a high level
  • the voltage magnitude is V H2 .
  • the high level of the first pulse signal V i and the low level of the first clock signal CK A arrive at the same time.
  • the process in which the gate driving unit of the present embodiment operates according to the operation timing chart shown in FIG. 7 is mainly different from the process in which the gate driving unit shown in FIG. 2 operates according to the operation timing chart shown in FIG.
  • the first clock signal CK A rises from a low level V L1 to a high level V H1 , and a high voltage is coupled through a second capacitor C2 to the gate of the fourth transistor T4 such that the fourth transistor T4 is turned on.
  • the fourth clock signal ECK Since the fourth clock signal ECK is a high level signal, the fourth clock signal ECK charges the second control node Q 2 through the turned-on fourth transistor T4, so that the potential V Q2 of the second control node Q 2 rises to V H2 -V TH4 , at which time the sixth transistor T6 and the seventh transistor T7 are turned on.
  • the potential V Q1 of the first control node Q 1 is pulled down to the low level V L by the turned-on sixth transistor T6.
  • the turned-on seventh transistor T7 the potential of the second electrode of the second transistor T2 is pulled down to the low level V L , that is, the gate signal V o outputted from the gate signal output terminal is pulled down to the low level V L .
  • the fourth transistor T4 is periodically turned on under the high level control of the first clock signal CK A , and the second control node Q 2
  • the potential V Q2 is always maintained at a high level, so that the sixth transistor T6 and the seventh transistor T7 are kept in an on state, whereby the gate signal V o outputted from the gate signal output terminal can be maintained as a low level scan signal.
  • the working process of the control module 13 and the first low-level maintenance module 14 at other times may be referred to the foregoing embodiment, and details are not described herein.
  • the ninth transistor T9 is in the off state.
  • the time t4 that is, after the second transistor T2 outputs the high-level gate signal V o , the potential V Q1 of the first control node Q 1 is pulled low to the low level, the fifth transistor T5, the eighth transistor T8 and a tenth transistor T10 is turned off, the fourth transistor T4 and the ninth transistor T9 is turned on in a periodic level control of the first clock signal CK a, Q 2 such that the second control node is charged to the high level, so that the first a sixth transistor T6, low maintenance means 14 and the seventh transistor T7 is in the oN state, and thus the gate signal V o is maintained in the low state.
  • the second and the tenth transistor is connected to the low level of the node Q 3 T10, so both the ninth transistor T9 is turned on or the tenth transistor T10 is turned on, will pull a fourth low potential of the control node Q is Q4 V 4 to a low level, so the potential of the fourth control node Q V Q4 4 is kept low, so that the eleventh transistor T11 and a twelfth transistor T12 is turned off status.
  • the gate driving unit maintains the low-level scan signal outputted by the gate signal output terminal through the first low-level maintaining module 14, and the second low-level sustaining module 15 is in the off state.
  • FIG. 8 is an operational timing diagram of another embodiment of the gate driving unit shown in FIG. 6.
  • the third clock signal EXCK is at a high level
  • the voltage magnitude is V H2
  • the fourth clock signal ECK is low.
  • the voltage is V L .
  • the gate driving unit maintains the low-level scan signal outputted by the gate signal output terminal through the second low-level maintaining module 15, and the first low-level maintaining module 14 It is in the off state.
  • the fourth clock signal ECK is at a low level
  • the second electrode of the fifth transistor T5 is connected to the low-level node Q3
  • whether the fourth transistor T4 is turned on or the fifth transistor T5 is turned on down the potential of the second control node Q and Q2 to the low level V 2, so the potential of the second control node Q V Q2 2 is kept low, so that the sixth transistor T6 and the seventh transistor T7 is in the OFF state That is, during the driving process of the circuit, the first low level maintaining module 14 is always in an off state.
  • the first control signal V c to a low level, so that the third transistor T3 is turned off.
  • the potential of the first clock signal CK A is a low level V L1
  • the potential of the first pulse signal V i is a high level V H1 .
  • the first transistor T1 is turned on, and the first pulse signal V i passes through the first transistor T1.
  • the eighth transistor T8 and the tenth transistor T10 are turned on, thereby causing the gate potential of the ninth transistor T9 to be pulled down.
  • the ninth transistor T9 is completely turned off, whereby the potential V Q4 of the fourth control node Q 4 can be completely pulled down to the low level V L by the turned-on tenth transistor T10, so that The eleventh transistor T11 and the twelfth transistor T12 are turned off, thereby causing the second low level maintaining module 15 to be in an off state.
  • the first control signal V c is still low.
  • the potential of the first pulse signal V i drops to a low level V L1 , causing the first transistor T1 to turn off.
  • the potential V Q1 of the first control node Q 1 remains at a high level, so that the second transistor T2 maintains an on state, and the potential of the first clock signal CK A rises from a low level V L1 to a high level V H1 , the gate signal output terminal is charged by the turned-on second transistor T2, so that the potential of the gate signal output terminal rises rapidly.
  • first transistor T1 Since the first transistor T1, the third transistor T3, the sixth transistor T6 and a twelfth transistor T12 is in the off state, resulting in a first control node Q 1 (i.e., the gate of the second transistor T2) in a floating state. Therefore, under the action of the capacitor bootstrap effect, as the voltage at the output of the gate signal increases, the voltage of the first control node Q 1 is raised to a higher voltage than V H1 -V TH1 , thereby the gate signal The output can be quickly charged to a high level V H1 to output a high level gate signal V o .
  • the first clock signal CK A falls from the high level V H1 to the low level V L1 , and since the potential V Q1 of the first control node Q 1 is still at the high level, the second transistor T2 remains turned on. The state, therefore, the gate signal output is discharged through the turned-on second transistor T2, so that the potential of the gate signal V o outputted from the gate signal output can be quickly dropped to a low level V L1 . Due to the capacitor bootstrap effect, the potential V Q1 of the first control node Q 1 drops to V H1 -V TH1 .
  • the first control signal V c rises from the low level to the high level, the third transistor T3 is turned on, whereby the potential of the first control node Q V Q1 1 is pulled down to the low level V L, so that the eighth The transistor T8 and the tenth transistor T10 are turned off. Since the first clock signal CK A is still at the low level V L1 , the ninth transistor T9 is still in the off state, so that the potential V Q4 of the fourth control node Q 4 is maintained at the low level V L .
  • the first clock signal CK A rises from a low level V L1 to a high level V H1 , and a high voltage is coupled through a second capacitor C2 to the gate of the ninth transistor T9 such that the ninth transistor T9 is turned on.
  • the third clock signal EXCK is a high level signal
  • the third clock signal EXCK charges the fourth control node Q 4 through the turned-on ninth transistor T9, so that the potential V Q2 of the fourth control node Q 4 rises to V H2 .
  • V TH9 is the threshold voltage of the ninth transistor T9, at which time the eleventh transistor T11 and the twelfth transistor T12 are turned on.
  • the potential V Q1 of the first control node Q 1 is pulled down to the low level V L by the turned-on twelfth transistor T12.
  • the turned-on eleventh transistor T11 the potential of the second electrode of the second transistor T2 is pulled down to the low level V L , that is, the gate signal V o outputted from the gate signal output terminal is pulled down to the low level V L.
  • the ninth transistor T9 is periodically turned on under the high level control of the first clock signal CK A , and the fourth control node Q 4
  • the potential V Q4 is always maintained at a high level, so that the eleventh transistor T11 and the twelfth transistor T12 are kept in an on state, whereby the gate signal V o outputted from the gate signal output terminal can be maintained as a low level scan signal.
  • the transistors in the first low level maintenance module 14 and the second low level maintenance module 15 will be in an alternate mode of operation.
  • the clock signal EXCK is at a low level
  • the clock signal ECK is at a high level.
  • the gate driving unit operates according to the operation timing chart shown in FIG. 7, and the transistor in the first low level maintaining module 14 The active state is used to maintain the low level of the gate signal output terminal, and the transistor in the second low level maintenance module 15 is in the off state; the clock signal EXCK is switched to the high level at the next moment, and the clock signal ECK is switched.
  • the gate driving unit operates according to the operation timing chart shown in FIG.
  • the transistor in the second low level maintaining module 15 is in an active state for maintaining the low level of the gate signal output terminal, and
  • the transistors in the first low level maintenance module 14 are in an off state.
  • the transistor in one of the low-level sustaining modules can be prevented from being in a long-term working state, which is advantageous for suppressing threshold voltage drift of the transistor and providing circuit operation. life.
  • the two low level maintenance modules 14, 15 share one control module 13, which can save circuit area.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 9 is a schematic structural view of another embodiment of the gate driving unit of the present invention.
  • the operation timing chart of the gate driving unit of the present embodiment is the same as the operation timing chart of the gate driving unit shown in FIG. 6.
  • the present embodiment is mainly different from the gate driving unit shown in FIG. 6 in that, in the present embodiment, the control module 13 further includes a thirteenth transistor T13 and a fourteenth transistor T14.
  • the gate of the thirteenth transistor T13 is used to input the third clock signal EXCK, the first pole of the thirteenth transistor T13 is connected to the first pole of the fourth transistor T4, and the fourth clock signal ECK is input, the tenth
  • the second pole of the three transistor T13 is connected to the second control node Q 2 .
  • the gate of the fourteenth transistor T14 is used to input the fourth clock signal ECK, and the first pole of the fourteenth transistor T14 is connected to the first pole of the ninth transistor T9 for inputting the third clock signal EXCK, the fourteenth transistor T14 is connected to the second electrode of the fourth control node Q 4.
  • the low voltage of the gate signal output terminal is realized by the transistors T6 and T7.
  • the sustain is maintained, and the fourteenth transistor T14 is turned on.
  • the third clock signal EXCK can be coupled to the fourth control node Q 4 through the turned-on fourteenth transistor T14, whereby the low level of the fourth control node Q 4 can be further stabilized, avoiding the fourth control node Q 4
  • the low level of instability causes leakage of the transistors T11 and T12, which is beneficial to the circuit output to be more stable.
  • the low level of the gate signal output terminal is maintained by the transistors T11 and T12, and the thirteenth transistor T13 is turned on.
  • the fourth clock signal ECK can be coupled to the second control node Q 2 via the turned-on thirteenth transistor T13, whereby the low level of the second control node Q 2 can be further stabilized, avoiding the second control node Q 2
  • the low level of instability causes leakage of the transistors T6 and T7, which is beneficial to the circuit output being more stable.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • FIG. 10 is a schematic structural view of another embodiment of a gate driving unit of the present invention.
  • the operation timing chart of the gate driving unit of the present embodiment is the same as the operation timing chart of the gate driving unit shown in FIG. 6.
  • the present embodiment is mainly different from the gate driving unit shown in FIG. 6 in that, in the present embodiment, the control module 13 further includes a sixteenth transistor T16 and a seventeenth transistor T17.
  • the gate of the sixteenth transistor T16 and the gate of the seventeenth transistor T17 are both connected to the gate of the first transistor T1 for inputting the first pulse signal V i , and the first pole of the sixteenth transistor T16 is connected to the first The fourth control node Q 4 , the second pole of the sixteenth transistor T16 is connected to the low level node Q 3 .
  • the first pole of the seventeenth transistor T17 is connected to the second control node Q 2 , and the second pole of the seventeenth transistor T17 is connected to the low level node Q 3 .
  • the sixteenth transistor T16 and the seventeenth transistor T17 are driven by the first pulse signal V i , and by adding the transistors T16 and T17, when the gate driving unit operates according to the operation timing chart shown in FIG. 7, at time t1,
  • the turned-on seventeenth transistor T17 can quickly pull down the gates of the sixth transistor T6 and the seventh transistor T7 to a low level V L , thereby suppressing leakage of transistors T6 and T7 at time t1, further reducing The output of the circuit rises with a delay.
  • the gate driving unit operates according to the operation timing chart shown in FIG. 8, at the time t1, the gates of the eleventh transistor T11 and the twelfth transistor T12 can be quickly pulled down through the turned-on sixteenth transistor T16.
  • the low level V L thereby suppresses leakage that may occur in the transistors T11 and T12 at time t1, and further reduces the output rise delay of the circuit.
  • FIG. 11 is a schematic structural view of another embodiment of a gate driving unit of the present invention.
  • Each gate driving unit is used to drive one scanning line. Therefore, the liquid crystal panel usually needs to be driven by a plurality of gate driving units, and the plurality of gate driving units are connected in a cascade manner, and the gate of each stage of the gate driving unit is gated.
  • the pole signal output is connected to a scan line.
  • the gate driving unit is different from the gate driving unit of the embodiment shown in FIG. 2 in that the gate driving unit of the present embodiment further includes a second low level maintaining module 16 for maintaining the second low level.
  • Module 16 includes a eighteenth transistor T18 and a nineteenth transistor T19. Assuming that the current stage gate driving unit is N, the previous stage gate driving unit is N-1, as shown in FIG.
  • the gate of the eighteenth transistor T18 of the current stage gate driving unit N and the nineteenth transistor T19 The gates are both connected to the second control node Q 2 of the previous stage gate driving unit N-1, and the first electrode of the eighteenth transistor T18 of the current stage gate driving unit N is connected to the current stage gate driving unit N
  • the first control node Q 1 , the second electrode of the eighteenth transistor T18 of the current stage gate driving unit N is connected to the low level node Q 3 of the current stage gate driving unit N.
  • the first pole of the nineteenth transistor T19 of the current stage gate driving unit N is connected to the second pole of the second transistor T2 of the current stage gate driving unit N, and the nineteenth transistor T19 of the current stage gate driving unit N a second current electrode connected to a low-level gate driving unit of the node N Q 3.
  • the first input signal of the first pole input of the fourth transistor T4 of the current stage gate driving unit N is the fourth clock signal ECK
  • the first pole of the fourth transistor T4 of the previous stage gate driving unit N-1 The input first input signal is the third clock signal EXCK.
  • the gate driving unit of the present embodiment is similar to the operation of the gate driving unit of the embodiment shown in FIG. 6. The main difference is that the second low level maintaining module 16 of the gate driving unit of the present embodiment passes the previous stage. The second control node of the gate drive unit is driven.
  • FIG. 12 is an operational timing diagram of an embodiment of the gate driving unit shown in FIG.
  • the high level of the first pulse signal V i(N) and the low level of the first clock signal CK A(N) come simultaneously.
  • the third clock signal ECXK is low level
  • the voltage magnitude is V L
  • the fourth clock signal ECK is high level
  • the voltage magnitude is V H2 .
  • the working process of the previous stage gate driving unit N-1 Similar to the process in which the gate driving unit shown in FIG. 6 operates according to the operation timing chart shown in FIG. 8, the specific working process will not be described herein.
  • the potential V Q2 (N-1) of the second control node Q 2 (N-1) of the previous stage gate driving unit N-1 is turned on by the turned-on fifth transistor T5 or the turned-on fourth transistor T4. Pulling down to the low level V L , that is, the second control node Q 2 (N-1) of the previous stage gate driving unit N-1 is kept at the low level V L , and the previous stage gate driving unit N-1 is Maintaining the low level of the corresponding gate signal output terminal by the second low level maintaining module 16 while the first low level maintaining module 14 is at the low level of the second control node Q 2 (N-1) Under control, it is in the off state.
  • the operation process is similar to the process in which the gate driving unit shown in FIG. 6 operates according to the operation timing chart shown in FIG. The working process is not described here.
  • the gates of the eighteenth transistor T18 and the nineteenth transistor T19 of the current stage gate driving unit N are connected to the second control node Q 2(N-1) of the previous stage gate driving unit N-1, Under the low level control of the second control node Q 2 (N-1) of the previous stage gate driving unit N-1, the eighteenth transistor T18 and the nineteenth transistor T19 of the current stage gate driving unit N are The off state, so the second low level maintaining module 16 of the current stage gate driving unit N is in an off state.
  • the potential V Q2 (N) of the second control node Q 2 (N) of the current stage gate driving unit N is maintained at a high level state, so that the sixth transistor T6 and the seventh transistor T7 are turned on.
  • a state in which the gate signal V o(N) of the corresponding gate signal output terminal is maintained at a low level that is, the current stage gate driving unit N maintains a low level of the gate signal output terminal by using the first low level maintaining module 14
  • the second low level maintenance module 16 is in an off state.
  • the third clock signal ECXK is at a low level
  • the fourth clock signal ECK is at a high level
  • the previous stage gate driving unit N-1 is corresponding to the second low level maintaining module 16
  • the low level of the gate signal output terminal is maintained, and the current stage gate drive unit N maintains the low level of the gate signal output terminal by the first low level sustaining module 14.
  • the third clock signal ECXK may also be a high level
  • the fourth clock signal ECK may also be a low level
  • the previous stage gate driving unit N-1 is using its first low
  • the level maintaining module 14 maintains the low level of the corresponding gate signal output terminal
  • the pole driving unit N maintains the low level of the gate signal output end by using the second low level maintaining module 16.
  • FIG. 13 is an operational timing chart of another embodiment of the gate driving unit shown in FIG.
  • the high level of the first pulse signal V i(N) overlaps with the high level of the first clock signal CK A(N) by 1/4 clock cycle, the third clock signal ECXK is high level, and the voltage magnitude is V H2 .
  • ECK fourth clock signal is low, the magnitude of the voltage V L, in this case, the gate driving unit before a gate driving unit N-1 during operation is shown in FIG. 6 shown in FIG. 7
  • the process of working sequence diagrams is similar, and the specific work process is not described here.
  • the fifth transistor T5 and the eighth transistor T8 of the previous stage gate driving unit N-1 are turned off, and the fourth transistor T4 is controlled at a high level of the first clock signal CK A(N-1)
  • the lower period is turned on, so that the potential V Q2 (N-1) of the second control node Q 2 (N-1) of the previous stage gate driving unit N-1 is maintained at a high level V H2 , that is, the previous stage
  • the gate driving unit N-1 maintains the low level of the corresponding gate signal output terminal by the first low level maintaining module 14, and the second low level maintaining module 16 thereof is in the off state.
  • the operation process is similar to the process in which the gate driving unit shown in FIG. 6 operates according to the operation timing chart shown in FIG. The working process is not described here.
  • the potential V Q2 (N) of the second control node Q 2 (N) of the current stage gate driving unit N is pulled down to the low level V L through the turned-on fifth transistor T5 or the turned-on fourth transistor T4. , that is, the second control node Q 2 (N) of the current stage gate driving unit N is kept at a low level V L , and the sixth transistor T6 and the seventh transistor T7 are in an off state, and thus the first low level maintaining module 14 is in the off state.
  • the eighteenth transistor T18 and the nineteenth transistor T19 of the current stage gate driving unit N are at the high level control of the second control node Q 2 (N-1) of the previous stage gate driving unit.
  • the second low level maintaining module 16 of the current stage gate driving unit N is in an on state, thereby maintaining the gate signal V o(N) of the corresponding gate signal output terminal at a low level, that is, The current stage gate driving unit N maintains the low level of the gate signal output terminal by the second low level maintaining module 16 while the first low level maintaining module 14 is in the off state.
  • the third clock signal ECXK is at a high level
  • the fourth clock signal ECK is at a low level
  • the previous stage gate driving unit N-1 is maintained by using the first low level thereof.
  • the module 14 maintains the low level of the corresponding gate signal output terminal
  • the current stage gate drive unit N maintains the low level of the gate signal output terminal by the second low level sustaining module 16.
  • the third clock signal ECXK may also be a low level
  • the fourth clock signal ECK may also be a high level, at which time the previous stage gate driving unit N-1 is using its second low.
  • the level maintaining module 16 maintains the low level of the corresponding gate signal output end, and the current stage gate driving unit N maintains the low level of the gate signal output end by using the first low level maintaining module 14 , and the specific analysis process may be Referring to the above description, this will not be repeated.
  • the adjacent two-stage gate driving units share one control module.
  • the current-stage gate driving unit N and the previous-stage gate driving unit N-1 share one control module, which is advantageous for reducing The number of transistors in a small circuit simplifies the circuit design and helps to further reduce the total area of the circuit.
  • the fifteenth transistor T15 may be further added to the control module of the gate driving unit shown in FIG. 11.
  • the connection manner of the fifteenth transistor T15 may refer to the fifteenth transistor shown in FIG.
  • the connection method of T15 is not described here.
  • the main difference from the gate driving unit shown in FIG. 2 is that the second electrode of the third transistor T3 is connected to the gate of the first transistor T1.
  • the first control signal input by the gate of the third transistor T3 is the second clock signal CK B , wherein the high level of the first clock signal CK A and the second clock signal CK The high level of B overlaps by 1/4 clock cycle, and the second clock signal CK B is also the first clock signal of the previous stage gate driving unit.
  • Fig. 15 is a timing chart showing the operation of the gate driving unit shown in Fig. 14.
  • a first pulse signal Vi is high level
  • the second clock signal CKB is high
  • the first transistor T1 and the third transistor T3 are in the ON state
  • the first pulse V i is turned by
  • the third transistor T3 charges the first control node Q 1 such that the potential V Q1 of the first control node Q 1 rises to a high level, thereby causing the second transistor T2 to be turned on.
  • the first clock signal CK A is at a low level, so the gate signal V o of the gate signal output terminal is pulled low to a low level by the turned-on second transistor T2.
  • the fifth transistor T5 and the eighth transistor T8 is turned on, and thus the potential of the second control node Q V Q2 2 is pulled down to a low level, so that the first The six transistor T6 and the seventh transistor T7 are turned off.
  • the first clock signal CK A is at a high level
  • the second clock signal CK B and the first pulse signal V i are at a high level during the first half of the time, at which time the potential V Q1 of the first control node Q 1 Keeping high level, so that the second transistor T2 is kept on, the potential of the gate signal output terminal rises rapidly, and the first clock signal CK A charges the gate signal output terminal, firstly under the influence of the capacitor bootstrap effect
  • the potential V Q1 of the control node Q 1 is also raised so that the gate signal output terminal can be quickly charged to a high level, thereby outputting a high level gate signal V o .
  • the second clock signal CK B and the first pulse signal V i are at a low level, at which time the first transistor T1 and the third transistor T3 are turned off, but due to the potential V Q1 of the first control node Q 1 It is high level, so the second transistor T2 remains turned on, so that the gate signal output terminal outputs a high level gate signal V o .
  • the first clock signal CK A falls from the high level V H1 to the low level V L1 , and since the potential V Q1 of the first control node Q 1 is still at the high level, the second transistor T2 remains turned on. The state, therefore, the gate signal output is discharged through the turned-on second transistor T2, so that the potential of the gate signal V o outputted from the gate signal output can be quickly lowered to a low level. Due to the capacitor bootstrap effect, the potential V Q1 of the first control node Q 1 drops to V H1 -V TH1 .
  • the second clock signal CKB rises from a low level to a high level, and the third transistor T3 is turned on, thereby pulling down the potential V Q1 of the first control node Q 1 to a low level of the first pulse signal V i .
  • the fifth transistor T5 and the eighth transistor T8 are turned off. Since the first clock signal CK A is still at the low level V L1 , the fourth transistor T4 is still in the off state, so that the potential V Q2 of the second control node Q 2 is maintained at the low level V L .
  • the first clock signal CK A rises from the low level V L1 to the high level V H1 , and the second capacitor C2 couples the high voltage to the gate of the fourth transistor T4 such that the fourth transistor T4 is turned on.
  • the high voltage source V DD charges the second control node Q 2 through the turned-on fourth transistor T4 such that the potential V Q2 of the second control node Q 2 rises to V H2 -V TH4 , where V TH4 is the fourth transistor T4
  • V TH4 is the fourth transistor T4
  • the threshold voltage at this time, the sixth transistor T6 and the seventh transistor T7 are turned on.
  • the potential V Q1 of the first control node Q 1 is pulled down to the low level V L by the turned-on sixth transistor T6.
  • the potential of the second electrode of the second transistor T2 is pulled down to the low level V L , that is, the gate signal V o outputted from the gate signal output terminal is pulled down to the low level V L .
  • the third transistor T3 is driven by the second clock signal CK B to further maintain the potential V Q1 of the first control node Q 1 at a low level.
  • the gate driving unit does not require the latter unit to provide a feedback signal.
  • control module 13 in the gate driving unit shown in FIG. 14 can be as shown in FIG. 5, FIG. 6, FIG. 9, FIG. 10 or The control module shown in FIG. 11 and also the second low level maintenance module shown in FIG. 6, FIG. 9, FIG. 10 or FIG.
  • the present invention also provides an embodiment of a gate driving circuit, the gate driving circuit includes M cascaded gate driving units, and M is an integer greater than 1, wherein the gate driving unit may be in any of the above embodiments.
  • the pulse signal input end of the Nth stage gate driving unit is connected to the gate signal output end of the N-1th stage gate driving unit, where N is an integer, and the value ranges from 1 ⁇ N ⁇ M.
  • the pulse signal input end of the Nth stage gate driving unit may also be connected to the gate signal output end of the N-2th stage gate driving unit, where N is an integer, and the value range is 2 ⁇ N ⁇ M.
  • each stage of the gate driving unit may be the same, for example, both may be the gate driving unit shown in FIG. 2, or both are the gates shown in FIG.
  • the driving units are either the gate driving units shown in FIG. 6, or both are the gate driving units shown in FIG. 9, or both are the gate driving units shown in FIG. 10, or both are as shown in FIG.
  • the gate drive units are either gate drive units as shown in FIG.
  • the structures of the gate driving units of different stages may also be different or partially the same.
  • Figure 19 is an operational timing diagram of an embodiment of the gate drive circuit of Figure 16.
  • the gate driving circuit comprises M cascaded gate driving units, wherein M is an integer greater than one.
  • a gate signal output of each gate drive unit is used to provide a scan signal to a scan line.
  • the pulse signal input end of the Nth stage gate driving unit is connected to the gate signal output end of the N-1th stage gate driving unit, where N is an integer, and the value ranges from 1 ⁇ N ⁇ M.
  • the pulse signal input terminal of the Nth stage gate driving unit can also Connected to the gate signal output of the N-2th gate drive unit, where N is an integer and ranges from 2 ⁇ N ⁇ M.
  • the gate driving circuit further includes a plurality of clock signal lines, wherein the four clock signal lines CK 1 CK CK 4 are shown , and the high level signal line V DD and the low level signal line are further included. V SS and the start signal line ST.
  • the start signal line ST is a pulse signal.
  • the M cascaded gate drive units are divided into two parts, the first to the M-4th gate drive units are the main drive units, and the M-3th to the Mth stage gate drive units are the additional stage gate drive units. .
  • the gate driving unit of each of the first to M-4th gate driving units may be the gate driving unit shown in FIG. 2 or may be the gate driving unit shown in FIG. 5.
  • the pulse signal input terminal (V i ) of the jth stage gate driving unit is connected to the gate signal output terminal of the J-2th stage gate driving unit, wherein J is an integer and ranges from 2 ⁇ J ⁇ M-4.
  • the pulse signal input terminals of the first-stage gate driving unit and the second-pole gate driving unit are connected to the enable signal line ST to obtain the first pulse signal V i through the enable signal line ST.
  • a clock signal input terminal (CK A ) of each gate driving unit is connected to one clock signal line, and a first pull-down control terminal (V c ) is connected to a gate signal output end of the K+3th stage gate driving unit.
  • the first control signal V c of each gate driving unit is a gate signal outputted by the gate signal output end of the K+3th stage gate driving unit, where K is an integer, and the value ranges from 1 ⁇ K ⁇ M-4.
  • the first input signal terminal of each gate driving unit is connected to the high level signal line V DD , and the low level node Q 3 is connected to the low level signal line V SS .
  • the pulse signal input end of the Jth stage gate driving unit may also be connected to the gate of the J-1th stage gate driving unit.
  • the pole signal output terminal where J is an integer, and the value ranges from 1 ⁇ J ⁇ M-4.
  • the gate driving unit of each of the M-3th to Mth stage gate driving units may be the gate driving unit shown in FIG. 14.
  • the pulse signal input end of each stage of the gate driving unit is connected to the gate signal output end of the upper stage gate driving unit, and the clock signal of the same gate driving unit
  • the input terminal (CK A ) and the first pull-down control terminal (CK B ) are connected to two different clock signal lines.
  • Figure 19 is an operational timing diagram of an embodiment of the gate drive circuit of Figure 17.
  • the gate driving circuit comprises M cascaded gate driving units, wherein M is an integer greater than one.
  • a gate signal output of each gate drive unit is used to provide a scan signal to a scan line.
  • the pulse signal input end of the Nth stage gate driving unit is connected to the gate signal output end of the N-1th stage gate driving unit, where N is an integer, and the value ranges from 1 ⁇ N ⁇ M.
  • the pulse signal input end of the Nth stage gate driving unit may be connected to the gate signal output end of the N-2th stage gate driving unit, where N is an integer, and the value ranges from 2 ⁇ N ⁇ M.
  • the gate driving circuit further includes a plurality of clock signal lines, and four clock signal lines CK 1 to CK 4 and two two-phase low-frequency clock signal lines EXCK and ECK are shown, and the high-definition
  • the start signal line ST is a pulse signal.
  • the M cascaded gate drive units are divided into two parts, the first to the M-4th gate drive units are the main drive units, and the M-3th to the Mth stage gate drive units are the additional stage gate drive units. .
  • the gate driving unit of each of the first to the M-4th gate driving units may be the gate driving unit shown in any of the embodiments of FIG. 6, FIG. 9, or FIG.
  • the pulse signal input terminal (V i ), the clock signal input terminal (CK A ), and the first pull-down control terminal (V c ) of the driving unit are connected in the same manner as the gate driving circuit shown in FIG. 16 . This will not be described one by one.
  • the first electrode of the fourth transistor T4 in the gate driving units of the first to M-4th stages is connected to the clock signal line ECK
  • the gate of the thirteenth transistor T13 is connected to the clock signal line EXCK
  • the ninth transistor T9 The first pole is connected to the clock signal line EXCK
  • the gate of the fourteenth transistor T14 is connected to the clock signal line ECK.
  • each of the gate driving units of the M-3th to Mth stage gate driving units is based on the gate driving unit shown in FIG.
  • the gate driving unit obtained by the transistors T9, T10, T11 and T12 in the gate driving unit shown in FIG. 6, the connection manner of the added transistors T9, T10, T11 and T12 is the same as that of the gate driving unit shown in FIG.
  • the connection is the same, in which the first pole of the transistor T4 is connected to the clock signal line ECK, and the first pole of the transistor T9 is connected to the clock signal line EXCK.
  • each of the gate drive units of the M-3th to Mth stage gate drive units is also The transistors T9, T10, T11, T12, T13 and T14 in the gate driving unit shown in FIG. 9 may be added on the basis of the gate driving unit shown in FIG. 14, and the added transistors T9, T10, T11, T12, T13 and T14 are connected in the same manner as the gate driving unit shown in FIG. 9, wherein the first electrode of the transistor T4 is connected to the clock signal line ECK, the gate of the transistor T13 is connected to the clock signal line EXCK, and the transistor The first pole of T9 is connected to the clock signal line EXCK, and the gate of the transistor T14 is connected to the clock signal line ECK.
  • Each of the gate driving units of the M-3th to Mth stage gate driving units may also be based on the gate driving unit shown in FIG. 14 and added to the gate driving unit shown in FIG.
  • Transistors T9, T10, T11, T12, T16, and T17, the added transistors T9, T10, T11, T12, T16, and T17 are connected in the same manner as the gate driving unit shown in FIG.
  • FIG. 19 is an operational timing diagram of an embodiment of the gate drive circuit of Figure 18.
  • the main difference from the gate driving circuit shown in FIG. 17 is that the gate driving units of the second to M-4 stages in the present embodiment adopt the structure of the gate driving unit shown in FIG. 11, that is, in the second to M- In the 4-stage gate driving unit, the gates of the transistors T18 and T19 of the second low-level sustaining module 16 of the H-th stage gate driving unit are connected to the second control node Q 2 of the H-1th-level gate driving unit.
  • H is an integer and ranges from 1 ⁇ H ⁇ M-4.
  • the connection manner of the first-stage gate driving unit and the M-3th-th M-th gate driving unit of the present embodiment is similar to that of the embodiment shown in FIG. 17, and details are not described herein.
  • the present invention also provides an embodiment of a display device
  • the display device is a liquid crystal display device, comprising a plurality of scan lines G 1 ⁇ G N, and a plurality of scan lines G 1 ⁇ G N provides a gate signal Gate drive circuit 21.
  • the gate drive circuit 21 is the gate drive circuit described in any of the above embodiments.
  • the control terminal of the low level maintaining module can be pulled down to a low level, thereby reducing the leakage of the low level maintaining module and improving the operating speed of the circuit.
  • FIG. 21 shows a signal waveform of a control terminal of a low-level maintenance module of a gate driving unit of the related art and a control terminal of a low-level maintenance module of the gate driving unit of the embodiment of the present invention ( That is, the signal waveform of the third pull-down control terminal, that is, the second control node.
  • the signal waveform 211 is a signal waveform of the control terminal of the conventional low-level maintenance module
  • the signal waveform 212 is a signal waveform of the control terminal of the low-level maintenance module (that is, a signal waveform of the second control node) of the embodiment of the present invention.
  • the driving phase ie, at the time t1 to t4, corresponding to the elliptical dotted line portion in FIG. 21
  • the power of the control terminal of the low-level maintenance module of the present invention is compared with the conventional low-level maintenance module.
  • the flat can be fully pulled down to V L , which can effectively reduce the leakage of the low level maintenance module.

Abstract

一种栅极驱动电路（21）及显示装置，所述栅极驱动电路（21）中，通过设置控制模块（13），用于在输出模块（12）输出栅极选通信号之前以及输出栅极选通信号期间将第二控制节点（Q2）的电位下拉至低电平（VL），由此可将第一低电平维持模块（14）的第二下拉控制端在输出模块（12）输出栅极选通信号之前以及输出栅极选通信号期间下拉至低电平（V L），使得第一低电平维持模块（14）处于截止状态。通过上述方式，能够减小第一低电平维持模块（14）的漏电，从而有利于减小栅极信号（Vo、Vo( N-1)、Vo( N )）输出的延迟，提高工作频率。

Description

栅极驱动电路及显示装置 【技术领域】
本发明涉及显示技术领域，特别是涉及一种栅极驱动电路及显示装置。
【背景技术】
平板显示器(FPD，Flat-Panel-Display)具有图像清晰度高、画面无闪烁、节能环保、轻薄等优点，为目前主流的显示器。近年来，平板显示器正向高帧频、高分辨率、更窄边框的方向发展。
在平板显示器的驱动方式中，例如对于平板液晶显示器，传统的驱动方式是采用集成电路(IC)的方式，将外围驱动电路通过COG(Chip On Glass，芯片绑定在玻璃基板上)等封装工艺连接到液晶面板上，这种方式不仅不利于显示器的轻薄化，且成本较高，外围驱动电路的引脚数量较多时还会影响显示器的机械和电学可靠性，尤其是对于高分辨率显示器，这种缺陷更加明显。集成显示驱动电路的出现很好地解决了上述问题。集成显示驱动电路是指将显示器的栅极驱动电路和数据驱动电路等外围驱动电路以薄膜晶体管(TFT，Thin Film Transistor)的形式和像素薄膜晶体管一起制作于液晶面板上。与传统的COG驱动方式相比，能够减少驱动芯片的数量及其压封程序，有利于降低成本，且能够使得显示器外围更加纤薄，模组更紧凑，有利于提高显示器的机械和电学的可靠性。
集成栅极驱动电路(Gate Driver on Array，GOA)得到了非常广泛的研究，但是随着显示器向着高帧频、高分辨率、更窄边框的方向发展，对集成栅极驱动电路的工作频率、电路占用面积也提出了更高的要求。在集成栅极驱动电路中，通常需要低电平维持晶体管来对栅极驱动电路的输出信号的低电平进行维持。然而在栅极驱动电路的驱动阶段，现有的电路设计中的低电平维持晶体管的控制极电位无法完全下拉至低电 平，导致了漏电的存在。而低电平维持晶体管的漏电，增大了栅极驱动电路的输出脉冲的上升、下降延迟，从而限制了电路的工作频率的提高。
【发明内容】
本发明主要解决的技术问题是提供一种栅极驱动电路及显示装置，能够减小低电平维持模块的漏电，从而有利于减小栅极信号输出的延迟，提高工作频率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种用于驱动液晶面板的栅极驱动电路，其中，包括M个级联的栅极驱动单元，其中M为大于1的整数，每个所述栅极驱动单元包括输入模块、输出模块、控制模块以及第一低电平维持模块；所述输入模块包括用于输入第一脉冲信号的脉冲信号输入端、用于输入第一控制信号的第一下拉控制端和耦合至第一控制节点的控制信号输出端，所述输入模块用于根据所述第一脉冲信号和所述第一控制信号控制所述第一控制节点的电位；所述输出模块包括耦合至所述第一控制节点的驱动控制端、用于输入第一时钟信号的时钟信号输入端以及栅极信号输出端，所述输出模块在所述第一控制节点的电位的控制下，通过所述栅极信号输出端输出栅极选通信号或栅极截止信号；所述控制模块包括用于输入所述第一时钟信号的时钟信号输入端、用于输入第一输入信号的第一输入信号端、耦合至第二控制节点的第二下拉控制端、耦合至所述第一控制节点的第一控制端以及耦合至低电平节点的第一下拉端，所述低电平节点用于输入低电平信号，所述控制模块至少用于在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间在所述第一控制节点的高电平控制下将所述第二控制节点的电位下拉至低电平；所述第一低电平维持模块包括耦合至所述第二控制节点的第三下拉控制端、耦合至所述第一控制节点的第一端、耦合至所述输出模块的栅极信号输出端的第二端以及耦合至所述低电平节点的第三端，所述第一低电平维持模块在所述第二控制节点的低电平控制下至少在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间处于截止状态；其中第N级栅极驱动单元的脉冲信号输入端连接至第N-1级栅极驱动单元的栅极信号输出端，其中N为整数， 取值范围为1＜N≤M，或者或第N级栅极驱动单元的脉冲信号输入端连接至第N-2级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为2＜N≤M。
其中，所述输入模块包括第一晶体管和第三晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极连接，用于输入所述第一脉冲信号，所述第一晶体管的第二极和所述第三晶体管的第一极连接至所述第一控制节点，所述第三晶体管的栅极用于输入所述第一控制信号，所述第三晶体管的第二极连接至所述低电平节点或连接至所述第一晶体管的第一极，所述第一控制信号为第二脉冲信号或第二时钟信号，所述第一时钟信号的高电平和所述第二时钟信号的高电平重叠1/4个时钟周期；所述输出模块包括第二晶体管，所述第二晶体管的栅极连接至所述第一控制节点，所述第二晶体管的第一极用于输入所述第一时钟信号，所述第二晶体管的第二极为所述栅极信号输出端；所述控制模块包括第四晶体管、第五晶体管、第八晶体管以及第二电容，所述第四晶体管的栅极与所述第八晶体管的第一极以及所述第二电容的一端相连，所述第二电容的另一端用于输入所述第一时钟信号，所述第八晶体管的栅极和所述第五晶体管的栅极连接至所述第一控制节点，所述第八晶体管的第二极和第五晶体管的第二极连接至所述低电平节点，所述第五晶体管的第一极和所述第四晶体管的第二极连接至所述第二控制节点，所述第四晶体管的第一极用于输入所述第一输入信号；所述第一低电平维持模块包括第六晶体管和第七晶体管，所述第六晶体管的栅极和所述第七晶体管的栅极连接至所述第二控制节点，所述第六晶体管的第一极连接至所述第一控制节点，所述第六晶体管的第二极和所述第七晶体管的第二极连接至所述低电平节点，所述第七晶体管的第一极连接至所述第二晶体管的第二极。
其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第 一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
其中，所述控制模块还包括第十五晶体管，所述第十五晶体管的栅极连接至所述第一晶体管的栅极，所述第十五晶体管的第一极连接至所述第二控制节点，所述第十五晶体管的第二极连接至所述低电平节点。
其中，还包括第二低电平维持模块，所述控制模块还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一控制节点；所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号。
其中，所述控制模块还包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极用于输入所述第三时钟信号，所述第十三晶体管的第一极连接至所述第四晶体管的第一极，所述第十三晶体管的第二极连接至所述第二控制节点，所述第十四晶体管的栅极用于输入所述第四时钟信号，所述第十四晶体管的第一极连接至所述第九晶体管的第一极，所述第十四晶体管的第二极连接至所述第九晶体管的第二极。
其中，所述控制单元还包括第十六晶体管和第十七晶体管，所述第十六晶体管的栅极与所述第十七晶体管的栅极以及所述第一晶体管的栅极连接，所述第十六晶体管的第一极与所述第九晶体管的第二极连接，所述第十六晶体管的第二极和所述第十七晶体管的第二极连接至所述低电平节点，所述第十七晶体管的第一极连接至所述第二控制节点。
其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述 第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
其中，每个所述栅极驱动单元还包括第二低电平维持模块，所述第二低电平维持模块包括第十八晶体管和第十九晶体管；其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；当前级栅极驱动单元的所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号。
其中，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元进一步还包括第二低电平维持模块，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述控制模块进一步还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一控制节点；所述第四晶体管的第一极输入的所述第一输入信号 为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号；其中第1级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；所述第M-3至第M级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至第一晶体管的第一极以输入第一脉冲信号且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号；第2至第M-4级栅极驱动单元中的每一级栅极驱动单元进一步还包括第十八晶体管和第十九晶体管，其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；当前级栅极驱动单元的所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号；其中第2至第M-4级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种一种显示装置，包括多条扫描线和为所述扫描线提供栅极信号的栅极驱动电路，其中所述栅极驱动电路包括M个级联的栅极驱动单元，其中M为大于1的整数，每个所述栅极驱动单元包括输入模块、输出模块、控制模块以及第一低电平维持模块；所述输入模块包括用于输入第一脉冲信号的脉冲信号输入端、用于输入第一控制信号的第一下拉控制端和耦合至第一控制节点的控制信号输出端，所述输入模块用于根据所述第一脉冲信号和所述第一控制信号控制所述第一控制节点的电位；所述输出模块包括耦合至所述第一控制节点的驱动控制端、用于输入第一时钟信号的时钟信号输入端以及栅极信号输出端，所述输出模块在所述第一控 制节点的电位的控制下，通过所述栅极信号输出端输出栅极选通信号或栅极截止信号；所述控制模块包括用于输入所述第一时钟信号的时钟信号输入端、用于输入第一输入信号的第一输入信号端、耦合至第二控制节点的第二下拉控制端、耦合至所述第一控制节点的第一控制端以及耦合至低电平节点的第一下拉端，所述低电平节点用于输入低电平信号，所述控制模块至少用于在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间在所述第一控制节点的高电平控制下将所述第二控制节点的电位下拉至低电平；所述第一低电平维持模块包括耦合至所述第二控制节点的第三下拉控制端、耦合至所述第一控制节点的第一端、耦合至所述输出模块的栅极信号输出端的第二端以及耦合至所述低电平节点的第三端，所述第一低电平维持模块在所述第二控制节点的低电平控制下至少在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间处于截止状态；其中第N级栅极驱动单元的脉冲信号输入端连接至第N-1级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为1＜N≤M，或者或第N级栅极驱动单元的脉冲信号输入端连接至第N-2级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为2＜N≤M。
其中，所述输入模块包括第一晶体管和第三晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极连接，用于输入所述第一脉冲信号，所述第一晶体管的第二极和所述第三晶体管的第一极连接至所述第一控制节点，所述第三晶体管的栅极用于输入所述第一控制信号，所述第三晶体管的第二极连接至所述低电平节点或连接至所述第一晶体管的第一极，所述第一控制信号为第二脉冲信号或第二时钟信号，所述第一时钟信号的高电平和所述第二时钟信号的高电平重叠1/4个时钟周期；所述输出模块包括第二晶体管，所述第二晶体管的栅极连接至所述第一控制节点，所述第二晶体管的第一极用于输入所述第一时钟信号，所述第二晶体管的第二极为所述栅极信号输出端；所述控制模块包括第四晶体管、第五晶体管、第八晶体管以及第二电容，所述第四晶体管的栅极与所述第八晶体管的第一极以及所述第二电容的一端相连，所述第 二电容的另一端用于输入所述第一时钟信号，所述第八晶体管的栅极和所述第五晶体管的栅极连接至所述第一控制节点，所述第八晶体管的第二极和第五晶体管的第二极连接至所述低电平节点，所述第五晶体管的第一极和所述第四晶体管的第二极连接至所述第二控制节点，所述第四晶体管的第一极用于输入所述第一输入信号；所述第一低电平维持模块包括第六晶体管和第七晶体管，所述第六晶体管的栅极和所述第七晶体管的栅极连接至所述第二控制节点，所述第六晶体管的第一极连接至所述第一控制节点，所述第六晶体管的第二极和所述第七晶体管的第二极连接至所述低电平节点，所述第七晶体管的第一极连接至所述第二晶体管的第二极。
其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
其中，所述控制模块还包括第十五晶体管，所述第十五晶体管的栅极连接至所述第一晶体管的栅极，所述第十五晶体管的第一极连接至所述第二控制节点，所述第十五晶体管的第二极连接至所述低电平节点。
其中，每个所述栅极驱动单元还包括第二低电平维持模块，所述控制模块还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一 控制节点；所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号。
其中，所述控制模块还包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极用于输入所述第三时钟信号，所述第十三晶体管的第一极连接至所述第四晶体管的第一极，所述第十三晶体管的第二极连接至所述第二控制节点，所述第十四晶体管的栅极用于输入所述第四时钟信号，所述第十四晶体管的第一极连接至所述第九晶体管的第一极，所述第十四晶体管的第二极连接至所述第九晶体管的第二极。
其中，所述控制单元还包括第十六晶体管和第十七晶体管，所述第十六晶体管的栅极与所述第十七晶体管的栅极以及所述第一晶体管的栅极连接，所述第十六晶体管的第一极与所述第九晶体管的第二极连接，所述第十六晶体管的第二极和所述第十七晶体管的第二极连接至所述低电平节点，所述第十七晶体管的第一极连接至所述第二控制节点。
其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
其中，每个所述栅极驱动单元还包括第二低电平维持模块，所述第二低电平维持模块包括第十八晶体管和第十九晶体管；其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；当前级栅极驱动单元的所述第四晶体管的第一极输入的所述第一 输入信号为第四时钟信号。
其中，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元进一步还包括第二低电平维持模块，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述控制模块进一步还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一控制节点；所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号；其中第1级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；所述第M-3至第M级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至第一晶体管的第一极以输入第一脉冲信号且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号；第2至第M-4级栅极驱动单元中的每一级栅极驱动单元进一步还包括第十八晶体管和第十九晶体管，其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；当前级栅极驱动单元的所 述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号；其中第2至第M-4级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号。
本发明的有益效果是：区别于现有技术的情况，本发明通过设置控制模块，用于在输出模块输出栅极选通信号之前以及输出栅极选通信号期间将第二控制节点的电位下拉至低电平，由此可将低电平维持模块的第三下拉控制端在输出模块输出栅极选通信号之前以及输出栅极选通信号期间下拉至低电平，使得低电平维持模块处于截止状态，从而可减少低电平维持模块的漏电，有利于减小输出模块输出栅极选通信号的输出延迟时间。
【附图说明】
图1是本发明栅极驱动单元一实施方式的结构示意图；
图2是本发明栅极驱动单元一实施方式的具体电路结构示意图；
图3是图2所示的栅极驱动单元一实施方式的工作时序图；
图4是图2所示的栅极驱动单元另一实施方式的工作时序图；
图5是本发明栅极驱动单元另一实施方式的具体电路结构示意图；
图6是本发明栅极驱动单元又一实施方式的具体电路结构示意图；
图7是图6所示的栅极驱动单元一实施方式的工作时序图；
图8是图6所示的栅极驱动单元另一实施方式的工作时序图；
图9是本发明栅极驱动单元又一实施方式的具体电路结构示意图；
图10是本发明栅极驱动单元又一实施方式的具体电路结构示意图；
图11是本发明栅极驱动单元又一实施方式的具体电路结构示意图；
图12是图11所示的栅极驱动单元一实施方式的工作时序图；
图13是图11所示的栅极驱动单元另一实施方式的工作时序图；
图14是本发明栅极驱动单元又一实施方式的具体电路结构示意图；
图15是图14所示的栅极驱动单元一实施方式的工作时序图；
图16是本发明栅极驱动电路一实施方式的结构示意图；
图17是本发明栅极驱动电路另一实施方式的结构示意图；
图18是本发明栅极驱动电路又一实施方式的结构示意图；
图19是本发明栅极驱动电路一实施方式的工作时序图；
图20是本发明显示装置一实施方式的结构示意图；
图21是本发明的低电平维持模块的第三下拉控制端的信号波形和传统的栅极驱动单元中的低电平维持模块的控制端的信号波形示意图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细描述。
参阅图1，本发明用于驱动液晶面板的栅极驱动单元一实施方式中，一个栅极驱动单元用于对液晶面板的一条扫描线输出扫描驱动信号，包括输入模块11、输出模块12、控制模块13以及第一低电平维持模块14。
其中，输入模块11包括用于输入第一脉冲信号Vi的脉冲信号输入端、用于输入第一控制信号Vc的第一下拉控制端和耦合至第一控制节点Q1的控制信号输出端。输入模块用于根据第一脉冲信号Vi和第一控制信号Vc控制第一控制节点Q1的电位。
输出模块12包括耦合至第一控制节点Q1的驱动控制端、用于输入第一时钟信号CKA的时钟信号输入端以及栅极信号输出端。其中栅极信号输出端用于与液晶面板的扫描线连接。输出模块12在第一控制节点Q1的电位的控制下，通过栅极信号输出端输出栅极信号Vo，其中栅极信号Vo包括栅极选通信号和栅极截止信号。栅极选通信号是指使与扫描线连接的像素薄膜晶体管导通的高电平扫描信号，栅极截止信号是指使与扫描线连接的像素薄膜晶体管截止的低电平扫描信号。
控制模块13包括用于输入第一时钟信号CKA的时钟信号输入端、用于输入第一输入信号Vii的第一输入信号端、耦合至第二控制节点Q2的第二下拉控制端、耦合至第一控制节点Q1的第一控制端以及耦合至低电平节点Q3的第一下拉端。其中，控制模块13至少用于在输出模块12输出栅极选通信号之前以及输出栅极选通信号期间在第一控制节点Q1的高电平控制下，将第二控制节点Q2的电位下拉至低电平。
进一步地，控制模块13还用于在输出模块12输出栅极选通信号之后在第一控制节点Q1的低电平控制下将第二控制节点的电位上拉至高电平。
第一低电平维持模块14包括耦合至第二控制节点Q2的第三下拉控制端、耦合至第一控制节点Q1的第一端、耦合至输出模块12的栅极驱动信号输出端的第二端以及耦合至低电平节点Q3的第三端。第一低电平维持模块14在第二控制节点Q2的低电平控制下至少在输出模块12输出栅极选通信号之前以及栅极选通信号期间处于截止状态。
进一步地，第一低电平维持模块14还用于在输出模块12输出栅极选通信号之后在第二控制节点Q2的高电平控制下处于导通状态，以将输出模块12的栅极信号输出端的电位下拉至低电平。
本实施方式中，第一低电平维持模块14的导通和截止由第三下拉控制端的电位决定，第三下拉控制端的电位为高电平时第一低电平维持模块14导通，以使得输出模块12的栅极信号输出端耦合至低电平节点Q3，进而使得输出模块12的栅极信号输出端维持低电平状态；当第三下拉控制端的电位为低电平时第一低电平维持模块14截止。通过设置控制模块13控制第二控制节点Q2的电位以控制第一低电平维持模块14的第三下拉控制端的电位，在输出模块12输出栅极选通信号之前以及输出栅极选通信号期间将第二控制节点Q2的电位下拉至低电平，由此可将第一低电平维持模块14的第三下拉控制端在输出模块12输出栅极选通信号之前以及输出栅极选通信号期间下拉至低电平，使得第一低电平维持模块14处于截止状态，从而可减小第一低电平维持模块14的漏电，避免了第一低电平维持模块14因漏电导通而将输出模块12的栅极信号输出端的电位拉低，从而有利于减小输出模块12输出栅极选通信号的输出延迟，提高电路的工作效率。此外，通过使控制模块13在输出模块12输出栅极选通信号之后控制第二控制节点Q2的电位上拉至高电平，从而导通第一低电平维持模块14，从而将输出模块12的栅极信号输出端的电位下拉至低电平，由此维持输出模块12的输出端的电位为低电平，从而可避免与栅极信号输出端连接的像素薄膜晶体管导通，防 止信号写入错误。
下面将结合具体的电路结构对本发明实施方式的栅极驱动单元进行说明。
实施例一：
参阅图2，在本发明栅极驱动单元的一具体实施方式中，输入模块11包括第一晶体管T1和第三晶体管T3。其中，第一晶体管T1的栅极和第一极短接作为输入模块11的脉冲信号输入端，用于输入第一脉冲信号Vi，第一晶体管T1的第二极和第三晶体管T3的第一极连接至第一控制节点Q1，第三晶体管T3的第二极连接至低电平节点Q3，第三晶体管T3的栅极作为输入模块11的第一下拉控制端，用于输入第一控制信号Vc。
输出模块12包括第二晶体管T2，进一步还包括第一电容C1。其中，第二晶体管T2的栅极作为输出模块12的驱动控制端，连接至第一控制节点Q1。第二晶体管T2的第一极作为输出模块12的时钟信号输入端，用于输入第一时钟信号CKA。第二晶体管T2的第二极为输出模块12的栅极信号输出端。第一电容C1的两端分别连接至第一控制节点Q1和第二晶体管T2的第二极。
控制模块13包括第四晶体管T4、第五晶体管T5、第八晶体管T8以及第二电容C2。其中，第四晶体管T4的栅极与第八晶体管T8的第一极以及第二电容C2的一端相连。第二电容C2的另一端作为控制模块13的时钟信号输入端，用于输入第一时钟信号CKA。第四晶体管T4的第一极作为控制模块13的第一输入信号端用于输入第一输入信号。第四晶体管T4的第二极和第五晶体管T5的第二极相连，并作为控制模块13的第二下拉控制端连接至第二控制节点Q2。第五晶体管T5的栅极和第八晶体管T8的栅极相连，并作为控制模块13的第一控制端连接至第一控制节点Q1。第五晶体管T5的第二极和第八晶体管T8的第二极相连，并作为控制模块13的第一下拉端连接至低电平节点Q3。
第一低电平维持模块14包括第六晶体管T6和第七晶体管T7。其中，第六晶体管T6的栅极和第七晶体管T7的栅极相连，并作为第一低 电平维持模块14的第三下拉控制端连接至第二控制节点Q2。第六晶体管T6的第一极作为第一低电平维持模块14的第一端连接至第一控制节点Q1。第七晶体管T7的第一极作为第一低电平维持模块14的第二端连接至第二晶体管T2的第二极。第六晶体管T6的第二极和第七晶体管T7的第二极相连，并作为第一低电平维持模块14的第三端连接至低电平节点Q3。
本实施方式中，第一脉冲信号Vi为前二级栅极驱动单元所输出的栅极信号，例如当前级栅极驱动单元为第3级栅极驱动单元，则当前级的第一脉冲信号Vi为第1级栅极驱动单元所输出的的栅极信号。当然，在其他方式中，第一脉冲信号Vi也可以是前一级栅极驱动单元所输出的栅极信号，或者也可以使用单独的信号源输入所需的第一脉冲信号Vi。第一时钟信号CKA为高频时钟信号，其高电平电压大小为VH1，低电平电压大小为VL1。第一控制信号Vc为第二脉冲信号。高电压源VDD连接第四晶体管T4的第一极以提供第一输入信号，即第一输入信号为高电平信号，其电压大小为VH2。低电压源VSS连接低电平节点Q3以提供低电平信号，其电压大小为VL。其中，VH1≥VH2，VL≥VL1。
结合图3，图3是图2所示栅极驱动单元一实施方式的工作时序图。本实施方式中，栅极驱动单元的工作过程可以分为两个阶段：驱动阶段(t1～t4时刻)和低电平维持阶段(t5时刻以后)。液晶面板为逐行扫描方式，因此，在一个画面帧里，栅极驱动单元仅在扫描时刻对其连接的扫描线输出一个高电平扫描信号，在高电平扫描信号输出后其他时间内栅极驱动单元的输出端需要维持在低电平状态，以避免导通与其连接的扫描线所连接的像素薄膜晶体管，防止信号写入错误。
具体地，在t1时刻，第一控制信号Vc为低电平，使得第三晶体管T3关断。第一时钟信号CKA的电位为低电平VL1，第一脉冲信号Vi的电位为高电平VH1，此时第一晶体管T1导通，第一脉冲信号Vi通过第一晶体管T1对第一控制节点Q1充电，使得第一控制节点Q1的电位VQ1充电至VH1-VTH1，其中VTH1为第一晶体管T1的阈值电压，由此使得第二晶体管T2的栅极电位为高电平VH1-VTH1，从而第二晶体管T2导通。 第二晶体管T2的导通，使得第二晶体管T2的第二极输出的栅极信号Vo被下拉至第一时钟信号CKA的低电平VL1。与此同时，由于第一控制节点Q1的电位VQ1为高电平VH1-VTH1，使得第五晶体管T5和第八晶体管T8导通，进而使得第四晶体管T4的栅极电位被下拉至低电平VL，因此第四晶体管T4被完全关断，由此通过导通的第五晶体管T5，可以将第二控制节点Q2的电位VQ2完全下拉至低电平VL，使得第六晶体管T6和第七晶体管T7被关断，由此使得第一低电平维持模块14处于截止状态。
在t2时刻，第一控制信号Vc仍为低电平。第一脉冲信号Vi的电位下降为低电平VL1，使得第一晶体管T1断开。此时，第一控制节点Q1的电位VQ1仍然保持高电平，使得第二晶体管T2保持导通状态，而第一时钟信号CKA的电位由低电平VL1上升为高电平VH1，通过导通的第二晶体管T2对栅极信号输出端进行充电，使得栅极信号输出端的电位快速上升。由于第一晶体管T1、第三晶体管T3以及第六晶体管T6处于关断状态，导致第一控制节点Q1(即第二晶体管T2的栅极)处于浮空状态。因此，在电容自举效应的作用下，随着栅极信号输出端电压的升高，第一控制节点Q1的电压被抬高至比VH1-VTH1更高的电压，从而栅极信号输出端可以快速充电到高电平VH1，以输出高电平的栅极信号Vo。
在t3时刻，第一时钟信号CKA由高电平VH1下降为低电平VL1，而由于第一控制节点Q1的电位VQ1仍然为高电平，使得第二晶体管T2保持导通状态，因此栅极信号输出端通过导通的第二晶体管T2进行放电，使得栅极信号输出端输出的栅极信号Vo的电位可以快速下降至低电平VL1。而由于电容自举效应，第一控制节点Q1的电位VQ1下降为VH1-VTH1。
在t4时刻，第一控制信号Vc从低电平上升为高电平，第三晶体管T3导通，从而将第一控制节点Q1的电位VQ1下拉至低电平VL，使得第五晶体管T5和第八晶体管T8关断。由于第一时钟信号CKA仍为低电平VL1，因此第四晶体管T4仍为关断状态，使得第二控制节点Q2的电位VQ2保持为低电平VL。
在t5时刻，第一时钟信号CKA由低电平VL1上升为高电平VH1，通过第二电容C2耦合高电压至第四晶体管T4的栅极，使得第四晶体管T4导通。高电压源VDD通过导通的第四晶体管T4对第二控制节点Q2充电，使得第二控制节点Q2的电位VQ2上升至VH2-VTH4，其中VTH4为第四晶体管T4的阈值电压，此时第六晶体管T6和第七晶体管T7导通。通过导通的第六晶体管T6，使得第一控制节点Q1的电位VQ1被下拉至低电平VL。通过导通的第七晶体管T7，使得第二晶体管T2的第二极的电位被下拉至低电平VL，即栅极信号输出端输出的栅极信号Vo被下拉至低电平VL。
在本实施方式中，在驱动阶段的t1～t3时刻期间，由于第四晶体管T4被完全关断，使得第二控制节点Q2的电位VQ2可以通过导通的第五晶体管T5被下拉至低电平VL，由此抑制了第六晶体管T6和第七晶体管T7的漏电，从而有利于减小栅极信号输出端输出的上升延迟时间，有利于提高电路的工作速度。
此外，在栅极信号输出端输出高电平扫描信号后，其所连接的扫描线处于非选通状态，栅极驱动单元的栅极信号输出端需要保持在低电平VL，以防止与对应扫描线连接的像素薄膜晶体管被导通而导致信号写入错误。理论上，第一控制节点Q1(即第二晶体管T2的栅极)的电位VQ1和栅极信号输出端(即第二晶体管T2的第二极)的电位Vo应当保持为低电平，但由于第二晶体管T2的源极和漏极之间存在寄生电容CGD2，当第一时钟信号CKA由低电平跳变为高电平时，会在第一控制节点Q1处产生耦合电压ΔVQ1。ΔVQ1可能导致第一时钟信号CKA对栅极信号输出端错误充电，使得栅极信号输出端输出的栅极信号Vo无法保持在低电平。通过本实施方式，在t5时刻之后，由于第五晶体管T5和第八晶体管T8处于关断状态，第四晶体管T4随着第一时钟信号CKA的高电平脉冲周期性导通，而第二控制节点Q2的电位VQ2始终保持为高电平，从而第六晶体管T6和第七晶体管T7保持导通状态，由此可维持栅极信号输出端输出的栅极信号Vo为低电平扫描信号。
参阅图4，图4是图2所示的栅极驱动单元另一实施方式的工作时 序图。在图3所示的实施方式中，第一脉冲信号Vi的高电平和第一时钟信号CKA的低电平同时到来。与图3所示的实施方式主要不同的是，在图4所示的工作时序图中，第一脉冲信号Vi的高电平和第一时钟信号CKA的高电平重叠1/4个时钟周期。
如图4所示，在t2～t3时刻期间，虽然第一脉冲信号Vi仍然有部分时间为高电平VH1，但由于第一控制节点Q1的电位VQ1被快速抬升至比VH1-VTH1更高的电位，因此第一晶体管T1仍然保持在断开的状态，不会对第一控制节点Q1的自举过程。栅极驱动单元在其他时刻的工作过程与图3所示的对应时刻的过程相类似，在此不进行一一赘述。
实施例二：
参阅图5，图5是本发明栅极驱动单元另一实施方式的具体电路结构示意图。与图2所示的实施方式主要不同在于，本实施方式中，控制模块13还包括第十五晶体管T15。其中，第十五晶体管T15的栅极连接至第一晶体管T1的栅极，第十五晶体管T15的第一极连接至第二控制节点Q2，第十五晶体管T15的第二极连接至低电平节点Q3。
第十五晶体管T15的栅极由第一脉冲信号Vi控制。通过增加第十五晶体管T15，在t1时刻，在第一脉冲信号Vi的高电平控制信号第十五晶体管T15导通，由此可以将第二控制节点Q2的电位VQ2快速地下拉至低电平VL，进一步抑制在t1时刻第七晶体管T7可能存在的漏电，有利于进一步减小第二晶体管T2的输出信号的上升延迟时间，提高电路的工作速度。
其中，本实施方式的栅极驱动单元的工作时序图与图2所示的栅极驱动单元的工作时序图相同，具体的工作过程可参考图3或图4所示的工作方式进行，在此不进行一一赘述。
实施例三：
参阅图6，图6是本发明栅极驱动单元又一实施方式的具体电路结构示意图。本实施方式中，与图2所示实施方式的主要不同在于，控制模块13还包括第九晶体管T9和第十晶体管T10。栅极驱动单元还包括第二低电平维持模块15，其中第二低电平维持模块15包括第十一晶体 管T11和第十二晶体管T12。
其中，第九晶体管T9的栅极连接至第四晶体管T4的栅极，第九晶体管T9的第一极用于输入第三时钟信号EXCK，第九晶体管T9的第二极与第十晶体管T10的第一极、第十一晶体管T11的栅极以及第十二晶体管T12的栅极均连接至第四控制节点Q4。第十晶体管T10的栅极和第八晶体管T8的栅极连接至第一控制节点Q1，第十晶体管T10的第二极连接至低电平节点Q3。第十一晶体管T11的第一极与第二晶体管T2的第二极连接，即连接至栅极信号输出端。第十一晶体管T11的第二极和第十二晶体管T12的第二极连接至低电平节点Q3。第十二晶体管T12的第一极连接至第一控制节点Q1。
此外，本实施方式中，第四晶体管T4输入的第一输入信号为第四时钟信号ECK。其中，第三时钟信号EXCK和第四时钟信号ECK为两相低频时钟信号。
在图2和图5所示的实施方式中，第一低电平维持模块14中的第六晶体管T6和第七晶体管T7处于近似的直流应力偏置之下，在长时间工作之后可能会发生严重的阈值电压漂移。当阈值电压漂移量超过一定程度时，将会导致电路失效。通过本实施方式的栅极驱动单元，可以减小晶体管的阈值电压漂移，增强电路的可靠性。
具体地，结合图6和图7，图7是图6所示的栅极驱动单元一实施方式的工作时序图。其中，第三时钟信号EXCK为低电平，电压大小为VL，第四时钟信号ECK为高电平，电压大小为VH2。第一脉冲信号Vi的高电平和第一时钟信号CKA的低电平同时到达。
本实施方式的栅极驱动单元根据图7所示的工作时序图进行工作的过程，与图2所示的栅极驱动单元根据图3所示的工作时序图进行工作的过程主要不同在于，在t5时刻，第一时钟信号CKA由低电平VL1上升为高电平VH1，通过第二电容C2耦合高电压至第四晶体管T4的栅极，使得第四晶体管T4导通。由于第四时钟信号ECK为高电平信号，因此第四时钟信号ECK通过导通的第四晶体管T4对第二控制节点Q2充电，使得第二控制节点Q2的电位VQ2上升至VH2-VTH4，此时第六晶体管T6 和第七晶体管T7导通。通过导通的第六晶体管T6，使得第一控制节点Q1的电位VQ1被下拉至低电平VL。通过导通的第七晶体管T7，使得第二晶体管T2的第二极的电位被下拉至低电平VL，即栅极信号输出端输出的栅极信号Vo被下拉至低电平VL。
在t5时刻之后，由于第五晶体管T5和第八晶体管T8处于关断状态，第四晶体管T4在第一时钟信号CKA的高电平控制下周期性导通，而第二控制节点Q2的电位VQ2始终保持为高电平，从而第六晶体管T6和第七晶体管T7保持导通状态，由此可维持栅极信号输出端输出的栅极信号Vo为低电平扫描信号。控制模块13和第一低电平维持模块14在其他时刻的工作过程可参考上述实施方式进行，对此不做一一赘述。
其中，在t1～t3时刻，由于第二控制节点Q2的电位VQ2保持在低电平，因此第九晶体管T9处于断开状态。在t4时刻之后，即第二晶体管T2输出高电平的栅极信号Vo之后，第一控制节点Q1的电位VQ1被拉低至低电平，第五晶体管T5、第八晶体管T8和第十晶体管T10被关断，第四晶体管T4和第九晶体管T9在第一时钟信号CKA的高电平控制下周期性导通，使得第二控制节点Q2被充电至高电平，使得第一低电平维持模块14中的第六晶体管T6和第七晶体管T7处于导通状态，进而将栅极信号Vo维持在低电平状态。
由于第三时钟信号EXCK为低电平信号，且第十晶体管T10的第二极连接至低电平节点Q3，因此不论是第九晶体管T9导通或第十晶体管T10导通，都将拉低第四控制节点Q4的电位VQ4至低电平，因此第四控制节点Q4的电位VQ4始终保持为低电平，从而使得第十一晶体管T11和第十二晶体管T12处于断开状态。
因此，根据图7所示的工作时序图，栅极驱动单元通过第一低电平维持模块14对栅极信号输出端所输出的低电平扫描信号进行维持，而第二低电平维持模块15则处于关断状态。
参阅图8，并结合图6，图8是图6所示的栅极驱动单元另一实施方式的工作时序图。其中，与图7所示的工作时序图主要不同的是，图8所示的时序工作图中，第三时钟信号EXCK为高电平，电压大小为VH2， 第四时钟信号ECK为低电平，电压大小为VL。根据图8所示的工作时序图，栅极驱动单元通过第二低电平维持模块15对栅极信号输出端所输出的低电平扫描信号进行维持，而第一低电平维持模块14则处于关断状态。
具体地，由于第四时钟信号ECK为低电平，而第五晶体管T5的第二极连接至低电平节点Q3，因此不论是第四晶体管T4导通或第五晶体管T5导通，都将拉低第二控制节点Q2的电位VQ2至低电平，因此第二控制节点Q2的电位VQ2始终保持为低电平，从而使得第六晶体管T6和第七晶体管T7处于断开状态，即在电路的驱动过程中，第一低电平维持模块14始终为断开状态。
在t1时刻，第一控制信号Vc为低电平，使得第三晶体管T3关断。第一时钟信号CKA的电位为低电平VL1，第一脉冲信号Vi的电位为高电平VH1，此时第一晶体管T1导通，第一脉冲信号Vi通过第一晶体管T1对第一控制节点Q1充电，使得第一控制节点Q1的电位VQ1充电至VH1-VTH1，其中VTH1为第一晶体管T1的阈值电压，由此使得第二晶体管T2的栅极电位为高电平VH1-VTH1，从而第二晶体管T2导通。第二晶体管T2的导通，使得第二晶体管T2的第二极输出的栅极信号Vo被下拉至第一时钟信号CKA的低电平VL1。与此同时，由于第一控制节点Q1的电位VQ1为高电平VH1-VTH1，使得第八晶体管T8和第十晶体管T10导通，进而使得第九晶体管T9的栅极电位被下拉至低电平VL，因此第九晶体管T9被完全关断，由此通过导通的第十晶体管T10，可以将第四控制节点Q4的电位VQ4完全下拉至低电平VL，使得第十一晶体管T11和第十二晶体管T12被关断，由此使得第二低电平维持模块15处于截止状态。
在t2时刻，第一控制信号Vc仍为低电平。第一脉冲信号Vi的电位下降为低电平VL1，使得第一晶体管T1断开。此时，第一控制节点Q1的电位VQ1仍然保持高电平，使得第二晶体管T2保持导通状态，而第一时钟信号CKA的电位由低电平VL1上升为高电平VH1，通过导通的第二晶体管T2对栅极信号输出端进行充电，使得栅极信号输出端的电位 快速上升。由于第一晶体管T1、第三晶体管T3、第六晶体管T6以及第十二晶体管T12处于关断状态，导致第一控制节点Q1(即第二晶体管T2的栅极)处于浮空状态。因此，在电容自举效应的作用下，随着栅极信号输出端电压的升高，第一控制节点Q1的电压被抬高至比VH1-VTH1更高的电压，从而栅极信号输出端可以快速充电到高电平VH1，以输出高电平的栅极信号Vo。
在t3时刻，第一时钟信号CKA由高电平VH1下降为低电平VL1，而由于第一控制节点Q1的电位VQ1仍然为高电平，使得第二晶体管T2保持导通状态，因此栅极信号输出端通过导通的第二晶体管T2进行放电，使得栅极信号输出端输出的栅极信号Vo的电位可以快速下降至低电平VL1。而由于电容自举效应，第一控制节点Q1的电位VQ1下降为VH1-VTH1。
在t4时刻，第一控制信号Vc从低电平上升为高电平，第三晶体管T3导通，从而将第一控制节点Q1的电位VQ1下拉至低电平VL，使得第八晶体管T8和第十晶体管T10关断。由于第一时钟信号CKA仍为低电平VL1，因此第9晶体管T9仍为关断状态，使得第四控制节点Q4的电位VQ4保持为低电平VL。
在t5时刻，第一时钟信号CKA由低电平VL1上升为高电平VH1，通过第二电容C2耦合高电压至第九晶体管T9的栅极，使得第九晶体管T9导通。由于第三时钟信号EXCK为高电平信号，因此第三时钟信号EXCK通过导通的第9晶体管T9对第四控制节点Q4充电，使得第四控制节点Q4的电位VQ2上升至VH2-VTH9，其中VTH9为第九晶体管T9的阈值电压，此时第十一晶体管T11和第十二晶体管T12导通。通过导通的第十二晶体管T12，使得第一控制节点Q1的电位VQ1被下拉至低电平VL。通过导通的第十一晶体管T11，使得第二晶体管T2的第二极的电位被下拉至低电平VL，即栅极信号输出端输出的栅极信号Vo被下拉至低电平VL。
在t5时刻之后，由于第八晶体管T8和第10晶体管T10处于关断状态，第九晶体管T9在第一时钟信号CKA的高电平控制下周期性导通，而第四控制节点Q4的电位VQ4始终保持为高电平，从而第十一晶体管 T11和第十二晶体管T12保持导通状态，由此可维持栅极信号输出端输出的栅极信号Vo为低电平扫描信号。
通过本实施方式，随着时钟信号EXCK和ECK的不断切换，第一低电平维持模块14和第二低电平维持模块15中的晶体管将处于交替工作的模式中。例如在当前时刻中时钟信号EXCK为低电平、时钟信号ECK为高电平，此时栅极驱动单元根据图7所示的工作时序图进行工作，第一低电平维持模块14中的晶体管处于工作状态用于维持栅极信号输出端的低电平，而第二低电平维持模块15中的晶体管则为关断状态；在下一时刻将时钟信号EXCK切换为高电平、时钟信号ECK切换为低电平，此时栅极驱动单元根据图8所示的工作时序图进行工作，第二低电平维持模块15中的晶体管处于工作状态用于维持栅极信号输出端的低电平，而第一低电平维持模块14中的晶体管则为关断状态。由此，通过两个低电平维持模块14、15的交替工作，可以避免其中一个低电平维持模块中的晶体管处于长时间的工作状态，有利于抑制晶体管的阈值电压漂移，提供电路的工作寿命。此外，两个低电平维持模块14、15共用一个控制模块13，能够节省电路面积。
实施例四：
参阅图9，图9是本发明栅极驱动单元另一实施方式的结构示意图，本实施方式的栅极驱动单元的工作时序图与图6所示的栅极驱动单元的工作时序图相同。如图9所示，本实施方式与图6所示的栅极驱动单元主要不同在于，在本实施方式中，控制模块13进一步还包括第十三晶体管T13和第十四晶体管T14。其中，第十三晶体管T13的栅极用于输入第三时钟信号EXCK，第十三晶体管T13的第一极连接至第四晶体管T4的第一极，输入的是第四时钟信号ECK，第十三晶体管T13的第二极连接至第二控制节点Q2。第十四晶体管T14的栅极用于输入第四时钟信号ECK，第十四晶体管T14的第一极连接至第九晶体管T9的第一极，用于输入第三时钟信号EXCK，第十四晶体管T14的第二极连接至第四控制节点Q4。
本实施方式，通过增加第十三晶体管T13和第十四晶体管T14，当 栅极驱动单元根据图7所示的工作时序图进行工作时，即利用晶体管T6、T7对栅极信号输出端的低电平进行维持，此时第十四晶体管T14为导通状态。通过导通的第十四晶体管T14可以将第三时钟信号EXCK耦合至第四控制节点Q4，由此可以进一步度稳定第四控制节点Q4的低电平，避免由于第四控制节点Q4的低电平不稳定而导致晶体管T11、T12的漏电，从而有利于电路输出更加稳定。当栅极驱动单元根据图8所示的工作时序图进行工作时，即利用晶体管T11、T12对对栅极信号输出端的低电平进行维持，此时第十三晶体管T13为导通状态。通过导通的第十三晶体管T13可以将第四时钟信号ECK耦合至第二控制节点Q2，由此可以进一步度稳定第二控制节点Q2的低电平，避免由于第二控制节点Q2的低电平不稳定而导致晶体管T6、T7的漏电，从而有利于电路输出更加稳定。
实施例五：
参阅图10，图10是本发明栅极驱动单元另一实施方式的结构示意图。本实施方式的栅极驱动单元的工作时序图与图6所示的栅极驱动单元的工作时序图相同。如图10所示，本实施方式与图6所示的栅极驱动单元主要不同在于，在本实施方式中，控制模块13进一步还包括第十六晶体管T16和第十七晶体管T17。
第十六晶体管T16的栅极与第十七晶体管T17的栅极均连接至第一晶体管T1的栅极，用于输入第一脉冲信号Vi，第十六晶体管T16的第一极连接至第四控制节点Q4，第十六晶体管T16的第二极连接至低电平节点Q3。第十七晶体管T17的第一极连接至第二控制节点Q2，第十七晶体管T17的第二极连接至低电平节点Q3。
第十六晶体管T16和第十七晶体管T17由第一脉冲信号Vi驱动，通过增加晶体管T16、T17，当栅极驱动单元根据图7所示的工作时序图进行工作时，在t1时刻，通过导通的第十七晶体管T17可以将第六晶体管T6、第七晶体管T7的栅极快速下拉至低电平VL，由此抑制了在t1时刻晶体管T6、T7可能产生的漏电，进一步减小电路的输出上升延迟。当栅极驱动单元根据图8所示的工作时序图进行工作时，在t1时刻，通 过导通的第十六晶体管T16可以将第十一晶体管T11和第十二晶体管T12的栅极快速下拉至低电平VL，由此抑制了在t1时刻晶体管T11、T12可能产生的漏电，进一步减小电路的输出上升延迟。
实施例六：
参阅图11，图11是本发明栅极驱动单元另一实施方式的结构示意图。每个栅极驱动单元用于驱动一条扫描线，因此液晶面板通常需要多个栅极驱动单元进行驱动，多个栅极驱动单元为级联的方式进行连接，每一级栅极驱动单元的栅极信号输出端连接一条扫描线。
本实施方式中，栅极驱动单元与图2所示实施方式的栅极驱动单元主要不同在于，本实施方式的栅极驱动单元还包括第二低电平维持模块16，第二低电平维持模块16包括第十八晶体管T18和第十九晶体管T19。假设当前级栅极驱动单元为N，前一级栅极驱动单元为N-1，如图11所示，当前级栅极驱动单元N的第十八晶体管T18的栅极和第十九晶体管T19的栅极均连接至前一级栅极驱动单元N-1的第二控制节点Q2，当前级栅极驱动单元N的第十八晶体管T18的第一极连接至当前级栅极驱动单元N的第一控制节点Q1，当前级栅极驱动单元N的第十八晶体管T18的第二极连接至当前级栅极驱动单元N的低电平节点Q3。当前级栅极驱动单元N的第十九晶体管T19的第一极连接至当前级栅极驱动单元N的第二晶体管T2的第二极，当前级栅极驱动单元N的第十九晶体管T19的第二极连接至当前级栅极驱动单元N的低电平节点Q3。
其中，当前级栅极驱动单元N的第四晶体管T4的第一极输入的第一输入信号为第四时钟信号ECK，前一级栅极驱动单元N-1的第四晶体管T4的第一极输入的第一输入信号为第三时钟信号EXCK。本实施方式的栅极驱动单元与图6所示实施方式的栅极驱动单元的工作过程相类似，主要不同在于本实施方式的栅极驱动单元的第二低电平维持模块16通过前一级栅极驱动单元的第二控制节点进行驱动。
具体地，结合图11和图12，图12是图11所示的栅极驱动单元一实施方式的工作时序图。第一脉冲信号Vi(N)的高电平和第一时钟信号CKA(N)的低电平同时到来。第三时钟信号ECXK为低电平，电压大小为 VL，第四时钟信号ECK为高电平，电压大小为VH2，此种情况下，前一级栅极驱动单元N-1的工作过程与图6所示的栅极驱动单元根据图8所示的工作时序图进行工作的过程相类似，具体的工作过程在此不进行一一赘述。其中，前一级栅极驱动单元N-1的第二控制节点Q2(N-1)的电位VQ2(N-1)通过导通的第五晶体管T5或导通的第四晶体管T4被下拉至低电平VL，即前一级栅极驱动单元N-1的第二控制节点Q2(N-1)保持为低电平VL，前一级栅极驱动单元N-1为利用其第二低电平维持模块16对对应的栅极信号输出端的低电平进行维持，而其第一低电平维持模块14在第二控制节点Q2(N-1)的低电平控制下为关断状态。
对于当前级栅极驱动单元N，由于第四时钟信号ECK为高电平，其工作过程与图6所示的栅极驱动单元根据图7所示的工作时序图进行工作的过程相类似，具体的工作过程在此不进行一一赘述。其中，由于当前级栅极驱动单元N的第十八晶体管T18和第十九晶体管T19的栅极连接至前一级栅极驱动单元N-1的第二控制节点Q2(N-1)，在前一级栅极驱动单元N-1的第二控制节点Q2(N-1)的低电平控制下，当前级栅极驱动单元N的第十八晶体管T18和第十九晶体管T19处于断开状态，因此当前级栅极驱动单元N的第二低电平维持模块16为关断状态。而在t5时刻之后，当前级栅极驱动单元N的第二控制节点Q2(N)的电位VQ2(N)保持在高电平状态，使得第六晶体管T6和第七晶体管T7处于导通状态，进而维持对应栅极信号输出端的栅极信号Vo(N)为低电平，即当前级栅极驱动单元N利用第一低电平维持模块14维持栅极信号输出端的低电平，而其第二低电平维持模块16则为关断状态。
其中，在上述情况中，第三时钟信号ECXK为低电平、第四时钟信号ECK为高电平，前一级栅极驱动单元N-1为利用其第二低电平维持模块16对对应的栅极信号输出端的低电平进行维持，当前级栅极驱动单元N利用第一低电平维持模块14维持栅极信号输出端的低电平。在另一种情况中，第三时钟信号ECXK也可以是高电平，而第四时钟信号ECK也可以是低电平，此时前一级栅极驱动单元N-1为利用其第一低电平维持模块14对对应的栅极信号输出端的低电平进行维持，当前级栅 极驱动单元N利用第二低电平维持模块16维持栅极信号输出端的低电平，具体的分析过程可参考上述描述，对此不做一一赘述。
结合图11和图13，图13是图11所示的栅极驱动单元另一实施方式的工作时序图。第一脉冲信号Vi(N)的高电平和第一时钟信号CKA(N)的高电平重叠1/4个时钟周期，第三时钟信号ECXK为高电平，电压大小为VH2，第四时钟信号ECK为低电平，电压大小为VL，此种情况下，前一级栅极驱动单元N-1的工作过程与图6所示的栅极驱动单元根据图7所示的工作时序图进行工作的过程相类似，具体的工作过程在此不进行一一赘述。其中，在t5时刻之后，前一级栅极驱动单元N-1的第五晶体管T5和第八晶体管T8关闭，第四晶体管T4在第一时钟信号CKA(N-1)的高电平控制下周期性导通，使得前一级栅极驱动单元N-1的第二控制节点Q2(N-1)的电位VQ2(N-1)保持为高电平VH2，即前一级栅极驱动单元N-1为利用其第一低电平维持模块14对对应的栅极信号输出端的低电平进行维持，而其第二低电平维持模块16为关断状态。
对于当前级栅极驱动单元N，由于第四时钟信号ECK为低电平，其工作过程与图6所示的栅极驱动单元根据图8所示的工作时序图进行工作的过程相类似，具体的工作过程在此不进行一一赘述。其中，当前级栅极驱动单元N的第二控制节点Q2(N)的电位VQ2(N)通过导通的第五晶体管T5或导通的第四晶体管T4被下拉至低电平VL，即当前级栅极驱动单元N的第二控制节点Q2(N)保持为低电平VL，其第六晶体管T6和第七晶体管T7处于断开状态，因此第一低电平维持模块14处于关断状态。而在t5时刻以后，当前级栅极驱动单元N的第十八晶体管T18和第十九晶体管T19在前一级栅极驱动单元的第二控制节点Q2(N-1)的高电平控制下处于导通状态，因此当前级栅极驱动单元N的第二低电平维持模块16处于导通状态，进而维持对应栅极信号输出端的栅极信号Vo(N)为低电平，即当前级栅极驱动单元N利用第二低电平维持模块16维持栅极信号输出端的低电平，而其第一低电平维持模块14则为关断状态。
其中，在上述情况中，第三时钟信号ECXK为高电平、第四时钟信号ECK为低电平，前一级栅极驱动单元N-1为利用其第一低电平维持 模块14对对应的栅极信号输出端的低电平进行维持，当前级栅极驱动单元N利用第二低电平维持模块16维持栅极信号输出端的低电平。在另一种情况中，第三时钟信号ECXK也可以是低电平，而第四时钟信号ECK也可以是高电平，此时前一级栅极驱动单元N-1为利用其第二低电平维持模块16对对应的栅极信号输出端的低电平进行维持，当前级栅极驱动单元N利用第一低电平维持模块14维持栅极信号输出端的低电平，具体的分析过程可参考上述描述，对此不做一一赘述。
通过本实施方式，使相邻两级栅极驱动单元共用一个控制模块，具体而言，使当前级栅极驱动单元N和前一级栅极驱动单元N-1共用一个控制模块，有利于减小电路中的晶体管的数目，简化电路设计，有利于进一步减小电路的总面积。
当然，在其他实施方式中，可以在图11所示的栅极驱动单元的控制模块中进一步增加第十五晶体管T15，第十五晶体管T15的连接方式可参考图5所示的第十五晶体管T15的连接方式，在此不做赘述。
实施例七：
参阅图14，在本发明栅极驱动单元的又一实施方式中，与图2所示的栅极驱动单元的主要不同在于，第三晶体管T3的第二极连接至第一晶体管T1的栅极，用于输入第一脉冲信号Vi，且第三晶体管T3的栅极所输入的第一控制信号为第二时钟信号CKB，其中第一时钟信号CKA的高电平和第二时钟信号CKB的高电平重叠1/4个时钟周期，第二时钟信号CKB也为前一级栅极驱动单元的第一时钟信号。
结合图15，图15是图14所示的栅极驱动单元的工作时序图。
在t1时刻，第一脉冲信号Vi为高电平，第二时钟信号CKB为高电平，第一晶体管T1和第三晶体管T3均处于导通状态，第一脉冲信号Vi可以通过导通的第三晶体管T3对第一控制节点Q1充电，使得第一控制节点Q1的电位VQ1升高至高电平，进而使得第二晶体管T2导通。而第一时钟信号CKA为低电平，因此通过导通的第二晶体管T2将栅极信号输出端的栅极信号Vo拉低至低电平。与此同时，在第一控制节点Q1的高电平控制下第五晶体管T5和第八晶体管T8导通，进而将第二控制 节点Q2的电位VQ2拉低至低电平，使得第六晶体管T6和第七晶体管T7断开。
在t2时刻，第一时钟信号CKA为高电平，第二时钟信号CKB和第一脉冲信号Vi在前半部分时间里为高电平，此时第一控制节点Q1的电位VQ1保持高电平，使得第二晶体管T2保持导通，栅极信号输出端的电位快速上升，而随着第一时钟信号CKA对栅极信号输出端的充电，在电容自举效应的影响下第一控制节点Q1的电位VQ1也被抬升，使得栅极信号输出端可以快速充电到高电平，从而输出高电平的栅极信号Vo。而在后半部分时间里第二时钟信号CKB和第一脉冲信号Vi为低电平，此时第一晶体管T1和第三晶体管T3关闭，但由于第一控制节点Q1的电位VQ1为高电平，因此第二晶体管T2保持导通，使得栅极信号输出端输出高电平的栅极信号Vo。
在t3时刻，第一时钟信号CKA由高电平VH1下降为低电平VL1，而由于第一控制节点Q1的电位VQ1仍然为高电平，使得第二晶体管T2保持导通状态，因此栅极信号输出端通过导通的第二晶体管T2进行放电，使得栅极信号输出端输出的栅极信号Vo的电位可以快速下降至低电平。而由于电容自举效应，第一控制节点Q1的电位VQ1下降为VH1-VTH1。
在t4时刻，第二时钟信号CKB从低电平上升为高电平，第三晶体管T3导通，从而将第一控制节点Q1的电位VQ1下拉至第一脉冲信号Vi的低电平，使得第五晶体管T5和第八晶体管T8关断。由于第一时钟信号CKA仍为低电平VL1，因此第四晶体管T4仍为关断状态，使得第二控制节点Q2的电位VQ2保持为低电平VL。
在t5时刻，第一时钟信号CKA由低电平VL1上升为高电平VH1，通过第二电容C2耦合高电压至第四晶体管T4的栅极，使得第四晶体管T4导通。高电压源VDD通过导通的第四晶体管T4对第二控制节点Q2充电，使得第二控制节点Q2的电位VQ2上升至VH2-VTH4，其中VTH4为第四晶体管T4的阈值电压，此时第六晶体管T6和第七晶体管T7导通。通过导通的第六晶体管T6，使得第一控制节点Q1的电位VQ1被下拉至低电平VL。通过导通的第七晶体管T7，使得第二晶体管T2的第二极的 电位被下拉至低电平VL，即栅极信号输出端输出的栅极信号Vo被下拉至低电平VL。此外，第三晶体管T3由第二时钟信号CKB驱动，可以进一步维持第一控制节点Q1的电位VQ1为低电平。
通过本实施方式，栅极驱动单元不需要后级单元提供反馈信号。
本领域技术人员可以理解的是，在本发明栅极驱动单元的实施方式中，图14所示的栅极驱动单元中的控制模块13可以采用如图5、图6、图9、图10或图11所示的控制模块，并且也可以增加如图6、图9、图10或图11所示的第二低电平维持模块。
本发明还提供一种栅极驱动电路的实施方式，栅极驱动电路包括M个级联的栅极驱动单元，M为大于1的整数，其中栅极驱动单元可以是上述任一实施方式中所述的栅极驱动单元。其中，第N级栅极驱动单元的脉冲信号输入端连接至第N-1级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为1＜N≤M。或者在另一种实现方式中，第N级栅极驱动单元的脉冲信号输入端也可以连接至第N-2级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为2＜N≤M。
其中，在M个级联的栅极驱动单元中，每一级栅极驱动单元的结构可以相同，例如可以均是图2所示的栅极驱动单元，或者均是图5所示的栅极驱动单元，或者均是图6所示的栅极驱动单元，或者均是图9所示的栅极驱动单元，或者均是图10所示的栅极驱动单元，或者均是图11所示的栅极驱动单元，或者均是图14所示的栅极驱动单元。
当然，在M个级联的栅极驱动单元中，各级栅极驱动单元的结构也可以不相同，或者部分相同。
实施例八：
参阅图16，并结合图19，图19是图16所示的栅极驱动电路一实施方式的工作时序图。其中，栅极驱动电路包括M个级联的栅极驱动单元，其中M为大于1的整数。每个栅极驱动单元的栅极信号输出端用于对一条扫描线提供扫描信号。其中第N级栅极驱动单元的脉冲信号输入端连接至第N-1级栅极驱动单元的栅极信号输出端，此时N为整数，取值范围为1＜N≤M。或者第N级栅极驱动单元的脉冲信号输入端也可以 连接至第N-2级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为2＜N≤M。
具体地，本实施方式中，栅极驱动电路还包括多条时钟信号线，图中示出了四条时钟信号线CK1～CK4，还包括高电平信号线VDD、低电平信号线VSS以及启动信号线ST。启动信号线ST为脉冲信号。M个级联的栅极驱动单元分为两部分，第1至第M-4级栅极驱动单元为主驱动单元，第M-3至第M级栅极驱动单元为附加级栅极驱动单元。
其中，第1至第M-4级栅极驱动单元中的每一级栅极驱动单元可以是图2所示的栅极驱动单元，或者也可以是图5所示的栅极驱动单元。
在第1至第M-4级栅极驱动单元中，第J级栅极驱动单元的脉冲信号输入端(Vi)连接至第J-2级栅极驱动单元的栅极信号输出端，其中J为整数，取值范围为2＜J≤M-4。而第1级栅极驱动单元和第2极栅极驱动单元的脉冲信号输入端连接至启动信号线ST，以通过启动信号线ST获得第一脉冲信号Vi。每个栅极驱动单元的时钟信号输入端(CKA)连接至一条时钟信号线，第一下拉控制端(Vc)连接至第K+3级栅极驱动单元的栅极信号输出端，即每个栅极驱动单元的第一控制信号Vc为第K+3级栅极驱动单元的栅极信号输出端所输出的栅极信号，其中K为整数，取值范围为1≤K≤M-4。每个栅极驱动单元的第一输入信号端连接至高电平信号线VDD，低电平节点Q3连接至低电平信号线VSS。
当然，在其他实施方式中，在第1至第M-4级栅极驱动单元中，第J级栅极驱动单元的脉冲信号输入端也可以连接至第J-1级栅极驱动单元的栅极信号输出端，其中J为整数，取值范围为1＜J≤M-4。
其中，第M-3至第M级栅极驱动单元(即第1至第4附加级)中的每一级栅极驱动单元可以为图14所示的栅极驱动单元。在第M-3至第M级栅极驱动单元中，每一级栅极驱动单元的脉冲信号输入端连接至上一级栅极驱动单元的栅极信号输出端，同一栅极驱动单元的时钟信号输入端(CKA)和第一下拉控制端(CKB)连接至两条不同的时钟信号线。
实施例九：
参阅图17，并结合图19，图19是图17所示的栅极驱动电路一实施方式的工作时序图。其中，栅极驱动电路包括M个级联的栅极驱动单元，其中M为大于1的整数。每个栅极驱动单元的栅极信号输出端用于对一条扫描线提供扫描信号。其中第N级栅极驱动单元的脉冲信号输入端连接至第N-1级栅极驱动单元的栅极信号输出端，此时N为整数，取值范围为1＜N≤M。或者第N级栅极驱动单元的脉冲信号输入端也可以连接至第N-2级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为2＜N≤M。
具体地，本实施方式中，栅极驱动电路还包括多条时钟信号线，图中示出了四条时钟信号线CK1～CK4以及两条两相低频时钟信号线EXCK、ECK，还包括高电平信号线VDD、低电平信号线VSS以及启动信号线ST。启动信号线ST为脉冲信号。M个级联的栅极驱动单元分为两部分，第1至第M-4级栅极驱动单元为主驱动单元，第M-3至第M级栅极驱动单元为附加级栅极驱动单元。
其中，第1至第M-4级栅极驱动单元中的每一级栅极驱动单元可以是图6、图9或图10任一实施方式所示的栅极驱动单元，每一级栅极驱动单元的脉冲信号输入端(Vi)、时钟信号输入端(CKA)以及第一下拉控制端(Vc)的连接方式与图16所示的栅极驱动电路的连接方式相同，在此不进行一一赘述。此外，第1至第M-4级栅极驱动单元中的第四晶体管T4的第一极连接至时钟信号线ECK，第十三晶体管T13的栅极连接至时钟信号线EXCK，第九晶体管T9的第一极连接至时钟信号线EXCK，第十四晶体管T14的栅极连接至时钟信号线ECK。
其中，第M-3至第M级栅极驱动单元(即第1至第4附加级)中的每一级栅极驱动单元为在图14所示的栅极驱动单元的基础上，增加图6所示的栅极驱动单元中的晶体管T9、T10、T11和T12所得到的栅极驱动单元，增加的晶体管T9、T10、T11和T12的连接方式与图6所示的栅极驱动单元的连接方式相同，其中晶体管T4的第一极连接至时钟信号线ECK，晶体管T9的第一极连接至时钟信号线EXCK。
当然，第M-3至第M级栅极驱动单元中的每一级栅极驱动单元也 可以是在图14所示的栅极驱动单元的基础上，增加图9所示的栅极驱动单元中的晶体管T9、T10、T11、T12、T13和T14，增加的晶体管T9、T10、T11、T12、T13和T14的连接方式与图9所示的栅极驱动单元的连接方式相同，其中晶体管T4的第一极连接至时钟信号线ECK，晶体管T13的栅极连接至时钟信号线EXCK，晶体管T9的第一极连接至时钟信号线EXCK，晶体管T14的栅极连接至时钟信号线ECK。第M-3至第M级栅极驱动单元中的每一级栅极驱动单元还可以是在图14所示的栅极驱动单元的基础上，增加图10所示的栅极驱动单元中的晶体管T9、T10、T11、T12、T16和T17，增加的晶体管T9、T10、T11、T12、T16和T17的连接方式与图10所示的栅极驱动单元的连接方式相同。
实施例十：
参阅图18，并结合图19，图19是图18所示的栅极驱动电路一实施方式的工作时序图。与图17所示的栅极驱动电路主要不同在于，本实施方式中的第2至M-4级栅极驱动单元采用图11所示的栅极驱动单元的结构，即在第2至M-4级栅极驱动单元中，第H级栅极驱动单元的第二低电平维持模块16的晶体管T18、T19的栅极连接至第H-1级栅极驱动单元的第二控制节点Q2，其中H为整数，取值范围为1＜H≤M-4。本实施方式的第1级栅极驱动单元和第M-3至第M级栅极驱动单元的连接方式与图17所示实施方式的连接方式相类似，在此不进行一一赘述。
参阅图20，本发明还提供一种显示装置的实施方式，显示装置为液晶显示装置，包括多条扫描线G1～GN，以及为多条扫描线G1～GN提供栅极信号的栅极驱动电路21。其中，栅极驱动电路21为前述任一实施方式所述的栅极驱动电路。通过对多条扫描线G1～GN提供扫描信号以驱动对应的像素薄膜晶体管，然后数据驱动电路22通过打开的像素薄膜晶体管对像素提供显示信号，由此实现显示装置的画面显示。
通过本发明实施方式的栅极驱动单元、栅极驱动电路以及显示装置，可以将低电平维持模块的控制端下拉至低电平，从而减小低电平维持模块的漏电，提高电路工作速度。如图21所示，图21示出了现有技 术的栅极驱动单元的低电平维持模块的控制端的信号波形和本发明实施方式的栅极驱动单元的低电平维持模块的控制端(即第三下拉控制端，也即第二控制节点)的信号波形。其中，信号波形211为传统的低电平维持模块的控制端的信号波形，信号波形212为本发明实施方式的低电平维持模块的控制端的信号波形(也即第二控制节点的信号波形)。从图中可以看出，在驱动阶段(即t1～t4时刻，对应图21中的椭圆虚线部分)，与传统的低电平维持模块相比，本发明的低电平维持模块的控制端的电平可以完全下拉至VL，从而可以有效减小低电平维持模块的漏电。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种用于驱动液晶面板的栅极驱动电路，其中，包括M个级联的栅极驱动单元，其中M为大于1的整数，每个所述栅极驱动单元包括输入模块、输出模块、控制模块以及第一低电平维持模块；
    所述输入模块包括用于输入第一脉冲信号的脉冲信号输入端、用于输入第一控制信号的第一下拉控制端和耦合至第一控制节点的控制信号输出端，所述输入模块用于根据所述第一脉冲信号和所述第一控制信号控制所述第一控制节点的电位；
    所述输出模块包括耦合至所述第一控制节点的驱动控制端、用于输入第一时钟信号的时钟信号输入端以及栅极信号输出端，所述输出模块在所述第一控制节点的电位的控制下，通过所述栅极信号输出端输出栅极选通信号或栅极截止信号；
    所述控制模块包括用于输入所述第一时钟信号的时钟信号输入端、用于输入第一输入信号的第一输入信号端、耦合至第二控制节点的第二下拉控制端、耦合至所述第一控制节点的第一控制端以及耦合至低电平节点的第一下拉端，所述低电平节点用于输入低电平信号，所述控制模块至少用于在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间在所述第一控制节点的高电平控制下将所述第二控制节点的电位下拉至低电平；
    所述第一低电平维持模块包括耦合至所述第二控制节点的第三下拉控制端、耦合至所述第一控制节点的第一端、耦合至所述输出模块的栅极信号输出端的第二端以及耦合至所述低电平节点的第三端，所述第一低电平维持模块在所述第二控制节点的低电平控制下至少在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间处于截止状态；
    其中第N级栅极驱动单元的脉冲信号输入端连接至第N-1级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为1＜N≤M，或者或第N级栅极驱动单元的脉冲信号输入端连接至第N-2级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为2＜N≤M。
  2. 根据权利要求1所述的栅极驱动电路，其中，
    所述输入模块包括第一晶体管和第三晶体管，所述第一晶体管的栅极和所 述第一晶体管的第一极连接，用于输入所述第一脉冲信号，所述第一晶体管的第二极和所述第三晶体管的第一极连接至所述第一控制节点，所述第三晶体管的栅极用于输入所述第一控制信号，所述第三晶体管的第二极连接至所述低电平节点或连接至所述第一晶体管的第一极，所述第一控制信号为第二脉冲信号或第二时钟信号，所述第一时钟信号的高电平和所述第二时钟信号的高电平重叠1/4个时钟周期；
    所述输出模块包括第二晶体管，所述第二晶体管的栅极连接至所述第一控制节点，所述第二晶体管的第一极用于输入所述第一时钟信号，所述第二晶体管的第二极为所述栅极信号输出端；
    所述控制模块包括第四晶体管、第五晶体管、第八晶体管以及第二电容，所述第四晶体管的栅极与所述第八晶体管的第一极以及所述第二电容的一端相连，所述第二电容的另一端用于输入所述第一时钟信号，所述第八晶体管的栅极和所述第五晶体管的栅极连接至所述第一控制节点，所述第八晶体管的第二极和第五晶体管的第二极连接至所述低电平节点，所述第五晶体管的第一极和所述第四晶体管的第二极连接至所述第二控制节点，所述第四晶体管的第一极用于输入所述第一输入信号；
    所述第一低电平维持模块包括第六晶体管和第七晶体管，所述第六晶体管的栅极和所述第七晶体管的栅极连接至所述第二控制节点，所述第六晶体管的第一极连接至所述第一控制节点，所述第六晶体管的第二极和所述第七晶体管的第二极连接至所述低电平节点，所述第七晶体管的第一极连接至所述第二晶体管的第二极。
  3. 根据权利要求2所述的栅极驱动电路，其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；
    第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
  4. 根据权利要求2所述的栅极驱动电路，其中，所述控制模块还包括第十五晶体管，所述第十五晶体管的栅极连接至所述第一晶体管的栅极，所述第十五晶体管的第一极连接至所述第二控制节点，所述第十五晶体管的第二极连接至所述低电平节点。
  5. 根据权利要求2所述的栅极驱动电路，其中，每个所述栅极驱动单元还包括第二低电平维持模块，所述控制模块还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；
    所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一控制节点；
    所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述控制模块还包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极用于输入所述第三时钟信号，所述第十三晶体管的第一极连接至所述第四晶体管的第一极，所述第十三晶体管的第二极连接至所述第二控制节点，所述第十四晶体管的栅极用于输入所述第四时钟信号，所述第十四晶体管的第一极连接至所述第九晶体管的第一极，所述第十四晶体管的第二极连接至所述第九晶体管的第二极。
  7. 根据权利要求5所述的栅极驱动电路，其中，所述控制单元还包括第十六晶体管和第十七晶体管，所述第十六晶体管的栅极与所述第十七晶体管的栅极以及所述第一晶体管的栅极连接，所述第十六晶体管的第一极与所述第九晶体管的第二极连接，所述第十六晶体管的第二极和所述第十七晶体管的第二极连接至所述低电平节点，所述第十七晶体管的第一极连接至所述第二控制节点。
  8. 根据权利要求5所述的栅极驱动电路，其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；
    第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
  9. 根据权利要求2所述的栅极驱动电路，其中，每个所述栅极驱动单元还包 括第二低电平维持模块，所述第二低电平维持模块包括第十八晶体管和第十九晶体管；
    其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；
    当前级栅极驱动单元的所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号。
  10. 根据权利要求2所述的栅极驱动电路，其中，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元进一步还包括第二低电平维持模块，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述控制模块进一步还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一控制节点；所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号；
    其中第1级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；所述第M-3至第M级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至第一晶体管的第一极以输入第一脉冲信号且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号；
    第2至第M-4级栅极驱动单元中的每一级栅极驱动单元进一步还包括第十 八晶体管和第十九晶体管，其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；当前级栅极驱动单元的所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号；
    其中第2至第M-4级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号。
  11. 一种显示装置，其中，包括多条扫描线和为所述扫描线提供栅极信号的栅极驱动电路，所述栅极驱动电路包括M个级联的栅极驱动单元，其中M为大于1的整数，每个所述栅极驱动单元包括输入模块、输出模块、控制模块以及第一低电平维持模块；
    所述输入模块包括用于输入第一脉冲信号的脉冲信号输入端、用于输入第一控制信号的第一下拉控制端和耦合至第一控制节点的控制信号输出端，所述输入模块用于根据所述第一脉冲信号和所述第一控制信号控制所述第一控制节点的电位；
    所述输出模块包括耦合至所述第一控制节点的驱动控制端、用于输入第一时钟信号的时钟信号输入端以及栅极信号输出端，所述输出模块在所述第一控制节点的电位的控制下，通过所述栅极信号输出端输出栅极选通信号或栅极截止信号；
    所述控制模块包括用于输入所述第一时钟信号的时钟信号输入端、用于输入第一输入信号的第一输入信号端、耦合至第二控制节点的第二下拉控制端、耦合至所述第一控制节点的第一控制端以及耦合至低电平节点的第一下拉端，所述低电平节点用于输入低电平信号，所述控制模块至少用于在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间在所述第一控制节点的高电平控制下将所述第二控制节点的电位下拉至低电平；
    所述第一低电平维持模块包括耦合至所述第二控制节点的第三下拉控制 端、耦合至所述第一控制节点的第一端、耦合至所述输出模块的栅极信号输出端的第二端以及耦合至所述低电平节点的第三端，所述第一低电平维持模块在所述第二控制节点的低电平控制下至少在所述输出模块输出栅极选通信号之前以及输出栅极选通信号期间处于截止状态；
    其中第N级栅极驱动单元的脉冲信号输入端连接至第N-1级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为1＜N≤M，或者或第N级栅极驱动单元的脉冲信号输入端连接至第N-2级栅极驱动单元的栅极信号输出端，其中N为整数，取值范围为2＜N≤M。
  12. 根据权利要求11所述的显示装置，其中，
    所述输入模块包括第一晶体管和第三晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极连接，用于输入所述第一脉冲信号，所述第一晶体管的第二极和所述第三晶体管的第一极连接至所述第一控制节点，所述第三晶体管的栅极用于输入所述第一控制信号，所述第三晶体管的第二极连接至所述低电平节点或连接至所述第一晶体管的第一极，所述第一控制信号为第二脉冲信号或第二时钟信号，所述第一时钟信号的高电平和所述第二时钟信号的高电平重叠1/4个时钟周期；
    所述输出模块包括第二晶体管，所述第二晶体管的栅极连接至所述第一控制节点，所述第二晶体管的第一极用于输入所述第一时钟信号，所述第二晶体管的第二极为所述栅极信号输出端；
    所述控制模块包括第四晶体管、第五晶体管、第八晶体管以及第二电容，所述第四晶体管的栅极与所述第八晶体管的第一极以及所述第二电容的一端相连，所述第二电容的另一端用于输入所述第一时钟信号，所述第八晶体管的栅极和所述第五晶体管的栅极连接至所述第一控制节点，所述第八晶体管的第二极和第五晶体管的第二极连接至所述低电平节点，所述第五晶体管的第一极和所述第四晶体管的第二极连接至所述第二控制节点，所述第四晶体管的第一极用于输入所述第一输入信号；
    所述第一低电平维持模块包括第六晶体管和第七晶体管，所述第六晶体管的栅极和所述第七晶体管的栅极连接至所述第二控制节点，所述第六晶体管的第一极连接至所述第一控制节点，所述第六晶体管的第二极和所述第七晶体管的第二极连接至所述低电平节点，所述第七晶体管的第一极连接至所述第二晶体管的第二极。
  13. 根据权利要求12所述的显示装置，其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；
    第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
  14. 根据权利要求12所述的显示装置，其中，所述控制模块还包括第十五晶体管，所述第十五晶体管的栅极连接至所述第一晶体管的栅极，所述第十五晶体管的第一极连接至所述第二控制节点，所述第十五晶体管的第二极连接至所述低电平节点。
  15. 根据权利要求12所述的显示装置，其中，每个所述栅极驱动单元还包括第二低电平维持模块，所述控制模块还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；
    所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一控制节点；
    所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号。
  16. 根据权利要求15所述的显示装置，其中，所述控制模块还包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极用于输入所述第三时钟信号，所述第十三晶体管的第一极连接至所述第四晶体管的第一极，所述第十三晶体管的第二极连接至所述第二控制节点，所述第十四晶体管的栅极用于输入所述第四时钟信号，所述第十四晶体管的第一极连接至所述第九晶体管的第一极，所述第十四晶体管的第二极连接至所述第九晶体管的第二极。
  17. 根据权利要求15所述的显示装置，其中，所述控制单元还包括第十六晶体管和第十七晶体管，所述第十六晶体管的栅极与所述第十七晶体管的栅极以 及所述第一晶体管的栅极连接，所述第十六晶体管的第一极与所述第九晶体管的第二极连接，所述第十六晶体管的第二极和所述第十七晶体管的第二极连接至所述低电平节点，所述第十七晶体管的第一极连接至所述第二控制节点。
  18. 根据权利要求15所述的显示装置，其中，第1至第M-4级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；
    第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述第三晶体管的第二极连接至所述第一晶体管的第一极且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号。
  19. 根据权利要求12所述的显示装置，其中，每个所述栅极驱动单元还包括第二低电平维持模块，所述第二低电平维持模块包括第十八晶体管和第十九晶体管；
    其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；
    当前级栅极驱动单元的所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号。
  20. 根据权利要求12所述的显示装置，其中，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元进一步还包括第二低电平维持模块，第1级栅极驱动单元和第M-3至第M级栅极驱动单元中每一级栅极驱动单元的所述控制模块进一步还包括第九晶体管和第十晶体管，所述第二低电平维持单元包括第十一晶体管和第十二晶体管；所述第九晶体管的栅极连接至所述第四晶体管的栅极，所述第九晶体管的第一极用于输入第三时钟信号，所述第九晶体管的第二极与所述第十晶体管的第一极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极连接，所述第十晶体管的栅极和所述第八晶体管的栅极连接至所述第一控制节点，所述第十晶体管的第二极连接至所述低电平节点，所述第十一晶体管的第一极与所述第二晶体管的第二极连接，所述第十一晶体 管的第二极和所述第十二晶体管的第二极连接至所述低电平节点，所述第十二晶体管的第一极连接至所述第一控制节点；所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号，所述第三时钟信号和所述第四时钟信号为两相低频时钟信号；
    其中第1级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号；所述第M-3至第M级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至第一晶体管的第一极以输入第一脉冲信号且所述第三晶体管的栅极输入的所述第一控制信号为第二时钟信号；
    第2至第M-4级栅极驱动单元中的每一级栅极驱动单元进一步还包括第十八晶体管和第十九晶体管，其中当前级栅极驱动单元的所述第十八晶体管的栅极和所述第十九晶体管的栅极连接至前一级栅极驱动单元的第二控制节点，当前级栅极驱动单元的所述第十八晶体管的第一极连接至当前级栅极驱动单元的第一控制节点，当前级栅极驱动单元的所述第十八晶体管的第二极连接至当前级栅极驱动单元的低电平节点，当前级栅极驱动单元的所述第十九晶体管的第一极连接至当前级栅极驱动单元的第二晶体管的第二极，当前级栅极驱动单元的所述第十九晶体管的第二极连接至当前级栅极驱动单元的低电平节点；当前级栅极驱动单元的所述第四晶体管的第一极输入的所述第一输入信号为第四时钟信号；
    其中第2至第M-4级栅极驱动单元中每一级栅极驱动单元的第三晶体管的第二极连接至低电平节点且所述第三晶体管的栅极输入的所述第一控制信号为第二脉冲信号。
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