WO2018126656A1 - 阵列基板行驱动单元、装置、驱动方法及显示装置 - Google Patents

阵列基板行驱动单元、装置、驱动方法及显示装置 Download PDF

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Publication number
WO2018126656A1
WO2018126656A1 PCT/CN2017/094820 CN2017094820W WO2018126656A1 WO 2018126656 A1 WO2018126656 A1 WO 2018126656A1 CN 2017094820 W CN2017094820 W CN 2017094820W WO 2018126656 A1 WO2018126656 A1 WO 2018126656A1
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Prior art keywords
pull
transistor
circuit
node
output
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PCT/CN2017/094820
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English (en)
French (fr)
Inventor
韩明夫
商广良
姚星
韩承佑
金志河
郑皓亮
袁丽君
王志冲
Original Assignee
京东方科技集团股份有限公司
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Priority to US15/751,066 priority Critical patent/US10902810B2/en
Publication of WO2018126656A1 publication Critical patent/WO2018126656A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to gate driving technology, and in particular to an array substrate row driving (GOA) device, method and display device.
  • GAA array substrate row driving
  • the driving circuit in the liquid crystal display is mainly completed by connecting an integrated circuit outside the liquid crystal panel.
  • integrating the peripheral driving circuit of the display and the pixel driving array on the same substrate has been a goal pursued in the display field.
  • TFT-based row and column driver circuits are important research directions for large-scale microelectronics. They may be applied to active display panels such as TFT-LCD and TFT-OLED, and may be applied to new displays such as transparent display, flexible display, and electronic tags.
  • the TFT row driving circuit includes a Gate-driver on Array (GOA) technology, which mainly includes an amorphous silicon (A-Si) TFT and an IGZO-TFT GOA circuit.
  • GOA Gate-driver on Array
  • A-Si amorphous silicon
  • IGZO-TFT GOA circuit a Gate-driver on Array
  • the GOA technology is a technology in which a gate driving circuit is directly fabricated on an array substrate to replace a driving chip fabricated by an external silicon chip. Since the GOA circuit can be directly fabricated around the panel, the process process is simplified, and the product cost can be reduced, and the integration of the liquid crystal panel can be improved, so that the panel tends to be thinner.
  • the leakage of the pull-up (PU) holding phase is increased due to the load of the input circuit, the reset circuit, and the pull-down circuit.
  • the invention provides an array substrate row driving unit, a device, a driving method and a display device.
  • Embodiments of the present invention provide a GOA unit including: an input circuit connected to an input signal a terminal and a pull-up node PU; a pull-down circuit connected to the first voltage signal terminal and the pull-up node PU; a pull-down control circuit connected to the pull-down circuit via the pull-down node PD; an output circuit connected to the clock signal terminal, the second a voltage signal terminal and a control circuit; a reset circuit connected to the reset signal terminal, the first voltage signal terminal and the pull-up node PU; and the control circuit connected to the pull-up node PU and the output circuit, wherein the input circuit is responsive Controlling a potential of the pull-up node PU at the received input signal; the output circuit generates an output signal in response to a clock signal input to the output circuit and a potential of the pull-up node PU; the control circuit is responsive to the output circuit The output signal disconnects its connection to the pull-up node PU.
  • the control circuit can include an inverter and a control switching element.
  • the control switching element may include a first transistor, a drain of the first transistor is connected to a gate signal end of the output circuit, a gate is connected to the inverter, and a source is connected to the source via a pull-up node PU The input circuit, the reset circuit, and the pull-down circuit.
  • the inverter may include second and third transistors, a gate and a drain of the second transistor may be connected to a third voltage signal terminal, a source may be connected to a gate of the first transistor, and the The drain of the third transistor.
  • the inverter may include second, third, and fourth transistors, and a drain of the second transistor and a gate and a drain of the fourth transistor may be connected to a DC high voltage signal, the second A gate of the transistor may be coupled to a source of the fourth transistor, and a source of the second transistor may be coupled to a gate of the first transistor and a drain of the third transistor.
  • the source of the third transistor can be coupled to a DC low voltage signal
  • the drain can be coupled to the source of the second transistor
  • the gate can be coupled to an output of the output circuit.
  • the resistance of the second transistor may be greater than the resistance of the third transistor.
  • the clock signal, the first voltage signal, the second voltage signal, and the third voltage signal may be input to the GOA unit.
  • Embodiments of the present invention also provide a driving method for a GOA unit according to the present invention, the driving method comprising the steps of: controlling, by an input circuit, a potential of the pull-up node PU in response to the received input signal;
  • the output circuit generates an output signal in response to a clock signal input to the output circuit and a potential of the pull-up node PU; the control circuit disconnects its connection with the pull-up node PU in response to the output signal generated by the output circuit.
  • control circuit may disconnect the source of the first transistor included in the control circuit from the pull-up node PU in response to an output signal generated by the output circuit.
  • the driving method of the GOA unit may further include: after disconnecting the source of the first transistor and the pull-up node PU, the control circuit turns on the source of the first transistor in response to a clock signal input to the output circuit Pull up the connection of the node PU.
  • Embodiments of the present invention also provide a GOA apparatus comprising a plurality of cascaded GOA units in accordance with the present invention.
  • the signal input of each GOA unit except the first GOA unit and the last GOA unit is connected to the output of the upper-level GOA unit adjacent thereto, except for the first
  • the reset signal terminal of each GOA unit other than the GOA unit and the last GOA unit is connected to the output terminal of the next-stage GOA unit adjacent thereto.
  • Embodiments of the present invention also provide a display device comprising a GOA device in accordance with the present invention.
  • the clock signal coupling effect can be increased, leakage in the PU holding phase can be reduced, and the turn-on voltage of the output transistor can be increased, thereby enabling significant transistor driving capability. Upgrade.
  • FIG. 1 is a schematic diagram showing the functional structure of each GOA unit in a gate driving circuit known to the inventors;
  • FIG. 2 is a schematic diagram showing the specific composition of a GOA unit known to the inventors
  • 3 is a timing chart of input and output signals of a GOA unit known to the inventors
  • FIG. 4 is a schematic diagram showing the functional structure of each GOA unit in a gate driving circuit according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a specific structure of a GOA unit according to a first embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a specific structure of a GOA unit according to a second embodiment of the present invention.
  • FIG. 7 is a timing diagram of input and output signals of a GOA unit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a control circuit in a GOA unit according to an embodiment of the present invention.
  • 9(a) and 9(b) are schematic diagrams showing the constitution of an inverter according to a first embodiment of the present invention.
  • 10(a) and 10(b) are schematic diagrams showing the structure of an inverter according to a second embodiment of the present invention.
  • Figure 11 is a comparison diagram of the voltage waveform of the pull-up node known to the inventors and the voltage waveform of the pull-up node of the embodiment of the present invention.
  • FIG. 12 is a flowchart of an implementation of a method for operating a GOA unit according to an embodiment of the present invention.
  • the indication that the first component is "connected” to the second component can include the case where the first component is electrically connected to the second component and some other component is interposed therebetween, and wherein The case where the first component is "directly connected” to the second component.
  • the representation of the first component "comprising" the second component is meant to include further components, and the possibility of adding other components will not be excluded, unless the contrary description is specifically indicated in the context.
  • the thin film transistor used in the embodiment of the present invention is symmetrical in source and drain, and all of its source and drain are interchangeable in name.
  • the thin film transistor can be divided into an N-type transistor or a P-type transistor according to the characteristics of the thin film transistor.
  • the first pole when the N-type thin film transistor is used, the first pole can be the source, and the second pole can be Is the drain.
  • the thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor.
  • the thin film transistor is an N-type transistor as an example. When the signal of the gate is at a high level, the thin film transistor is turned on. However, it can be understood that when a P-type transistor is used, the timing of the driving signal needs to be adjusted accordingly.
  • FIG. 1 is a schematic diagram showing the functional structure of each GOA unit in a gate driving circuit known to the inventors.
  • FIG. 1 is a schematic diagram showing the functional structure of each GOA unit in the GOA circuit known to the inventors.
  • the GOA circuit has a multi-level GOA unit, and each stage of the GOA unit can drive two adjacent rows of pixels. Specifically, each level of the GOA unit drives adjacent two rows of pixels through two gate drive lines, and outputs high power in the GOA unit. When the signal is flat, the corresponding adjacent two rows of pixels are driven to be turned on by the corresponding gate driving lines, so that the adjacent two rows of pixels can receive the data signal; and the low level signal is outputted in the GOA unit. When the corresponding two rows of pixels are turned off, the reception of the data signal is stopped.
  • the multi-level GOA unit in the gate driving circuit sequentially outputs a high level signal, and drives one by one in units of two adjacent pixels.
  • each GOA unit includes an input circuit 10, a pull-down control circuit 20, a pull-down circuit 30, a reset circuit 40, and an output circuit 50.
  • the input circuit 10 is connected to the input signal terminal and the pull-up node PU.
  • the pull-down control circuit 20 is connected to the pull-down circuit 30 via the pull-down node PD.
  • the pull-down circuit 30 is connected to the pull-up node PU and the pull-down node PD.
  • the reset circuit 40 is connected to the reset signal terminal, the pull-up node PU, and the pull-down node PD.
  • the output circuit 50 is connected to the clock signal terminal, the pull-up node PU, and the output terminal. The output circuit 50 is turned on when the CLK is at a high level, thereby outputting an output signal as an input signal of the next stage.
  • Fig. 2 is a schematic view showing the specific constitution of a GOA unit known to the inventors.
  • each stage of the GOA unit includes an input circuit 10, a pull-down control circuit 20, a pull-down circuit 30, a reset circuit 40, and an output circuit 50.
  • the input circuit 10 supplies a high level voltage signal to the pull-up node PU in response to an output signal of the upper stage GOA unit.
  • the pull-down control circuit 20 turns on the pull-down circuit when the pull-up node PU voltage is at a high level, thereby causing the pull-down node PD voltage to decrease.
  • the reset circuit 40 is connected to the reset signal terminal Reset, the first DC low-level voltage signal terminal LVGL (the first voltage signal terminal) and the pull-up node PU, and the first DC is responsive to the reset signal Reset outputted by the reset signal terminal.
  • the low level voltage signal LVGL is supplied to the pull up node PU.
  • the output circuit 50 is turned on when the CLK is high level, and the PU voltage of the pull-up node is further increased, thereby completing the charging process of the transistor.
  • the pull-down circuit 30 supplies the first low-level voltage signal LVGL to the pull-up node PU and the output terminal Output in response to the voltage signal of the pull-down node PD.
  • ⁇ V (Vgh-Vgl)*(CgsM3+CgdM3+CgsM11+CgdM11+C1)/
  • FIG. 4 is a schematic diagram showing the functional structure of each GOA unit in a gate driving circuit according to an embodiment of the present invention.
  • a GOA device may typically include a plurality of cascaded GOA units, each GOA unit including an input circuit 10, a pull-down control circuit 20, a pull-down circuit 30, a reset circuit 40, an output circuit 50, and a control circuit 60.
  • a GOA device can be applied to various displays such as a liquid crystal display.
  • the control circuit 60 is connected between the pull-up node PU and the output circuit 50.
  • One end of the path 60 is connected to the input circuit 10, the reset circuit 40, and the pull-down circuit 30 via the pull-up node PU, and the other end is connected to the output circuit 50.
  • the output circuit 50 is responsive to a level of the clock signal CLK input to the output circuit, specifically in response to a high level of CLK, to generate an output signal.
  • the control circuit 60 can cut off the connection with the pull-up node PU, that is, disconnect the input circuit, the reset circuit, and the pull-down circuit, in response to the output signal generated by the output circuit 50, thereby forming a new pull-up node PU2.
  • FIG. 5 is a schematic diagram showing the specific composition of a GOA unit according to a first embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing the specific structure of a GOA unit according to a second embodiment of the present invention.
  • 7 is a timing diagram of input and output signals of a GOA unit in accordance with an embodiment of the present invention.
  • the timing of the input and output signals of the GOA unit known to the inventors is as shown in FIG.
  • the input and output signal timing of the GOA unit of the present invention is as shown in FIG. 7, wherein CLK is the clock signal of the GOA unit; input is the input signal of the input circuit, that is, the output signal of the GOA unit of the previous stage; PU represents the pull-up point.
  • Vd_1 and Pd_2 represent the voltage of the first pull-down point and the second pull-down point
  • Outc and Gout are the output signals of the output circuit
  • Reset is the reset input of the GOA circuit, that is, the output signal of the next-stage GOA unit
  • Vddo And Vdde are alternating high-level voltage signals and low-level voltage signals
  • VGH is a DC high-level voltage signal (third voltage signal terminal), and the voltage thereof can be, for example but not limited to, 20-30V
  • LVGL and VGL respectively
  • the voltage of the first DC low voltage signal LVGL may be, for example but not limited to, -10V
  • the second DC low voltage signal VGL The voltage can be, for example, but not limited to, -8V.
  • the input circuit 10 is coupled to the signal input terminal Input and the pull-up node PU, and is configured to provide a high-level voltage signal Input to the pull-up node PU in response to the input signal Input of the signal input terminal.
  • the input circuit 10 includes a transistor M1 whose gate and drain are connected to a signal input terminal Input and whose source is connected to a pull-up node PU.
  • the pull-up node PU voltage is at a high level, and the pull-down circuit is turned on, thereby lowering the pull-down node PD voltage.
  • the specific implementation structure, control mode, and the like of the input circuit 10 do not constitute a limitation on the embodiments of the present disclosure.
  • the reset circuit 40 is connected to the reset signal terminal Reset, the first DC low-level voltage signal terminal LVGL and the pull-up node PU, and is configured to respond to the reset signal Reset outputted by the reset signal terminal to set the first DC low-level voltage signal LVGL.
  • the reset circuit 40 includes transistors M2, M10A, and M10B. The gate of transistor M2 is connected to the Reset terminal, and the drain is connected to the drain of M10A and M10B. The pole is connected to the first DC low voltage signal LVGL terminal.
  • the pull-down control circuit 20 is connected to the high-level voltage signal terminal Vdde or Vddo, the pull-down circuit 30, and the pull-down nodes Pd_1 and Pd_2, and is configured to provide the first low-level voltage signal LVGL to the pull-down in response to the voltage signal of the pull-up node PU.
  • the nodes Pd_1 and Pd_2; and the high-level voltage signal Vdde or Vddo are supplied to the pull-down nodes Pd_1 and Pd_2 in response to the high-level voltage signal Vdde or Vddo.
  • the pull-down control circuit 20 when the pull-up node PU is at a high level, the transistor M6A and the transistor M6B are turned on, and the pull-down node Pd_1 or Pd_2 is pulled low, that is, the pull-down is equal to or close to the low.
  • the level of the level When the pull-up node PU is at a low level, the transistor M6A and the transistor M6B are turned off, while the high-level voltage Vddo or Vdde turns on the transistor M5A and the transistor M5B, so that the pull-down node Pd_1 or Pd_2 is at a high level.
  • the pull-down control circuit 20 described above is merely an example, and it may have other structures.
  • the high-level voltages Vddo and Vdde are inverted in timing, so that the two pull-down circuits operate alternately, thereby achieving an effect of prolonging the service life.
  • the pull-down circuit 30 is connected to the pull-down control circuit 20, the pull-up node PU, the first DC low-level voltage signal terminal LVGL, the pull-down node PD, and the output circuit 50, configured to respond to the voltage signal of the pull-down node PD, to be the first
  • the DC low level voltage signal LVGL is supplied to the pull-up node PU and the output circuit 50.
  • the pull-down circuit 30 includes a transistor M8A, a transistor M6A, a transistor M8B, and a transistor M6B.
  • the gates of the M8A, M6A, M8B, and M6B are connected to the pull-up node PU, and the source is connected to the first DC low-level voltage signal terminal LVGL, and the transistor M8A.
  • the drain of M8B is connected to the pull-down control circuit 20, the drain of the transistor M6A is connected to the first pull-down node Pd_1, and the drain of the transistor M6B is connected to the second pull-down node Pd_2.
  • the output circuit 50 is connected to the clock signal terminal CLK, the second DC low-level voltage signal terminal VGL (second voltage signal terminal), the control circuit 60, and the output terminals Outc and Gout of the present stage, and is configured to be input in response to the clock signal terminal.
  • the clock signal CLK provides the output of the stage Outc and Gout.
  • the circuit 50 includes output transistors M3 and M11, and noise reduction transistors M12A, M12B, M13A, and M13B.
  • the drains of the output transistors M3 and M11 are connected to the clock signal terminal CLK, and the gate is connected to the control circuit 60.
  • the source of the output transistor M3 is connected to the drains of the noise reduction transistors M13A and M13B, and the source of the output transistor M11 is connected to the drains of the noise reduction transistors M12A and M12B.
  • the sources of the noise reduction transistors M12A and M12B are connected to the first DC low level voltage signal terminal LVGL, the gate of the noise reduction transistor M12A is connected to the first pull-down point Pd_1, and the gate of the noise reduction transistor M12B is connected to the Two pull-down points Pd_2.
  • the sources of the noise reduction transistors M13A and M13B are connected to the second DC low level voltage The signal terminal VGL, the gate of the noise reduction transistor M13A is connected to the first pull-down point Pd_1, and the gate of the noise reduction transistor M13B is connected to the second pull-down point Pd_2.
  • the output circuit 50 performs output according to the trigger of the rising edge of the clock signal when the pull-up node PU voltage is at the high level, and stops the output according to the trigger of the falling edge of the clock signal.
  • FIG. 8 is a schematic diagram of a control circuit in a GOA unit in accordance with an embodiment of the present invention.
  • control circuit includes an inverter and a control switching element, one end of which is connected to the rising node PU and the other end is connected to the output circuit 50.
  • control switching element is a first transistor M16 whose drain is connected to the gate signal terminal of the output circuit (ie, the pull-up node PU2 formed later), the gate Connected to one end of the inverter, the source is connected to the input circuit, the reset circuit, and the pull-down circuit via the pull-up node PU.
  • the inverter includes a second transistor M18 and a third transistor M17 connected in series.
  • the resistance of the second transistor M18 is greater than the resistance of the third transistor M17.
  • the gate of the second transistor M18 is connected to the VGH, that is, the DC high voltage signal, so that the second transistor M18 is always in an on state.
  • the drain of the third transistor M17 is connected to the source of the second transistor M18 and is connected to the gate of the first transistor M16. Since the second transistor M18 is turned on, the drain of the third transistor M17, the source of the second transistor M18, and the gate of the first transistor M16 each have a high level, and the first transistor M16 is thus turned on. Further, in most cases, since the levels of the output signals Outc and Gout are low, the third transistor M17 is turned off.
  • the gate drive signal OUTPUT_n-1 When the gate drive signal OUTPUT_n-1 is outputted by the upper stage GOA unit, that is, when the input of the GOA unit of the present stage is at a high level, the transistor M1 of the input circuit is turned on, causing the PU voltage of the pull-up node to rise. The voltage of the boosted pull-up node PU causes the output transistors M3 and M11 to conduct. Thereafter, when the clock signal CLK of the output circuit 50 transitions from a low level to a high level, since the output transistors M3 and M11 are turned on, the high level signal of the clock signal CLK is transmitted to the gate of M3 and the gate of M11. pole.
  • the source of M11 that is, the output of Outc
  • the source of M3, that is, the output of Gout outputs a high-level signal Gout.
  • the high level signal Outc is connected to the gate of the third transistor M17 in the inverter such that the third transistor M17 is turned on.
  • the third transistor M17 is turned on, since the resistance of the third transistor M17 is smaller than the resistance of the second transistor M18, the electric average of the drain of M17, the source of M18, and the gate of M16 is lowered.
  • the lowering of the gate level of M16 causes the closing of the first transistor M16 Broken.
  • the turn-off of the first transistor M16 causes the connection of the control circuit 60 to the pull-up node PU to be disconnected, that is, the connection of the control circuit 60 to the input circuit, the reset circuit and the pull-down circuit is disconnected, which is equivalent to disconnecting the transistor M1.
  • ⁇ V' (Vgh - Vgl) * (CgsM3 + CgdM3 + CgsM11 + CgdM11 + C1) /
  • the transistor M17 In the case where the output of the Outc output and the Gout output are stopped, the transistor M17 is turned off. Since the DC high level voltage signal VGH is always applied to the drain and gate of the second transistor M18, the second transistor M18 remains turned on. The level of the drain of M17, the source of M18, and the gate of M16 rises. The rise of the gate level of M16 directly causes the first transistor M16 to be turned on. The conduction of the first transistor M16 causes the connection of the control circuit 60 to the pull-up node PU to resume.
  • next stage GOA unit When the next stage GOA unit outputs OUTPUT_n+2, that is, when the RESET of the GOA unit of this stage is high level, M2 is turned on, discharging the PU of the pull-up node, and pulling down the voltage of the pull-up node PU, so that the gates of M3 and M11 are made. The voltage is pulled low, M3 and M11 are disconnected, CLK cannot be sent to the gates of M3 and M11, M3 and M11 remain off, and the OUTPUT_n output and OUTPUT_n+1 output of the GOA unit of this stage stop output.
  • circuit structure of Fig. 6 is substantially the same as that of Fig. 5 except for the inverter portion.
  • the inverter of FIG. 6 includes a second transistor M18, a third transistor M17, and a fourth transistor M19, wherein the drain of the second transistor M18 and the gate and the drain of the fourth transistor M19 are both connected to a DC high voltage signal.
  • the gate of the second transistor M18 is connected to the source of the fourth transistor M19, and the source of the second transistor M18 is connected to the gate of the first transistor M16 and the drain of the third transistor M17.
  • the inverter structure of FIG. 6 can compensate for the output attenuation as compared with the inverter structure of FIG.
  • the gate voltage of the first transistor M16 is lowered in one step, thereby achieving a better anti-leakage effect.
  • FIG. 9(a)-10(b) are schematic diagrams showing the constitution of an inverter according to a first embodiment of the present invention.
  • 10(a) and 10(b) are schematic diagrams showing the constitution of an inverter according to a second embodiment of the present invention.
  • Fig. 9(a) corresponds to the inverter structure in the first embodiment of the present invention
  • Fig. 9(a) corresponds to the inverter structure in the second embodiment of the present invention.
  • the second embodiment can further increase the gate voltage of the second transistor M18, thereby compensating for output attenuation, achieving a better isolation effect of the high control circuit.
  • inverter structure of the present invention is not limited to the above structure, but any other suitable inverter may be employed depending on the actual application.
  • Figure 11 is a comparison diagram of the pull-up node voltage waveform known to the inventors and the pull-up node voltage waveform of the embodiment of the present invention.
  • the waveform of the black thick line 111 is the voltage of the new pull-up node PU2 of the present invention
  • the waveform of the black thin line 112 is the pull-up node PU voltage known to the inventors.
  • the black thick line 111 is significantly higher than the black thin line 112, that is, the voltage of the new pull-up node PU2 is significantly increased. Further, the slope of the thick black line 111 is significantly smaller than that of the black thin line 112, which indicates that the leakage phenomenon in the PU holding stage is improved.
  • the invention isolates the clock-coupled transistor in the GOA circuit from other voltage dividing transistors by the insertion of the control circuit, enhances the clock coupling effect, and realizes the voltage increase of the pull-up node and the leakage reduction. This causes the voltage at the gate control terminals of the transistors M3 and M11 of the output circuit to be significantly increased, thereby reducing the turn-on time of the transistors M3 and M11, further enhancing the driving ability of the transistors M3 and M11.
  • FIG. 12 is a flowchart showing an implementation of a driving method of a GOA unit according to an embodiment of the present invention.
  • the method may mainly include the following steps:
  • Step S1 The input circuit controls the potential of the pull-up node PU in response to the received input signal. That is, the input circuit receives the high-level voltage signal output by the upper-level GOA unit as an input signal, and turns on the transistor M1 in response to the high-level voltage signal, thereby controlling the potential of the pull-up node PU to change to a high level. .
  • Step S2 The output circuit generates an output signal in response to a clock signal input to the output circuit and a potential of the pull-up node PU. That is, when the clock signal CLK of the output circuit 50 transitions from a low level to a high level, since the output transistors M3 and M11 are turned on, the high level signal of the clock signal CLK is transmitted to the gate of M3 and the gate of M11. pole.
  • the source of M11 that is, the output of Outc, outputs a high level signal.
  • Outc, and the source of M3, that is, the Gout output outputs a high level signal Gout.
  • Step S3 The control circuit disconnects the connection with the pull-up node PU, that is, disconnects the input circuit, the reset circuit, and the pull-down circuit, in response to the output signal generated by the output circuit.
  • the control circuit turns off the first transistor M16 by the action of the inverter, thereby disconnecting the input circuit, the reset circuit and the pull-down circuit, thereby improving the new pull-up node.
  • the source of M11 that is, the high-level signal Outc outputted from the output of the Outc, causes the third transistor M17 to be turned on. Since the resistance of the third transistor M17 is smaller than the resistance of the second transistor M18, the electric average of the drain of M17, the source of M18, and the gate of M16 is lowered, which causes the first transistor M16 to be turned off. This is equivalent to removing the loads of the transistors M1, M2, M6A, M6B, M8A, M8B, M10A, and M10B, thereby enhancing the clock coupling effect and further increasing the output voltage of the drain of the first transistor M16.
  • step S3 when the falling edge of the clock signal of the output circuit comes, the output transistors M3 and M11 are turned off, and the level of the Outc output and the Gout output are rapidly pulled low.
  • the transistor M17 is turned off, and the levels of the drain of M17, the source of M18, and the gate of M16 rise.
  • the gate level of the first transistor M16 is raised such that the first transistor M16 is turned on.
  • the conduction of the first transistor M16 causes the connection of the control circuit 60 to the pull-up node PU to resume, thereby turning on the connection of the source of the first transistor M16 to the pull-up node PU.
  • Components included in embodiments of the invention are not limited to software or hardware, and may be configured to be stored in an addressable storage medium and run on one or more processors.
  • these components may include components such as software components, object-oriented components, class components, and task components, processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuitry , data, databases, data structures, tables, arrays, and variables.
  • the functionality provided in the components and corresponding components can be combined in fewer components or can be further separated into additional components.
  • each component described as a single component can be distributed and practiced, and similarly, components described as distributed can also be practiced in an integrated form.

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Abstract

一种阵列基板行驱动单元、装置、驱动方法及显示装置。阵列基板行驱动单元包括：输入电路(10)，连接到输入信号端(Input)和上拉节点(PU)；下拉电路(30)，连接到第一电压信号端(LVGL)和上拉节点(PU)；下拉控制电路(20)，经由下拉节点(PD)连接到下拉电路(30)；输出电路(50)，连接到时钟信号端(CLK)、第二电压信号端(VGL)和控制电路(60)；复位电路(40)，连接到复位信号端(Reset)、第一电压信号端(LVGL)和上拉节点(PU)；和控制电路(60)，连接到上拉节点(PU)和输出电路(50)。其中输入电路(10)响应于所接收的输入信号(input)，控制上拉节点(PU)的电位(S1)；输出电路(50)响应于输入到输出电路(50)的时钟信号(CLK)以及上拉节点(PU)的电位，生成输出信号(S2)；控制电路(60)响应于输出电路所生成的输出信号(Outc、Gout)，断开其与上拉节点（PU）的连接(S3)。

Description

阵列基板行驱动单元、装置、驱动方法及显示装置 技术领域
本发明涉及栅极驱动技术，尤其涉及一种阵列基板行驱动(GOA)装置、方法及显示装置。
背景技术
在现有技术中，液晶显示器中的驱动电路主要是通过在液晶面板外部连接集成电路来完成的。长期以来，将显示器的周边驱动电路与像素驱动阵列集成于同一基板一直是显示领域追求的目标。基于TFT的行列驱动电路是大尺寸微电子学的重要研究方向,其可能应用于TFT-LCD、TFT-OLED等有源显示面板，并可能应用于透明显示、柔性显示、电子标签等新型显示器。
TFT行驱动电路包括阵列基板行驱动(Gate-driver on Array,简称GOA)技术，其主要包括非晶硅(A-Si)TFT以及IGZO-TFT的GOA电路。GOA技术是直接将栅极驱动电路制作在阵列基板上，以替代外接硅芯片制作的驱动芯片的一种技术。由于GOA电路可直接制作在面板周围，简化了制程工艺，而且还可降低产品成本，提高液晶面板的集成度，从而使面板趋向于更加薄型化。
然而，在大尺寸高分辨率LCD产品中，晶体管充电时间大幅减少，对于8K A-Si产品，一行像素的开启时间只有3.7μs，实际有效的像素充电时间则更少，因此即使充电时间0.1μs量级的增加都可以促使充电率的明显提升，实现更高显示质量。
此外，在现有GOA电路中，由于输入电路、复位电路以及下拉电路的负载，导致拉高(PU)保持阶段漏电增加。
有鉴于此，在当前情况下，迫切希望提高上拉节点电压，降低PU保持阶段漏电，从而增强GOA电路驱动能力，降低像素的下降时间，进而增加充电时间。
发明内容
本发明提供了一种阵列基板行驱动单元、装置、驱动方法及显示装置。
本发明的实施例提供了一种GOA单元，包括：输入电路，连接到输入信 号端和上拉节点PU；下拉电路，连接到第一电压信号端和上拉节点PU；下拉控制电路，经由下拉节点PD连接到所述下拉电路；输出电路，连接到时钟信号端、第二电压信号端和控制电路；复位电路，连接到复位信号端、第一电压信号端和上拉节点PU；和该控制电路，连接到上拉节点PU和所述输出电路，其中所述输入电路响应于所接收的输入信号，控制上拉节点PU的电位；所述输出电路响应于输入到输出电路的时钟信号以及上拉节点PU的电位，生成输出信号；所述控制电路响应于输出电路所生成的输出信号，断开其与上拉节点PU的连接。
所述控制电路可包括反相器和控制开关元件。
所述控制开关元件可包括第一晶体管，所述第一晶体管的漏极连接到所述输出电路的栅极信号端，栅极连接到所述反相器，源极经由上拉节点PU连接到所述输入电路、所述复位电路和所述下拉电路。
所述反相器可包括第二和第三晶体管，所述第二晶体管的栅极与漏极可连接到第三电压信号端，源极可连接到所述第一晶体管的栅极以及所述第三晶体管的漏极。
所述反相器可包括第二、第三和第四晶体管，所述第二晶体管的漏极以及所述第四晶体管的栅极和漏极均可连接到直流高电压信号，所述第二晶体管的栅极可连接到所述第四晶体管的源极，所述第二晶体管的源极可连接到所述第一晶体管的栅极以及所述第三晶体管的漏极。
所述第三晶体管的源极可连接到直流低电压信号，漏极可连接到所述第二晶体管的源极，并且栅极可连接到所述输出电路的输出端。
所述第二晶体管的电阻可大于所述第三晶体管的电阻。
所述时钟信号、所述第一电压信号、所述第二电压信号和所述第三电压信号可输入到所述GOA单元。
本发明的实施例还提供了一种用于根据本发明的GOA单元的驱动方法，所述驱动方法包括以下步骤：由输入电路响应于所接收的输入信号，控制上拉节点PU的电位；由输出电路响应于输入到输出电路的时钟信号以及上拉节点PU的电位，生成输出信号；由控制电路响应于输出电路所生成的输出信号，断开其与上拉节点PU的连接。
在所述GOA单元的驱动方法中，控制电路可响应于输出电路所生成的输出信号，断开该控制电路中包括的第一晶体管的源极与上拉节点PU的连接。
所述GOA单元的驱动方法可进一步包括：在断开第一晶体管的源极与上拉节点PU的连接之后，控制电路响应于输入到输出电路的时钟信号，接通第一晶体管的源极与上拉节点PU的连接。
本发明的实施例还提供了一种GOA装置，包括级联的多个根据本发明的GOA单元。
在所述级联的多个GOA单元中，除了第一GOA单元和最后GOA单元之外的每个GOA单元的信号输入端连接到与其相邻的上一级GOA单元的输出端，除了第一GOA单元和最后GOA单元之外的每个GOA单元的复位信号端连接到与其相邻的下一级GOA单元的输出端。
本发明的实施例还提供了一种显示装置，包括根据本发明的GOA装置。
根据本发明，通过提供这样的阵列基板行驱动单元、装置、方法及显示装置，可以增加时钟信号耦合效果，减少PU保持阶段的漏电，增加输出晶体管的开启电压，从而能实现晶体管驱动能力的显著提升。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本发明的限制。
图1为本发明人已知的栅极驱动电路中每个GOA单元的功能结构示意图；
图2为本发明人已知的GOA单元的具体组成结构示意图；
图3为本发明人已知的GOA单元的输入输出信号时序图；
图4为根据本发明实施例的栅极驱动电路中每个GOA单元的功能结构示意图；
图5为根据本发明第一实施例的GOA单元的具体组成结构示意图；
图6为根据本发明第二实施例的GOA单元的具体组成结构示意图；
图7为根据本发明实施例的GOA单元的输入输出信号的时序图；
图8为根据本发明实施例的GOA单元中的控制电路的示意图；
图9(a)和9(b)为根据本发明第一实施例的反相器的组成结构示意图；
图10(a)和10(b)为根据本发明第二实施例的反相器的组成结构示意图；
图11为本发明人已知的上拉节点电压波形与本发明实施例的上拉节点电压波形的对照图；和
图12为根据本发明实施例的GOA单元的操作方法的实现流程图。
具体实施方式
参考附图来描述本发明的实施例，以便详细描述本发明，使得具有本发明所属技术领域的普通知识的技术人员能容易地实践本发明。然而，本发明可按照各种形式实现，并且不受到以下实施例的限制。在图中，为了本发明的清楚描述，将省略与本发明不直接相关的组件的说明，并且贯穿图中使用相同附图标记来指定相同或相似元件。
此外，贯穿整个说明书，应理解的是，指示第一组件“连接”到第二组件的表示可包括其中第一组件电气连接到第二组件并在其间插入有某一其它组件的情况、以及其中第一组件“直接连接”到第二组件的情况。此外，应理解的是，指示第一组件“包括”第二组件的表示意味着可进一步包括其它组件，不排除将添加其它组件的可能性，除非在上下文中特别指出相反的描述。
需要说明的是，本发明实施例中采用的薄膜晶体管是源极和漏极对称的，所有其源极和漏极在名称上可以互换。此外，按照薄膜晶体管的特性区分可以将薄膜晶体管分为N型晶体管或P型晶体管，在本公开实施例中，当采用N型薄膜晶体管时，其第一极可以是源极，第二极可以是漏极。本公开实施例中所采用的薄膜晶体管可以为N型晶体管，也可以为P型晶体管。在以下实施例中，均薄膜晶体管是N型晶体管为例进行说明，即栅极的信号是高电平时，薄膜晶体管导通。但是可以理解的是，当采用P型晶体管时，需要相应调整驱动信号的时序。
下面，将参考附图来详细描述本发明的优选实施例。
图1为本发明人已知的栅极驱动电路中每个GOA单元的功能结构示意图。
如附图1所示为本发明人已知的GOA电路中每个GOA单元的功能结构示意图。该GOA电路具有多级GOA单元，每级GOA单元可以驱动相邻的两行像素，具体地，每级GOA单元通过两条栅极驱动线驱动相邻的两行像素，在GOA单元输出高电平信号时，通过相应的栅极驱动线驱动相应的相邻两行像素打开，使得所述相邻两行像素能够接收数据信号；在GOA单元输出低电平信号 时，相应的相邻两行像素关闭，停止接收数据信号。如此，在一帧画面里，栅极驱动电路中的多级GOA单元，依次输出高电平信号，以相邻两行像素为单位逐一进行驱动。
如图1所示，每一GOA单元包括输入电路10、下拉控制电路20、下拉电路30、复位电路40和输出电路50。输入电路10连接到输入信号端和上拉节点PU。下拉控制电路20经由下拉节点PD连接到下拉电路30。所述下拉电路30连接到上拉节点PU和下拉节点PD。复位电路40连接到复位信号端、上拉节点PU和下拉节点PD。输出电路50连接到时钟信号端、上拉节点PU和输出端。输出电路50在所述CLK高电平时导通，从而输出输出信号作为下一级的输入信号。
图2为本发明人已知的GOA单元的具体组成结构示意图。具体地，如图1和2所示，每级GOA单元包含输入电路10、下拉控制电路20、下拉电路30、复位电路40和输出电路50。输入电路10响应于上一级GOA单元的输出信号，将高电平电压信号提供给上拉节点PU。下拉控制电路20在上拉节点PU电压为高电平时，导通下拉电路，从而使得下拉节点PD电压降低。复位电路40连接复位信号端Reset、第一直流低电平电压信号端LVGL(第一电压信号端)和上拉节点PU，其响应于复位信号端输出的复位信号Reset，将第一直流低电平电压信号LVGL提供给上拉节点PU。输出电路50在所述CLK高电平时导通，上拉节点PU电压进一步升高，从而完成晶体管的充电过程。下拉电路30响应下拉节点PD的电压信号，将第一低电平电压信号LVGL提供给上拉节点PU和输出端Output。
在时钟信号上升沿到来时，所述上拉节点PU的电压增加如下：
ΔV＝(Vgh-Vgl)*(CgsM3+CgdM3+CgsM11+CgdM11+C1)/
(CgsM3+CgdM3+CgsM11+CgdM11+C1+2*CgsM8+2*CgdM8+CgsM1+2CgdM10+CgdM2+2*CgsM6+2*CgdM6)           等式(1)
图4为根据本发明实施例的栅极驱动电路中每个GOA单元的功能结构示意图。
根据本发明实施例的GOA装置可典型地包括多个级联的GOA单元，每一GOA单元包括输入电路10、下拉控制电路20、下拉电路30、复位电路40、输出电路50和控制电路60。根据本发明实施例的GOA装置可应用到诸如液晶显示器等各种显示器。
如图4中，控制电路60连接在上拉节点PU和输出电路50之间，该控制电 路60的一端经由上拉节点PU连接到所述输入电路10、复位电路40和下拉电路30，另一端连接到输出电路50。输出电路50能响应于输入到输出电路的时钟信号CLK的电平，具体是响应于CLK的高电平，生成输出信号。控制电路60能响应于输出电路50生成的输出信号，切断与上拉节点PU的连接，也就是，切断与所述输入电路、复位电路和下拉电路的连接，从而形成新的上拉节点PU2。
图5为根据本发明第一实施例的GOA单元的具体组成结构示意图。图6为根据本发明第二实施例的GOA单元的具体组成结构示意图。图7为根据本发明实施例的GOA单元的输入输出信号的时序图。
本发明人已知的GOA单元的输入输出信号时序如图3所示。本发明的GOA单元的输入输出信号时序如图7所示，其中，CLK是GOA单元的时钟信号；input是输入电路的输入信号，也就是上一级GOA单元的输出信号；PU代表上拉点的电压；Pd_1和Pd_2代表第一下拉点和第二下拉点的电压；Outc和Gout是输出电路的输出信号；Reset是GOA电路的复位输入，也就是下一级GOA单元的输出信号；Vddo和Vdde是交替变化的高电平电压信号和低电平电压信号；VGH为直流高电平电压信号(第三电压信号端)，其电压可以例如是但不限于20-30V；LVGL和VGL分别为第一直流低电平电压信号和第二直流低电平电压信号，第一直流低电平电压信号LVGL的电压可以例如是但不限于-10V，第二直流低电平电压信号VGL的电压可以例如是但不限于-8V。
下面结合图5-7进行具体描述。
在图5中，输入电路10连接信号输入端Input、和上拉节点PU，被配置以响应信号输入端的输入信号Input，将高电平电压信号Input提供给上拉节点PU。
输入电路10包括晶体管M1，其栅极和漏极连接到信号输入端Input，源极连接到上拉节点PU。当输入信号input跳变为高电平时，上拉节点PU电压为高电平，下拉电路导通，由此降低下拉节点PD电压。输入电路10的具体实现结构和控制方式等不构成对本公开实施例的限制。
复位电路40连接复位信号端Reset、第一直流低电平电压信号端LVGL和上拉节点PU，被配置以响应复位信号端输出的复位信号Reset，将第一直流低电平电压信号LVGL提供给上拉节点PU。复位电路40包括晶体管M2、M10A和M10B。晶体管M2的栅极连接Reset端，漏极连接M10A和M10B的漏极，源 极连接第一直流低电平电压信号LVGL端。
下拉控制电路20连接高电平电压信号端Vdde或Vddo、下拉电路30和下拉节点Pd_1和Pd_2，被配置以响应于上拉节点PU的电压信号，将第一低电平电压信号LVGL提供给下拉节点Pd_1和Pd_2；以及响应于高电平电压信号Vdde或Vddo，将高电平电压信号Vdde或Vddo提供给下拉节点Pd_1和Pd_2。
具体来说，在下拉控制电路20中，当上拉节点PU为高电平时，晶体管M6A和晶体管M6B导通，将下拉节点Pd_1或Pd_2拉为低电平，即下拉为等于或接近所述低电平的电平。当上拉节点PU为低电平时，晶体管M6A和晶体管M6B截止，同时高电平电压Vddo或Vdde导通晶体管M5A和晶体管M5B，使得下拉节点Pd_1或Pd_2处于高电平。
上述的下拉控制电路20仅仅是示例，其还可以具有其它结构。高电平电压Vddo和Vdde在时序上反相，使得两个下拉电路交替工作，从而达到延长使用寿命的效果。
下拉电路30连接到下拉控制电路20、上拉节点PU、第一直流低电平电压信号端LVGL、下拉节点PD和输出电路50，被配置以响应于下拉节点PD的电压信号，将第一直流低电平电压信号LVGL提供给上拉节点PU和输出电路50。
下拉电路30包括晶体管M8A、晶体管M6A、晶体管M8B、晶体管M6B，其中M8A、M6A、M8B、M6B的栅极连接上拉节点PU，源极连接第一直流低电平电压信号端LVGL，晶体管M8A和M8B的漏极连接到下拉控制电路20，晶体管M6A的漏极连接到第一下拉节点Pd_1，并且晶体管M6B的漏极连接到第二下拉节点Pd_2。
输出电路50连接到时钟信号端CLK、第二直流低电平电压信号端VGL(第二电压信号端)、控制电路60和本级输出端Outc和Gout，被配置以响应于时钟信号端输入的时钟信号CLK，而提供本级输出Outc和Gout。
电路50包括输出晶体管M3和M11、以及降噪晶体管M12A、M12B、M13A和M13B。输出晶体管M3和M11的漏极连接到时钟信号端CLK，栅极连接到控制电路60。输出晶体管M3的源极连接到降噪晶体管M13A和M13B的漏极，输出晶体管M11的源极连接到降噪晶体管M12A和M12B的漏极。降噪晶体管M12A和M12B的源极连接到第一直流低电平电压信号端LVGL，降噪晶体管M12A的栅极连接到第一下拉点Pd_1，并且降噪晶体管M12B的栅极连接到第二下拉点Pd_2。降噪晶体管M13A和M13B的源极连接到第二直流低电平电压 信号端VGL，降噪晶体管M13A的栅极连接到第一下拉点Pd_1，并且降噪晶体管M13B的栅极连接到第二下拉点Pd_2。
根据本公开实施例的输出电路50在上拉节点PU电压为高电平时，根据时钟信号上升沿的触发，而进行输出，并根据时钟信号下降沿的触发，而停止输出。
图8为根据本发明实施例的GOA单元中的控制电路的示意图。
如图8中所示，控制电路包括反相器和控制开关元件，所述控制电路的一端连接到上升节点PU，另一端连接到输出电路50。
在图5和6中，该控制开关元件是第一晶体管M16，该第一晶体管M16的漏极连接到该输出电路的栅极信号端(即，稍后形成的上拉节点PU2)，栅极连接到该反相器的一端，源极经由上拉节点PU连接到输入电路、复位电路以及下拉电路。
在图5中，反相器包括串联连接的第二晶体管M18和第三晶体管M17。该第二晶体管M18的电阻大于该第三晶体管M17的电阻。第二晶体管M18的栅极与漏极一起连接到VGH，即直流高电压信号，使得第二晶体管M18始终处于导通状态。第三晶体管M17的漏极与第二晶体管M18的源极连接，并与第一晶体管M16的栅极连接。由于第二晶体管M18导通，所以，第三晶体管M17的漏极、第二晶体管M18的源极、以及第一晶体管M16的栅极均具有高电平，第一晶体管M16因此导通。此外，在大多数情况下，因为输出信号Outc和Gout的电平为低，因此第三晶体管M17关断。
下面详细描述根据本发明实施例的GOA单元的工作过程。
在上一级GOA单元输出栅极驱动信号OUTPUT_n-1时，即本级GOA单元的Input为高电平时，输入电路的晶体管M1导通，导致上拉节点PU电压升高。升高的上拉节点PU的电压使得输出晶体管M3和M11导通。之后，在输出电路50的时钟信号CLK由低电平跳变为高电平时，由于输出晶体管M3和M11导通，所以将时钟信号CLK的高电平信号传输到M3的栅极和M11的栅极。M11的源极即Outc输出端输出高电平信号Outc，并且M3的源极即Gout输出端输出高电平信号Gout。该高电平信号Outc连接到反相器中的第三晶体管M17的栅极，使得第三晶体管M17导通。在第三晶体管M17导通的情况下，由于第三晶体管M17的电阻小于第二晶体管M18的电阻，所以M17的漏极、M18的源极、以及M16的栅极的电平均降低。M16的栅极电平降低导致第一晶体管M16的关 断。第一晶体管M16的关断导致控制电路60与上拉节点PU的连接断开，也就是断开了控制电路60与输入电路、复位电路和下拉电路的连接，这相当于断开了晶体管M1、M2、M6A、M6B、M8A、M8B、M10A以及M10B的负载。
此时，新形成的上拉节点PU2的电压增加如下：
ΔV’＝(Vgh-Vgl)*(CgsM3+CgdM3+CgsM11+CgdM11+C1)/
(CgsM3+CgdM3+CgsM11+CgdM11+C1+CgdM16)           等式(2)
根据以上等式(1)和等式(2)的比较，可以看出，ΔV’的值明显高于ΔV的值。也就是说，与本发明人已知的电路相比，这实现了上拉节点电压的进一步提升。
接下来，在时钟信号CLK由高电平变为低电平时，输出晶体管M3和M11被断开，Outc输出端和Gout输出端电平被迅速拉低，所以输出停止。
在Outc输出端和Gout输出端输出停止的情况下，晶体管M17截止。由于直流高电平电压信号VGH一直施加到第二晶体管M18的漏极和栅极，所以第二晶体管M18保持导通。M17的漏极、M18的源极、以及M16的栅极的电平升高。M16的栅极电平升高直接导致第一晶体管M16导通。第一晶体管M16的导通导致控制电路60与上拉节点PU的连接恢复。
在下一级GOA单元输出OUTPUT_n+2时，即本级GOA单元的RESET为高电平时，M2导通，为上拉节点PU放电，将上拉节点PU的电压拉低，使得M3和M11栅极的电压被拉低，M3和M11断开，CLK不能被送到M3和M11的栅极，M3和M11保持断开状态，本级GOA单元的OUTPUT_n输出端和OUTPUT_n+1输出端停止输出。
在上述过程中，在CLK为高电平时，也就是本级GOA单元正常输出时，M12A、M12A、M13A、M13A也导通，用于起到稳定上拉节点PU的电压以及降低噪声的作用。
图6的电路结构与图5基本相同，除了反相器部分。
图6的反相器包括第二晶体管M18、第三晶体管M17和第四晶体管M19，其中该第二晶体管M18的漏极与该第四晶体管M19的栅极和漏极均连接到直流高电压信号，该第二晶体管M18的栅极连接到该第四晶体管M19的源极，该第二晶体管M18的源极连接到该第一晶体管M16的栅极以及该第三晶体管M17的漏极。
图6的反相器结构与图5的反相器结构相比，能补偿输出衰减，从而能进 一步降低第一晶体管M16的栅极电压，由此实现更佳的防漏电效果。
具体可以参考图9(a)-10(b)。图9(a)和9(b)为根据本发明第一实施例的反相器的组成结构示意图。图10(a)和10(b)为根据本发明第二实施例的反相器的组成结构示意图。
图9(a)对应于本发明第一实施例中的反相器结构，图9(a)对应于本发明第二实施例中的反相器结构。根据图9(b)和10(b)的波形图可以看出，第二实施例能进一步提高第二晶体管M18的栅极电压，由此补偿输出衰减，实现高控制电路更好的隔离效果。
然而，本领域技术人员应注意的是，本发明的反相器结构不限于上述结构，而是可以根据实际应用情况采用任何其他适当反相器。
图11为本发明人已知的上拉节点电压波形与本发明实施例的上拉节点电压波形的对照图。其中黑色粗线111的波形为本发明的新上拉节点PU2电压，黑色细线112的波形为本发明人已知的上拉节点PU电压。
根据图11，可以看出黑色粗线111明显高于黑色细线112，即新上拉节点PU2电压显著增高。此外，黑色粗线111的斜率明显小于黑色细线112，这说明PU保持阶段的漏电现象得到了改善。
本发明通过控制电路的插入，使得GOA电路中与时钟耦合的晶体管与其他的分压晶体管隔离，增强时钟耦合效果，实现了上拉节点电压增高以及漏电减小。这导致输出电路的晶体管M3和M11的栅极控制端的电压显著增高，从而降低了晶体管M3和M11的开启时间，进一步增强了晶体管M3和M11的驱动能力。
图12为根据本发明实施例的GOA单元的驱动方法的实现流程图。
如图12所示，所述方法主要可以包括如下步骤：
步骤S1：输入电路响应于所接收的输入信号，控制上拉节点PU的电位。即，该输入电路接收上一级GOA单元输出的高电平电压信号作为输入信号，并响应于该高电平电压信号使得晶体管M1导通，从而控制上拉节点PU的电位改变为高电平。
步骤S2：输出电路响应于输入到输出电路的时钟信号以及上拉节点PU的电位，生成输出信号。即，在输出电路50的时钟信号CLK由低电平跳变为高电平时，由于输出晶体管M3和M11导通，所以将时钟信号CLK的高电平信号传输到M3的栅极和M11的栅极。M11的源极即Outc输出端输出高电平信号 Outc，并且M3的源极即Gout输出端输出高电平信号Gout。
步骤S3：控制电路响应于输出电路所生成的输出信号，断开与上拉节点PU的连接，也就是断开所述输入电路、复位电路和下拉电路的连接。在输出信号为高电平的情况下，控制电路通过反相器的作用使得第一晶体管M16关断，从而断开与所述输入电路、复位电路和下拉电路的连接，进而提高新上拉节点PU2的电压。
具体来说，M11的源极即Outc输出端输出的高电平信号Outc使得第三晶体管M17导通。由于第三晶体管M17的电阻小于第二晶体管M18的电阻，所以M17的漏极、M18的源极、以及M16的栅极的电平均降低，这导致第一晶体管M16关断。这相当于去除了晶体管M1、M2、M6A、M6B、M8A、M8B、M10A以及M10B的负载，从而增强了时钟耦合效果，并进一步提高了第一晶体管M16的漏极的输出电压。
在步骤S3之后，在输出电路的时钟信号下降沿到来时，输出晶体管M3和M11被断开，Outc输出端和Gout输出端电平被迅速拉低。这时，晶体管M17截止，M17的漏极、M18的源极、以及M16的栅极的电平升高。第一晶体管M16的栅极电平升高使得第一晶体管M16导通。第一晶体管M16的导通导致控制电路60与上拉节点PU的连接恢复，从而接通第一晶体管M16的源极与上拉节点PU的连接。
本发明的实施例中包括的组件不限于软件或硬件，并且可被配置为存储在可寻址储存介质中并在一个或多个处理器上运行。
所以，作为示例，这些组件可包括诸如软件组件、面向对象组件、类组件、和任务组件的组件、处理、功能、属性、过程、子例程、程序代码段、驱动器、固件、微代码、电路、数据、数据库、数据结构、表格、阵列、和变量。组件和对应组件中提供功能性可被组合在较少组件中，或者可被进一步分离为附加组件。例如，描述为单一组件的每一组件可被分布并实践，并且类似地，描述为分布的组件也可以按照集成形式来实践。
当然，本领域技术人员将认识到，除非操作序列所特别指示或需要的，否则可省略、并发或顺序执行、或按照不同次序执行上述处理中的某些步骤。此外，没有组件、元件或处理应被看作对于任何特定要求保护的实施例所必要的，并且能在其他实施例中组合这些组件、元件或处理的每一个。
尽管已与特定实施例相关地描述了本发明的方法和系统，但是一些或全 部组件或其操作可使用具有通用目的硬件架构的计算机系统来实现。
本发明的描述意欲用于说明，并且本领域技术人员将理解的是，能按照其它详细形式来容易地修改本发明，而不改变本发明的技术精神或必要特征。所以，上述实施例应被理解为示范性而不是限制性的。因此，本发明的精神不限于提出的实施例，并且可经由与本发明相同精神的范围内的组件的添加、修改、删除或插入，而容易地设计其它实施例，但是可理解的是，这些其它实施例也可以被包括在本发明的范围中。
本申请要求于2017年1月3日递交的中国专利申请第201710001592.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种阵列基板行驱动GOA单元，包括：
    输入电路，连接到输入信号端和上拉节点PU；
    下拉电路，连接到第一电压信号端和上拉节点PU；
    下拉控制电路，经由下拉节点PD连接到所述下拉电路；
    输出电路，连接到时钟信号端、第二电压信号端和控制电路；
    复位电路，连接到复位信号端、第一电压信号端和上拉节点PU；和
    该控制电路，连接到上拉节点PU和所述输出电路，
    其中所述输入电路响应于所接收的输入信号，控制上拉节点PU的电位；
    所述输出电路响应于输入到输出电路的时钟信号以及上拉节点PU的电位，生成输出信号；
    所述控制电路响应于输出电路所生成的输出信号，断开其与上拉节点PU的连接。
  2. 根据权利要求1所述的GOA单元，其中：
    所述控制电路包括反相器和控制开关元件。
  3. 根据权利要求2所述的GOA单元，其中：
    所述控制开关元件包括第一晶体管，所述第一晶体管的漏极连接到所述输出电路的栅极信号端，栅极连接到所述反相器，源极经由上拉节点PU连接到所述输入电路、所述复位电路和所述下拉电路。
  4. 根据权利要求3所述的GOA单元，其中：
    所述反相器包括第二和第三晶体管，所述第二晶体管的栅极与漏极连接到第三电压信号端，源极连接到所述第一晶体管的栅极以及所述第三晶体管的漏极。
  5. 根据权利要求3所述的GOA单元，其中：
    所述反相器包括第二、第三和第四晶体管，所述第二晶体管的漏极以及所述第四晶体管的栅极和漏极均连接到直流高电压信号，所述第二晶体管的栅极连接到所述第四晶体管的源极，所述第二晶体管的源极连接到所述第一晶体管的栅极以及所述第三晶体管的漏极。
  6. 根据权利要求4或5所述的GOA单元，其中所述第三晶体管的源极连接到所述第一电压信号端，漏极连接到所述第二晶体管的源极，并且栅极 连接到所述输出电路的输出端。
  7. 根据权利要求4到6的任一个所述的GOA单元，其中所述第二晶体管的电阻大于所述第三晶体管的电阻。
  8. 根据权利要求1到7的任一个所述的GOA单元，其中，所述时钟信号、所述第一电压信号、所述第二电压信号和所述第三电压信号输入到所述GOA单元。
  9. 一种用于根据权利要求1-8的任一个所述的GOA单元的驱动方法，所述驱动方法包括以下步骤：
    由输入电路响应于所接收的输入信号，控制上拉节点PU的电位；
    由输出电路响应于输入到输出电路的时钟信号以及上拉节点PU的电位，生成输出信号；
    由控制电路响应于输出电路所生成的输出信号，断开其与上拉节点PU的连接。
  10. 根据权利要求9所述的GOA单元的驱动方法，其中：
    控制电路响应于输出电路所生成的输出信号，断开该控制电路中包括的第一晶体管的源极与上拉节点PU的连接。
  11. 根据权利要求10所述的GOA单元的驱动方法，进一步包括：
    在断开第一晶体管的源极与上拉节点PU的连接之后，控制电路响应于输入到输出电路的时钟信号，接通第一晶体管的源极与上拉节点PU的连接。
  12. 一种GOA装置，包括级联的多个根据权利要求1-8的任一个所述的GOA单元。
  13. 根据权利要求12的GOA装置，其中在所述级联的多个GOA单元中，
    除了第一GOA单元和最后GOA单元之外的每个GOA单元的信号输入端连接到与其相邻的上一级GOA单元的输出端，
    除了第一GOA单元和最后GOA单元之外的每个GOA单元的复位信号端连接到与其相邻的下一级GOA单元的输出端。
  14. 一种显示装置，包括根据权利要求12所述的GOA装置。
PCT/CN2017/094820 2017-01-03 2017-07-28 阵列基板行驱动单元、装置、驱动方法及显示装置 WO2018126656A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI719505B (zh) * 2019-06-17 2021-02-21 友達光電股份有限公司 元件基板
EP3839936A4 (en) * 2018-08-13 2022-03-16 Boe Technology Group Co., Ltd. SLIDER REGISTER UNIT, DRIVE METHOD, GATE DRIVER CIRCUIT AND DISPLAY DEVICE

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564458A (zh) 2017-10-27 2018-01-09 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN108711401B (zh) 2018-08-10 2021-08-03 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109584780B (zh) * 2019-01-30 2020-11-06 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN112309335B (zh) * 2019-07-31 2021-10-08 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
US11308839B2 (en) * 2019-11-13 2022-04-19 Hannstar Display Corporation Signal generating circuit and display device
CN112967646B (zh) * 2020-11-11 2022-12-16 重庆康佳光电技术研究院有限公司 低电平有效的goa单元和显示屏
CN113035258A (zh) * 2021-03-09 2021-06-25 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示面板
CN114078417B (zh) * 2021-11-19 2024-01-09 京东方科技集团股份有限公司 Goa电路及其驱动方法、显示面板和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065578A (zh) * 2012-12-13 2013-04-24 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN103474038A (zh) * 2013-08-09 2013-12-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器与显示装置
CN103700355A (zh) * 2013-12-20 2014-04-02 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN104021769A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示屏
CN105096865A (zh) * 2015-08-06 2015-11-25 京东方科技集团股份有限公司 移位寄存器的输出控制单元、移位寄存器及其驱动方法以及栅极驱动装置
CN105185349A (zh) * 2015-11-04 2015-12-23 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置
US20160307531A1 (en) * 2015-04-07 2016-10-20 Shenzhen China Star Optoelectronics Technology Co. Ltd. GOA Circuit and Liquid Crystal Display

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9437324B2 (en) * 2013-08-09 2016-09-06 Boe Technology Group Co., Ltd. Shift register unit, driving method thereof, shift register and display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065578A (zh) * 2012-12-13 2013-04-24 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN103474038A (zh) * 2013-08-09 2013-12-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器与显示装置
CN103700355A (zh) * 2013-12-20 2014-04-02 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN104021769A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示屏
US20160307531A1 (en) * 2015-04-07 2016-10-20 Shenzhen China Star Optoelectronics Technology Co. Ltd. GOA Circuit and Liquid Crystal Display
CN105096865A (zh) * 2015-08-06 2015-11-25 京东方科技集团股份有限公司 移位寄存器的输出控制单元、移位寄存器及其驱动方法以及栅极驱动装置
CN105185349A (zh) * 2015-11-04 2015-12-23 京东方科技集团股份有限公司 一种移位寄存器、栅极集成驱动电路及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3839936A4 (en) * 2018-08-13 2022-03-16 Boe Technology Group Co., Ltd. SLIDER REGISTER UNIT, DRIVE METHOD, GATE DRIVER CIRCUIT AND DISPLAY DEVICE
TWI719505B (zh) * 2019-06-17 2021-02-21 友達光電股份有限公司 元件基板

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