WO2020199486A1 - Goa电路结构及驱动方法 - Google Patents

Goa电路结构及驱动方法 Download PDF

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Publication number
WO2020199486A1
WO2020199486A1 PCT/CN2019/103685 CN2019103685W WO2020199486A1 WO 2020199486 A1 WO2020199486 A1 WO 2020199486A1 CN 2019103685 W CN2019103685 W CN 2019103685W WO 2020199486 A1 WO2020199486 A1 WO 2020199486A1
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Prior art keywords
unit
stage
goa unit
goa
signal terminal
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PCT/CN2019/103685
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English (en)
French (fr)
Inventor
朱静
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020199486A1 publication Critical patent/WO2020199486A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display, in particular to a GOA circuit structure and driving method.
  • the GOA (Gate Driver On Array) circuit is an important part of the liquid crystal display device.
  • the gate line scan driving signal circuit is fabricated on the Array substrate by using the existing thin film transistor liquid crystal display Array process to realize the integration of the gate progressive scan drive. Item technology.
  • the existing GOA circuit usually includes a plurality of cascaded GOA units, and each level of GOA unit correspondingly drives a level of horizontal scan lines.
  • the main structure of GOA unit includes pull-up circuit (pull-high circuit), pull-up control circuit, pull-down circuit (pull-down circuit) and pull-down holding circuit (pull-down holding circuit), as well as the bootstrap (Boast) capacitor responsible for potential elevation, etc., the pull-up control circuit can also be called pre-charge circuit (pre-charge circuit).
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as a gate signal;
  • the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and is generally connected to the stage transmission signal or gate signal transmitted by the previous-stage GOA circuit;
  • the pull-down circuit is responsible Pull down the gate signal to a low level at the first time, that is, turn off the gate signal;
  • the pull-down sustain circuit is responsible for the gate output signal and the gate signal of the pull-up circuit (usually called the control node Q( of the GOA unit) n)) is maintained in an off state (ie, a negative potential);
  • the bootstrap capacitor is responsible for controlling the second rise of the node Q(n), which is beneficial to the output of the gate signal output terminal G(n) of the pull-up circuit.
  • the current common method is to increase the number of clock signals (CK) to make the output pulse of the gate wider.
  • CK clock signals
  • Border Size the border size of the panel
  • the main purpose of the present invention is to provide a GOA circuit structure and driving method, which can increase the precharge time, thereby increasing the actual charging time of the pixel and improving the charging rate of the pixel.
  • the present invention provides a GOA circuit structure, which includes a plurality of cascaded GOA units, wherein the nth level GOA unit is used to output a gate drive signal to the nth level horizontal scan line.
  • the nth-level GOA unit includes a pull-up control unit, a bootstrap unit, a pull-up unit, a pull-down unit, and a pull-down maintenance unit; wherein the pull-up control unit receives a start signal in a first stage to enable the first The control node (Qn) of the n-level GOA unit is pulled up to a first high potential; wherein the pull-up control unit is connected to the stage transmission signal terminal (STn-3) and the n-3th level of the n-3th GOA unit The gate signal terminal (Gn-3) of the first stage and the control node (Qn) of the nth stage GOA unit; in the first stage, the pull-up control unit is from the n-3th stage GOA unit The stage transmission signal terminal (STn-3) receives the start signal, and then controls the nth stage GOA unit according to the gate signal of the gate signal terminal (Gn-3) of the n-3 stage The node (Qn) is at the first high potential; the bootstrap unit
  • the pull-up control unit includes a first thin film transistor (T11), the gate of which is connected to the stage transmission signal output terminal (STn-3) of the n-3th stage GOA unit, Its source is connected to the gate signal output terminal (Gn-3) of the n-3th stage, and its drain is connected to the control node (Qn) of the nth stage GOA unit.
  • T11 first thin film transistor
  • the bootstrap unit includes a bootstrap capacitor and a second transistor (T22), and the bootstrap capacitor is connected to the control node (Qn) of the n-th GOA unit and the The stage transmission signal terminal (STn) of the nth stage GOA unit; the gate of the second transistor (T22) is connected to the control node (Qn) of the nth stage GOA unit, and its source is connected to the clock signal terminal ( CK), the drain of which is connected to the stage signal terminal (STn) of the nth stage GOA unit.
  • the pull-up unit includes a third transistor (T21), and the gate of the third transistor (T21) is connected to the control node (Qn) of the nth level GOA unit, which The source is connected to the high voltage direct current signal terminal (LC1), and the drain is connected to the gate signal terminal (Gn) of the nth stage.
  • the pull-down unit is connected to the control node (Qn) of the nth level GOA unit, the gate signal terminal (Gn) of the nth level GOA unit, and the n+3 level GOA
  • the pull-down unit includes a fourth transistor (T31) and a fifth transistor (T41); the source of the fourth transistor (T31) is connected to the source of the nth level GOA unit Gate signal terminal (Gn); the source of the fifth transistor (T41) is connected to the control node (Qn) of the n-th GOA unit, and the fourth transistor (T31) and the fifth transistor (T41)
  • the drains are commonly connected to the first DC low-level terminal (VSSQ); the gates of the fourth transistor (T31) and the fifth transistor (T41) are commonly connected to the stage transfer signal of the n+3th GOA unit End (STn+3).
  • the present invention also provides a GOA circuit structure, which includes a plurality of cascaded GOA units, wherein the nth level GOA unit is used to output a gate drive signal to the nth level horizontal scan line, and the nth level GOA unit includes a Pull-up control unit, a bootstrap unit, a pull-up unit, a pull-down unit, and a pull-down maintenance unit; wherein the pull-up control unit receives a start signal in a first stage to enable the control node of the nth-stage GOA unit (Qn) is pulled up to a first high level; the bootstrap unit pulls up the control node (Qn) of the n-th GOA unit to a higher second stage according to a clock signal in a second stage High potential; the pull-up unit outputs a pulse width of two pulse widths of the clock signal according to the first high potential and the second high potential of the control node (Qn) of the nth GOA unit and a high voltage direct current signal Times the gate
  • the pull-up control unit is connected to the stage signal terminal (STn-3) of the n-3th stage GOA unit, the gate signal terminal (Gn-3) of the n-3 stage and The control node (Qn) of the nth level GOA unit; in the first stage, the pull-up control unit receives the data from the stage transmission signal end (STn-3) of the n-3th level GOA unit The start signal, and then the control node (Qn) of the nth stage GOA unit is at the first high potential according to the gate signal of the gate signal terminal (Gn-3) of the n-3th stage.
  • the pull-up control unit includes a first thin film transistor (T11), the gate of which is connected to the stage transmission signal output terminal (STn-3) of the n-3th stage GOA unit, Its source is connected to the gate signal output terminal (Gn-3) of the n-3th stage, and its drain is connected to the control node (Qn) of the nth stage GOA unit.
  • T11 first thin film transistor
  • the bootstrap unit is connected to the control node (Qn) of the nth level GOA unit, a clock signal terminal (CK), and the stage transmission signal terminal (STn) of the nth level GOA unit ,
  • the clock signal terminal (CK) provides the clock signal; the second stage starts when the control node (Qn) of the n-th GOA unit is pulled up to a first high potential.
  • the bootstrap unit includes a bootstrap capacitor and a second transistor (T22), and the bootstrap capacitor is connected to the control node (Qn) of the n-th GOA unit and the The stage transmission signal terminal (STn) of the nth stage GOA unit; the gate of the second transistor (T22) is connected to the control node (Qn) of the nth stage GOA unit, and its source is connected to the clock signal terminal ( CK), the drain of which is connected to the stage signal terminal (STn) of the nth stage GOA unit.
  • the pull-up unit is connected to the control node (Qn) of the nth stage GOA unit, a high voltage direct current signal terminal (LC1) and the gate signal terminal (Gn) of the nth stage. );
  • the high-voltage direct current signal terminal (LC1) provides the high-voltage direct current signal.
  • the pull-up unit includes a third transistor (T21), and the gate of the third transistor (T21) is connected to the control node (Qn) of the nth level GOA unit, which The source is connected to the high voltage direct current signal terminal (LC1), and the drain is connected to the gate signal terminal (Gn) of the nth stage.
  • the pull-down unit is connected to the control node (Qn) of the nth level GOA unit, the gate signal terminal (Gn) of the nth level GOA unit, and the n+3 level GOA
  • the pull-down unit includes a fourth transistor (T31) and a fifth transistor (T41); the source of the fourth transistor (T31) is connected to the source of the nth level GOA unit Gate signal terminal (Gn); the source of the fifth transistor (T41) is connected to the control node (Qn) of the n-th GOA unit, and the fourth transistor (T31) and the fifth transistor (T41)
  • the drains are commonly connected to the first DC low-level terminal (VSSQ); the gates of the fourth transistor (T31) and the fifth transistor (T41) are commonly connected to the stage transfer signal of the n+3th GOA unit End (STn+3).
  • the present invention also provides a driving method of GOA circuit structure, which includes the steps:
  • a pull-up control step receiving a start signal from the stage transmission signal terminal (STn-3) of the n-3th stage GOA unit, and then according to the gate of the n-3 stage gate signal terminal (Gn-3) The signal causes the control node (Qn) of the n-th GOA unit to be pulled up to a first high potential;
  • a pull-up step the control node (Qn) of the n-th GOA unit is pulled up to a higher second high potential according to a clock signal, and according to the first high potential of the control node (Qn) And a second high potential and a high voltage direct current signal to output a gate drive signal with a pulse width twice the pulse width of the clock signal to the gate signal terminal (Gn) of the nth stage GOA unit;
  • a pull-down step when the level transmission signal terminal (STn+3) of the n+3 level GOA unit is at a high potential, connect the control node (Qn) of the n level GOA unit to the n level GOA unit The potential of the gate signal terminal (Gn) is pulled down to a first DC low level; and
  • a sustaining step maintaining the control node (Qn) of the nth level GOA unit at the first DC low level, and maintaining the potential of the gate signal terminal (Gn) of the nth level GOA unit At a second DC low level.
  • the present invention is mainly based on the existing GOA circuit architecture.
  • the two low-frequency AC signals received by the pull-down sustaining unit are changed to DC high-voltage signals.
  • the high-voltage DC signals make the pulses output by the gate signal output terminal The width is doubled, thereby increasing the pixel pre-charging time, thereby increasing the actual charging time of the pixel and improving the charging rate of the pixel.
  • FIG. 1 is a schematic circuit diagram of a preferred embodiment of the n-th stage GOA unit of the GOA circuit architecture of the present invention.
  • FIG. 2 is a schematic diagram of a waveform of a preferred embodiment of the n-th GOA unit of the GOA circuit architecture of the present invention.
  • FIG. 3 is a flowchart of a preferred embodiment of the driving method of the GOA circuit architecture of the present invention.
  • FIG. 1 is a schematic circuit diagram of a preferred embodiment of the n-th GOA unit of the GOA circuit architecture of the present invention.
  • the GOA circuit architecture of the present invention includes a plurality of cascaded GOA units, where the nth level GOA unit is used to output gate drive signals to the nth level scan line, and the nth level GOA unit includes a pull-up control unit 100, A bootstrap unit 200, a pull-up unit 300, a pull-down unit 400, and a pull-down maintenance unit 500.
  • the operation of the n-th GOA unit can be divided into four stages according to the actions of different units, which will be listed in detail below.
  • the pull-up control unit 100 mainly receives a start signal in the first stage so that the control node (Qn) of the n-th GOA unit is pulled up to a first high potential.
  • the pull-up control unit 100 is connected to the stage transmission signal terminal (STn-3) of the n-3th stage GOA unit and the gate signal terminal (Gn-3 ) And the control node (Qn) of the nth level GOA unit, wherein the start signal is from the stage transmission signal terminal (STn-3) of the n-3th level GOA unit.
  • STn-3 stage transmission signal terminal
  • Gn-3 gate signal terminal
  • the pull-up control unit 100 receives the start signal from the stage transmission signal terminal (STn-3) of the n-3th GOA unit
  • the pull-up control unit pulls up the potential of the control node (Qn) of the nth stage GOA unit according to the gate signal of the gate signal terminal (Gn-3) of the n-3th stage
  • a first high potential as shown in FIG. 2, the waveform of the control node (Qn) is at the first high potential during the input period of the start signal of the corresponding stage transmission signal terminal (STn-3).
  • the pull-up control unit 100 specifically includes a first thin film transistor (T11).
  • the gate of the first thin film transistor (T11) is connected to the stage transmission signal output terminal (STn-3) of the n-3th GOA unit to receive the start signal to turn on the first thin film transistor (T11) .
  • the source of the first thin film transistor (T11) is connected to the gate signal output terminal (Gn-3) of the n-3th stage to receive the gate signal terminal (Gn- 3) from the n-3th stage. 3) The gate signal.
  • the drain of the first thin film transistor (T11) is connected to the control node (Qn) of the nth level GOA unit, so as to turn on the control node of the nth level GOA unit when the first thin film transistor (T11) is turned on
  • the potential of (Qn) is pulled up to the first high potential.
  • the bootstrapping unit 200 mainly pulls the control node (Qn) of the n-th GOA unit to a second high level according to a clock signal (CK) in the second stage.
  • the bootstrap unit 200 is connected to the control node (Qn) of the nth level GOA unit, a clock signal terminal (CK), and the stage transmission signal terminal (STn) of the nth level GOA unit;
  • the clock signal terminal (CK) is used to provide the clock signal, and the second stage starts when the control node (Qn) of the n-th GOA unit is pulled up to the first high potential, as shown in Figure 2
  • the waveform of the control node (Qn) is pulled high again in the first pulse corresponding to the clock signal CKn and is at the second high potential.
  • the second high potential is higher than the first high potential, and the second high potential may be twice the voltage level (VGH).
  • the bootstrap unit 200 includes a bootstrap capacitor Cb and a second transistor (T22), wherein the bootstrap capacitor Cb is connected to the control node (Qn) of the nth-stage GOA unit and all
  • the stage transmission signal terminal (STn) of the nth level GOA unit is used to pull up and maintain the potential of the control node (Qn);
  • the gate of the second transistor (T22) is connected to the control of the nth level GOA unit Node (Qn)
  • the source of the second transistor (T22) is connected to the clock signal terminal (CK)
  • the drain of the second transistor (T22) is connected to the stage signal terminal of the nth stage GOA unit (STn)
  • the second transistor (T22) is mainly used to output another start signal through the stage transmission signal terminal (STn) of the nth stage GOA unit to control the opening and closing of the next stage GOA unit, such as Figure 2 shows the output signal (STn) of the stage transmission signal terminal (STn).
  • the pull-up unit 300 is mainly based on the first high potential and the second high potential of the control node (Qn) of the n-th GOA unit and a high voltage direct current signal output with a pulse width equal to the pulse width of the clock signal.
  • the pull-up unit 300 To the gate signal terminal (Gn) of the n-th GOA unit.
  • the pull-up unit 300 generates the gate driving signal according to the potential change of the node (Qn) and the high-voltage direct current signal.
  • the waveform of the gate driving signal (Gn) is The corresponding node (Qn) is generated during the period when the corresponding node (Qn) is at the first high potential and the second high potential.
  • the pulse waveform corresponding to the potential change of the node (Qn) rises in two stages, and the width of the pulse waveform is approximately equivalent to the clock signal (CKn)
  • the pulse width is twice.
  • the pull-up unit 300 is connected to the control node (Qn) of the nth-stage GOA unit, a high-voltage DC signal terminal (LC1), and the gate signal terminal of the nth stage. (Gn), wherein the high-voltage direct current signal terminal (LC1) is used to output the high-voltage direct current signal.
  • the pull-up unit 300 includes a third transistor (T21), wherein the gate of the third transistor (T21) is connected to the control node (Qn) of the nth stage GOA unit, and the The source of the third transistor (T21) is connected to the high-voltage DC signal terminal (LC1), and the drain of the third transistor (T21) is connected to the gate signal terminal (Gn) of the nth stage to output the The gate drive signal to the nth level scan line.
  • T21 third transistor
  • the pull-down unit 400 mainly pulls down the potentials of the control node (Qn) of the n-th GOA unit and the gate signal terminal (Gn) of the n-th GOA unit to a first stage in a third stage. DC low level. Specifically, as shown in FIG.
  • the pull-down unit 400 is connected to the control node (Qn) of the nth level GOA unit, the gate signal terminal (Gn) of the nth level GOA unit, and the The stage transmission signal terminal (STn+3) of the n+3 level GOA unit and a first DC low level terminal (VSSQ); in more detail, the pull-down unit 400 is connected to the n+3 level GOA unit When the level transmission signal terminal (STn+3) outputs a high potential, the control node (Qn) of the nth level GOA unit and the gate signal terminal (Gn) of the nth level GOA unit are pulled down to the point where The first DC low level provided by the first DC low level terminal (VSSQ).
  • the third stage starts when the stage transmission signal terminal (STn+3) of the n+3 stage GOA unit is at a high potential, as shown in FIG. 2, the waveform of the gate drive signal (Gn) During the period when the corresponding stage transmission signal terminal (STn+3) is at a high potential, it is pulled down from a high potential to a low potential.
  • the pull-down unit 400 mainly includes a fourth transistor (T31) and a fifth transistor (T41); the source of the fourth transistor (T31) is connected to the first transistor (T31).
  • the drains of the transistors (T41) are commonly connected to the first DC low-level terminal (VSSQ); the gates of the fourth transistor (T31) and the fifth transistor (T41) are commonly connected to the n+3 level GOA
  • the pull-down sustaining unit 500 mainly maintains the control node (Qn) of the n-th GOA unit at the first DC low level in a fourth stage, and controls the gate of the n-th GOA unit The potential of the signal terminal (Gn) is maintained at a second DC low level.
  • the pull-down sustain unit 500 is mainly connected to the control node (Qn) of the nth stage GOA unit, the gate signal terminal (Gn) of the nth stage, the high voltage direct current signal terminal (LC1), and the A DC low-level terminal (VSSQ) and a second DC low-level terminal (VSSG); the pull-down maintaining unit maintains the control node (Qn) of the nth-stage GOA unit at the first DC low voltage And maintain the potential of the gate signal terminal (Gn) of the nth level GOA unit at the second DC low level provided by the second DC low level terminal (VSSG).
  • the voltage of the first direct current signal is less than the voltage of the second direct current signal, so the drain of the fourth transistor (T31) is connected to the first direct current low level terminal (VSSQ).
  • the falling time (Falling Time) of the waveform output by the gate signal terminal (Gn) of the n-th GOA unit can be relatively reduced, thereby solving the problem of long falling time. Causes the problem of poor picture display quality.
  • the GOA circuit structure is particularly applied to a large-size liquid crystal panel prepared based on amorphous silicon (a-Si) thin film transistors or based on indium gallium zinc oxide (IGZO) thin film transistors.
  • a-Si amorphous silicon
  • IGZO indium gallium zinc oxide
  • the present invention also provides a driving method of the above GOA circuit structure, including the steps:
  • a pull-up control step S1 Receive a start signal from the stage transmission signal terminal (STn-3) of the n-3th stage GOA unit, and then follow the gate signal terminal (Gn-3) of the n-3 stage The pole signal causes the control node (Qn) of the n-th GOA unit to be pulled up to a first high potential;
  • a pull-up step S2 the control node (Qn) of the n-th GOA unit is pulled up to a higher second high level according to a clock signal, and according to the first high level of the control node (Qn) Output a gate drive signal with a pulse width twice the pulse width of the clock signal to the gate signal terminal (Gn) of the nth-stage GOA unit;
  • a pull-down step S3 when the level transmission signal terminal (STn+3) of the n+3 level GOA unit is at a high potential, the control node (Qn) of the n level GOA unit is connected to the n level GOA unit Pull down the potential of the gate signal terminal (Gn) to a first DC low level; and
  • a sustaining step S4 maintaining the control node (Qn) of the nth-stage GOA unit at the first DC low level, and changing the potential of the gate signal terminal (Gn) of the nth-stage GOA unit Maintained at a second DC low level.
  • the present invention allows the pull-up control unit and the bootstrap unit to control sequentially so that the control node of the n-th GOA unit is at the first high potential and the second high potential, and Let the pull-down unit output a gate drive signal according to the change in the potential of the control node and a high voltage direct current signal, so that the pulse of the output gate drive signal can be doubled, thereby increasing the pixel precharge time, thereby realizing an increase in pixels
  • the actual charging time is improved, and the charging rate of the pixel is improved.
  • the circuit structure of the present invention also relatively reduces the falling time of the output waveform of the gate drive signal. Time), which can solve the problem of poor screen display quality due to long fall time.

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Abstract

一种GOA电路结构及驱动方法， GOA电路结构包括一上拉控制单元（100）、一自举单元（200）、一上拉单元（300）、一下拉单元（400）以及一下拉维持单元（500），上拉控制单元（100）与自举单元（200）依序控制第n级GOA单元的控制节点（Qn）位于第一高电位和第二高电位，上拉单元（300）依据控制节点（Qn）的电位变化及一高压直流信号（LC1）输出栅极驱动信号（Gn），GOA电路结构可使栅极驱动信号（Gn）的脉冲变宽两倍，从而增加像素预充电时间。

Description

GOA电路结构及驱动方法 技术领域
本发明涉及显示领域，特别是涉及一种GOA电路结构及驱动方法。
 背景技术
GOA（Gate Driver On Array）电路是液晶显示装置中的一个重要组成部分，利用现有薄膜晶体管液晶显示器Array制程将Gate行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描驱动的一项技术。
现有的GOA电路，通常包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。GOA单元的主要结构包括上拉电路(pull-high circuit)，上拉控制电路，下拉电路(pull-down circuit)和下拉维持电路(pull-down holding circuit)，以及负责电位抬高的自举(Boast)电容等，上拉控制电路也可以称为预充电路(pre-charge circuit)。上拉电路主要负责将时钟信号(Clock)输出为栅极信号；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA电路传递过来的级传信号或者栅极信号；下拉电路负责在第一时间将栅极信号拉低为低电位，即关闭栅极信号；下拉维持电路则负责将栅极输出信号和上拉电路的栅极信号(通常称为该GOA单元的控制节点Q(n))维持在关闭状态(即负电位)；自举电容则负责控制节点Q(n)的二次抬升，这样有利于上拉电路的栅极信号输出端G(n)的输出。
 技术问题
然而，对于设置在高解析度且搭配高频率（120HZ）的液晶面板中的GOA电路，由于充电时间较短，栅极线的电阻电容负载(RC Loading)较重，导致栅极脉冲信号(Gate Pulse)的失真(Distortion)非常严重，即Gn输出讯号的下降时间(Falling Time)数值较大，导致错充风险高。为了避免错充风险，现有技术会将栅极线转态时间点到数据转态时间点的时间加长，故而实际充电时间就更短，导致充电能力不足。
目前的常用作法为增加时钟信号(CK)的数量，进而使栅极的输出脉冲变宽，但是由于面板的边框尺寸(Border Size)的限制，此作法较难实现。
故，有必要提供一种GOA电路结构及驱动方法，以解决现有技术所存在的问题。
 技术解决方案
有鉴于现有技术的缺点，本发明的主要目的在于提供一种GOA电路结构及驱动方法，可以增加预充电时间，进而实现增加像素的实际充电时间，提升像素的充电率。
为达成本发明的前述目的，本发明提供一种GOA电路结构，其包括级联的多个GOA单元，其中第n级GOA单元用以对第n级水平扫描线输出栅极驱动信号，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；其中所述上拉控制单元于一第一阶段接收一启动信号而使第n级GOA单元的控制节点(Qn)被拉高至一第一高电位；其中所述上拉控制单元连接第n-3级GOA单元的级传信号端(STn-3)、第n-3级的栅极信号端(Gn-3)和所述第n级GOA单元的控制节点(Qn)；在所述第一阶段中，所述上拉控制单元自所述第n-3级GOA单元的级传信号端(STn-3)接收所述启动信号，并接着依据所述第n-3级的栅极信号端(Gn-3)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位；所述自举单元于一第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至更高的一第二高电位；其中所述自举单元连接所述第n级GOA单元的控制节点(Qn)、一时钟信号端(CK)及第n级GOA单元的级传信号端(STn)，所述时钟信号端(CK)提供所述时钟信号；所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位；所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；其中所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、一高压直流信号端(LC1)和所述第n级的栅极信号端(Gn)；所述高压直流信号端(LC1)提供所述高压直流信号；所述下拉单元于一第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及所述下拉维持单元于一第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
在本发明的一实施例中，所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极连接所述第n-3级GOA单元的级传信号输出端(STn-3)，其源极连接所述第n-3级的栅极信号输出端(Gn-3)，其漏极连接所述第n级GOA单元的控制节点(Qn)。
在本发明的一实施例中，所述自举单元包括一自举电容及一第二晶体管(T22)，所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；所述第二晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述时钟信号端(CK)，其漏极连接所述第n级GOA单元的级传信号端(STn)。
在本发明的一实施例中，所述上拉单元包括一第三晶体管(T21)，所述第三晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述高压直流信号端(LC1)，其漏极连接所述第n级的栅极信号端(Gn)。
在本发明的一实施例中，所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+3级GOA单元的级传信号端(STn+3)以及一第一直流低电平端(VSSQ)；所述第一直流低电平端(VSSQ)提供所述第一直流低电平；所述第三阶段开始于第n+3级GOA单元的级传信号端(STn+3)处于高电位时。
在本发明的一实施例中，所述下拉单元包括一第四晶体管(T31)及一第五晶体管(T41)；所述第四晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)；所述第五晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)，所述第四晶体管(T31)和第五晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)；所述第四晶体管(T31)和第五晶体管(T41)的栅极共同连接所述第n+3级GOA单元的级传信号端(STn+3)。
本发明还提供一种GOA电路结构，其包括级联的多个GOA单元，其中第n级GOA单元用以对第n级水平扫描线输出栅极驱动信号，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；其中所述上拉控制单元于一第一阶段接收一启动信号而使第n级GOA单元的控制节点(Qn)被拉高至一第一高电位；所述自举单元于一第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至更高的一第二高电位；所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；所述下拉单元于一第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及所述下拉维持单元于一第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
在本发明的一实施例中，所述上拉控制单元连接第n-3级GOA单元的级传信号端(STn-3)、第n-3级的栅极信号端(Gn-3)和所述第n级GOA单元的控制节点(Qn)；在所述第一阶段中，所述上拉控制单元自所述第n-3级GOA单元的级传信号端(STn-3)接收所述启动信号，并接着依据所述第n-3级的栅极信号端(Gn-3)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位。
在本发明的一实施例中，所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极连接所述第n-3级GOA单元的级传信号输出端(STn-3)，其源极连接所述第n-3级的栅极信号输出端(Gn-3)，其漏极连接所述第n级GOA单元的控制节点(Qn)。
在本发明的一实施例中，所述自举单元连接所述第n级GOA单元的控制节点(Qn)、一时钟信号端(CK)及第n级GOA单元的级传信号端(STn)，所述时钟信号端(CK)提供所述时钟信号；所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位。
在本发明的一实施例中，所述自举单元包括一自举电容及一第二晶体管(T22)，所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；所述第二晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述时钟信号端(CK)，其漏极连接所述第n级GOA单元的级传信号端(STn)。
在本发明的一实施例中，所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、一高压直流信号端(LC1)和所述第n级的栅极信号端(Gn)；所述高压直流信号端(LC1)提供所述高压直流信号。
在本发明的一实施例中，所述上拉单元包括一第三晶体管(T21)，所述第三晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述高压直流信号端(LC1)，其漏极连接所述第n级的栅极信号端(Gn)。
在本发明的一实施例中，所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+3级GOA单元的级传信号端(STn+3)以及一第一直流低电平端(VSSQ)；所述第一直流低电平端(VSSQ)提供所述第一直流低电平；所述第三阶段开始于第n+3级GOA单元的级传信号端(STn+3)处于高电位时。
在本发明的一实施例中，所述下拉单元包括一第四晶体管(T31)及一第五晶体管(T41)；所述第四晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)；所述第五晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)，所述第四晶体管(T31)和第五晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)；所述第四晶体管(T31)和第五晶体管(T41)的栅极共同连接所述第n+3级GOA单元的级传信号端(STn+3)。
本发明还提供一种GOA电路结构的驱动方法，其包含步骤：
一上拉控制步骤：从第n-3级GOA单元的级传信号端(STn-3)接收一启动信号，并接着依据第n-3级的栅极信号端(Gn-3)的栅极信号使第n级GOA单元的控制节点(Qn)被拉高至一第一高电位；
一上拉步骤：依据一时钟信号使所述第n级GOA单元的控制节点(Qn)被拉高至更高的一第二高电位，并且依据所述控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
一下拉步骤：于第n+3级GOA单元的级传信号端(STn+3)处于高电位时，将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
一维持步骤：将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
 有益效果
本发明主要是基于现有 GOA 电路架构的基础上，将原本下拉维持单元接收的两个低频交流信号，改为一直流高压信号，藉由所述高压直流讯号使栅极信号输出端输出的脉冲变宽两倍，从而增加像素预充电时间，进而实现增加像素的实际充电时间，提升像素的充电率。
 附图说明
图1是本发明GOA 电路架构的第n级GOA单元一优选实施例的一电路示意图。
图2是本发明GOA 电路架构的第n级GOA单元一优选实施例的一波形示意图。
图3是本发明GOA 电路架构的驱动方法的一优选实施例的一流程图。
 本发明的实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
参考图1，图1是本发明GOA 电路架构的第n级GOA单元一优选实施例的一电路示意图。本发明的GOA 电路架构包括多个级联的GOA单元，其中第n级GOA单元用以对第n级扫描线输出栅极驱动信号，所述第n级GOA单元包括一上拉控制单元100、一自举单元200、一上拉单元300、一下拉单元400以及一下拉维持单元500。所述第n级GOA单元的操作依据其不同单元的动作可以分成四个阶段，以下将详细列举说明。
如图1所示，所述上拉控制单元100主要是于第一阶段接收一启动信号而使所述第n级GOA单元的控制节点(Qn)被拉高至一第一高电位。具体而言，在本实施例中，所述上拉控制单元100连接第n-3级GOA单元的级传信号端(STn-3)、第n-3级的栅极信号端(Gn-3)和第n级GOA单元的控制节点(Qn)，其中所述启动信号是来自所述第n-3级GOA单元的级传信号端(STn-3)。更详细地，进一步参考图2所示，在第一阶段中，当所述上拉控制单元100自所述第n-3级GOA单元的级传信号端(STn-3)接收所述启动信号时，所述上拉控制单元依据所述第n-3级的栅极信号端(Gn-3)的栅极信号使所述第n级GOA单元的控制节点(Qn)的电位被拉高处于一第一高电位，如图2所示，控制节点(Qn)的波形在对应级传信号端(STn-3)的启动信号输入期间处于第一高电位。
在一实施例中，如图1所示，所述上拉控制单元100具体包括一第一薄膜晶体管(T11)。所述第一薄膜晶体管(T11)的栅极是连接所述第n-3级GOA单元的级传信号输出端(STn-3)，以接收所述启动信号而打开第一薄膜晶体管(T11)。所述第一薄膜晶体管(T11)的源极连接所述第n-3级的栅极信号输出端(Gn-3)，以接收来自所述第n-3级的栅极信号端(Gn-3)的栅极信号。所述第一薄膜晶体管(T11)的漏极则连接所述第n级GOA单元的控制节点(Qn)，以在第一薄膜晶体管(T11)打开时将所述第n级GOA单元的控制节点(Qn)的电位拉高至所述第一高电位。
如图1所示，所述自举单元200主要是于第二阶段依据一时钟信号(CK)将所述第n级GOA单元的控制节点(Qn)拉高至一第二高电位。具体而言，所述自举单元200是连接所述第n级GOA单元的控制节点(Qn)、一时钟信号端(CK)及第n级GOA单元的级传信号端(STn)；其中所述时钟信号端(CK)用以提供所述时钟信号，所述第二阶段则开始于所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位之时，如图2所示，控制节点(Qn)的波形在对应时钟信号CKn的第一个脉冲被再次拉高而处于第二高电位。所述第二高电位高于所述第一高电位，且所述第二高电位可以是两倍的电压位准（VGH）。
在一实施例中，所述自举单元200包括一自举电容Cb及一第二晶体管(T22)，其中所述自举电容Cb连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)，用以拉高并维持控制节点(Qn)的电位；所述第二晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第二晶体管(T22)的源极连接所述时钟信号端(CK)，所述第二晶体管(T22)的漏极连接所述第n级GOA单元的级传信号端(STn)，所述第二晶体管(T22)主要用以通过所述第n级GOA单元的级传信号端(STn)输出另一启动信号，以控制下一级GOA单元的打开和关闭，如图2所示的级传信号端(STn)的输出信号(STn)。
所述上拉单元300主要是依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)。换言之，所述上拉单元300是依据节点(Qn)的电位变化与所述高压直流信号来生成所述栅极驱动信号，如图2所示，所述栅极驱动信号(Gn)的波形在对应节点(Qn)处于第一高电位和第二高电位的期间生成，其脉冲波形对应节点(Qn)的电位变化分两阶段抬升，其脉冲波形的宽度大约相当于所述时钟信号(CKn)的脉冲宽度的两倍。具体而言，如图1所示，所述上拉单元300连接所述第n级GOA单元的控制节点(Qn)、一高压直流信号端(LC1)和所述第n级的栅极信号端(Gn)，其中所述高压直流信号端(LC1)用以输出所述高压直流信号。
在一实施例中，所述上拉单元300包括一第三晶体管(T21)，其中所述第三晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，所述第三晶体管(T21)的源极连接所述高压直流信号端(LC1)，所述第三晶体管(T21)的漏极则连接所述第n级的栅极信号端(Gn)，以输出所述栅极驱动信号至第n级扫描线。
所述下拉单元400主要是于一第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平。具体如图1所示，在本实施例中，所述下拉单元400连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+3级GOA单元的级传信号端(STn+3)以及一第一直流低电平端(VSSQ)；更详细地，所述下拉单元400是于所述第n+3级GOA单元的级传信号端(STn+3)输出高电位时，将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至所述第一直流低电平端(VSSQ)提供的第一直流低电平。也就是说，所述第三阶段开始于第n+3级GOA单元的级传信号端(STn+3)处于高电位时，如图2所示，所述栅极驱动信号(Gn)的波形在对应级传信号端(STn+3)处于高电位的期间从高电位被拉低为低电位。
在一实施例中，如图1所示，所述下拉单元400主要包括一第四晶体管(T31)及一第五晶体管(T41)；所述第四晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)；所述第五晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)，所述第四晶体管(T31)和第五晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)；所述第四晶体管(T31)和第五晶体管(T41)的栅极共同连接所述第n+3级GOA单元的级传信号端(STn+3)。
所述下拉维持单元500主要是于一第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。所述下拉维持单元500主要是连接所述第n级GOA单元的控制节点(Qn)、所述第n级的栅极信号端(Gn)、所述高压直流信号端(LC1)、所述第一直流低电平端(VSSQ)及一第二直流低电平端(VSSG)；所述下拉维持单元将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于所述第二直流低电平端(VSSG)提供的第二直流低电平。
在一实施例中，所述第一直流信号的电压小于第二直流信号的电压，故所述第四晶体管(T31)的漏极连接所述第一直流低电平端(VSSQ)，相较于连接第二直流低电平端(VSSG)，可相对减少所述第n级GOA单元的栅极信号端(Gn)输出的波形的下降时间(Falling Time)，从而可以解决因下降时间长而导致画面显示品质差的问题。
在一实施例中，所述GOA电路结构特别是应用于基于非晶硅(a-Si)薄膜晶体管制备的或是基于铟镓锌氧化物(IGZO)薄膜晶体管制备的大尺寸液晶面板。
进一步图3所示，依据上述的GOA电路结构，本发明还提供一种上述GOA电路结构的驱动方法，包含步骤：
一上拉控制步骤S1：从第n-3级GOA单元的级传信号端(STn-3)接收一启动信号，并接着依据第n-3级的栅极信号端(Gn-3)的栅极信号使第n级GOA单元的控制节点(Qn)被拉高至一第一高电位；
一上拉步骤S2：依据一时钟信号使所述第n级GOA单元的控制节点(Qn)被拉高至更高的一第二高电位，并且依据所述控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
一下拉步骤S3：于第n+3级GOA单元的级传信号端(STn+3)处于高电位时，将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
一维持步骤S4：将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
综上所述，相较于现有技术，本发明通过让所述上拉控制单元与自举单元依序控制使第n级GOA单元的控制节点位于第一高电位和第二高电位，并让下拉单元依据所述控制节点的电位变化及一高压直流信号输出栅极驱动信号，可使输出的所述栅极驱动信号的脉冲变宽两倍，从而增加像素预充电时间，进而实现增加像素的实际充电时间，提升像素的充电率，本发明的电路结构也相对减少栅极驱动信号输出波形的下降时间(Falling Time)，从而可以解决因下降时间长而导致画面显示品质差的问题。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (16)

  1. 一种GOA电路结构，其包括级联的多个GOA单元，其中第n级GOA单元用以对第n级水平扫描线输出栅极驱动信号，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；其特征在于，
    所述上拉控制单元于一第一阶段接收一启动信号而使第n级GOA单元的控制节点(Qn)被拉高至一第一高电位；其中所述上拉控制单元连接第n-3级GOA单元的级传信号端(STn-3)、第n-3级的栅极信号端(Gn-3)和所述第n级GOA单元的控制节点(Qn)；在所述第一阶段中，所述上拉控制单元自所述第n-3级GOA单元的级传信号端(STn-3)接收所述启动信号，并接着依据所述第n-3级的栅极信号端(Gn-3)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位；
    所述自举单元于一第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至更高的一第二高电位；其中所述自举单元连接所述第n级GOA单元的控制节点(Qn)、一时钟信号端(CK)及第n级GOA单元的级传信号端(STn)，所述时钟信号端(CK)提供所述时钟信号；所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位；
    所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；其中所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、一高压直流信号端(LC1)和所述第n级的栅极信号端(Gn)；所述高压直流信号端(LC1)提供所述高压直流信号；
    所述下拉单元于一第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
    所述下拉维持单元于一第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
  2. 如权利要求1所述的GOA电路结构，其特征在于：所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极连接所述第n-3级GOA单元的级传信号输出端(STn-3)，其源极连接所述第n-3级的栅极信号输出端(Gn-3)，其漏极连接所述第n级GOA单元的控制节点(Qn)。
  3. 如权利要求1所述的GOA电路结构，其特征在于：所述自举单元包括一自举电容及一第二晶体管(T22)，所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；所述第二晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述时钟信号端(CK)，其漏极连接所述第n级GOA单元的级传信号端(STn)。
  4. 如权利要求1所述的GOA电路结构，其特征在于：所述上拉单元包括一第三晶体管(T21)，所述第三晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述高压直流信号端(LC1)，其漏极连接所述第n级的栅极信号端(Gn)。
  5. 如权利要求1所述的GOA电路结构，其特征在于：所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+3级GOA单元的级传信号端(STn+3)以及一第一直流低电平端(VSSQ)；所述第一直流低电平端(VSSQ)提供所述第一直流低电平；所述第三阶段开始于第n+3级GOA单元的级传信号端(STn+3)处于高电位时。
  6. 如权利要求5所述的GOA电路结构，其特征在于：所述下拉单元包括一第四晶体管(T31)及一第五晶体管(T41)；所述第四晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)；所述第五晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)，所述第四晶体管(T31)和第五晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)；所述第四晶体管(T31)和第五晶体管(T41)的栅极共同连接所述第n+3级GOA单元的级传信号端(STn+3)。
  7. 一种GOA电路结构，其包括级联的多个GOA单元，其中第n级GOA单元用以对第n级水平扫描线输出栅极驱动信号，所述第n级GOA单元包括一上拉控制单元、一自举单元、一上拉单元、一下拉单元以及一下拉维持单元；其特征在于，
    所述上拉控制单元于一第一阶段接收一启动信号而使第n级GOA单元的控制节点(Qn)被拉高至一第一高电位；
    所述自举单元于一第二阶段依据一时钟信号将所述第n级GOA单元的控制节点(Qn)拉高至更高的一第二高电位；
    所述上拉单元依据所述第n级GOA单元的控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
    所述下拉单元于一第三阶段将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
    所述下拉维持单元于一第四阶段将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
  8. 如权利要求7所述的GOA电路结构，其特征在于：所述上拉控制单元连接第n-3级GOA单元的级传信号端(STn-3)、第n-3级的栅极信号端(Gn-3)和所述第n级GOA单元的控制节点(Qn)；在所述第一阶段中，所述上拉控制单元自所述第n-3级GOA单元的级传信号端(STn-3)接收所述启动信号，并接着依据所述第n-3级的栅极信号端(Gn-3)的栅极信号使所述第n级GOA单元的控制节点(Qn)处于所述第一高电位。
  9. 如权利要求8所述的GOA电路结构，其特征在于：所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极连接所述第n-3级GOA单元的级传信号输出端(STn-3)，其源极连接所述第n-3级的栅极信号输出端(Gn-3)，其漏极连接所述第n级GOA单元的控制节点(Qn)。
  10. 如权利要求7所述的GOA电路结构，其特征在于：所述自举单元连接所述第n级GOA单元的控制节点(Qn)、一时钟信号端(CK)及第n级GOA单元的级传信号端(STn)，所述时钟信号端(CK)提供所述时钟信号；所述第二阶段开始于所述第n级GOA单元的控制节点(Qn)被拉高至第一高电位。
  11. 如权利要求10所述的GOA电路结构，其特征在于：所述自举单元包括一自举电容及一第二晶体管(T22)，所述自举电容连接所述第n级GOA单元的控制节点(Qn)及所述第n级GOA单元的级传信号端(STn)；所述第二晶体管(T22)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述时钟信号端(CK)，其漏极连接所述第n级GOA单元的级传信号端(STn)。
  12. 如权利要求7所述的GOA电路结构，其特征在于：所述上拉单元连接所述第n级GOA单元的控制节点(Qn)、一高压直流信号端(LC1)和所述第n级的栅极信号端(Gn)；所述高压直流信号端(LC1)提供所述高压直流信号。
  13. 如权利要求12所述的GOA电路结构，其特征在于：所述上拉单元包括一第三晶体管(T21)，所述第三晶体管(T21)的栅极连接所述第n级GOA单元的控制节点(Qn)，其源极连接所述高压直流信号端(LC1)，其漏极连接所述第n级的栅极信号端(Gn)。
  14. 如权利要求7所述的GOA电路结构，其特征在于：所述下拉单元连接所述第n级GOA单元的控制节点(Qn)、所述第n级GOA单元的栅极信号端(Gn)、第n+3级GOA单元的级传信号端(STn+3)以及一第一直流低电平端(VSSQ)；所述第一直流低电平端(VSSQ)提供所述第一直流低电平；所述第三阶段开始于第n+3级GOA单元的级传信号端(STn+3)处于高电位时。
  15. 如权利要求14所述的GOA电路结构，其特征在于：所述下拉单元包括一第四晶体管(T31)及一第五晶体管(T41)；所述第四晶体管(T31)的源极连接所述第n级GOA单元的栅极信号端(Gn)；所述第五晶体管(T41)的源极连接所述第n级GOA单元的控制节点(Qn)，所述第四晶体管(T31)和第五晶体管(T41)的漏极共同连接所述第一直流低电平端(VSSQ)；所述第四晶体管(T31)和第五晶体管(T41)的栅极共同连接所述第n+3级GOA单元的级传信号端(STn+3)。
  16. 一种GOA电路结构的驱动方法，其特征在于：所述驱动方法包含步骤：
    一上拉控制步骤：从第n-3级GOA单元的级传信号端(STn-3)接收一启动信号，并接着依据第n-3级的栅极信号端(Gn-3)的栅极信号使第n级GOA单元的控制节点(Qn)被拉高至一第一高电位；
    一上拉步骤：依据一时钟信号使所述第n级GOA单元的控制节点(Qn)被拉高至更高的一第二高电位，并且依据所述控制节点(Qn)的第一高电位和第二高电位以及一高压直流信号输出一脉冲宽度为所述时钟信号的脉冲宽度两倍的栅极驱动信号至第n级GOA单元的栅极信号端(Gn)；
    一下拉步骤：于第n+3级GOA单元的级传信号端(STn+3)处于高电位时，将所述第n级GOA单元的控制节点(Qn)与所述第n级GOA单元的栅极信号端(Gn)的电位拉低至一第一直流低电平；以及
    一维持步骤：将所述第n级GOA单元的控制节点(Qn)维持于所述第一直流低电平，并将所述第n级GOA单元的栅极信号端(Gn)的电位维持于一第二直流低电平。
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