WO2019033493A1 - Goa电路及液晶显示装置 - Google Patents

Goa电路及液晶显示装置 Download PDF

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WO2019033493A1
WO2019033493A1 PCT/CN2017/101975 CN2017101975W WO2019033493A1 WO 2019033493 A1 WO2019033493 A1 WO 2019033493A1 CN 2017101975 W CN2017101975 W CN 2017101975W WO 2019033493 A1 WO2019033493 A1 WO 2019033493A1
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circuit
goa unit
pull
goa
nth stage
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PCT/CN2017/101975
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English (en)
French (fr)
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王添鸿
陈书志
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/578,245 priority Critical patent/US10360866B2/en
Publication of WO2019033493A1 publication Critical patent/WO2019033493A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of liquid crystal displays, and in particular to a GOA circuit and a liquid crystal display device.
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • notebooks because of their high image quality, power saving, thin body and wide application range.
  • each sub-pixel has a thin film transistor (TFT) having a gate connected to a horizontal scan line, a drain connected to a vertical data line, and a source connected to the source.
  • TFT thin film transistor
  • Applying a sufficient voltage on the horizontal scanning line causes all the TFTs on the horizontal scanning line to be turned on.
  • the pixel electrodes on the horizontal scanning line are connected to the data lines in the vertical direction, thereby connecting the data lines.
  • the display signal voltage is written into the pixel, and the transmittance of different liquid crystals is controlled to achieve the effect of controlling the color.
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by an external chip (IC) of the panel, and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • IC external chip
  • Gate Driver On Array (GOA) technology which uses the existing thin film transistor liquid crystal display array (Array) process to fabricate the gate scan drive signal circuit on the Array substrate to realize the Gate on the Array substrate. The way the line scan is driven.
  • the existing GOA circuit generally includes a plurality of cascaded GOA units, and each level of the GOA unit corresponds to driving a level one horizontal scan line.
  • the main structure of the GOA unit includes a pull-high circuit, a pull-up control circuit, a pull-down circuit and a pull-down holding circuit, and a bootstrap responsible for potential elevation ( Boast), etc.
  • the pull-up control circuit can also be called a pre-charge circuit;
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as a gate signal;
  • the pull-up control circuit is responsible for controlling the pull-up circuit.
  • the turn-on time is generally connected to the pass signal or the gate signal transmitted from the GOA circuit of the previous stage; the pull-down circuit is responsible for pulling the gate signal low to the low level at the first time, that is, turning off the gate signal; the pull-down sustain circuit is responsible for the gate
  • the pole output signal and the gate signal of the pull-up circuit (commonly referred to as Q point) are maintained in the off state (ie, the negative potential); the bootstrap capacitor is responsible for the secondary rise of the Q point, which is beneficial to the G of the pull-up circuit. ) Output.
  • the conventional GOA circuit architecture mainly consists of a pull-up control circuit (including T11), a pull-up circuit (including T21, T22), a pull-down circuit, a pull-down sustain circuit, and a bootstrap capacitor Cb.
  • the pull-up control circuit is connected to the level signal output terminal ST(N-4) of the N-4th GOA unit and the gate signal output terminal G(N-4), which is responsible for controlling The open time of the pull circuit and the pre-charging of the node Q(N);
  • the pull-up circuit is connected to the clock signal CK(N) and the level signal output terminal ST(N) of the N-th stage GOA unit is responsible for the clock signal CK(N)
  • the gate signal output terminal G(N) of the Nth stage is outputted to the corresponding horizontal scan line and the staged signal of the output Nth stage GOA unit;
  • the pull-down circuit is responsible for pulling down the gate signal output terminal G of the Nth stage (N) a potential;
  • a pull-down sustain circuit for maintaining the potential of the gate signal output terminal G(N) of the Nth stage and the potential of the node Q(N) of the pull-up circuit to make the gate signal output terminal G(N)
  • the output gate signal is maintained in the off state.
  • FIG. 2 is a schematic diagram of the output signal of the node Q in the conventional GOA circuit architecture.
  • the horizontal axis is time and the vertical axis is voltage, showing the waveform of the node Q in the 1 to 8 GOA unit;
  • the CK input signal corresponds to the waveform of the STV input signal.
  • the horizontal axis is time and the vertical axis is voltage.
  • the start signal STV and the high frequency clock signals of the input level 1 to 6 GOA units are displayed.
  • CK as shown in Fig. 3, the high-frequency clock signal CK of each level of the GOA unit is a normal CK output waveform, and the CK waveform is sequentially generated without relative advance output.
  • the pull-up control circuit needs to input the level-transmitting signal and the gate signal of the N-4th GOA unit to start, the first stages of the GOA circuit need to input the start signal STV instead of the level-transmitting signal as the GOA turn-on signal and the Q-node pre-charge.
  • the signal causes the first three levels of Q node output waveforms to be inconsistent with the normal level Q node output (see Figure 2).
  • Another object of the present invention is to provide a liquid crystal display device in which the Q node output waveforms of the GOA units of each stage in the GOA circuit are identical.
  • the present invention provides a GOA circuit comprising: a plurality of cascaded GOA units, wherein an Nth stage GOA unit controls charging of an Nth horizontal scanning line, the Nth stage GOA unit including Pull control circuit, pull-up circuit, pull-down circuit, pull-down to maintain power And a bootstrap capacitor; the pull-up circuit, the pull-down sustain circuit, the pull-down circuit and the bootstrap capacitor are respectively connected to the node and the gate signal output end of the Nth stage GOA unit, and the first clock of the Nth stage GOA unit The signal is input to the pull-up circuit, and the output signal output end of the Nth stage GOA unit is connected to the pull-up circuit, and the pull-up control circuit is connected to the node of the Nth stage GOA unit; the pull-up control circuit includes:
  • a first thin film transistor having a gate connected to a level signal output end of the N-mth GOA unit, m being a natural number, a source and a drain respectively connected to a gate of the second thin film transistor and input to the Nth stage GOA unit a second clock signal, the second clock signal being opposite in phase to the first clock signal;
  • the source and the drain of the second thin film transistor are respectively connected to the level signal output end of the N-th stage GOA unit and the node of the Nth stage GOA unit.
  • a start signal is input to the level signal output end of the N-mth GOA unit in the first m-level GOA unit.
  • the gate of the first thin film transistor is connected to the output signal output end of the N-4th GOA unit, and the source and the drain of the second thin film transistor are respectively connected to the level transmission signal of the N-4th GOA unit.
  • the output and the node of the Nth stage GOA unit is connected to the input signal output end of the N-4th GOA unit, and the source and the drain of the second thin film transistor are respectively connected to the level transmission signal of the N-4th GOA unit.
  • a start signal is input to the level signal output end of the N-4th GOA unit in the first four stages of the GOA unit.
  • the GOA circuit includes eight first clock signals having the same waveform and different initial phases.
  • the initial phases of the eight first clock signals are arranged in accordance with the phase difference of ⁇ /4.
  • the GOA circuit includes two or more first clock signals having the same waveform and different initial phases.
  • the GOA circuit is based on an amorphous silicon thin film transistor.
  • the pull-up circuit comprises:
  • a third thin film transistor having a gate connected to a node of the Nth stage GOA unit, a source and a drain respectively connected to a gate signal output end of the Nth stage GOA unit and inputting the first clock signal;
  • a fourth thin film transistor having a gate connected to a node of the Nth stage GOA unit, a source and a drain respectively connected to the level signal output end of the Nth stage GOA unit and inputting the first clock signal.
  • the present invention also provides a liquid crystal display device comprising the above GOA circuit.
  • the present invention also provides a GOA circuit comprising: a plurality of cascaded GOA units, wherein the Nth stage GOA unit controls charging of the Nth horizontal scanning line, the Nth stage GOA unit including a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, and a bootstrap capacitor; the pull-up circuit, the pull-down sustain circuit, the pull-down circuit, and the bootstrap capacitor are respectively connected to the node and the gate signal output end of the Nth stage GOA unit, the first a first clock signal of the N-stage GOA unit is input to the pull-up circuit, and a level signal output end of the N-th stage GOA unit is connected to the pull-up circuit.
  • the pull-up control circuit is connected to a node of the Nth stage GOA unit; the pull-up control circuit includes:
  • a first thin film transistor having a gate connected to a level signal output end of the N-mth GOA unit, m being a natural number, a source and a drain respectively connected to a gate of the second thin film transistor and input to the Nth stage GOA unit a second clock signal, the second clock signal being opposite in phase to the first clock signal;
  • the source and the drain of the second thin film transistor are respectively connected to the level signal output end of the N-th stage GOA unit and the node of the Nth stage GOA unit;
  • a start signal is input to the level signal output end of the N-mth GOA unit in the first m-level GOA unit;
  • the GOA circuit comprises two or more first clock signals having the same waveform and different initial phases
  • the GOA circuit is based on an amorphous silicon thin film transistor
  • the pull-up circuit comprises:
  • a third thin film transistor having a gate connected to a node of the Nth stage GOA unit, a source and a drain respectively connected to a gate signal output end of the Nth stage GOA unit and inputting the first clock signal;
  • a fourth thin film transistor having a gate connected to a node of the Nth stage GOA unit, a source and a drain respectively connected to the level signal output end of the Nth stage GOA unit and inputting the first clock signal.
  • the GOA circuit and the liquid crystal display device of the present invention can improve the performance of the node Q in each level of the GOA unit, so that the Q node output waveforms of the GOA units of each level are consistent.
  • FIG. 1 is a schematic diagram of a conventional ordinary GOA circuit architecture
  • FIG. 2 is a schematic diagram of a node Q output signal in a conventional GOA circuit architecture
  • FIG. 3 is a schematic diagram showing waveforms corresponding to a CK input signal and an STV input signal in a conventional GOA circuit architecture
  • FIG. 4 is a schematic diagram of a preferred embodiment of a GOA circuit architecture of the present invention.
  • FIG. 5 is a schematic diagram of waveforms corresponding to a CK input signal and an STV input signal in a preferred embodiment of the GOA circuit architecture of the present invention
  • FIG. 6 is a schematic diagram of a node Q output signal in a preferred embodiment of the GOA circuit architecture of the present invention.
  • FIG. 4 it is a schematic diagram of a preferred embodiment of the GOA circuit architecture of the present invention, mainly by Pull-up control circuit (including T11 and T12), pull-up circuit (including T21, T22), pull-down circuit, pull-down sustain circuit, and bootstrap capacitor Cb.
  • the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit and pre-charging the node Q(N); the pull-up circuit is connected to the high-frequency clock signal CK(N) and the N-th stage GOA unit
  • the level signal output terminal ST(N) is responsible for outputting the clock signal CK(N) through the gate signal output terminal G(N) of the Nth stage to the corresponding horizontal scanning line and outputting the level of the Nth stage GOA unit.
  • the pull-down circuit is responsible for pulling down the potential of the gate signal output terminal G(N) of the Nth stage;
  • the pull-down sustain circuit is for maintaining the potential of the gate signal output terminal G(N) of the Nth stage and the pull-up circuit
  • the potential of the node Q(N) is such that the gate signal output from the gate signal output terminal G(N) is maintained in the off state.
  • the bootstrap capacitor Cb is responsible for the secondary rise of the node Q(N), which is advantageous for the output of the pull-up circuit.
  • the gate of the thin film transistor T11 is connected to the level signal output terminal ST(N-4) of the N-4th stage GOA unit, and the source and the drain of the thin film transistor T12 are respectively connected to the Nth.
  • the specific structure of the pull-up control circuit shown in FIG. 4 is only used to illustrate the present invention.
  • the present invention adds a TFT named T12 by changing the pull-up control circuit, so that the node Q(N) points of the GOA units of each level are changed.
  • the output waveforms behave consistently to avoid inconsistent voltages driving T21.
  • the invention only adds a thin film transistor T12 on the basis of the existing GOA circuit; the original STV input signal does not need to be changed; the pull-up control circuit after the change generally includes: a thin film transistor T11 whose gate is connected to the N-m level.
  • the source and the drain are respectively connected to the gate of the thin film transistor T12 and the input clock signal XCK(N), the clock signal XCK(N) is opposite to the clock signal CK(N); the source and the drain of the thin film transistor T12 are respectively connected to the level signal output end of the N-th stage GOA unit and the node Q of the Nth stage GOA unit ( N).
  • the start signal STV is required to input the level-transmitted signal output of the N-th-level GOA unit in the previous m-level GOA unit.
  • the pull-up circuit specifically includes: a thin film transistor T21 having a gate connected to the node Q(N), and a source and a drain connected to the gate signal output terminal G(N) and Input clock signal CK(N); thin film transistor T22 whose gate is connected to node Q(N), source and drain are respectively connected to the level signal output terminal ST(N) of the Nth stage GOA unit and the input clock signal CK ( N).
  • the GOA circuit includes eight first clock signals CK(N) having the same waveform and different initial phases, specifically CK1 to CK8, and the initial phases are arranged in accordance with the phase difference of ⁇ /4.
  • first clock signals CK(N) having the same waveform and different initial phases, specifically CK1 to CK8, and the initial phases are arranged in accordance with the phase difference of ⁇ /4.
  • multiple high-frequency clock signals are generally used to drive, and each GOA unit corresponds to one of the clock signals.
  • the four clock signals of CK5 (XCK1) to CK8 (XCK4) are turned on earlier when STV is turned on; the falling edge of STV signal corresponds to the second rising edge of CK5 (XCK1).
  • the GOA circuit of the present invention includes two or more clock signals CK(N) having the same waveform and different initial phases, which are prepared based on amorphous silicon thin film transistors.
  • the invention proposes a design scheme of a novel GOA circuit. On the basis of the original GOA circuit, adding a TFT can make the output waveforms of all series of Q nodes be consistent, and the invention is applicable to all amorphous silicon (a- Si), a GOA circuit having a number of clock signals greater than or equal to two.
  • the GOA circuit of the present invention can be applied to a corresponding liquid crystal display device.
  • FIG. 6 is a schematic diagram of a node Q output signal in a preferred embodiment of the GOA circuit architecture of the present invention.
  • the horizontal axis is time and the vertical axis is voltage. It can be seen that the output waveforms of the first three stages of Q nodes are consistent with the output of the normal level Q node.
  • the GOA circuit and the liquid crystal display device of the present invention can improve the performance of the node Q in each level of the GOA unit, so that the Q node output waveforms of the GOA units of each level are consistent.

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Abstract

一种GOA电路及液晶显示装置，能够使各级GOA单元的Q节点输出波形表现一致。GOA电路包括：第N级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路，以及自举电容(Cb)；第一时钟信号(CK(N))输入上拉电路，第N级GOA单元的级传信号输出端(ST(N))与上拉电路连接；上拉控制电路包括：第一薄膜晶体管(T11)，其栅极连接第N－m级GOA单元的级传信号输出端，源极和漏极分别连接第二薄膜晶体管(T12)的栅极和输入第二时钟信号(XCK(N))；第二薄膜晶体管(T12)的源极和漏极分别连接第N－m级GOA单元的级传信号输出端和节点(Q(N))。

Description

GOA电路及液晶显示装置 技术领域
本发明涉及液晶显示器领域，尤其涉及一种GOA电路及液晶显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
主动式液晶显示器中，每个子像素具有一个薄膜晶体管(TFT)，其栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得该条水平扫描线上的所有TFT打开，此时该条水平扫描线上的像素电极会与垂直方向上的数据线连通，从而将数据线上的显示信号电压写入像素，控制不同液晶的透光度进而达到控制色彩的效果。目前主动式液晶显示面板水平扫描线的驱动主要由面板外接的芯片(IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。阵列基板行驱动(Gate Driver On Array，简称GOA)技术，也就是利用现有薄膜晶体管液晶显示器阵列(Array)制程将栅极(Gate)行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式。
现有的GOA电路，通常包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。GOA单元的主要结构包括上拉电路(pull-high circuit)，上拉控制电路，下拉电路(pull-down circuit)和下拉维持电路(pull-down holding circuit)，以及负责电位抬高的自举(Boast)电容等，上拉控制电路也可以称为预充电路(pre-charge circuit)；上拉电路主要负责将时钟信号(Clock)输出为栅极信号；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA电路传递过来的级传信号或者栅极信号；下拉电路负责在第一时间将栅极信号拉低为低电位，即关闭栅极信号；下拉维持电路则负责将栅极输出信号和上拉电路的栅极信号(通常称为Q点)维持在关闭状态(即负电位)；自举电容则负责Q点的二次抬升，这样有利于上拉电路的G(N)输出。
因为GOA技术可以节省栅极芯片(gate IC)、实现窄边框(narrow border) 等优势，目前GOA技术已经广泛的运用于面板设计当中，因此设计新型的GOA电路是有必要的。但是，目前使用启动信号STV作为GOA开启信号以及Q点预充电信号的情况下，前几级Q点波形由于预充电时间差异，会出现波形不一致的情况。
参见图1，现有的普通GOA电路架构主要由上拉控制电路(包含T11)，上拉电路(包含T21，T22)，下拉电路，下拉维持电路，和自举电容Cb等组成。其中，对于第N级GOA单元，其上拉控制电路连接第N-4级GOA单元的级传信号输出端ST(N-4)和栅极信号输出端G(N-4)，负责控制上拉电路的打开时间以及对节点Q(N)预充电；上拉电路连接时钟信号CK(N)和第N级GOA单元的级传信号输出端ST(N)，负责将时钟信号CK(N)通过第N级的栅极信号输出端G(N)输出至对应的水平扫描线以及输出第N级GOA单元的级传信号；下拉电路负责拉低第N级的栅极信号输出端G(N)的电位；下拉维持电路用于维持拉低第N级的栅极信号输出端G(N)的电位和上拉电路的节点Q(N)的电位，以使栅极信号输出端G(N)所输出栅极信号维持在关闭状态。
参见图2及图3，图2为现有的普通GOA电路架构中节点Q输出信号示意图，横轴为时间，纵轴为电压，显示了1至8级GOA单元中节点Q的波形；图3为现有的普通GOA电路架构中CK输入信号与STV输入信号对应波形示意图，横轴为时间，纵轴为电压，显示了启动信号STV和输入1至6级各级GOA单元的高频时钟信号CK，由图3可见各级GOA单元的高频时钟信号CK为正常CK输出波形，CK波形顺序产生，无相对提前输出。由于上拉控制电路需要输入第N-4级GOA单元的级传信号和栅极信号来启动，所以GOA电路的最初几级需要输入启动信号STV代替级传信号作为GOA开启信号以及Q节点预充电信号，从而造成前三级Q节点输出波形与正常级Q节点输出不一致(参见图2)。
发明内容
因此，本发明的目的在于提供一种GOA电路，使其各级GOA单元的Q节点输出波形表现一致。
本发明的另一目的在于提供一种液晶显示装置，使其GOA电路中各级GOA单元的Q节点输出波形表现一致。
为实现上述目的，本发明提供了一种GOA电路，包括：多个级联的GOA单元，其中第N级GOA单元对第N级水平扫描线的充电进行控制，该第N级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电 路，以及自举电容；该上拉电路，下拉维持电路，下拉电路和自举电容分别与该第N级GOA单元的节点和栅极信号输出端连接，该第N级GOA单元的第一时钟信号输入该上拉电路，该第N级GOA单元的级传信号输出端与该上拉电路连接，该上拉控制电路与该第N级GOA单元的节点连接；该上拉控制电路包括：
第一薄膜晶体管，其栅极连接第N－m级GOA单元的级传信号输出端，m为自然数，源极和漏极分别连接第二薄膜晶体管的栅极和输入该第N级GOA单元的第二时钟信号，该第二时钟信号与第一时钟信号相位相反；
该第二薄膜晶体管的源极和漏极分别连接该第N－m级GOA单元的级传信号输出端和该第N级GOA单元的节点。
其中，一启动信号输入前m级GOA单元中的第N－m级GOA单元的级传信号输出端。
其中，该第一薄膜晶体管的栅极连接第N－4级GOA单元的级传信号输出端，该第二薄膜晶体管的源极和漏极分别连接该第N－4级GOA单元的级传信号输出端和该第N级GOA单元的节点。
其中，一启动信号输入前四级GOA单元中的第N－4级GOA单元的级传信号输出端。
其中，该GOA电路包括波形相同、初始相位不同的八种第一时钟信号。
其中，所述八种第一时钟信号的初始相位按照π/4的相位差等差排列。
其中，该GOA电路包括波形相同、初始相位不同的两种或两种以上的第一时钟信号。
其中，该GOA电路基于非晶硅薄膜晶体管制备。
其中，所述上拉电路包括：
第三薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的栅极信号输出端和输入该第一时钟信号；
第四薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的级传信号输出端和输入该第一时钟信号。
本发明还提供了一种液晶显示装置，包括上述的GOA电路。
本发明还提供一种GOA电路，包括：多个级联的GOA单元，其中第N级GOA单元对第N级水平扫描线的充电进行控制，该第N级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路，以及自举电容；该上拉电路，下拉维持电路，下拉电路和自举电容分别与该第N级GOA单元的节点和栅极信号输出端连接，该第N级GOA单元的第一时钟信号输入该上拉电路，该第N级GOA单元的级传信号输出端与该上拉电路连接， 该上拉控制电路与该第N级GOA单元的节点连接；该上拉控制电路包括：
第一薄膜晶体管，其栅极连接第N－m级GOA单元的级传信号输出端，m为自然数，源极和漏极分别连接第二薄膜晶体管的栅极和输入该第N级GOA单元的第二时钟信号，该第二时钟信号与第一时钟信号相位相反；
该第二薄膜晶体管的源极和漏极分别连接该第N－m级GOA单元的级传信号输出端和该第N级GOA单元的节点；
其中，一启动信号输入前m级GOA单元中的第N－m级GOA单元的级传信号输出端；
其中，该GOA电路包括波形相同、初始相位不同的两种或两种以上的第一时钟信号；
其中，该GOA电路基于非晶硅薄膜晶体管制备；
其中，所述上拉电路包括：
第三薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的栅极信号输出端和输入该第一时钟信号；
第四薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的级传信号输出端和输入该第一时钟信号。
综上，本发明的GOA电路及液晶显示装置能够提升各级GOA单元中节点Q的表现，使各级GOA单元的Q节点输出波形表现一致。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的普通GOA电路架构示意图；
图2为现有的普通GOA电路架构中节点Q输出信号示意图；
图3为现有的普通GOA电路架构中CK输入信号与STV输入信号对应波形示意图；
图4为本发明GOA电路架构一较佳实施例的示意图；
图5为本发明GOA电路架构一较佳实施例中CK输入信号与STV输入信号对应波形示意图；
图6为本发明GOA电路架构一较佳实施例中节点Q输出信号示意图。
具体实施方式
参见图4，其为本发明GOA电路架构一较佳实施例的示意图，主要由 上拉控制电路(包含T11和T12)，上拉电路(包含T21，T22)，下拉电路，下拉维持电路，和自举电容Cb等组成。其中，对于第N级GOA单元，其上拉控制电路负责控制上拉电路的打开时间以及对节点Q(N)预充电；上拉电路连接高频时钟信号CK(N)和第N级GOA单元的级传信号输出端ST(N)，负责将时钟信号CK(N)通过第N级的栅极信号输出端G(N)输出至对应的水平扫描线以及输出第N级GOA单元的级传信号；下拉电路负责拉低第N级的栅极信号输出端G(N)的电位；下拉维持电路用于维持拉低第N级的栅极信号输出端G(N)的电位和上拉电路的节点Q(N)的电位，以使栅极信号输出端G(N)所输出栅极信号维持在关闭状态。自举电容Cb则负责节点Q(N)的二次抬升，这样有利于上拉电路的输出。
在此较佳实施例中，该薄膜晶体管T11的栅极连接第N－4级GOA单元的级传信号输出端ST(N－4)，薄膜晶体管T12的源极和漏极分别连接该第N－4级GOA单元的级传信号输出端ST(N－4)和该第N级GOA单元的节点Q(N)。此时需要提供启动信号STV输入前四级GOA单元中的第N－4级GOA单元的级传信号输出端ST(N－4)，从而开启整个GOA电路以及作为节点Q(N)的预充电信号。
图4中所示上拉控制电路具体结构仅用于举例说明本发明，本发明通过改变上拉控制电路，新增一颗命名为T12的TFT，使得各级GOA单元的节点Q(N)点输出波形表现一致，避免驱动T21的电压不一致。本发明只在现有GOA电路基础上，增加一颗薄膜晶体管T12；原先STV输入信号无需做变更；改变后上拉控制电路一般来说包括：薄膜晶体管T11，其栅极连接第N－m级GOA单元的级传信号输出端，m为自然数(图4所示为m＝4时电路架构)，源极和漏极分别连接薄膜晶体管T12的栅极和输入时钟信号XCK(N)，时钟信号XCK(N)与时钟信号CK(N)相位相反；薄膜晶体管T12的源极和漏极分别连接该第N－m级GOA单元的级传信号输出端和该第N级GOA单元的节点Q(N)。对于前m级GOA单元，需要启动信号STV输入前m级GOA单元中的第N－m级GOA单元的级传信号输出端。
在图4所示的较佳实施例中，上拉电路具体包括：薄膜晶体管T21，其栅极连接该节点Q(N)，源极和漏极分别连接栅极信号输出端G(N)和输入时钟信号CK(N)；薄膜晶体管T22，其栅极连接节点Q(N)，源极和漏极分别连接第N级GOA单元的级传信号输出端ST(N)和输入时钟信号CK(N)。
参见图5，其为本发明GOA电路架构该较佳实施例中CK输入信号与 STV输入信号对应波形示意图，横轴为时间，纵轴为电压。该较佳实施例中，该GOA电路包括波形相同、初始相位不同的八种第一时钟信号CK(N)，具体为CK1～CK8，初始相位按照π/4的相位差等差排列。对于大尺寸高分辨率面板，一般都会采用多个高频时钟信号的方式来驱动，各个GOA单元分别对应其中一个时钟信号。参见图5，若为8个时钟信号，则CK5(XCK1)～CK8(XCK4)四个时钟信号在STV开启时，提前开启；STV信号下降沿对应CK5(XCK1)第二个上升沿。
一般来说，本发明的GOA电路包括波形相同、初始相位不同的两种或两种以上的时钟信号CK(N)，该GOA电路基于非晶硅薄膜晶体管制备。本发明提出了一种新型的GOA电路的设计方案，在原有GOA电路基础上，增加一个TFT，即可使得所有级数的Q节点输出波形表现一致，本发明适用于所有非晶硅(a-si)、时钟信号数目大于或等于2的GOA电路。本发明的GOA电路可以应用于相应的液晶显示装置中。
图6为本发明GOA电路架构一较佳实施例中节点Q输出信号示意图，横轴为时间，纵轴为电压，可见前三级Q节点输出波形与正常级Q节点输出一致。
综上，本发明的GOA电路及液晶显示装置能够提升各级GOA单元中节点Q的表现，使各级GOA单元的Q节点输出波形表现一致。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (15)

  1. 一种GOA电路，包括：多个级联的GOA单元，其中第N级GOA单元对第N级水平扫描线的充电进行控制，该第N级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路，以及自举电容；该上拉电路，下拉维持电路，下拉电路和自举电容分别与该第N级GOA单元的节点和栅极信号输出端连接，该第N级GOA单元的第一时钟信号输入该上拉电路，该第N级GOA单元的级传信号输出端与该上拉电路连接，该上拉控制电路与该第N级GOA单元的节点连接；该上拉控制电路包括：
    第一薄膜晶体管，其栅极连接第N－m级GOA单元的级传信号输出端，m为自然数，源极和漏极分别连接第二薄膜晶体管的栅极和输入该第N级GOA单元的第二时钟信号，该第二时钟信号与第一时钟信号相位相反；
    该第二薄膜晶体管的源极和漏极分别连接该第N－m级GOA单元的级传信号输出端和该第N级GOA单元的节点。
  2. 如权利要求1所述的GOA电路，其中，一启动信号输入前m级GOA单元中的第N－m级GOA单元的级传信号输出端。
  3. 如权利要求1所述的GOA电路，其中，该第一薄膜晶体管的栅极连接第N－4级GOA单元的级传信号输出端，该第二薄膜晶体管的源极和漏极分别连接该第N－4级GOA单元的级传信号输出端和该第N级GOA单元的节点。
  4. 如权利要求3所述的GOA电路，其中，一启动信号输入前四级GOA单元中的第N－4级GOA单元的级传信号输出端。
  5. 如权利要求3所述的GOA电路，其中，该GOA电路包括波形相同、初始相位不同的八种第一时钟信号。
  6. 如权利要求5所述的GOA电路，其中，所述八种第一时钟信号的初始相位按照π/4的相位差等差排列。
  7. 如权利要求1所述的GOA电路，其中，该GOA电路包括波形相同、初始相位不同的两种或两种以上的第一时钟信号。
  8. 如权利要求1所述的GOA电路，其中，该GOA电路基于非晶硅薄膜晶体管制备。
  9. 如权利要求1所述的GOA电路，其中，所述上拉电路包括：
    第三薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的栅极信号输出端和输入该第一时钟信号；
    第四薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的级传信号输出端和输入该第一时钟信号。
  10. 一种液晶显示装置，包括如权利要求1所述的GOA电路。
  11. 一种GOA电路，包括：多个级联的GOA单元，其中第N级GOA单元对第N级水平扫描线的充电进行控制，该第N级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路，以及自举电容；该上拉电路，下拉维持电路，下拉电路和自举电容分别与该第N级GOA单元的节点和栅极信号输出端连接，该第N级GOA单元的第一时钟信号输入该上拉电路，该第N级GOA单元的级传信号输出端与该上拉电路连接，该上拉控制电路与该第N级GOA单元的节点连接；该上拉控制电路包括：
    第一薄膜晶体管，其栅极连接第N－m级GOA单元的级传信号输出端，m为自然数，源极和漏极分别连接第二薄膜晶体管的栅极和输入该第N级GOA单元的第二时钟信号，该第二时钟信号与第一时钟信号相位相反；
    该第二薄膜晶体管的源极和漏极分别连接该第N－m级GOA单元的级传信号输出端和该第N级GOA单元的节点；
    其中，一启动信号输入前m级GOA单元中的第N－m级GOA单元的级传信号输出端；
    其中，该GOA电路包括波形相同、初始相位不同的两种或两种以上的第一时钟信号；
    其中，该GOA电路基于非晶硅薄膜晶体管制备；
    其中，所述上拉电路包括：
    第三薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的栅极信号输出端和输入该第一时钟信号；
    第四薄膜晶体管，其栅极连接该第N级GOA单元的节点，源极和漏极分别连接该第N级GOA单元的级传信号输出端和输入该第一时钟信号。
  12. 如权利要求11所述的GOA电路，其中，该第一薄膜晶体管的栅极连接第N－4级GOA单元的级传信号输出端，该第二薄膜晶体管的源极和漏极分别连接该第N－4级GOA单元的级传信号输出端和该第N级GOA单元的节点。
  13. 如权利要求12所述的GOA电路，其中，一启动信号输入前四级GOA单元中的第N－4级GOA单元的级传信号输出端。
  14. 如权利要求12所述的GOA电路，其中，该GOA电路包括波形相同、初始相位不同的八种第一时钟信号。
  15. 如权利要求14所述的GOA电路，其中，所述八种第一时钟信号 的初始相位按照π/4的相位差等差排列。
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CN103440839A (zh) * 2013-08-09 2013-12-11 京东方科技集团股份有限公司 移位寄存单元、移位寄存器和显示装置
CN105096904A (zh) * 2015-09-30 2015-11-25 京东方科技集团股份有限公司 栅极驱动电路、显示装置和驱动方法

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