WO2020015138A1 - 一种goa电路及液晶显示装置 - Google Patents

一种goa电路及液晶显示装置 Download PDF

Info

Publication number
WO2020015138A1
WO2020015138A1 PCT/CN2018/105926 CN2018105926W WO2020015138A1 WO 2020015138 A1 WO2020015138 A1 WO 2020015138A1 CN 2018105926 W CN2018105926 W CN 2018105926W WO 2020015138 A1 WO2020015138 A1 WO 2020015138A1
Authority
WO
WIPO (PCT)
Prior art keywords
goa unit
circuit
pull
goa
signal
Prior art date
Application number
PCT/CN2018/105926
Other languages
English (en)
French (fr)
Inventor
朱静
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020015138A1 publication Critical patent/WO2020015138A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a GOA circuit and a liquid crystal display device capable of improving the reliability of an amorphous silicon (a_Si) GOA circuit.
  • a_Si amorphous silicon
  • Array substrate line driver (Gate, Driver, Array, GOA) technology is one of the driving methods of making the gate line drive circuit on the array (Array) substrate by using the existing TFT-LCD array process. Item technology. GOA technology can save the gate chip (IC), which is beneficial to the design and cost reduction of the narrow border on the side of the gate driver of the display screen. It is widely used and studied.
  • the existing GOA circuit usually includes a plurality of cascaded GOA units, and each stage of the GOA unit drives a horizontal scanning line correspondingly.
  • the main structure of the GOA unit includes a pull-high circuit, a pull-up control circuit, a pull-down circuit, and a pull-down holding circuit, as well as a bootstrap that is responsible for raising the potential ( Boast) capacitors, etc., the pull-up control circuit can also be called a pre-charge circuit.
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as the gate signal;
  • the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and is generally connected to the stage-level signal or gate signal transmitted from the previous GOA circuit;
  • the pull-down circuit is responsible for The gate signal is pulled to a low potential at the first time, that is, the gate signal is turned off;
  • the pull-down maintenance circuit is responsible for pulling the gate output signal and the gate signal of the pull-up circuit (commonly referred to as the node Q (n of the GOA unit) )) Is maintained in the off state (ie, negative potential);
  • the bootstrap capacitor is responsible for the second lifting of node Q (n), which is beneficial to the output of the gate signal output terminal G (n) of the pull-up circuit.
  • the existing GOA circuit is mainly composed of a pull-up control circuit (including the thin film transistor T11), a pull-up circuit (including the thin film transistor T21), a pull-down circuit, a pull-down sustaining circuit, and a bootstrap capacitor Cb.
  • the pull-up control circuit is connected to the stage signal output terminal ST (n-1), the gate signal output terminal G (n-1) of the n-1 stage GOA unit, and the n-th stage.
  • the node Q (n) of the GOA unit is responsible for controlling the opening time of the pull-up circuit and pre-charging the node Q (n); the pull-up circuit is connected to the AC signal CK / XCK and the gate signal output terminal G (n) of the n-th GOA unit.
  • n) is responsible for outputting the AC signal CK / XCK through the gate signal output terminal G (n) of the n-th GOA unit to the corresponding horizontal scanning line; the pull-down circuit connects the node Q (n) and the n-th GOA unit.
  • the gate signal output terminal G (n) of the n-stage GOA unit and the gate signal output terminal G (n + 1) of the n + 1th stage GOA unit are responsible for pulling down the gate signal output terminal G of the nth stage GOA unit.
  • the pull-down sustaining circuit connects the node Q (n) of the n-th stage GOA unit and the gate signal output terminal G (n) of the n-th stage GOA unit to maintain the gate of the n-th stage GOA unit pulled down
  • FIG. 2 is a timing diagram of input signals in the circuit shown in FIG. 1.
  • the horizontal axis is time and the vertical axis is voltage.
  • the required signal is fed from a level shifter unit at the system end, where STV is the start signal, and the AC signal CK / XCK is high-frequency AC power with completely opposite phases. Since the pull-up control circuit needs to input the stage signal and gate signal of the n-1th GOA unit to start, the first stage of the GOA circuit needs to input the start signal STV instead of the stage signal and the gate signal as the GOA start signal. And the pre-charge signal of node Q1 of the first-level GOA unit.
  • An object of the present invention is to provide a GOA circuit and a liquid crystal display device. Compared with the existing GOA circuit, it can reduce the risk of leakage and improve the reliability of the GOA circuit.
  • the present invention provides a GOA circuit, including: a plurality of cascaded GOA units, wherein the n-th GOA unit controls the charging of the n-th horizontal scanning line, and the n-th GOA unit includes A pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, and a bootstrap capacitor; the pull-up control circuit is connected to the stage signal output terminal of the n-1th GOA unit, the second AC signal, and the nth GOA The node of the unit, the pull-up circuit is connected to the first AC signal and the gate signal output terminal of the n-th GOA unit, and the pull-down circuit is connected to the node of the n-th GOA unit and the n-th GOA unit The gate signal output terminal and the gate signal output terminal of the n + 1th stage GOA unit, the pull-down sustaining circuit is connected to the node of the nth stage GOA unit and the gate signal output terminal of the n
  • the present invention also provides a GOA circuit, which includes: a plurality of cascaded GOA units, wherein the n-th GOA unit controls the charging of the n-th horizontal scanning line, and the n-th GOA unit
  • the pull-up control circuit includes a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down sustaining circuit, and a bootstrap capacitor; the pull-up control circuit is connected to the stage signal output terminal of the n-1th GOA unit, the second AC signal, and the nth stage A node of a level GOA unit, the pull-up circuit is connected to the first AC signal and a gate signal output terminal of the n-th GOA unit, and the pull-down circuit is connected to a node of the n-th GOA unit and the n-th GOA A gate signal output terminal of the unit and a gate signal output terminal of the n + 1th stage GOA unit, and the pull-down maintaining circuit is connected to a node
  • the present invention further provides a liquid crystal display device.
  • the liquid crystal display device includes a GOA circuit, and the GOA circuit includes: a plurality of cascaded GOA units, where the n-th GOA unit has an n-th level Scan line charging is controlled.
  • the n-th GOA unit includes a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, and a bootstrap capacitor.
  • the pull-up control circuit is connected to the n-1 level GOA unit.
  • the pull-up circuit is connected to the first AC signal and the gate signal output of the n-th GOA unit
  • the pull-down circuit is connected to the first a node of an n-level GOA unit, a gate signal output of the n-th GOA unit, and a gate signal output of an n + 1-th GOA unit
  • the pull-down maintaining circuit is connected to the node of the n-th GOA unit
  • the bootstrap capacitor is respectively connected to the node of the n-th GOA unit and the gate signal output of the n-th GOA unit, the first Two AC signals and the first AC signal
  • the pull-up control circuit includes: a first thin film transistor, a gate of which is connected to a stage signal output terminal of the n-1th GOA unit, a source connected to a drain of a fifth thin film transistor, and
  • the GOA circuit according to the present invention only adds a thin film transistor connected in the form of a diode on the basis of the existing GOA circuit, and accesses a reverse signal with a phase opposite to the signal connected by the pull-up circuit, so that the pull-up control circuit
  • the waveform of the connection between the first thin film transistor and the new thin film transistor is close to the DC signal corresponding to the high potential of the AC signal, so there is no need to add a new DC signal line. Therefore, under the premise of not increasing the fan-out space of the GOA circuit, the drain of the first thin film transistor is connected to a high-potential DC signal by using the existing signal, and the node Q (n) of the n-th GOA unit can be leaked during the potential maintenance stage. The risk is greatly reduced, thereby improving the trustworthy performance of the GOA circuit without increasing the size of the bezel, which is conducive to the realization of the narrow bezel design of the display panel.
  • FIG. 1 is a schematic diagram of an existing GOA circuit architecture
  • FIG. 2 is a timing diagram of an input signal in the circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of an embodiment of a GOA circuit according to the present invention.
  • FIG. 4 is a timing diagram of an input signal of the circuit shown in FIG. 3;
  • FIG. 5 is a timing diagram of a node Q (n) of the circuit shown in FIG. 3;
  • FIG. 6 is a schematic diagram of the Id-Vg curve of the circuit shown in FIG. 3.
  • the "first" or “down” of the second feature may include the first and second features in direct contact, and may also include the first and second features. Not directly, but through another characteristic contact between them.
  • the first feature is “above”, “above”, and “above” the second feature, including that the first feature is directly above and obliquely above the second feature, or merely indicates that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below”, and “below” of the second feature, including the fact that the first feature is directly below and obliquely below the second feature, or merely indicates that the first feature is less horizontal than the second feature.
  • the GOA circuit includes: a plurality of cascaded GOA units, wherein the n-th GOA unit controls the charging of the n-th horizontal scanning line.
  • the n-th stage GOA unit includes a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down sustaining circuit, and a bootstrap capacitor Cb;
  • the pull-up control circuit is connected to the stage signal output terminal of the n-1th GOA unit ST (n-1), the second AC signal XCK / CK and the node Q (n) of the n-th GOA unit, the pull-up circuit connects the first AC signal CK / XCK and the gate signal of the n-th GOA unit
  • An output terminal G (n) the pull-down circuit is connected to the node Q (n) of the n-th GOA unit, the gate signal output terminal G (n) of the n-th GOA unit, and the gate of the n + 1-th GOA unit
  • a signal output terminal G (n + 1), the pull-down sustaining circuit is connected to a node Q (n) of the n-th GOA unit and a gate signal output G (n
  • the pull-up control circuit is connected to the stage signal output terminal ST (n-1) of the n-1th stage GOA unit, the second AC signal XCK / CK, and the node Q (n) of the nth stage GOA unit, It is responsible for controlling the opening time of the pull-up circuit and pre-charging the node Q (n).
  • the pull-up control circuit includes: a first thin-film transistor T11 and a diode; a gate of the first thin-film transistor T11 is connected to a stage-transmission signal output terminal ST (n-1) of the n-1th GOA unit, a source and a drain; The poles are respectively connected to the cathode of the diode and the node Q (n) of the n-th GOA unit, and the anode of the diode is connected to the second AC signal XCK / CK.
  • the second AC signal XCK / CK is opposite to the phase of the first AC signal CK / XCK, that is, when the first AC signal is CK, the second AC signal is XCK; when the first AC signal is XCK, the second AC signal For CK.
  • CK and XCK are high-frequency alternating currents with completely opposite phases, and their high and low potentials are 28V and -8V, respectively.
  • the diode uses a fifth thin film transistor T1A, the gate of which is connected to the source is connected to the second AC signal XCK / CK, and the drain is connected to the source of the first thin film transistor T11. That is, the fifth thin film transistor T1A is connected in a diode form, and a reverse signal (XCK / CK) having a phase opposite to a signal (CK / XCK) connected to the pull-up circuit is connected.
  • the waveform of the point M at the connection of the first thin film transistor T11 and the fifth thin film transistor T1A is close to the DC signal corresponding to the high potential of the AC signal CKH.
  • the node Q (n) is in the potential holding phase (that is, the first The second stage and the later time points), Vgs ⁇ 0, Vds is smaller than the previous design, the gate signal falling (Gate Falling) is reduced, the leakage risk is greatly reduced, and the reliability performance of the GOA circuit is greatly improved. Moreover, it is not necessary to add a new DC signal line, which can further facilitate the realization of the narrow border design of the display panel.
  • the pull-up control circuit needs to input the stage signal ST (n-1) and the second AC signal XCK / CK of the n-1 stage GOA unit to start
  • the first stage of the GOA circuit needs to input the start signal STV instead of the stage transmission
  • the signal is used as the GOA on signal and the precharge signal of node Q1 of the first-level GOA unit. That is, a start signal STV is input to the stage signal output terminal ST1 of the first stage GOA unit.
  • the pull-up circuit is connected to the first AC signal CK / XCK and the gate signal output terminal G (n) of the n-th GOA unit, and is responsible for passing the first AC signal CK / XCK through the gate of the n-th GOA unit.
  • the polar signal output terminal G (n) is output to the corresponding horizontal scanning line.
  • the pull-up circuit includes: a second thin film transistor T21, a gate of which is connected to a node Q (n) of an n-th GOA unit, and a source and a drain of which are respectively connected to the first AC signal CK / XCK And the gate signal output terminal G (n) of the n-th GOA unit.
  • the pull-down circuit is connected to the node Q (n) of the n-th GOA unit, the gate signal output terminal G (n) of the n-th GOA unit, and the gate signal output G of the n + 1-th GOA unit.
  • (n + 1) is responsible for pulling down the potential of the gate signal output terminal G (n) of the n-th GOA unit.
  • the pull-down circuit includes a third thin film transistor T31 and a fourth thin film transistor T41.
  • the third thin film transistor T31 has a gate connected to a gate signal output terminal G (n + 1) of the n + 1th stage GOA unit, and a source and a drain connected to the first direct current signal VSSQ and the nth stage GOA unit respectively.
  • the gate signal output terminal G (n) of the n-level GOA unit the potential of the first DC signal VSSQ is lower than the potential of the second DC signal VSSG.
  • VSSQ and VSSG are both low-voltage direct currents, and the potentials are ⁇ 8V and ⁇ 5V, respectively.
  • the use of two VSSs can reduce the decline of the gate signal.
  • the second thin-film transistor T21 of the pull-up circuit and the first thin-film transistor T11 of the pull-up control circuit are locked tighter, which greatly reduces the risk of leakage. The reliability of the GOA circuit is strong. Promotion.
  • the pull-down sustaining circuit connects the node Q (n) of the n-th GOA unit and the gate signal output terminal G (n) of the n-th GOA unit to maintain the gate signal output of the n-th GOA unit pulled down
  • the potential of the terminal G (n) and the potential of the node Q (n) of the n-th GOA unit are such that the gate signal output from the gate signal output terminal G (n) of the n-th GOA unit is maintained in a closed state.
  • FIG. 4 is a timing diagram of an input signal of the circuit shown in FIG. 3;
  • FIG. 5 is a timing diagram of a node Q (n) of the circuit shown in FIG. 3; and
  • FIG. 6 is a schematic diagram of an Id-Vg curve of the circuit shown in FIG. 3.
  • STV, CK, and XCK can all use the signals used by the existing GOA circuit, and the waveform of the point M at the connection between T11 and T1A is close to the DC signal corresponding to the AC signal high potential CKH.
  • the high and low potentials of STV are 28V and -5V, respectively; CK and XCK are high-frequency alternating currents with completely opposite signals, and their high and low potentials are 28V and -8V respectively; the high and low potentials of ST (n-1) are 28V and -8V respectively; G The high and low potentials of (n) are 28V and -5V respectively; the point M is DC and the potential is 27V; the potential of Q (n) corresponding to the high potential stage of ST (n-1) is 28V and the corresponding high potential of G (n) The potential of the stage is 52V, and its low potential is -8V; VSSQ and VSSG are low-voltage direct current, and the potentials are -8V and -5V, respectively.
  • the waveform at point M is close to the DC signal corresponding to the high potential CKH of the AC signal, so there is no need to add a new DC signal line.
  • the output point Q (n) of T11 is Vgs ⁇ 0 during the potential maintenance stage (that is, the second stage No. 2 of Q (n) and the subsequent time points), and Vds is smaller than the previous design ( As shown in Table 1).
  • the present invention greatly reduces the risk of leakage, greatly improves the reliability performance of the GOA circuit, and facilitates the realization of a narrow bezel design of the display panel because a new DC signal line is not required.
  • the GOA circuit according to the present invention only adds a thin film transistor connected in the form of a diode on the basis of the existing GOA circuit, and receives a reverse signal (phase opposite to the signal (CK / XCK)) connected to the pull-up circuit ( XCK / CK), so that the waveform at the point M of the connection between the first thin film transistor T11 and the newly added thin film transistor T1A of the pull-up control circuit is close to the DC signal corresponding to the AC signal high potential CKH, so there is no need to add a new DC signal line.
  • the existing thin-film transistor T11 is connected to a high-potential DC signal by using the existing signal, so that the node Q (n) has a risk of leakage during the potential maintenance stage. It is greatly reduced, thereby improving the reliability performance of the GOA circuit, and does not increase the size of the bezel, which is conducive to the realization of the narrow bezel design of the display panel.
  • the GOA circuit is prepared based on an amorphous silicon thin film transistor. That is, the present invention is applicable to all GOA circuits of amorphous silicon (a-si).
  • the GOA circuit of the present invention can be applied to a corresponding liquid crystal display device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种GOA电路及液晶显示装置，通过在现有GOA电路的基础上在上拉控制电路增加一颗连接成二极管形式的薄膜晶体管（T1A），接入与上拉电路接入的信号（CK/XCK）相位相反的反向信号（XCK/CK），使得上拉控制电路的第一薄膜晶体管（T11）的源极接高电位的直流信号，因而无需增加新的直流信号线，在不增加GOA电路扇出空间的前提下，借用现有的信号实现第一薄膜晶体管（T11）的源极接高电位的直流信号，可以使第n级GOA单元的节点（Q(n)）在电位维持阶段漏电风险减小，提升GOA电路的信赖性能，且不增加边框的尺寸，利于实现显示面板窄边框设计。

Description

一种GOA电路及液晶显示装置 技术领域
本发明涉及液晶显示技术领域，尤其是涉及一种可提高非晶硅(a_Si)GOA电路信赖性能(Releability)的GOA电路及液晶显示装置。
背景技术
随着光电与半导体技术的发展，液晶显示器(Liquid Crystal Display，LCD)也得到了蓬勃发展。在诸多液晶显示器中，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT‐LCD)具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等优越特性。阵列基板行驱动(Gate Driver on Array，GOA)技术，是利用现有TFT‐LCD阵列制程将栅极行驱动电路制作在阵列(Array)基板上，实现对栅极逐行扫描的驱动方式的一项技术。GOA技术可以节省栅极芯片(Gate IC)，有利于显示屏栅极行驱动(Gate Driver)侧窄边框(narrow border)的设计和成本的降低，得到广泛地应用和研究。
现有的GOA电路，通常包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。GOA单元的主要结构包括上拉电路(pull‐high circuit)，上拉控制电路，下拉电路(pull‐down circuit)和下拉维持电路(pull‐down holding circuit)，以及负责电位抬高的自举(Boast)电容等，上拉控制电路也可以称为预充电路(pre‐charge circuit)。上拉电路主要负责将时钟信号(Clock)输出为栅极信号；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA电路传递过来的级传信号或者栅极信号；下拉电路负责在第一时间将栅极信号拉低为低电位，即关闭栅极信号；下拉维持电路则负责将栅极输出信号和上拉电路的栅极信号(通常称为该GOA单元的节点Q(n))维持在关闭状态(即负电位)；自举电容则负责节点Q(n)的二次抬升，这样有利于上拉电路的栅极信号输出端G(n)的输出。
技术问题
参见图1，现有的GOA电路架构示意图。现有的GOA电路主要由上拉控制电路(包含薄膜晶体管T11)，上拉电路(包含薄膜晶体管T21)，下拉电路，下拉维持电路，和自举电容Cb等组成。其中，对于第n级GOA单元，其上拉控制电路连接第n‐1级GOA单元的级传信号输出端ST(n‐1)、栅极信号输出端G(n‐1)和第n级GOA单元的节点Q(n)，负责控制上拉电路的打开时间以及对节点Q(n)预充电；上拉电路连接交流信号CK/XCK和第n级GOA单元的栅极信号输出端G(n)，负责将交流信号CK/XCK通过第n级GOA单元的栅极信号输出端G(n)输出至对应的水平扫描线；下拉电路连接第n级GOA单元的节点Q(n)、第n级GOA单元的栅极信号输出端G(n)和第n+1级GOA单元的栅极信号输出端G(n+1)，负责拉低第n级GOA单元的栅极信号输出端G(n)的电位；下拉维持电路连接第n级GOA单元的节点Q(n)和第n级GOA单元的栅极信号输出端G(n)，用于维持拉低第n级GOA单元的栅极信号输出端G(n)的电位和第n级GOA单元的节点Q(n)的电位，以使第n级GOA单元的栅极信号输出端G(n)所输出栅极信号维持在关闭状态。
参见图2，图2为图1所示电路中输入信号的时序图，横轴为时间，纵轴为电压。所需信号是从系统端的电平转换器(Level Shifter)单元给入，其中，STV是启动信号，交流信号CK/XCK是相位完全相反的高频交流电。由于上拉控制电路需要输入第n‐1级GOA单元的级传信号和栅极信号来启动，所以GOA电路的最初一级需要输入启动信号STV代替级传信号以及栅极信号，作为GOA开启信号以及第1级GOA单元的节点Q1的预充电信号。
在第n级GOA单元的节点Q(n)的电位维持阶段存在栅极信号下降(Gate Falling)，造成漏电，影响非晶硅GOA电路的信赖性能。所以减少漏电风险对提升非晶硅GOA电路的信赖性能有很大意义。
技术解决方案
本发明的目的在于，提供一种GOA电路及液晶显示装置，与现有的GOA电路相比，可以减少漏电风险，提升GOA电路的信赖性能。
为实现上述目的，本发明提供了一种GOA电路，包括：级联的多个GOA单元，其中第n级GOA单元对第 n级水平扫描线的充电进行控制，所述第n级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路以及自举电容；所述上拉控制电路连接第n‐1级GOA单元的级传信号输出端、第二交流信号和第n级GOA单元的节点，所述上拉电路连接第一交流信号和第n级GOA单元的栅极信号输出端，所述下拉电路连接所述第n级GOA单元的节点、所述第n级GOA单元的栅极信号输出端和第n+1级GOA单元的栅极信号输出端，所述下拉维持电路连接所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端，所述自举电容分别与所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端连接，所述第二交流信号与所述第一交流信号相位相反；所述上拉控制电路包括：第一薄膜晶体管，其栅极连接所述第n‐1级GOA单元的级传信号输出端，源极连接第五薄膜晶体管的漏极，漏极连接所述第n级GOA单元的节点，所述第五薄膜晶体管的栅极与源极相接后连接所述第二交流信号；所述上拉电路包括：第二薄膜晶体管，其栅极连接所述第n级GOA单元的节点，源极和漏极分别连接所述第一交流信号和所述第n级GOA单元的栅极信号输出端。
为实现上述目的，本发明还提供了一种GOA电路，包括：级联的多个GOA单元，其中第n级GOA单元对第n级水平扫描线的充电进行控制，所述第n级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路，以及自举电容；所述上拉控制电路连接第n‐1级GOA单元的级传信号输出端、第二交流信号和第n级GOA单元的节点，所述上拉电路连接第一交流信号和第n级GOA单元的栅极信号输出端，所述下拉电路连接所述第n级GOA单元的节点、所述第n级GOA单元的栅极信号输出端和第n+1级GOA单元的栅极信号输出端，所述下拉维持电路连接所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端，所述自举电容分别与所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端连接，所述第二交流信号与所述第一交流信号相位相反；所述上拉控制电路包括：第一薄膜晶体管，其栅极连接所述第n‐1级GOA单元的级传信号输出端，源极和漏极分别连接二极管的阴极和所述第n级GOA单元的节点，所述二极管的阳极连接所述第二交流信号。
为实现上述目的，本发明还提供了一种液晶显示装置，所述液晶显示装置包括GOA电路，所述GOA电路包括：级联的多个GOA单元，其中第n级GOA单元对第n级水平扫描线的充电进行控制，所述第n级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路以及自举电容；所述上拉控制电路连接第n‐1级GOA单元的级传信号输出端、第二交流信号和第n级GOA单元的节点，所述上拉电路连接第一交流信号和第n级GOA单元的栅极信号输出端，所述下拉电路连接所述第n级GOA单元的节点、所述第n级GOA单元的栅极信号输出端和第n+1级GOA单元的栅极信号输出端，所述下拉维持电路连接所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端，所述自举电容分别与所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端连接，所述第二交流信号与所述第一交流信号相位相反；所述上拉控制电路包括：第一薄膜晶体管，其栅极连接所述第n‐1级GOA单元的级传信号输出端，源极连接第五薄膜晶体管的漏极，漏极连接所述第n级GOA单元的节点，所述第五薄膜晶体管的栅极与源极相接后连接所述第二交流信号；所述上拉电路包括：第二薄膜晶体管，其栅极连接所述第n级GOA单元的节点，源极和漏极分别连接所述第一交流信号和所述第n级GOA单元的栅极信号输出端。
有益效果
本发明所述的GOA电路，仅在现有GOA电路的基础上增加一颗连接成二极管形式的薄膜晶体管，接入与上拉电路接入的信号相位相反的反向信号，使得上拉控制电路的第一薄膜晶体管和新增薄膜晶体管的连接处波形接近交流信号高电位对应的直流信号，因而无需增加新的直流信号线。从而在不增加GOA电路扇出空间的前提下，借用现有的信号实现第一薄膜晶体管的漏极接高电位的直流信号，可以使第n级GOA单元节点Q(n)在电位维持阶段漏电风险大大减小，从而提升GOA电路的信赖性能，并不增加边框的尺寸，利于实现显示面板窄边框设计。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1，现有的GOA电路架构示意图；
图2为图1所示电路中输入信号的时序图；
图3，本发明所述的GOA电路一实施例的示意图；
图4为图3所示电路的输入信号的时序图；
图5为图3所示电路的节点Q(n)的时序图；
图6为图3所示电路的Id‐Vg曲线示意图。
本发明的实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
参考图3，本发明所述的GOA电路一实施例的示意图。所述的GOA电路包括：级联的多个GOA单元，其中第n级GOA单元对第n级水平扫描线的充电进行控制。所述第n级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路，以及自举电容Cb；所述上拉控制电路连接第n‐1级GOA单元的级传信号输出端ST(n‐1)、第二交流信号XCK/CK和第n级GOA单元的节点Q(n)，所述上拉电路连接第一交流信号CK/XCK和第n级GOA单元的栅极信号输出端G(n)，所述下拉电路连接第n级GOA单元的节点Q(n)、第n级GOA单元的栅极信号输出端G(n)和第n+1级GOA单元的栅极信号输出端G(n+1)，所述下拉维持电路连接第n级GOA单元的节点Q(n)和第n级GOA单元的栅极信号输出端G(n)，所述自举电容Cb分别与第n级GOA单元的节点Q(n)和第n级GOA单元的栅极信号输出端G(n)连接；所述第二交流信号XCK/CK与所述第一交流信号CK/XCK相位相反。
具体的，所述上拉控制电路连接第n‐1级GOA单元的级传信号输出端ST(n‐1)、第二交流信号XCK/CK和第n级GOA单元的节点Q(n)，负责控制上拉电路的打开时间以及对节点Q(n)预充电。所述上拉控制电路包括：第一薄膜晶体管T11和二极管；第一薄膜晶体管T11，其栅极连接第n‐1级GOA单元的级传信号输出端ST(n‐1)，源极和漏极分别连接二极管的阴极和第n级GOA单元的节点Q(n)，所述二极管的阳极连接第二交流信号XCK/CK。所述第二交流信号XCK/CK与第一交流信号CK/XCK相位相反，即当第一交流信号为CK时，第二交流信号为XCK；当第一交流信号为XCK时，第二交流信号为CK。本实施例中，CK、XCK是相位完全相反的高频交流电，其高低电位分别是28V、‐8V。
本实施例中，所述二极管采用第五薄膜晶体管T1A，其栅极与源极相接后连接第二交流信号XCK/CK，漏极连接第一薄膜晶体管T11的源极。即，第五薄膜晶体管T1A连接成二极管形式，接入与上拉电路接入的信号(CK/XCK)相位相反的反向信号(XCK/CK)。第一薄膜晶体管T11和第五薄膜晶体管T1A的连接处M点的波形接近交流信号高电位CKH对应的直流信号，这样节点Q(n)在电位维持(Holding)阶段(即Q(n)的第二阶段及后面的时间点)，Vgs<<0,Vds较之前设计减小，栅极信号下降(Gate Falling)程度降低，大大减少了漏电风险，GOA电路的信赖性能大力提升。且无需增加新的直流信号线，可以进一步利于实现显示面板窄边框设计(Narrow Border Design)。
由于上拉控制电路需要输入第n‐1级GOA单元的级传信号ST(n‐1)和第二交流信号XCK/CK来启动，所以GOA电路的最初一级需要输入启动信号STV代替级传信号，作为GOA开启信号以及第1级GOA单元的节点Q1 的预充电信号。即，一启动信号STV输入第1级GOA单元的级传信号输出端ST1。
具体的，所述上拉电路连接第一交流信号CK/XCK和第n级GOA单元的栅极信号输出端G(n)，负责将第一交流信号CK/XCK通过第n级GOA单元的栅极信号输出端G(n)输出至对应的水平扫描线。本实施例中，所述上拉电路包括：第二薄膜晶体管T21，其栅极连接第n级GOA单元的节点Q(n)，源极和漏极分别连接所述第一交流信号CK/XCK和第n级GOA单元的栅极信号输出端G(n)。
具体的，所述下拉电路连接第n级GOA单元的节点Q(n)、第n级GOA单元的栅极信号输出端G(n)和第n+1级GOA单元的栅极信号输出端G(n+1)，负责拉低第n级GOA单元的栅极信号输出端G(n)的电位。本实施例中，所述下拉电路包括：第三薄膜晶体管T31和第四薄膜晶体管T41。第三薄膜晶体管T31，其栅极连接第n+1级GOA单元的栅极信号输出端G(n+1)，源极和漏极分别连接第一直流信号VSSQ和第n级GOA单元的节点Q(n)；第四薄膜晶体管T41，其栅极连接第n+1级GOA单元的栅极信号输出端G(n+1)，源极和漏极分别连接第二直流信号VSSG和第n级GOA单元的栅极信号输出端G(n)，所述第一直流信号VSSQ的电位小于与第二直流信号VSSG的电位。本实施例中，VSSQ、VSSG均为低压直流电，电位分别为‐8V、‐5V。利用两条VSS可以实现栅极信号下降程度降低，上拉电路的第二薄膜晶体管T21和上拉控制电路的第一薄膜晶体管T11锁的更紧，大大减少了漏电风险，GOA电路的信赖性能大力提升。
具体的，下拉维持电路连接第n级GOA单元的节点Q(n)和第n级GOA单元的栅极信号输出端G(n)，用于维持拉低第n级GOA单元的栅极信号输出端G(n)的电位和第n级GOA单元的节点Q(n)的电位，以使第n级GOA单元的栅极信号输出端G(n)所输出栅极信号维持在关闭状态。
接下来结合附图对本发明提供的GOA电路对减少漏电风险、提升信赖性能的表现作进一步说明。其中，图4为图3所示电路的输入信号的时序图；图5为图3所示电路的节点Q(n)的时序图；图6为图3所示电路的Id‐Vg曲线示意图。
其中，STV、CK、XCK均可采用现有GOA电路所使用的信号，T11和T1A的连接处M点的波形接近交流信号高电位CKH对应的直流信号。STV的高低电位分别是28V、‐5V；CK、XCK是信号完全相反的高频交流电，其高低电位分别是28V，‐8V；ST(n‐1)的高低电位分别是28V、‐8V；G(n)的高低电位分别是28V、‐5V；M点是直流电，电位为27V；Q(n)对应ST(n‐1)的高电位阶段的电位为28V，对应G(n)的高电位阶段的电位为52V，其低电位为‐8V；VSSQ、VSSG是低压直流电，电位分别为‐8V、‐5V。利用两条VSS可以实现栅极信号下降程度降低，T21和T11锁的更紧，减少漏电。
M点的波形接近交流信号高电位CKH对应的直流信号，因而无需增加新的直流信号线。对应第n级GOA单元，T11的输出点Q(n)在电位维持阶段(即Q(n)的第二阶段No.2及后面的时间点)Vgs<<0，Vds较之前设计减小(如表1所示)。结合图6所示Id‐Vg曲线示意图可以看出，本发明大大减少了漏电风险，GOA电路信赖性能大力提升，且由于无需增加新的直流信号线，利于实现显示面板窄边框设计。
Figure PCTCN2018105926-appb-000001
表1，本发明与现有设计节点Q(n)对应的不同时间段相应的Vgs及Vds电位差异。
本发明所述的GOA电路，仅在现有GOA电路的基础上增加一颗连接成二极管形式的薄膜晶体管，接入与上拉电路接入的信号(CK/XCK)相位相反的反向信号(XCK/CK)，使得上拉控制电路的第一薄膜晶体管T11和新增薄膜晶体管T1A的连接处M点的波形接近交流信号高电位CKH对应的直流信号，因而无需增加新的直流信号线。从而在不增加GOA电路扇出(Layout)空间的前提下，借用现有的信号实现第一薄膜晶体管T11的漏极接高电位的直流信号，可以使节点Q(n)在电位维持阶段漏电风险大大减小，从而提升GOA电路的信赖性能，并不增加边框的尺寸，利于实现显示面板窄边框设计。
所述GOA电路基于非晶硅薄膜晶体管制备。即，本发明适用于所有非晶硅(a‐si)的GOA电路。本发明的GOA电路可以应用于相应的液晶显示装置中。
工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (14)

  1. 一种GOA电路，包括：级联的多个GOA单元，其中第n级GOA单元对第n级水平扫描线的充电进行控制，所述第n级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路以及自举电容；其中，
    所述上拉控制电路连接第n-1级GOA单元的级传信号输出端、第二交流信号和第n级GOA单元的节点，所述上拉电路连接第一交流信号和第n级GOA单元的栅极信号输出端，所述下拉电路连接所述第n级GOA单元的节点、所述第n级GOA单元的栅极信号输出端和第n+1级GOA单元的栅极信号输出端，所述下拉维持电路连接所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端，所述自举电容分别与所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端连接，所述第二交流信号与所述第一交流信号相位相反；
    所述上拉控制电路包括：第一薄膜晶体管，其栅极连接所述第n-1级GOA单元的级传信号输出端，源极连接第五薄膜晶体管的漏极，漏极连接所述第n级GOA单元的节点，所述第五薄膜晶体管的栅极与源极相接后连接所述第二交流信号；
    所述上拉电路包括：第二薄膜晶体管，其栅极连接所述第n级GOA单元的节点，源极和漏极分别连接所述第一交流信号和所述第n级GOA单元的栅极信号输出端。
  2. 如权利要求1所述的GOA电路，其中，一启动信号输入第1级GOA单元的级传信号输出端。
  3. 如权利要求1所述的GOA电路，其中，所述下拉电路包括：第三薄膜晶体管，其栅极连接所述第n+1级GOA单元的栅极信号输出端，源极和漏极分 别连接第一直流信号和所述第n级GOA单元的节点；
    第四薄膜晶体管，其栅极连接所述第n+1级GOA单元的栅极信号输出端，源极和漏极分别连接第二直流信号和所述第n级GOA单元的栅极信号输出端，所述第一直流信号的电位小于所述第二直流信号的电位。
  4. 如权利要求1所述的GOA电路，其中，所述GOA电路基于非晶硅薄膜晶体管制备。
  5. 一种GOA电路，包括：级联的多个GOA单元，其中第n级GOA单元对第n级水平扫描线的充电进行控制，所述第n级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路以及自举电容(Cb)；其中，
    所述上拉控制电路连接第n-1级GOA单元的级传信号输出端、第二交流信号和第n级GOA单元的节点，所述上拉电路连接第一交流信号和第n级GOA单元的栅极信号输出端，所述下拉电路连接所述第n级GOA单元的节点、所述第n级GOA单元的栅极信号输出端和第n+1级GOA单元的栅极信号输出端，所述下拉维持电路连接所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端，所述自举电容分别与所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端连接，所述第二交流信号与所述第一交流信号相位相反；
    所述上拉控制电路包括：第一薄膜晶体管，其栅极连接所述第n-1级GOA单元的级传信号输出端，源极和漏极分别连接二极管的阴极和所述第n级GOA单元的节点，所述二极管的阳极连接所述第二交流信号。
  6. 如权利要求5所述的GOA电路，其中，一启动信号输入第1级GOA单元的级传信号输出端。
  7. 如权利要求5所述的GOA电路，其中，所述二极管采用第五薄膜晶体管；
    所述第五薄膜晶体管，其栅极与源极相接后连接所述第二交流信号，漏极连接所述第一薄膜晶体管的源极。
  8. 如权利要求5所述的GOA电路，其中，所述上拉电路包括：第二薄膜晶体管，其栅极连接所述第n级GOA单元的节点，源极和漏极分别连接所述第一交流信号和所述第n级GOA单元的栅极信号输出端。
  9. 如权利要求5所述的GOA电路，其中，所述下拉电路包括：第三薄膜晶体管，其栅极连接所述第n+1级GOA单元的栅极信号输出端，源极和漏极分别连接第一直流信号和所述第n级GOA单元的节点；
    第四薄膜晶体管，其栅极连接所述第n+1级GOA单元的栅极信号输出端，源极和漏极分别连接第二直流信号和所述第n级GOA单元的栅极信号输出端，所述第一直流信号的电位小于所述第二直流信号的电位。
  10. 如权利要求5所述的GOA电路，其中，所述GOA电路基于非晶硅薄膜晶体管制备。
  11. 一种液晶显示装置，其中，所述液晶显示装置包括GOA电路，所述GOA电路包括：级联的多个GOA单元，其中第n级GOA单元对第n级水平扫描线的充电进行控制，所述第n级GOA单元包括上拉控制电路，上拉电路，下拉电路，下拉维持电路以及自举电容；其中，
    所述上拉控制电路连接第n-1级GOA单元的级传信号输出端、第二交流信号和第n级GOA单元的节点，所述上拉电路连接第一交流信号和第n级GOA单元的栅极信号输出端，所述下拉电路连接所述第n级GOA单元的节点、所述第n级GOA单元的栅极信号输出端和第n+1级GOA单元的栅极信号输出端，所述下拉维持电路连接所述第n级GOA单元的节点和所述第n级GOA单元的栅极信号输出端，所述自举电容分别与所述第n级GOA单元的节点 和所述第n级GOA单元的栅极信号输出端连接，所述第二交流信号与所述第一交流信号相位相反；
    所述上拉控制电路包括：第一薄膜晶体管，其栅极连接所述第n-1级GOA单元的级传信号输出端，源极连接第五薄膜晶体管的漏极，漏极连接所述第n级GOA单元的节点，所述第五薄膜晶体管的栅极与源极相接后连接所述第二交流信号；
    所述上拉电路包括：第二薄膜晶体管，其栅极连接所述第n级GOA单元的节点，源极和漏极分别连接所述第一交流信号和所述第n级GOA单元的栅极信号输出端。
  12. 如权利要求11所述的液晶显示装置，其中，一启动信号输入第1级GOA单元的级传信号输出端。
  13. 如权利要求11所述的液晶显示装置，其中，所述下拉电路包括：第三薄膜晶体管，其栅极连接所述第n+1级GOA单元的栅极信号输出端，源极和漏极分别连接第一直流信号和所述第n级GOA单元的节点；
    第四薄膜晶体管，其栅极连接所述第n+1级GOA单元的栅极信号输出端，源极和漏极分别连接第二直流信号和所述第n级GOA单元的栅极信号输出端，所述第一直流信号的电位小于所述第二直流信号的电位。
  14. 如权利要求11所述的液晶显示装置，其中，所述GOA电路基于非晶硅薄膜晶体管制备。
PCT/CN2018/105926 2018-07-20 2018-09-17 一种goa电路及液晶显示装置 WO2020015138A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810802546.7A CN108735177A (zh) 2018-07-20 2018-07-20 一种goa电路及液晶显示装置
CN201810802546.7 2018-07-20

Publications (1)

Publication Number Publication Date
WO2020015138A1 true WO2020015138A1 (zh) 2020-01-23

Family

ID=63927216

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/105926 WO2020015138A1 (zh) 2018-07-20 2018-09-17 一种goa电路及液晶显示装置

Country Status (2)

Country Link
CN (1) CN108735177A (zh)
WO (1) WO2020015138A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109767717A (zh) * 2019-03-19 2019-05-17 合肥京东方光电科技有限公司 电压自维持电路及其驱动方法、移位寄存器、栅极驱动电路、显示装置
CN110599979A (zh) * 2019-09-29 2019-12-20 南京中电熊猫平板显示科技有限公司 栅极驱动电路及栅极驱动方法及显示装置
CN110827776B (zh) 2019-10-16 2021-07-06 Tcl华星光电技术有限公司 Goa器件及栅极驱动电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1637549A (zh) * 2003-12-30 2005-07-13 Lg.菲利浦Lcd株式会社 有源矩阵显示器件
US20070047691A1 (en) * 2005-08-30 2007-03-01 Ming-Chun Tseng Bidirectional shift register
CN103839518A (zh) * 2012-11-27 2014-06-04 乐金显示有限公司 移位寄存器及其驱动方法
CN105632446A (zh) * 2016-03-30 2016-06-01 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、显示装置
CN107068087A (zh) * 2017-03-31 2017-08-18 深圳市华星光电技术有限公司 一种goa驱动电路
CN107331366A (zh) * 2017-08-29 2017-11-07 深圳市华星光电半导体显示技术有限公司 一种goa电路及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1637549A (zh) * 2003-12-30 2005-07-13 Lg.菲利浦Lcd株式会社 有源矩阵显示器件
US20070047691A1 (en) * 2005-08-30 2007-03-01 Ming-Chun Tseng Bidirectional shift register
CN103839518A (zh) * 2012-11-27 2014-06-04 乐金显示有限公司 移位寄存器及其驱动方法
CN105632446A (zh) * 2016-03-30 2016-06-01 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、显示装置
CN107068087A (zh) * 2017-03-31 2017-08-18 深圳市华星光电技术有限公司 一种goa驱动电路
CN107331366A (zh) * 2017-08-29 2017-11-07 深圳市华星光电半导体显示技术有限公司 一种goa电路及显示装置

Also Published As

Publication number Publication date
CN108735177A (zh) 2018-11-02

Similar Documents

Publication Publication Date Title
WO2019085578A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
TWI400686B (zh) 液晶顯示器之移位暫存器
WO2020224154A1 (zh) Goa电路和显示装置
TWI404036B (zh) 液晶顯示器
WO2018120330A1 (zh) 栅极驱动电路以及液晶显示装置
US10121442B2 (en) Driving methods and driving devices of gate driver on array (GOA) circuit
CN109509459B (zh) Goa电路及显示装置
WO2016037381A1 (zh) 基于igzo制程的栅极驱动电路
WO2021142922A1 (zh) 一种goa电路和显示装置
WO2018209938A1 (zh) 移位寄存器单元、栅极驱动电路、显示器以及栅极驱动方法
CN107358931B (zh) Goa电路
WO2020019433A1 (zh) 包括goa电路的液晶面板及其驱动方法
WO2019090875A1 (zh) Goa电路
CN107689221B (zh) Goa电路
WO2020259574A1 (zh) 阵列基板行驱动电路单元与其驱动电路及液晶显示面板
CN108806584A (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
WO2022007147A1 (zh) Goa电路以及显示面板
WO2020015138A1 (zh) 一种goa电路及液晶显示装置
WO2015051643A1 (zh) 电平转换模块、阵列基板及显示装置
US20180182299A1 (en) Scanning drive circuit and flat display device having the same
WO2018107533A1 (zh) 一种栅极驱动电路及驱动方法、显示装置
WO2020199486A1 (zh) Goa电路结构及驱动方法
WO2019033492A1 (zh) Goa电路及液晶显示装置
TWI411232B (zh) 移位暫存器電路
US10360866B2 (en) GOA circuit and liquid crystal display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18926867

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18926867

Country of ref document: EP

Kind code of ref document: A1