WO2019085578A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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WO2019085578A1
WO2019085578A1 PCT/CN2018/099669 CN2018099669W WO2019085578A1 WO 2019085578 A1 WO2019085578 A1 WO 2019085578A1 CN 2018099669 W CN2018099669 W CN 2018099669W WO 2019085578 A1 WO2019085578 A1 WO 2019085578A1
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Prior art keywords
pull
circuit
output
sub
node
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PCT/CN2018/099669
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English (en)
French (fr)
Inventor
黄飞
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/343,729 priority Critical patent/US10997886B2/en
Publication of WO2019085578A1 publication Critical patent/WO2019085578A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present application relates to the field of display technologies, and in particular, to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • Liquid crystal display has the advantages of low radiation, small size and low energy consumption, and is widely used in electronic products such as notebook computers, flat-panel televisions or mobile phones.
  • a shift register including a first input sub-circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, a pull-down sub-circuit, and n output sub-circuits, wherein n ⁇ 2, n is a positive integer; the first input sub-circuit is connected to the first signal input terminal, the first control voltage terminal, and the pull-up node, and the first input sub-circuit is configured to be under the control of the first signal input terminal The voltage of the first control voltage terminal is output to the pull-up node; each of the output sub-circuits of each stage is connected to the pull-up node, the signal output end, and the output clock signal end, and each of the output sub-circuits is configured as Outputting, by the pull-up node, a signal of the output clock signal end to the signal output end; the first pull-down control sub-circuit is connected to the first control voltage end, the first clock signal end a pull-down node,
  • the first input sub-circuit includes a first transistor; a gate of the first transistor is coupled to the first signal input, and a first electrode is coupled to the first control voltage The second pole is connected to the pull-up node.
  • each of the output sub-circuits includes an output transistor and a voltage stabilizing capacitor; a gate of the output transistor is coupled to the pull-up node, and a first pole is coupled to the output clock signal terminal The second pole is connected to the signal output terminal; one end of the voltage stabilizing capacitor is connected to the pull-up node, and the other end is connected to the output signal output end.
  • the first pull-down control sub-circuit includes a second transistor; a gate of the second transistor is coupled to the first clock signal terminal, and a first pole is coupled to the first Controlling a voltage terminal, a second pole connected to the pull-down node; the second pull-down control sub-circuit comprising a third transistor; a gate of the third transistor being connected to the pull-up node, the first pole being connected to the a pull-down node, the second pole is connected to the first voltage terminal; the pull-down sub-circuit includes a fourth transistor; a gate of the fourth transistor is connected to the pull-down node, and a first pole is connected to the pull-up node a second pole is coupled to the first voltage terminal.
  • the pull-down sub-circuit is further connected to each of the signal outputs, and the pull-down sub-circuit is further configured to pull the potential of the signal output low under the control of the pull-down node To the first voltage terminal;
  • the pull-down sub-circuit further includes a plurality of output pull-down transistors; a gate of each of the output pull-down transistors is connected to the pull-down node, a first pole is connected to a signal output, and a second A pole is connected to the first voltage terminal.
  • the shift register further includes a first regulated noise reduction sub-circuit connected between the first input sub-circuit and the pull-up node, the first regulated voltage drop a noise sub-circuit is further connected to the first voltage terminal, and/or a second voltage terminal; the first voltage-stabilizing noise reduction sub-circuit is configured to be at the first voltage terminal and/or the second voltage terminal Under control, the voltage of the pull-up node is regulated and noise-reduced.
  • the first regulated noise reduction sub-circuit includes a first capacitor, and/or a fifth transistor; one end of the first capacitor is coupled to an output of the first input sub-circuit The other end is connected to the first voltage terminal; the gate of the fifth transistor is connected to the second voltage terminal, the first pole is connected to the output end of the first input sub-circuit, and the second pole is connected Go to the pull up node.
  • the shift register further includes a second voltage stabilization noise reduction sub-circuit connected between the first pull-down control sub-circuit and the pull-down node, the second voltage regulator a noise reduction sub-circuit is further connected to the first voltage terminal and/or a second voltage terminal; the second voltage-stabilizing noise reduction sub-circuit is configured to be at the first voltage terminal and/or the second voltage terminal Under control, the voltage of the pull-down node is regulated and noise-reduced.
  • the second regulated noise reduction sub-circuit includes a second capacitor, and/or a sixth transistor; one end of the second capacitor is electrically connected to the first pull-down control sub-circuit The other end is connected to the first voltage end; the gate of the sixth transistor is connected to the second voltage end, and the first pole is connected to the output end of the first pull-down control sub-circuit, A second pole is connected to the pull down node.
  • the shift register further includes a second input sub-circuit; the second input sub-circuit is coupled to the second signal input terminal, the second control voltage terminal, the pull-up node, The first input sub-circuit is configured to output the voltage of the second control voltage terminal to the pull-up node under the control of the second signal input terminal.
  • the shift register further includes a third pull-down control sub-circuit; the third pull-down control sub-circuit is connected to the second control voltage terminal, the second clock signal terminal, and the pull-down a node; the third pull-down control sub-circuit is configured to output a voltage of the second control voltage terminal to the pull-down node under control of the second clock signal terminal.
  • the second input sub-circuit includes an eighth transistor; a gate of the eighth transistor is coupled to the second signal input, and a first electrode is coupled to the second control voltage The second pole is connected to the pull-up node.
  • the third pull-down control sub-circuit includes a ninth transistor; a gate of the ninth transistor is coupled to the second clock signal terminal, and a first pole is coupled to the second control At the voltage terminal, the second pole is connected to the pull-down node.
  • a gate drive circuit shift register comprising a plurality of cascaded shift registers of any one of the first aspects, wherein the first signal input of the first stage shift register is connected The start signal terminal; in addition to the first stage shift register, the first signal input of each stage shift register is connected to the last signal output end of the shift register of the stage shift register.
  • a third aspect provides a gate driving circuit including a plurality of cascaded shift registers having a second input sub-circuit; a first signal input end of the first stage shift register is coupled to the start signal terminal; In addition to the one-stage shift register, the first signal input of each stage shift register is connected to the last signal output of the shift register of the previous stage of the shift register; except for the last stage shift register, a second signal input terminal of the first stage shift register is connected to the first signal output end of the shift register of the next stage of the shift register; a second signal input end of the last stage shift register is connected to the Start signal end.
  • a display device comprising the gate driving circuit according to the second aspect or the third aspect.
  • a method for driving a shift register as described above includes: a charging phase, and the first input sub-circuit is controlled by the first signal input terminal a voltage of the control voltage terminal is output to the pull-up node; the second pull-down control sub-circuit pulls the voltage of the pull-down node to the first voltage terminal under the control of the pull-up node; each output sub-circuit stores the pull-up node a signal, and under the control of the pull-up node, respectively output signals outputted from the respective output clock signal ends to signal output terminals connected to the respective output sub-circuits; in the output stage, the respective output sub-circuits will be a signal stored in a stage is output to the pull-up node, and under the control of the pull-up node, the signals of the respective output clock signals are sequentially output to the signal output ends connected to the output sub-circuits, and each signal The output terminal sequentially outputs a gate scan signal; in the reset
  • FIG. 1 is a schematic structural diagram of a shift register according to some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of each sub-circuit of FIG. 1;
  • FIG. 3 is a signal timing diagram for controlling the shift register shown in FIG. 2;
  • FIG. 4 is a schematic structural view of the shift register shown in FIG. 1 , the pull-down sub-circuit is further connected to the signal output ends of each stage;
  • FIG. 5 is a schematic structural diagram of each sub-circuit of FIG. 4;
  • FIG. 6 is a schematic structural diagram of the shift register shown in FIG. 4 further including a first voltage-stabilizing noise reduction sub-circuit and a second voltage-stabilizing noise reduction sub-circuit;
  • FIG. 7 is a schematic structural diagram of each sub-circuit of FIG. 6;
  • FIG. 8 is a schematic structural diagram of the shift register shown in FIG. 4 further including an electronic discharge circuit
  • FIG. 9 is a schematic structural diagram of each sub-circuit of FIG. 7;
  • FIG. 10 is a schematic structural diagram of the shift register shown in FIG. 1 further including a first input sub-circuit and a third pull-down control sub-circuit;
  • FIG. 11 is a schematic structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 12 is a signal timing diagram for controlling the forward output of the shift register shown in FIG. 11;
  • FIG. 13 is a schematic structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 14b is a schematic structural diagram of another gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 15 is a schematic diagram of a specific structure of a shift register provided by the related art.
  • the liquid crystal display comprises a color film substrate and an array substrate which are opposite to each other, wherein the array substrate can be divided into a display area and a peripheral area located around the display area.
  • the display area is provided with horizontally intersecting gate lines and data lines, and the gate lines and the data lines intersect to define a plurality of sub-pixels.
  • the peripheral area is provided with a data driving circuit, and the data driving circuit can sequentially latch the input display data and the clock signal, convert it into an analog signal, and input it to the data line.
  • the peripheral region is further provided with a gate driving circuit, and the gate driving circuit can convert the input clock signal into a voltage that controls the sub-pixel strobe or unstrobed through the shift register, and applies the above to the above Sub-pixel connected gate lines.
  • the gate driving circuit can integrate a circuit mainly composed of a TFT (Thin Film Transistor) gate switch in the periphery by using a GOA (Gate Driver on Array) design. region.
  • the output of each stage of the shift register in the GOA circuit is connected to a row of gate lines.
  • the gate line is scanned row by row, when a row of gate lines is scanned, the gate scan signal outputted from the output terminal of the shift register connected to the gate line can be received, and is connected to the unscanned gate line.
  • the shift register is in a state where the gate scan signal is not output.
  • each stage shift register in the above GOA circuit can only output a gate scan signal to a row of gate lines.
  • the number of shift registers needs to match the number of gate lines, so that As a result, it is not conducive to achieving a narrow bezel design of the display panel.
  • the shift register includes a first input sub-circuit 10, a first pull-down control sub-circuit 30, and a second pull-down control.
  • the circuit 40, the pull-down sub-circuit 50, and the n output sub-circuits 20 eg, the first output sub-circuit, the second output sub-circuit, the n-th output sub-circuit, where n ⁇ 2, n is a positive integer.
  • the first input sub-circuit 10 is connected to the first signal input terminal INPUT1 (hereinafter referred to as INPUT is simply referred to as INP), the first control voltage terminal CN, and the pull-up node PU, and the first input sub-circuit 10 is configured to be input at the first signal. Under the control of the terminal INP1, the voltage supplied from the first control voltage terminal CN is output to the pull-up node PU.
  • Each output sub-circuit 20 is connected to a pull-up node PU, a signal output end, and an output clock signal end.
  • the output sub-circuit 20 is configured to output a signal of the output clock signal terminal CLK to the signal output terminal under the control of the pull-up node PU. .
  • the output clock signal terminals and signal output terminals to which any two output sub-circuits 20 are connected may be different.
  • the first output sub-circuit is connected to the output clock signal terminal CLK1, the signal output terminal OUTPUT1 (hereinafter referred to as OUTPUT is simply referred to as OTP);
  • the second output sub-circuit is connected to the output clock signal terminal CLK2, and the signal output terminal OTP2;
  • the nth output sub-circuit is connected to the output clock signal terminal CLKn, and the signal output terminal OTPn.
  • first pull-down control sub-circuit 30 is connected to the first control voltage terminal CN, the first clock signal terminal CK1, and the pull-down node PD, and the first pull-down control sub-circuit 30 is configured to be under the control of the first clock signal terminal CK1. And outputting the voltage provided by the first control voltage terminal CN to the pull-down node PD.
  • the second pull-down control sub-circuit 40 is connected to the pull-up node PU, the pull-down node PD, the first voltage terminal VGL, and the second pull-down control sub-circuit 40 is configured to pull down the voltage of the pull-down node PD under the control of the pull-up node PU to The first voltage.
  • the pull-down sub-circuit 50 is connected to the pull-up node PU, the pull-down node PD, the first voltage terminal VGL, and the pull-down sub-circuit 50 is configured to pull down the voltage of the pull-up node PU to the first voltage under the control of the pull-down node PD.
  • some embodiments of the present disclosure provide a shift register including a first input sub-circuit 10, a first pull-down control sub-circuit 30, a second pull-down control sub-circuit 40, a pull-down sub-circuit 30, and n output sub- Circuit 20.
  • the first input sub-circuit 10 is connected to the first signal input terminal INP1, the first control voltage terminal CN, and the pull-up node PU.
  • the first input sub-circuit 10 is configured to be under the control of the first signal input terminal INP1.
  • the voltage of the first control voltage terminal CN is output to the pull-up node PU.
  • Each output sub-circuit 20 is connected to the pull-up node PU, the signal output end, and the output clock signal end, and the output sub-circuit 20 is configured to output the signal of the output clock signal terminal CLK to the signal output under the control of the pull-up node PU. end.
  • the first pull-down control sub-circuit 30 is connected to the first control voltage terminal CN, the first clock signal terminal CK1, and the pull-down node PD, and the first pull-down control sub-circuit 30 is configured to be under the control of the first clock signal terminal CK1.
  • the voltage of the first control voltage terminal CN is output to the pull-down node PD.
  • the second pull-down control sub-circuit 40 is connected to the pull-up node PU, the pull-down node PD, the first voltage terminal VGL, and the second pull-down control sub-circuit 40 is configured to pull down the voltage of the pull-down node PD under the control of the pull-up node PU to The first voltage terminal VGL.
  • the pull-down sub-circuit 50 is connected to the pull-up node PU, the pull-down node PD, and the first voltage terminal VGL.
  • the pull-down sub-circuit 50 is configured to pull down the voltage of the pull-up node PU to the first voltage terminal VGL under the control of the pull-down node PD.
  • the potential the first voltage.
  • the potential of the pull-up node PU can be controlled by the first input sub-circuit 10 in an image frame, and the pull-up node PU can control the output clocks of the respective output sub-circuits 20 to which they are connected.
  • the signal terminals for example, the clock signals of CLK1, CLK2, ... CLKn are sequentially output to the signal output terminals to which the respective output sub-circuits 20 are connected, such as OTP1, OTP2, ... OTPn, so that the respective signal output terminals, such as OTP1, OTP2, ... OTPn, are
  • the gate scan signals can be sequentially output to the gate lines connected to the respective signal output terminals, for example, OTP1, OTP2, ... OTPn.
  • first pull-down control sub-circuit 30 and the second pull-down control sub-circuit 40 can control the potential of the pull-down node PD to pull down the potential of the pull-down node PD to the potential of the first voltage terminal VGL; or pull down the potential of the node PD Pulled high so that the pull-down node PD can control the pull-down sub-circuit 50 to pull down the potential of the pull-up node PU to the potential of the first voltage terminal VGL.
  • each stage shift register has a plurality of signal output terminals, such as OTP1, OTP2, ... OTPn, so that the first stage shift register can be respectively connected to the plurality of gate lines through different signal output ends, thereby making one
  • the stage shift register allows progressive scanning of multiple gate lines.
  • an output clock signal end of the shift register for example, the clock signal of CLK1 is at a high level
  • the first output of the output signal of the output clock signal terminal CLK1 is received.
  • the signal output terminal OTP1 connected to the circuit outputs a gate scan signal.
  • the clock signals output from the other output clock signal terminals for example, CLK2 ...
  • CLKn are at a low level, so that the signal output terminals OTP2 ... connected to the second output sub-circuit are connected to the signal output of the n-th output sub-circuit.
  • the terminal OTPn or the like does not output the gate scan signal so that the plurality of gate lines connected to the first stage shift register can not simultaneously receive the gate scan signal to realize progressive scanning of the plurality of gate lines.
  • the first stage shift register does not need to output the gate scan signal only to one row of gate lines, and the layout area of the shift register occupying the peripheral area in the GOA circuit on the display panel can be reduced, thereby realizing a narrower border effect.
  • the first shift sub-register has two output sub-circuits, for example, the first output sub-circuit 21 and the second output sub-circuit 22 as shown in FIG. 2, and the above-mentioned sub-circuits in the shift register shown in FIG.
  • the circuit structure is described in detail.
  • the first input sub-circuit 10 may include a first transistor T1.
  • the gate of the first transistor T1 is connected to the first signal input terminal INP1, the first pole is connected to the first control voltage terminal CN, and the second pole is connected to the pull-up node PU.
  • Each output sub-circuit 20 includes an output transistor M and a voltage stabilizing capacitor CC.
  • the gate of the output transistor M is connected to the pull-up node PU, the first pole is connected to the output clock signal terminal, and the second pole is connected to the signal output terminal.
  • One end of the voltage stabilizing capacitor CC is connected to the pull-up node PU, and the other end is connected to the output signal output end.
  • the first output sub-circuit 21 includes the first output transistor M1 and the first voltage stabilizing capacitor CC1.
  • the gate of the first output transistor M1 is connected to the pull-up node PU, the first pole is connected to the output first output clock signal terminal CLK1, and the second pole is connected to the first signal output terminal OTP1.
  • One end of the first voltage stabilizing capacitor CC1 is connected to the pull-up node PU, and the other end is connected to the output first signal output terminal OTP1.
  • the second output sub-circuit 22 includes a second output transistor M2 and a second voltage stabilizing capacitor CC2.
  • the gate of the second output transistor M2 is connected to the pull-up node PU, the first pole is connected to the second output clock signal terminal CLK2, and the second pole is connected to the second signal output terminal OTP2.
  • One end of the second voltage stabilizing capacitor CC2 is connected to the pull-up node PU, and the other end is connected to the output second signal output terminal OTP2.
  • the first pull-down control sub-circuit 30 includes a second transistor T2.
  • the gate of the second transistor T2 is connected to the first clock signal terminal CK1, the first electrode is connected to the first control voltage terminal CN, and the second electrode is connected to the pull-down node PD.
  • the second pull-down control sub-circuit 40 includes a third transistor T3.
  • the gate of the third transistor T3 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the first voltage terminal VGL.
  • the pull-down sub-circuit 50 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the first voltage terminal VGL.
  • the transistor may be an N-type transistor or a P-type transistor; it may be an enhancement transistor or a depletion transistor.
  • the first pole of the transistor may be a source, the second pole may be a drain, or the first pole of the transistor may be a drain, and the second pole is a source, which is not limited in the disclosure.
  • the respective transistors in the shift register shown in FIG. 2 are turned on and off in different stages (P1 to P4) in an image frame.
  • the first voltage terminal VGL is constantly outputting a DC low level
  • the first control voltage terminal CN outputs a DC high level in the image frame as an example.
  • the signal output terminals for example, OTP1, OTP2, ... OTPn respectively output a high level
  • the signal output terminal outputs a gate scan signal
  • the signal output terminal when the signal output terminal output terminal outputs a low level, the signal is indicated.
  • the output terminal does not output a gate scan signal as an example for description.
  • the first transistor T1 since the first signal input terminal INP1 outputs a high level, the first transistor T1 is turned on, thereby transmitting the high level of the output of the first control voltage terminal CN to the pull-up node PU, and passing the first voltage regulator.
  • the capacitor CC1 and the second regulator capacitor CC2 store the high level of the pull-up node PU.
  • the first output transistor M1 and the second output transistor M2 are turned on, and the low level outputted by the first output clock signal terminal CLK1 is transmitted to the first signal output terminal OTP1 through the first output transistor M1. . Further, the low level outputted by the second output clock signal terminal CLK2 is transmitted to the second signal output terminal OTP2 through the second output transistor M2. Further, under the control of the pull-up node PU, the third transistor T3 is turned on, thereby pulling down the potential of the pull-down node PD to the first voltage terminal VGL through the third transistor T3, and thus the fourth transistor T4 is in an off state.
  • the second transistor T2 is in an off state.
  • the first signal output terminal OTP1 and the second signal output terminal OTP2 in the stage shift register output a low level in the first phase P1.
  • the first transistor T1 since the first signal input terminal INP1 outputs a low level, the first transistor T1 is in an off state.
  • the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 charge the high level of the first stage P1 to the pull-up node PU, so that the first output transistor M1 and the second output transistor M2 are in the second stage P2. Keep on.
  • the high level outputted by the first output clock signal terminal CLK1 can still be transmitted to the first signal output terminal OTP1 through the first output transistor M1, and the low level outputted by the second output clock signal terminal CLK2 can still pass the first
  • the two output transistors M2 are transmitted to the second signal output terminal OTP2.
  • the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 are respectively coupled to the first signal output terminal OTP1 and the second signal output terminal.
  • the potential of one end of the OTP2 phase connection is increased, so under the bootstrap action of the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2, the first stabilizing capacitor CC1 and the second stabilizing capacitor CC2 and the pull-up node PU
  • the potential of the connected one end is also correspondingly increased, so that the potential of the pull-up node PU is further increased to effectively maintain the first output transistor M1 and the second output transistor M2 in a conducting state in the second phase P2, thereby
  • the high level of the first output clock signal terminal CLK1 can be continuously and stably output as a gate scan signal to the gate line connected to the first signal output terminal OTP1.
  • the third transistor T3 is in an on state
  • the second transistor T2 and the fourth transistor T4 are in an off state.
  • the first signal output terminal OTP1 outputs a high level in the second phase P2 to output a gate scan signal to the gate line connected to the first signal output terminal OTP1.
  • other signal output terminals for example, the second signal output terminal OTP2, output a low level, that is, no gate scan signal is output.
  • the first transistor T1 since the first signal input terminal INP1 outputs a low level, the first transistor T1 is turned off.
  • the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 charge the high level of the first stage P1 to the pull-up node PU, so that the first output transistor M1 and the second output transistor M2 remain in the third stage P3. Keep on.
  • the low level of the first output clock signal terminal CLK1 is output to the first signal output terminal OTP1 through the first output transistor M1 to reset the first signal output terminal OTP1 such that the first signal output terminal
  • the gate line connected to the OTP1 is no longer receiving the above-mentioned gate scan signal; the high level output of the second output clock signal terminal CLK2 is outputted to the second signal output terminal OTP2.
  • the potential of the pull-up node PU is maintained at a high level to maintain the first output transistor M1 and the second output transistor M2 in conduction.
  • the state is such that a high level output from the second output clock signal terminal CLK2 can be output as a gate scan signal to a gate line connected to the second signal output terminal OTP2.
  • the third transistor T3 is in an on state, and the second transistor T2 and the fourth transistor T4 are in an off state.
  • the second signal output terminal OTP2 outputs a high level in the third phase P3 to output a gate scan signal to the gate line connected to the second signal output terminal OTP2.
  • other signal output terminals for example, the first signal output terminal OTP1, output a low level, that is, no gate scan signal is output.
  • the second transistor T2 since the first clock signal terminal CK1 outputs a high level, the second transistor T2 is turned on, and the high level output from the first clock signal terminal CK1 is transmitted to the pull-down node PD through the second transistor T2.
  • the fourth transistor T4 Under the control of the pull-down node PD, the fourth transistor T4 is turned on, and the potential of the pull-up node PU is pulled down to the first voltage terminal VGL through the fourth transistor T4 to reset the pull-up node PU. Under the control of the pull-up node PU, the third transistor T3, the first output transistor M1, and the second output transistor M2 are turned off, so that the first signal output terminal OTP1 and the second signal output terminal OTP2 do not output a gate scan signal.
  • the fourth phase P4 may be repeated before the start of the next image frame (ie, the first signal input terminal INP1 is again input with a high level), so that the potential of the pull-down node PD remains high, and the control of the pull-down node PD
  • the potential of the pull-up node PU is pulled low so that the first output transistor M1 and the second output transistor M2 are in an off state.
  • first-stage shift register including two output sub-circuits
  • the first-stage shift register includes more output sub-circuits
  • the working processes of the first phase P1 and the fourth phase P4 are unchanged, except that it is necessary to increase the number of output sub-circuits between the first phase P1 and the fourth phase P4 so that the output sub-circuits are outputted one by one.
  • the specific working principle of the phase of the polar scan signal is the same as that of the second phase P2 and the third phase P3, and will not be repeated here.
  • the on and off processes of the transistors in the above embodiments are described by taking all transistors as N-type transistors as an example. When all transistors are P-type, some control signals in FIG. 3 need to be flipped and shifted. The on and off processes of the transistors of the respective sub-circuits in the register are the same as those described above, and are not described herein again.
  • the pull-down sub-circuit 50 is also connected to respective signal outputs, such as OTP1, OTP2, ... OTPn, and the pull-down sub-circuit 50 is also configured to be in the pull-down node.
  • the potentials of the respective signal outputs such as OTP1, OTP2, ... OTPn, are pulled down to the first voltage terminal VGL to further reset the respective signal outputs, for example, OTP1, OTP2, ... OTPn.
  • the pull-down sub-circuit 50 may also include an output pull-down transistor.
  • the gate of the output pull-down transistor is connected to the pull-down node PD, the first pole is connected to the signal output terminal, and the second pole is connected to the first voltage terminal VGL.
  • the pull-down sub-circuit 50 may further include a first output pull-down transistor Q1 and a second The output pull-down transistor Q2.
  • the gate of the first output pull-down transistor Q1 is connected to the pull-down node PD, the first pole is connected to the first signal output terminal OTP1, and the second pole is connected to the first voltage terminal VGL.
  • the gate of the second output pull-down transistor Q2 is connected to the pull-down node PD, the first pole is connected to the second signal output terminal OTP2, and the second pole is connected to the first voltage terminal VGL.
  • the first output pull-down transistor Q1 and the second output pull-down transistor Q2 are turned on, and the first signal output terminal is passed through the first output pull-down transistor Q1.
  • the potential of the OTP1 is pulled down to the first voltage terminal VGL; the potential of the second signal output terminal OTP2 is pulled down to the first voltage terminal VGL through the second output pull-down transistor Q2 to respectively correspond to the first signal output terminal OTP1 and the second signal output terminal OTP2 resets, and prevents abnormal output of the first signal output terminal OTP1 and the second signal output terminal OTP2, thereby improving the stability of the shift register operation.
  • the shift register shown in FIG. 13 further includes a tenth transistor T10 and an eleventh transistor T11.
  • the gate of the eleventh transistor T11 is connected to the second voltage terminal VGH, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the gates of the tenth transistor T10 and the second output transistor M2.
  • the first pole of the tenth transistor T10 is connected to the last signal output terminal of the shift register, for example, the output pull-down transistor connected to the second signal output terminal OTP2 in FIG. 13, for example, the gate of the second output pull-down transistor Q2,
  • the two poles are connected to the first voltage terminal VGL.
  • the eleventh transistor T10 and the eleventh transistor T11 are both N-type transistors as an example.
  • the eleventh transistor T11 is used as a single-tube transmission gate. The operation is always in an on state, so that the noise clutter of the gates of the tenth transistor T10 and the second output transistor M2 can be further reduced by the eleventh transistor T11, and the gates of the tenth transistor T10 and the second output transistor M2 are stabilized. Extreme signal.
  • the tenth transistor T10 is in an on state, so that the gate potential of the second output pull-down transistor Q2 can be pulled down to the first voltage terminal VGL, and the second output pull-down The transistor Q2 is turned off, so as to prevent the signal output from the second signal output terminal OTP2 from being pulled down to the first voltage terminal VGL when the second signal output terminal OTP2 outputs the gate scan signal.
  • the shift register further includes a first voltage stabilizing noise reduction sub-circuit 60 connected between the first input sub-circuit 10 and the pull-up node PU, the first stable
  • the voltage noise reduction sub-circuit 60 can also be connected to the first voltage terminal VGL and/or the second voltage terminal VGH.
  • the first voltage stabilizing noise reduction sub-circuit 60 is configured to stabilize the voltage of the pull-up node PU and reduce the noise clutter of the pull-up node PU under the control of the first voltage terminal VGL and/or the second voltage terminal VGH.
  • the specific circuit structure of the first voltage stabilizing noise reduction sub-circuit 60 will be exemplified below.
  • the first regulated noise reduction sub-circuit 60 may include a first capacitor C1 and a fifth transistor T5.
  • the first regulated noise reduction sub-circuit 60 may include only the first capacitor C1 described above.
  • the first regulated noise reduction sub-circuit 62 may include only the fifth transistor T5 described above.
  • One end of the first capacitor C1 is connected to the output terminal of the first input sub-circuit 10, and the other end is connected to the first voltage terminal VGL.
  • the gate of the fifth transistor T5 is connected to the second voltage terminal VGH, the first pole is connected to the output of the first input sub-circuit 10, and the second pole is connected to the pull-up node PU.
  • the output end of the first input sub-circuit 10 means that, in the first input sub-circuit 10, the voltage of the first control voltage terminal CN is output to the pull-up node PU under the control of the first signal input terminal INP1.
  • the output of the first input sub-circuit 10 in FIG. 7 is the second pole of the first transistor T1.
  • the first capacitor C1 can filter the noise clutter of the pull-up node PU under the filtering effect of the first capacitor C1.
  • the bootstrap function of the first capacitor C1 can be used to keep the pull-up node PU stable.
  • the first regulated noise reduction sub-circuit 60 includes the fifth transistor T5
  • the second voltage terminal VGH connected to the gate of the fifth transistor T5 can output a constant DC high level, and thus at the second voltage terminal VGH
  • the fifth transistor T5 operates as a single-tube transmission gate and can be always in an on state.
  • the signal outputted by the first input sub-circuit 10 is transmitted to the pull-up node PU via the fifth transistor T5, thereby stabilizing the voltage of the pull-up node PU, while the fifth transistor T5 can reduce the clutter transmission of the output signal of the first input sub-circuit 10 to The probability of pulling the node PU, thereby reducing the noise clutter of the pull-up node PU.
  • the shift register further includes a second regulated noise reduction sub-circuit 70 coupled between the first pull-down control sub-circuit 30 and the pull-down node PD,
  • the second regulated noise reduction sub-circuit 70 can also be coupled to the first voltage terminal VGL and/or the second voltage terminal VGH.
  • the second regulated noise reduction sub-circuit 70 is configured to stabilize the voltage of the pull-down node PD and reduce the noise clutter of the pull-down node PD under the control of the first voltage terminal VGL and/or the second voltage terminal VGH.
  • the specific circuit structure of the second regulated noise reduction sub-circuit 70 will be exemplified below.
  • the second regulated noise reduction sub-circuit 70 may include a second capacitor C2 and a sixth transistor T6 as shown in FIG.
  • the second voltage stabilizing noise reduction sub-circuit 70 may include only the second capacitor C2 described above.
  • the second regulated noise reduction sub-circuit 70 may include only the sixth transistor T6 described above.
  • the second voltage-stabilizing noise reduction sub-circuit 70 can include only the second capacitor C2, one end of the second capacitor C2 is directly connected to the output end of the first pull-down control sub-circuit 30, and the other end is connected to the first end. Voltage terminal VGL.
  • the output end of the first pull-down control sub-circuit 30 means that the voltage of the first control voltage terminal CN is output under the control of the first clock signal terminal CK1 in the first pull-down control sub-circuit 30.
  • the output of the first pull-down control sub-circuit 30 is the second pole of the second transistor T2.
  • the second capacitor C2 can filter the noise clutter of the pull-down node PD under the filtering effect of the second capacitor C2.
  • the pull-down node PD can be kept stable by the bootstrap action of the second capacitor C2.
  • the second regulated noise reduction sub-circuit 70 includes only the sixth transistor T6, the gate of the sixth transistor T6 is connected to the second voltage terminal VGH, the first pole is connected to the output terminal of the pull-down control sub-circuit 30, and the second The pole is connected to the pulldown node PD.
  • the second regulated noise reduction sub-circuit 70 includes the second capacitor C2 and the sixth transistor T6, one end of the second capacitor C2 is connected to the second pole of the sixth transistor T6, so that the sixth transistor T6 can be passed.
  • One end of the second capacitor C2 is electrically connected to the output of the first pull-down control sub-circuit 30.
  • the sixth transistor T6 Under the control that the second voltage terminal VGH constantly outputs a high level, the sixth transistor T6 operates as a single-tube transmission gate and is always in an on state.
  • the signal output by the first pull-down control sub-circuit 30 is transmitted to the pull-down node PD via the sixth transistor T6, thereby stabilizing the voltage of the pull-down node PD, while the sixth transistor T6 can reduce the output signal of the first pull-down control sub-circuit 30.
  • the probability that the wave is transmitted to the pull-down node PD, thereby reducing the noise clutter of the pull-down node PD.
  • the shift register may further include a discharge electronic circuit 80 connected to the pull-down node PD and a reset signal terminal RESET (RST for short).
  • the discharge electronic circuit 80 is configured to output the voltage of the reset signal terminal RST to the pull-down node PD under the control of the reset signal terminal RST.
  • the electronic discharge circuit 80 includes a seventh transistor T7, the gate and the first pole of the seventh transistor T7 are connected to the reset signal terminal RST, and the second pole is connected to the pull-down node. PD.
  • a high level is input to the reset signal terminal RST, and under the control of the reset signal terminal RST, the seventh transistor T7 is turned on, and the reset signal terminal RST is output through the seventh transistor T7.
  • the high level is transferred to the pull-down node PD, thereby pulling the potential of the pull-down node PD high.
  • the first output pull-down transistor Q1 and the second output pull-down transistor Q2 are turned on, so that the first signal output terminal OTP1 and the second are respectively passed through the first output pull-down transistor Q1 and the second output pull-down transistor Q2.
  • the potential of the signal output terminal OTP2 is pulled down to the first voltage terminal VGL.
  • the shift register may further include a second input sub-circuit 11 and a third pull-down control sub-circuit 31.
  • the second input sub-circuit 11 is connected to the second signal input terminal INP2, the second control voltage terminal CNB, and the pull-up node PU.
  • the first input sub-circuit 10 is configured to output the voltage of the second control voltage terminal CNB to the pull-up node PU under the control of the second signal input terminal INP2.
  • the third pull-down control sub-circuit 31 is connected to the second control voltage terminal CNB, the second clock signal terminal CK2, and the pull-down node PD.
  • the third pull-down control sub-circuit 31 is configured to output the voltage of the second control voltage terminal CNB to the pull-down node PD under the control of the second clock signal terminal CK2.
  • the second input sub-circuit 11 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the second signal input terminal INP2, and the first electrode is connected to the second control voltage terminal CNB, The two poles are connected to the pull-up node PU.
  • the third pull-down control sub-circuit 31 includes a ninth transistor T9 whose gate is connected to the second clock signal terminal CK2, the first electrode is connected to the second control voltage terminal CNB, and the second electrode is connected to the pull-down node PD.
  • first control voltage terminal CN and the second control voltage terminal CNB in FIG. 11 can be used as the control signal terminal of the positive anti-sweep.
  • the GOA circuit having the plurality of stages of the above shift register can scan the plurality of gate lines connected to the GOA circuit in a reverse direction (from bottom to top).
  • the first signal input terminal INP1 of the first stage shift register is connected to the last stage signal output end OTP of the upper stage shift register, and the second signal input end INP2 is connected to the first signal output end OTP1 of the next stage shift register.
  • CN is high and CNB is low.
  • a high level is input to the first signal input terminal INP1, and a low level is input to the second signal input terminal INP2.
  • the fifth transistor T5 and the sixth transistor T6 are always in an on state.
  • the first transistor T1 since the first signal input terminal INP1 outputs a high level, the first transistor T1 is turned on, thereby outputting the high level of the first signal input terminal INP1 to the pull-up node PU through the fifth transistor T5, and passing The first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 store the high level.
  • the fifth transistor T5 can reduce the probability that the clutter of the output signal of the first transistor T1 is transmitted to the pull-up node PU, thereby reducing noise clutter of the pull-up node PU.
  • the first capacitor C1 Under the filtering action of the first capacitor C1, the first capacitor C1 can filter the noise clutter of the pull-up node PU, and at the same time, the bootstrap node PU can be kept stable by the bootstrap action of the first capacitor C1.
  • the first output transistor M1 and the second output transistor M2 are turned on, and the low level outputted by the first output clock signal terminal CLK1 is transmitted to the first signal output terminal OTP1 through the first output transistor M1.
  • the low level outputted by the second output clock signal terminal CLK2 is transmitted to the second signal output terminal OTP2 through the second output transistor M2.
  • the third transistor T3 and the tenth transistor T10 are turned on, and the potential of the pull-down node PD is pulled down to the first voltage terminal VGL through the third transistor T3 and the tenth transistor T10.
  • the eighth transistor T8 is in an off state. Since the first clock signal terminal CK1 outputs a low level, the second transistor T2 is in an off state. Since the second clock signal terminal CK2 outputs a low level, the ninth transistor T9 is in an off state. Since the potential of the pull-down node PD is at a low level, the fourth transistor T4, the first output pull-down transistor Q1, and the second output pull-down transistor Q2 are in an off state. Since the reset signal terminal RST outputs a low level, the seventh transistor T7 is in an off state.
  • each of the signal output terminals for example, the first signal output terminal OTP1 and the second signal output terminal OTP2, outputs a low level in the first phase P1.
  • the first transistor T1 since the first signal input terminal INP1 outputs a low level, the first transistor T1 is in an off state.
  • the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 charge the high level pull-up node PU of the first stage P1, so that the first output transistor M1 and the second output transistor M2 remain in an on state.
  • the high level outputted by the first output clock signal terminal CLK1 is transmitted to the first signal output terminal OTP1 through the first output transistor M1, and the low level outputted from the second output clock signal terminal CLK2 is passed through the second output transistor M2. Transfer to the second signal output OTP2.
  • the potential of the pull-up node PU is further increased to maintain the first output transistor M1 and the second output transistor M2 in an on state. Therefore, the high level of the first output clock signal terminal CLK1 can be continuously outputted as a gate scan signal to the gate line connected to the first signal output terminal OTP1.
  • the third transistor T3 is in an on state
  • the second transistor T2 the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, the first output pull-down transistor Q1, and the second output pull-down transistor Q2
  • the seventh transistor T7 is in an off state.
  • the first signal output terminal OTP1 outputs a high level in the second phase P2 to output a gate scan signal to the gate line connected to the first signal output terminal OTP1.
  • other signal output terminals for example, the second signal output terminal OTP2, output a low level, that is, no gate scan signal is output.
  • the first transistor T1 since the first signal input terminal INP1 outputs a low level, the first transistor T1 is turned off.
  • the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 charge the high level of the first stage P1 to the pull-up node PU, thereby keeping the first output transistor M1 and the second output transistor M2 in an on state.
  • the low level outputted by the first output clock signal terminal CLK1 is transmitted to the first signal output terminal OTP1 through the first output transistor M1, and the high level outputted from the second output clock signal terminal CLK2 is passed through the second output transistor M2. Transfer to the second signal output OTP2.
  • the potential of the pull-up node PU is maintained at a high level to maintain the first output transistor M1 and the second output transistor M2 in conduction.
  • the state is such that a high level of the second output clock signal terminal CLK2 can be output as a gate scan signal to a gate line connected to the second signal output terminal OTP2.
  • the third transistor T3 is in an on state
  • the second transistor T2 the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the first output pull-down transistor Q1
  • the two output pull-down transistors Q2 are in an off state.
  • the second signal output terminal OTP2 outputs a high level in the third phase P3 to output a gate scan signal to the gate line connected to the second signal output terminal OTP2.
  • other signal output terminals for example, the first signal output terminal OTP1, output a low level.
  • the second transistor T2 since the first clock signal terminal CK1 outputs a high level, the second transistor T2 is turned on, outputs a high level of the first clock signal terminal CK1 to the sixth transistor T6, and is output to the sixth transistor T6 through the sixth transistor T6. Pull down the node PD.
  • the sixth transistor T6 can stabilize the voltage of the pull-down node PD, and the sixth transistor T6 can also reduce the probability that the output signal of the second transistor T2 is transmitted to the pull-down node PD, thereby reducing noise clutter of the pull-down node PD.
  • the second capacitor C2 under the filtering action of the second capacitor C2, the second capacitor C2 can filter the noise clutter of the pull-down node PD, and the bootstrap action of the second capacitor C1 can keep the pull-down node PD stable.
  • the fourth transistor T4 Under the control of the pull-down node PD, the fourth transistor T4 is turned on, and the potential of the pull-up node PU is pulled down to the first voltage terminal VGL through the fourth transistor T4 to reset the pull-up node PU.
  • the first output pull-down transistor Q1 and the second output pull-down transistor Q2 are turned on, and the potential of the first signal output terminal OTP1 is pulled down to the first voltage terminal VGL through the first output pull-down transistor Q1.
  • the potential of the second signal output terminal OTP2 is pulled down to the first voltage terminal VGL through the second output pull-down transistor Q2 to reset the first signal output terminal OTP1 and the second signal output terminal OTP2, respectively.
  • the third transistor T3, the first output transistor M1, and the second output transistor M2 are turned off.
  • the fourth phase P4 may be repeated before the next image frame to keep the potential of the pull-down node PD high, and under the control of the pull-down node PD, pull down the potential of the pull-up node PU to make the first output transistor M1 and the second output transistor M2 are in an off state.
  • the shift register when the shift register is reversely scanned, a low level is input to the first control voltage terminal CN, and a high level is input to the second control voltage terminal CNB.
  • the first phase P1 at the second signal input end. Under the control of INP2, the voltage of the second control voltage terminal CNB is output to the pull-up node PU; in the fourth phase P4, the high level is input to the second clock signal terminal CK2, and under the control of the second clock signal terminal CK2, The voltage of the second control voltage terminal CNB is output to the pull-down node PD.
  • the working principle of the second stage P2 and the third stage P3 is the same as that of the forward output, and will not be described here.
  • the shift register is exemplified by including 10 transistors and 2 capacitors as shown in FIG. 15 to sequentially output gate scan signals to two rows of gate lines, and it is necessary to include two cascade shifts at this time.
  • Register ie 20 transistors and 2 capacitors.
  • the first stage shift register provided by some embodiments of the present disclosure can sequentially output gate scan signals to at least two rows of gate lines, and can use fewer transistors than existing shift registers, thereby Reduce the power consumption of the shift register.
  • Some embodiments of the present disclosure provide a gate driving circuit as shown in FIG. 14a, including a plurality of cascaded shift registers as provided in FIGS. 1-9, wherein the first stage shift register The first signal input terminal INP1 of RS1 is connected to the start signal terminal STV.
  • the first signal input terminal INP1 of each stage shift register is connected to the last signal output terminal of the shift register of the stage shift register.
  • the start signal terminal STV is configured to output a start signal, and the first stage shift register RS1 of the gate drive circuit starts to scan the gate lines (G1, G2, ..., Gn) line by line after receiving the start signal.
  • FIG. 14a is an illustration of an example in which each stage shift register includes a two-stage signal output terminal OTP. Specifically, the first signal input terminal INP1 of the first stage shift register RS1 is connected to the start signal terminal STV.
  • the first signal input terminal INP1 of each stage shift register is connected to the second signal output terminal OTP2 of the shift register of the upper stage of the stage shift register.
  • some embodiments of the present disclosure provide a gate driving circuit including a plurality of cascaded shift registers as shown in FIGS. 1-9, having the same as shown in FIGS.
  • the same structure and advantageous effects of any one of the shift registers have been described in the foregoing embodiments because the foregoing embodiment has already explained the specific structure and advantageous effects of the above shift register.
  • Some embodiments of the present disclosure also provide a gate driving circuit, as shown in FIG. 14b, including a plurality of cascaded shift registers as shown in FIG. 10 or FIG.
  • the first signal input terminal INP1 of the first stage shift register RS1 is connected to the start signal terminal STV.
  • the first signal input terminal INP1 of each stage shift register is connected to the last signal output terminal of the shift register of the stage shift register.
  • the second signal input terminal INP2 of each stage shift register is connected to the first signal output terminal OTP1 of the shift register of the next stage of the stage shift register.
  • the second signal input terminal INP2 of the last stage shift register RSn is connected to the start signal terminal STV.
  • the start signal terminal STV is configured to output a start signal
  • the first stage shift register RS1 of the gate drive circuit starts to positively control the gate lines (G1, G2, ..., Gn) after receiving the start signal. line-by-line scan.
  • the last stage shift register RSn of the gate drive circuit starts reverse row-by-row scanning of the gate lines (G1, G2, ..., Gn) after receiving the start signal.
  • FIG. 14b is an illustration of an example in which each stage shift register includes a two-stage signal output terminal OTP. Specifically, the first signal input terminal INP1 of the first stage shift register RS1 is connected to the start signal terminal STV.
  • the first signal input terminal INP1 of each stage shift register is connected to the second signal output terminal OTP2 of the shift register of the upper stage of the stage shift register.
  • the second signal input terminal INP2 of each stage shift register is connected to the first signal output terminal OTP1 of the shift register of the next stage of the stage shift register.
  • the second signal input terminal INP2 of the last stage shift register RSn is connected to the start signal terminal STV.
  • some embodiments of the present disclosure provide a gate driving circuit including any one of the shift registers as shown in FIG. 10 or FIG. 11 having the shift shown in FIG. 10 or FIG.
  • the same structure and advantageous effects of the bit register since the foregoing embodiment has explained the specific structure and advantageous effects of the above shift register, the present disclosure will not be described again.
  • Some embodiments of the present disclosure provide a display device including any of the gate driving circuits as described above, having the same structure and advantageous effects as the gate driving circuit provided by the foregoing embodiments, since the foregoing embodiments have been The structure and beneficial effects of the gate driving circuit are described in detail, and are not described herein again.
  • Some embodiments of the present disclosure also provide a method for driving any one of the above shift registers.
  • the driving method includes:
  • the first input sub-circuit 10 outputs the voltage of the first control voltage terminal CN to the pull-up node PU under the control of the first signal input terminal INP1.
  • the second pull-down control sub-circuit 40 pulls down the voltage of the pull-down node PD to the first voltage terminal VGL under the control of the pull-up node PU.
  • Each of the output sub-circuits 20 stores a signal of the pull-up node PU, and outputs a clock signal outputted from each of the output clock signal terminals CLK to a signal output terminal to which each of the output sub-circuits 20 is connected under the control of the pull-up node PU. Further, neither the first pull-down control sub-circuit 30 nor the pull-down sub-circuit 50 is turned on.
  • each sub-circuit in the above shift register is as shown in FIG. 2, and the transistors in each sub-circuit are N-type transistors, wherein the shift register of FIG. 2 includes a two-stage output sub-circuit, that is, the first output.
  • the sub-circuit 21 and the second output sub-circuit 22 are illustrated as an example.
  • the first output clock signal terminal CLK1 and the second output clock signal terminal CLK2 are input with a low level
  • the first input signal terminal INP1 is input with a high level
  • the pull-up node PU is at a high level
  • the pull-down node PD is at a low level
  • each signal output terminal outputs a low level.
  • the on and off states of the transistors in the respective sub-circuits are: since the first signal input terminal INP1 outputs a high level, the first transistor T1 is turned on, thereby turning the first signal input terminal INP1 The high level of the output is transmitted to the pull-up node PU, and the high level is stored by the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2. Under the control of the pull-up node PU, the first output transistor M1 and the second output transistor M2 are turned on, and the low level outputted by the first output clock signal terminal CLK1 is transmitted to the first signal output terminal OTP1 through the first output transistor M1.
  • the low level outputted by the second output clock signal terminal CLK2 is transmitted to the second signal output terminal OTP2 through the second output transistor M2.
  • the third transistor T3 is turned on, and the potential of the pull-down node PD is pulled down to the first voltage terminal VGL. Since the potential of the pull-down node PD is low, the fourth transistor T4 It is in the cutoff state.
  • the second transistor T2 is in an off state.
  • Each of the output sub-circuits 20 outputs the signal stored in the previous stage to the pull-up node PU, and sequentially outputs the signals of the respective output clock signal terminals CLK to the signal output terminals connected to the respective output sub-circuits 20 under the control of the pull-up node PU.
  • Each signal output terminal sequentially outputs a gate scan signal.
  • the first pull-down control sub-circuit 40 and the pull-down sub-circuit 50 are not turned on, and the first input sub-circuit 10 has no signal output.
  • each sub-circuit in the above shift register is as shown in FIG. 2, and the transistors in each sub-circuit are N-type transistors, wherein the shift register of FIG. 2 includes a two-stage output sub-circuit, that is, the first output sub- The circuit 21 and the second output sub-circuit 22 are illustrated as an example.
  • the above output stage includes a second stage P2 and a third stage P3.
  • the first output clock signal terminal CLK1 is input to the high level
  • the second output clock signal terminal CLK2 is input to the low level
  • the first signal input terminal INP1 is input low.
  • Level the first clock signal terminal CK1 inputs a low level.
  • the pull-up node PU is at a high level
  • the pull-down node PD is at a low level
  • the first signal output terminal OTP1 outputs a high level
  • the second signal output terminal OTP2 outputs a low level.
  • the first output clock signal terminal CLK1 inputs a low level
  • the second output clock signal terminal CLK2 inputs a high level
  • the first signal input terminal INP1 inputs a low level
  • first The clock signal terminal CK1 inputs a low level
  • the pull-up node PU is at a high level
  • the pull-down node PD is at a low level
  • the first signal output terminal OTP1 outputs a low level to reset the first signal output terminal OTP1
  • the second signal output terminal OTP2 outputs a high level.
  • the on and off states of the transistors in the respective sub-circuits are: since the first signal input terminal INP1 outputs a low level, the first transistor T1 is in an off state.
  • the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 charge the high level pull-up node PU of the first stage P1, so that the first output transistor M1 and the second output transistor M2 remain in an on state.
  • the high level outputted by the first output clock signal terminal CLK1 is transmitted to the first signal output terminal OTP1 through the first output transistor M1, and the low level outputted from the second output clock signal terminal CLK2 is passed through the second output transistor M2. Transfer to the second signal output OTP2.
  • the potential of the pull-up node PU is further increased to maintain the first output transistor M1 and the second output transistor M2 in an on state. Therefore, the high level of the first output clock signal terminal CLK1 can be output as a gate scan signal to the gate line connected to the first signal output terminal OTP1. Further, with the first phase P1, the third transistor T3 is in an on state, and the second transistor T2 and the fourth transistor T4 are in an off state.
  • the on/off state of the transistors in each of the sub-circuits is such that the first transistor T1 is turned off because the first signal input terminal INP1 outputs a low level.
  • the first voltage stabilizing capacitor CC1 and the second voltage stabilizing capacitor CC2 charge the high level pull-up node PU of the first stage P1, so that the first output transistor M1 and the second output transistor M2 remain in an on state.
  • the low level of the first output clock signal terminal CLK1 is output to the first signal output terminal OTP1 through the first output transistor M1 to reset the first signal output terminal OTP1, and the second output clock signal terminal CLK2
  • the high level is transmitted to the second signal output terminal OTP2 through the second output transistor M2, thereby outputting a gate scan signal to the gate line connected to the second signal output terminal OTP2.
  • the potential of the pull-up node PU is maintained at a high level to maintain the first output transistor M1 and the second output transistor M2 in conduction.
  • the state is such that the high level of the second output clock signal terminal CLK2 can be output as a continuous gate scan signal to the gate line connected to the second signal output terminal OTP2.
  • the third transistor T3 is in an on state, and the second transistor T2 and the fourth transistor T4 are in an off state.
  • the first pull-down control sub-circuit 30 Under the control of the first clock signal terminal CK1, the first pull-down control sub-circuit 30 outputs the voltage of the first control voltage terminal CN to the pull-down node PD.
  • the pull-down sub-circuit 50 pulls down the voltage of the pull-up node PU to the first voltage terminal VGL under the control of the pull-down node PD.
  • the first input sub-circuit 10 has no signal output, and no signal output is outputted at each signal output end.
  • each sub-circuit in the above shift register is as shown in FIG. 2, and the transistors in each sub-circuit are N-type transistors, as shown in FIG. 3, in the fourth stage P4, the first output clock signal end CLK1 inputs a low level, the second output clock signal terminal CLK2 inputs a high level, the first clock signal terminal CK1 inputs a high level, and the first signal input terminal INP1 inputs a low level.
  • the pull-up node PU is at a low level
  • the pull-down node PD is at a high level
  • the first signal output terminal OTP1 outputs a low level
  • the second signal output terminal OTP2 outputs a low level.
  • the on and off states of the transistors in the respective sub-circuits are: since the first clock signal terminal CK1 outputs a high level, the second transistor T2 is turned on, and the first transistor T2 is turned on. The high level of the clock signal terminal CK1 is output to the pull-down node PD. Under the control of the pull-down node PD, the fourth transistor T4 is turned on, and the potential of the pull-up node PU is pulled down to the first voltage terminal VGL through the fourth transistor T4 to reset the pull-up node PU.
  • the third transistor T3 and the first output transistor M1 are turned off, so that the first signal output terminal OTP1 and the second signal output terminal OUTPU T2 do not output a gate scan signal, thereby being used for each signal output terminal. Reset.
  • the fourth phase P4 may be repeated before the next image frame to keep the potential of the pull-down node PD high, and under the control of the pull-down node PD, pull down the potential of the pull-up node PU such that the output transistor M is at Cutoff status.
  • the potential of the pull-up node PU can be controlled by the first input sub-circuit 10 in an image frame, and the pull-up node PU can control the clock signals of each output sub-circuit 20 to output the clock signal terminal CLK.
  • the signals are sequentially outputted to the respective signal outputs so that the respective signal outputs can sequentially output the gate scan signals to the gate lines connected to the respective signal output terminals in the output stage.
  • first pull-down control sub-circuit 30 and the second pull-down control sub-circuit 40 can control the potential of the pull-down node PD to pull down the potential of the pull-down node PD to the potential of the first voltage terminal VGL; or pull down the potential of the node PD Pulled high so that the pull-down node PD can control the pull-down sub-circuit 50 to pull down the potential of the pull-up node PU to the potential of the first voltage terminal VGL.
  • the first output sub-circuit receiving the output signal of the output clock signal terminal CLK1 is connected.
  • the signal output terminal OTP1 outputs a gate scan signal.
  • the clock signals output from the other output clock signal terminals, for example, CLK2 ... CLKn are at a low level, so that the signal output terminals OTP2 ... connected to the second output sub-circuit are connected to the signal output of the n-th output sub-circuit.
  • the terminal OTPn or the like does not output the gate scan signal, so each signal output terminal can output a gate scan signal to the gate line connected to the signal output terminal, respectively.
  • the first-stage shift register can output a multi-level gate scan signal.
  • the first stage shift register does not need to output the gate scan signal to only one row of gate lines, and the area of the GOA circuit layout on the display panel can be reduced, thereby achieving a narrower border effect.

Abstract

本公开的一些实施例提供移位寄存器及其驱动方法、栅极驱动电路、显示装置。该移位寄存器包括第一输入子电路，其在第一信号输入端的控制下，将第一控制电压端的电压输出至上拉节点；n个输出子电路，在上拉节点的控制下，依次将输出时钟信号端的信号输出至各个信号输出端；第一下拉控制子电路，在第一时钟信号端的控制下，将第一控制电压端的电压输出至下拉节点；第二下拉控制子电路，在上拉节点的控制下，将下拉节点的电压下拉至第一电压；下拉子电路，在下拉节点的控制下，将上拉节点的电压下拉至第一电压。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
本申请要求于2017年10月31日提交中国专利局、申请号为201711048848.1、申请名称为“移位寄存器单元及其驱动方法、栅极驱动电路、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)具有低辐射、体积小及低耗能等优点，被广泛地应用在笔记本电脑、平面电视或移动电话等电子产品中。
发明内容
第一方面，提供一种移位寄存器，包括第一输入子电路、第一下拉控制子电路、第二下拉控制子电路、下拉子电路以及n个输出子电路，其中n≥2，n为正整数；所述第一输入子电路连接到第一信号输入端、第一控制电压端、上拉节点，所述第一输入子电路配置为在所述第一信号输入端的控制下，将所述第一控制电压端的电压输出至所述上拉节点；每级每个所述输出子电路连接到所述上拉节点、信号输出端、输出时钟信号端，每个所述输出子电路配置为在所述上拉节点的控制下，将所述输出时钟信号端的信号输出至所述信号输出端；所述第一下拉控制子电路连接到所述第一控制电压端、第一时钟信号端、下拉节点，所述第一下拉控制子电路配置为在所述第一时钟信号端的控制下，将所述第一控制电压端的电压输出至所述下拉节点；所述第二下拉控制子电路连接到所述上拉节点、所述下拉节点、第一电压端，所述第二下拉控制子电路配置为在所述上拉节点的控制下，将所述下拉节点的电压下拉至所述第一电压；所述下拉子电路连接到所述上拉节点、所述下拉节点、所述第一电压端，所述下拉子电路配置为在所述下拉节点的控制下，将所述上拉节点的电压下拉至所述第一电压。在本公开的一些实施例中，所述第一输入子电路包括第一晶体管；所述第一晶体管的栅极连接到所述第一信号输入端，第一极连接到所述第一控制电压端，第二极连接到所述上拉节点。
在本公开的一些实施例中，所述第一输入子电路包括第一晶体管；所述第一晶体管的栅极连接到所述第一信号输入端，第一极连接到所述第一控制电压端，第二极连 接到所述上拉节点。
在本公开的一些实施例中，每个所述输出子电路包括输出晶体管和稳压电容；所述输出晶体管的栅极连接到所述上拉节点，第一极连接到所述输出时钟信号端，第二极连接到所述信号输出端；所述稳压电容的一端连接到所述上拉节点，另一端连接到所述输出信号输出端。
在本公开的一些实施例中，所述第一下拉控制子电路包括第二晶体管；所述第二晶体管的栅极连接到所述第一时钟信号端，第一极连接到所述第一控制电压端，第二极连接到所述下拉节点；所述第二下拉控制子电路包括第三晶体管；所述第三晶体管的栅极连接到所述上拉节点，第一极连接到所述下拉节点，第二极连接到所述第一电压端；所述下拉子电路包括第四晶体管；所述第四晶体管的栅极连接到所述下拉节点，第一极连接到所述上拉节点，第二极连接到所述第一电压端。
在本公开的一些实施例中，所述下拉子电路还连接到各个所述信号输出端，所述下拉子电路还配置为在所述下拉节点的控制下，将所述信号输出端的电位拉低至所述第一电压端；所述下拉子电路还包括多个输出下拉晶体管；每个所述输出下拉晶体管的栅极连接到所述下拉节点，第一极连接到一信号输出端，第二极连接到所述第一电压端。
在本公开的一些实施例中，所述移位寄存器还包括连接于所述第一输入子电路与所述上拉节点之间的第一稳压降噪子电路，所述第一稳压降噪子电路还连接到所述第一电压端，和/或，第二电压端；所述第一稳压降噪子电路配置为在所述第一电压端和/或所述第二电压端的控制下，对所述上拉节点的电压进行稳压降噪。
在本公开的一些实施例中，所述第一稳压降噪子电路包括第一电容，和/或，第五晶体管；所述第一电容的一端连接到所述第一输入子电路的输出端，另一端连接到所述第一电压端；所述第五晶体管的栅极连接到所述第二电压端，第一极连接到所述第一输入子电路的输出端，第二极连接到所述上拉节点。
在本公开的一些实施例中，所述移位寄存器还包括连接于所述第一下拉控制子电路与所述下拉节点之间的第二稳压降噪子电路，所述第二稳压降噪子电路还连接到所述第一电压端、和/或第二电压端；所述第二稳压降噪子电路配置为在所述第一电压端和/或所述第二电压端的控制下，对所述下拉节点的电压进行稳压降噪。
在本公开的一些实施例中，所述第二稳压降噪子电路包括第二电容，和/或第六晶体管；所述第二电容的一端电连接到所述第一下拉控制子电路的输出端，另一端连接到所述第一电压端；所述第六晶体管的栅极连接到所述第二电压端，第一极连接到所述第一下拉控制子电路的输出端，第二极连接到所述下拉节点。
在本公开的一些实施例中，所述移位寄存器还包括第二输入子电路；所述第二输入子电路连接到第二信号输入端、第二控制电压端、所述上拉节点，所述第一输入子电路配置为在所述第二信号输入端的控制下，将所述第二控制电压端的电压输出至所述上拉节点。
在本公开的一些实施例中，所述移位寄存器还包括第三下拉控制子电路；所述第三下拉控制子电路连接到所述第二控制电压端、第二时钟信号端、所述下拉节点；所述第三下拉控制子电路配置为在所述第二时钟信号端的控制下，将所述第二控制电压端的电压输出至所述下拉节点。
在本公开的一些实施例中，所述第二输入子电路包括第八晶体管；所述第八晶体管的栅极连接到所述第二信号输入端，第一极连接到所述第二控制电压端，第二极连接到所述上拉节点。
在本公开的一些实施例中，所述第三下拉控制子电路包括第九晶体管；所述第九晶体管的栅极连接到所述第二时钟信号端，第一极连接到所述第二控制电压端，第二极连接到所述下拉节点。
第二方面，提供一种栅极驱动电路移位寄存器，包括多个级联的如第一方面所述的任意一种移位寄存器，第一级移位寄存器的第一信号输入端连接到起始信号端；除了第一级移位寄存器以外，每一级移位寄存器的第一信号输入端连接到该级移位寄存器的上一级移位寄存器的最后一个信号输出端。
第三方面，提供一种栅极驱动电路，包括多个级联的具有第二输入子电路的移位寄存器；第一级移位寄存器的第一信号输入端连接到起始信号端；除了第一级移位寄存器以外，每一级移位寄存器的第一信号输入端连接到该级移位寄存器的上一级移位寄存器的最后一个信号输出端；除了最后一级移位寄存器以外，每一级移位寄存器的第二信号输入端连接到该级移位寄存器的下一级移位寄存器的第一个信号输出端；最后一级移位寄存器的第二信号输入端连接到所述起始信号端。
第四方面，提供一种显示装置，包括如第二方面或第三方面所述的栅极驱动电路。
第五方面，提供一种配置为驱动如上所述的移位寄存器的方法，一图像帧内，所述驱动方法包括：充电阶段，第一输入子电路在第一信号输入端的控制下，将第一控制电压端的电压输出至上拉节点；第二下拉控制子电路在所述上拉节点的控制下，将下拉节点的电压下拉至所述第一电压端；各个输出子电路存储所述上拉节点的信号，并在所述上拉节点的控制下，将各个输出时钟信号端输出的信号分别输出至各个所述输出子电路所连接的信号输出端；输出阶段，所述各个输出子电路将上一阶段存储的信号输出至所述上拉节点，在所述上拉节点的控制下，依次将所述各个输出时钟信号 端的信号输出至各个所述输出子电路所连接的信号输出端，各个信号输出端依次输出栅极扫描信号；复位阶段，在第一时钟信号端的控制下，第一下拉控制子电路将所述第一控制电压端的电压输出至所述下拉节点；下拉子电路在所述下拉节点的控制下，将所述上拉节点的电压下拉至所述第一电压端。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一些实施例提供的一种移位寄存器的结构示意图；
图2为图1中各个子电路的具体结构示意图；
图3为控制图2所示的移位寄存器的一种信号时序图；
图4为图1所示的移位寄存器中，下拉子电路还连接到各级信号输出端的结构示意图；
图5为图4中各个子电路的具体结构示意图；
图6为图4所示的移位寄存器还包括第一稳压降噪子电路和第二稳压降噪子电路的结构示意图；
图7为图6中各个子电路的具体结构示意图；
图8为图4所示的移位寄存器还包括放电子电路的结构示意图；
图9为图7中各个子电路的具体结构示意图；
图10为图1所示的移位寄存器还包括第一输入子电路和第三下拉控制子电路的结构示意图；
图11为本公开的一些实施例提供的一种移位寄存器的具体结构示意图；
图12为控制图11所示的移位寄存器正向输出的一种信号时序图；
图13为本公开的一些实施例提供的另一种移位寄存器的具体结构示意图；
图14a为本公开的一些实施例提供的一种栅极驱动电路的结构示意图；
图14b为本公开的一些实施例提供的另一种栅极驱动电路的结构示意图；
图15为相关技术提供的移位寄存器的一种具体结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的 所有其他实施例，都属于本公开保护的范围。
液晶显示器包括相互对盒的彩膜基板和阵列基板，其中，阵列基板可以划分为显示区域和位于显示区域周边的周边区域。上述显示区域设置有横纵交叉的栅线和数据线，栅线和数据线交叉界定出多个亚像素。周边区域设置有数据驱动电路，该数据驱动电路可以将输入的显示数据及时钟信号定时顺序锁存，转换成模拟信号后输入到数据线。此外，周边区域还设置有栅级驱动电路，该栅极驱动电路可以将输入的时钟信号经过移位寄存器转换成控制上述亚像素选通或未被选通的电压，并逐行施加到与上述亚像素相连接的栅线上。
在相关技术中，上述栅极驱动电路可以采用GOA(Gate Driver on Array，阵列基板行驱动)设计方式将主要由TFT(Thin Film Transistor，薄膜场效应晶体管)栅极开关构成的电路集成在上述周边区域。其中，GOA电路中的每一级移位寄存器的输出端与一行栅线相连接。栅线在逐行被扫描的过程中，一行栅线被扫描时，能够接收到与该栅线相连接移位寄存器的输出端输出的栅极扫描信号，而与未被扫描的栅线所连接的移位寄存器处于未输出栅极扫描信号的状态。
然而，上述GOA电路中的每一级移位寄存器仅能向一行栅线输出栅极扫描信号，在显示面板上制作GOA电路时，移位寄存器的个数需要与栅线行数相匹配，这样一来，不利于实现显示面板的窄边框设计。
为了解决上述问题，本公开的一些实施例提供一种移位寄存器，如图1所示，该移位寄存器包括第一输入子电路10、第一下拉控制子电路30、第二下拉控制子电路40、下拉子电路50以及n个输出子电路20(例如，第一输出子电路、第二输出子电路……第n输出子电路)，其中n≥2，n为正整数。
其中，第一输入子电路10连接到第一信号输入端INPUT1(以下将INPUT简称为INP)、第一控制电压端CN、上拉节点PU，第一输入子电路10配置为在第一信号输入端INP1的控制下，将第一控制电压端CN提供的电压输出至上拉节点PU。
每个输出子电路20连接到上拉节点PU、信号输出端、输出时钟信号端，输出子电路20配置为在上拉节点PU的控制下，将输出时钟信号端CLK的信号输出至信号输出端。
在本公开的一些实施例中，任意两个输出子电路20连接到的输出时钟信号端以及信号输出端可以不相同。例如，如图1所示，第一输出子电路连接到输出时钟信号端CLK1，信号输出端OUTPUT1(以下将OUTPUT简称为OTP)；第二输出子电路连接到输出时钟信号端CLK2，信号输出端OTP2；第n输出子电路连接到输出时钟信号端CLKn，信号输出端OTPn。
此外，第一下拉控制子电路30连接到第一控制电压端CN、第一时钟信号端CK1、下拉节点PD，第一下拉控制子电路30配置为在第一时钟信号端CK1的控制下，将第一控制电压端CN提供的电压输出至下拉节点PD。
第二下拉控制子电路40连接到上拉节点PU、下拉节点PD、第一电压端VGL，第二下拉控制子电路40配置为在上拉节点PU的控制下，将下拉节点PD的电压下拉至第一电压。
下拉子电路50连接到上拉节点PU、下拉节点PD、第一电压端VGL，下拉子电路50配置为在下拉节点PD的控制下，将上拉节点PU的电压下拉至第一电压。
基于此，本公开的一些实施例提供一种移位寄存器，包括第一输入子电路10、第一下拉控制子电路30、第二下拉控制子电路40、下拉子电路30以及n个输出子电路20。其中，第一输入子电路10连接到第一信号输入端INP1、第一控制电压端CN、上拉节点PU，第一输入子电路10配置为在第一信号输入端INP1的控制下，将所述第一控制电压端CN的电压输出至上拉节点PU。每个输出子电路20均连接到上拉节点PU、信号输出端、输出时钟信号端，输出子电路20配置为在上拉节点PU的控制下，将输出时钟信号端CLK的信号输出至信号输出端。第一下拉控制子电路30连接到第一控制电压端CN、第一时钟信号端CK1、下拉节点PD，第一下拉控制子电路30配置为在第一时钟信号端CK1的控制下，将第一控制电压端CN的电压输出至下拉节点PD。第二下拉控制子电路40连接到上拉节点PU、下拉节点PD、第一电压端VGL，第二下拉控制子电路40配置为在上拉节点PU的控制下，将下拉节点PD的电压下拉至第一电压端VGL。下拉子电路50连接到上拉节点PU、下拉节点PD、第一电压端VGL，下拉子电路50配置为在下拉节点PD的控制下，将上拉节点PU的电压下拉至第一电压端VGL的电位，即第一电压。
在此基础上，在一图像帧内，通过第一输入子电路10可以对上拉节点PU的电位进行控制，而该上拉节点PU可以控制各个输出子电路20将其各自所连接的输出时钟信号端，例如CLK1、CLK2……CLKn的时钟信号依次输出至各个输出子电路20所连接的信号输出端例如OTP1、OTP2……OTPn，以使得各个信号输出端，例如OTP1、OTP2……OTPn在输出阶段能够分别对与各个信号输出端，例如OTP1、OTP2……OTPn所连接的栅线依次输出栅极扫描信号。
此外，第一下拉控制子电路30和第二下拉控制子电路40能够控制下拉节点PD的电位，以将下拉节点PD的电位下拉至第一电压端VGL的电位；或者将下拉节点PD的电位拉高，以使得下拉节点PD能够控制下拉子电路50将上拉节点PU的电位下拉至第一电压端VGL的电位。
由上述可知，每一级移位寄存器具有多个信号输出端，例如OTP1、OTP2……OTPn，因此一级移位寄存器可以通过不同的信号输出端分别与多条栅线相连接，从而使得一级移位寄存器就可以对多条栅线进行逐行扫描。为了实现逐行扫描，在同一级移位寄存器中，当该移位寄存器的一个输出时钟信号端，例如CLK1的时钟信号为高电平时，接收该输出时钟信号端CLK1输出信号的第一输出子电路所连接的信号输出端OTP1输出栅极扫描信号。此时，其他输出时钟信号端，例如CLK2……CLKn输出的时钟信号为低电平，从而与第二输出子电路相连接的信号输出端OTP2……与第n输出子电路相连接的信号输出端OTPn等不输出栅极扫描信号从而能够使得与一级移位寄存器相连接的多条栅线不会同时接收到栅极扫描信号，以实现多条栅线的逐行扫描。这样一来，一级移位寄存器无需仅向一行栅线输出栅极扫描信号，可以减少显示面板上GOA电路中移位寄存器占据周边区域的布图面积，从而实现更窄边框的效果。
以一级移位寄存器具有两个输出子电路，例如如图2所示的第一输出子电路21和第二输出子电路22为例，对图1所示的移位寄存器中上述各个子电路的电路结构进行详细的举例说明。
在本公开的一些实施例中，如图2所示，第一输入子电路10可以包括第一晶体管T1。第一晶体管T1的栅极连接到第一信号输入端INP1，第一极连接到第一控制电压端CN，第二极连接到上拉节点PU。
每个输出子电路20包括输出晶体管M和稳压电容CC。输出晶体管M的栅极连接到上拉节点PU，第一极连接到输出时钟信号端，第二极连接到信号输出端。稳压电容CC的一端连接到上拉节点PU，另一端连接到输出信号输出端。
在一级移位寄存器具有两个输出子电路，例如第一输出子电路21和第二输出子电路22的情况下，第一输出子电路21包括第一输出晶体管M1和第一稳压电容CC1。第一输出晶体管M1的栅极连接到上拉节点PU，第一极连接到输出第一输出时钟信号端CLK1，第二极连接到第一信号输出端OTP1。第一稳压电容CC1的一端连接到上拉节点PU，另一端连接到输出第一信号输出端OTP1。
第二输出子电路22包括第二输出晶体管M2和第二稳压电容CC2。第二输出晶体管M2的栅极连接到上拉节点PU，第一极连接到第二输出时钟信号端CLK2，第二极连接到第二信号输出端OTP2。第二稳压电容CC2的一端连接到上拉节点PU，另一端连接到输出第二信号输出端OTP2。
如图2所示，第一下拉控制子电路30包括第二晶体管T2。第二晶体管T2的栅极连接到第一时钟信号端CK1，第一极连接到第一控制电压端CN，第二极连接到下拉节点PD。
第二下拉控制子电路40包括第三晶体管T3。第三晶体管T3的栅极连接到上拉节点PU，第一极连接到下拉节点PD，第二极连接到第一电压端VGL。
下拉子电路50包括第四晶体管T4。第四晶体管T4的栅极连接到下拉节点PD，第一极连接到上拉节点PU，第二极连接到第一电压端VGL。
需要说明的是，上述晶体管可以为N型晶体管，也可以为P型晶体管；可以为增强型晶体管，也可以为耗尽型晶体管。此外，上述晶体管的第一极可以为源极，第二极可以为漏极，或者上述晶体管的第一极可以为漏极，第二极为源极，本公开对此不作限定。
以下以上述晶体管均为N型晶体管为例，并结合图3对如图2所示的移位寄存器中的各个晶体管，在一图像帧内的不同阶段(P1～P4)的通断情况进行详细的举例说明。本公开的一些实施例中是以第一电压端VGL恒定输出直流低电平，且在该图像帧内第一控制电压端CN输出直流高电平为例进行的说明。此外，以下实施例均是以信号输出端，例如OTP1、OTP2……OTPn分别输出高电平时，表示上述该信号输出端输出栅极扫描信号，而当信号输出端输出低电平时，表示上述信号输出端未输出栅极扫描信号为例进行说明。
第一阶段P1，INP1＝1，CLK1＝0，CLK2＝0，CK1＝0，PU＝1，PD＝0。其中“0”表示低电平，“1”表示高电平。
在此情况下，由于第一信号输入端INP1输出高电平，因此第一晶体管T1导通，从而将第一控制电压端CN输出的高电平传输至上拉节点PU，并通过第一稳压电容CC1和第二稳压电容CC2对上拉节点PU的高电平进行存储。
在上拉节点PU的控制下，第一输出晶体管M1和第二输出晶体管M2导通，通过第一输出晶体管M1将第一输出时钟信号端CLK1输出的低电平传输至第一信号输出端OTP1。此外，通过第二输出晶体管M2将第二输出时钟信号端CLK2输出的低电平传输至第二信号输出端OTP2。此外，在上拉节点PU的控制下，第三晶体管T3导通，从而通过第三晶体管T3将下拉节点PD的电位下拉至第一电压端VGL，因此第四晶体管T4处于截止状态。
此外，由于第一时钟信号端CK1输出低电平，因此第二晶体管T2处于截止状态。
综上所述，该级移位寄存器中的第一信号输出端OTP1和第二信号输出端OTP2在上述第一阶段P1均输出低电平。
第二阶段P2，INP1＝0，CLK1＝1，CLK2＝0，CK1＝0，PU＝1，PD＝0。
在此情况下，由于第一信号输入端INP1输出低电平，因此第一晶体管T1处于截止状态。第一稳压电容CC1和第二稳压电容CC2将第一阶段P1存储的高电平对上拉 节点PU进行充电，从而使得第一输出晶体管M1和第二输出晶体管M2在该第二阶段P2保持导通状态。在此情况下，第一输出时钟信号端CLK1输出的高电平仍然可以通过第一输出晶体管M1传输至第一信号输出端OTP1，第二输出时钟信号端CLK2输出的低电平仍然可以通过第二输出晶体管M2传输至第二信号输出端OTP2。
此外，当第一信号输出端OTP1和第二信号输出端OTP2均输出高电平时，上述第一稳压电容CC1和第二稳压电容CC2分别与第一信号输出端OTP1和第二信号输出端OTP2相连接的一端的电位有所提升，因此在第一稳压电容CC1和第二稳压电容CC2的自举作用下，第一稳压电容CC1和第二稳压电容CC2与上拉节点PU相连接的一端的电位也相应得到提升，从而使得上拉节点PU的电位进一步升高，以有效维持第一输出晶体管M1和第二输出晶体管M2在第二阶段P2处于导通的状态，从而使得第一输出时钟信号端CLK1的高电平能够持续稳定的作为栅极扫描信号输出至与第一信号输出端OTP1相连接的栅线上。
此外，同第一阶段P1，第三晶体管T3处于导通状态，第二晶体管T2和第四晶体管T4处于截止状态。
综上所述，第一信号输出端OTP1在第二阶段P2输出高电平，以向与第一信号输出端OTP1相连接的栅线输出栅极扫描信号。除第一信号输出端OTP1外，其他各个信号输出端，例如第二信号输出端OTP2输出低电平，即不输出栅极扫描信号。
第三阶段P3，INP1＝0，CLK1＝0，CLK2＝1，CK1＝0，PU＝1，PD＝0。
在此情况下，由于第一信号输入端INP1输出低电平，因此第一晶体管T1截止。第一稳压电容CC1和第二稳压电容CC2将第一阶段P1存储的高电平对上拉节点PU进行充电，从而使得第一输出晶体管M1和第二输出晶体管M2在第三阶段P3仍然保持导通状态。
在此情况下，第一输出时钟信号端CLK1的低电平通过第一输出晶体管M1输出至第一信号输出端OTP1，以对第一信号输出端OTP1进行复位，使得与该第一信号输出端OTP1相连接的栅线不再接受到上述栅极扫描信号；第二输出时钟信号端CLK2的高电平输出至第二信号输出端OTP2。
此外，在第一稳压电容CC1和第二稳压电容CC2的自举作用下，上拉节点PU的电位维持高电平，以维持第一输出晶体管M1和第二输出晶体管M2处于导通的状态，从而使得第二输出时钟信号端CLK2输出的高电平能够作为栅极扫描信号输出至与第二信号输出端OTP2相连接的栅线上。此外，同第一阶段P1，第三晶体管T3处于导通状态，第二晶体管T2和第四晶体管T4处于截止状态。
综上所述，第二信号输出端OTP2在第三阶段P3输出高电平，以向与第二信号输 出端OTP2相连接的栅线输出栅极扫描信号。除第二信号输出端OTP2外，其他各个信号输出端，例如第一信号输出端OTP1输出低电平，即不输出栅极扫描信号。
第四阶段P4，INP1＝0，CLK1＝0，CLK2＝0，CK1＝1，PU＝0，PD＝1。
在此情况下，由于第一时钟信号端CK1输出高电平，第二晶体管T2导通，通过第二晶体管T2将第一时钟信号端CK1输出的高电平传输至下拉节点PD。
在下拉节点PD的控制下，第四晶体管T4导通，通过第四晶体管T4将上拉节点PU的电位下拉至第一电压端VGL，以对上拉节点PU进行复位。在上拉节点PU的控制下，第三晶体管T3、第一输出晶体管M1、第二输出晶体管M2截止，以使第一信号输出端OTP1和第二信号输出端OTP2不输出栅极扫描信号。
接下来，可以在下一图像帧开始(即，第一信号输入端INP1再次输入高电平)之前重复第四阶段P4，以使得下拉节点PD的电位保持高电平，并在下拉节点PD的控制下，拉低上拉节点PU的电位以使得第一输出晶体管M1和第二输出晶体管M2处于截止状态。
需要说明的是，上述实施例是以一级移位寄存器包括两个输出子电路为例进行的说明，当一级移位寄存器包括更多个输出子电路时，该移位寄存器在工作时，第一阶段P1和第四阶段P4的工作过程不变，不同之处在于，需要根据输出子电路的个数增加第一阶段P1和第四阶段P4之间的能够使得各个输出子电路逐个输出栅极扫描信号的阶段具体工作原理和第二阶段P2和第三阶段P3相同，此处不再赘述。
此外，上述实施例中晶体管的导通、截止过程是以所有晶体管为N型晶体管为例进行说明的，当所有晶体管均为P型时，需要对图3中部分控制信号进行翻转，而移位寄存器中各个子电路的晶体管的通、断过程同上所述，此处不再赘述。
在此基础上，在本公开的一些实施例中，如图4所示，下拉子电路50还连接到各个信号输出端，例如OTP1、OTP2……OTPn，下拉子电路50还配置为在下拉节点PD的控制下，将各个信号输出端，例如OTP1、OTP2……OTPn的电位拉低至第一电压端VGL，以进一步对各个信号输出端，例如，OTP1、OTP2……OTPn进行复位。
在此情况下，在本公开的一些实施例中，下拉子电路50还可以包括输出下拉晶体管。其中，输出下拉晶体管的栅极连接到下拉节点PD，第一极连接到信号输出端，第二极连接到第一电压端VGL。
以移位寄存器包括两级输出子电路，即第一输出子电路21和第二输出子电路22为例，如图5所示，下拉子电路50还可以包括第一输出下拉晶体管Q1和第二输出下拉晶体管Q2。其中，第一输出下拉晶体管Q1的栅极连接到下拉节点PD，第一极连接到第一信号输出端OTP1，第二极连接到第一电压端VGL。第二输出下拉晶体管Q2 的栅极连接到下拉节点PD，第一极连接到第二信号输出端OTP2，第二极连接到第一电压端VGL。
在此情况下，上述第四阶段P4中，在下拉节点PD的控制下，第一输出下拉晶体管Q1和第二输出下拉晶体管Q2导通，并通过第一输出下拉晶体管Q1将第一信号输出端OTP1的电位下拉至第一电压端VGL；通过第二输出下拉晶体管Q2将第二信号输出端OTP2的电位下拉至第一电压端VGL，以分别对第一信号输出端OTP1和第二信号输出端OTP2进行复位，同时防止第一信号输出端OTP1和第二信号输出端OTP2异常输出，提高了移位寄存器工作的稳定性。
在此基础上，如图13所示，上述移位寄存器如图13所示，还包括第十晶体管T10和第十一晶体管T11。
第十一晶体管T11的栅极连接到第二电压端VGH，第一极连接到上拉节点PU，第二极连接到第十晶体管T10以及第二输出晶体管M2的栅极。
第十晶体管T10的第一极连接到移位寄存器中最后一个信号输出端，例如图13中第二信号输出端OTP2相连接的输出下拉晶体管，例如上述第二输出下拉晶体管Q2的栅极，第二极连接到第一电压端VGL。
在此情况下，以上述第十晶体管T10和第十一晶体管T11均为N型晶体管为例，在第二电压端VGH恒定输出高电平的情况下，第十一晶体管T11作为单管传输门工作，一直处于导通状态，从而可以利用第十一晶体管T11进一步降低第十晶体管T10以及第二输出晶体管M2的栅极的噪声杂波，并稳定第十晶体管T10以及第二输出晶体管M2的栅极的信号。此外，在上拉节点PU为高电平时，第十晶体管T10处于导通的状态，从而能够将上述第二输出下拉晶体管Q2的栅极电位下拉至第一电压端VGL，此时第二输出下拉晶体管Q2截止，从而避免在第二信号输出端OTP2输出栅极扫描信号时，将该第二信号输出端OTP2输出的信号拉低至第一电压端VGL。
在本公开的一些实施例中，如图6所示，移位寄存器还包括连接于在第一输入子电路10与上拉节点PU之间的第一稳压降噪子电路60，第一稳压降噪子电路60还可以连接到第一电压端VGL和/或第二电压端VGH。第一稳压降噪子电路60配置为在上述第一电压端VGL和/或第二电压端VGH的控制下稳定上拉节点PU的电压、降低上拉节点PU的噪声杂波。
以下对第一稳压降噪子电路60的具体电路结构进行举例说明。
在本公开的一些实施例中，如图7所示，第一稳压降噪子电路60可以包括第一电容C1和第五晶体管T5。或者，在本公开的另一些实施例中，第一稳压降噪子电路60可以仅包括上述第一电容C1。又或者，在本公开的另一些实施例中，上述第一稳压降 噪子电路62可以仅包括上述第五晶体管T5。
第一电容C1的一端连接到第一输入子电路10的输出端，另一端连接到第一电压端VGL。第五晶体管T5的栅极连接到第二电压端VGH，第一极连接到第一输入子电路10的输出端，第二极连接到上拉节点PU。
需要说明的是，第一输入子电路10的输出端是指，第一输入子电路10中，在第一信号输入端INP1的控制下，将第一控制电压端CN的电压输出至上拉节点PU的一端。图7中第一输入子电路10的输出端为第一晶体管T1的第二极。
在此情况下，当第一稳压降噪子电路60包括第一电容C1时，在第一电容C1的滤波作用下，第一电容C1可以对上拉节点PU的噪声杂波进行滤除，同时可以利用第一电容C1的自举作用保持上拉节点PU稳定。
当第一稳压降噪子电路60包括第五晶体管T5时，该第五晶体管T5的栅极所连接的第二电压端VGH可以恒定的输出直流高电平，因此在第二电压端VGH的控制下，第五晶体管T5作为单管传输门工作，可以一直处于导通状态。第一输入子电路10输出的信号经第五晶体管T5传输至上拉节点PU，从而稳定上拉节点PU的电压，同时第五晶体管T5可以降低第一输入子电路10的输出信号的杂波传输至上拉节点PU的几率，从而降低上拉节点PU的噪声杂波。
此外，在本公开的一些实施例中，如图6所示，移位寄存器还包括连接于在第一下拉控制子电路30与下拉节点PD之间的第二稳压降噪子电路70，第二稳压降噪子电路70还可以连接到第一电压端VGL和/或第二电压端VGH。第二稳压降噪子电路70配置为在第一电压端VGL和/或第二电压端VGH的控制下，稳定下拉节点PD的电压、降低下拉节点PD的噪声杂波。
以下对第二稳压降噪子电路70的具体电路结构进行举例说明。
在本公开的一些实施例中，第二稳压降噪子电路70可以包括如图7所示第二电容C2和第六晶体管T6。或者，在本公开的另一些实施例中，上述第二稳压降噪子电路70可以仅包括上述第二电容C2。又或者，在本公开的另一些实施例中，上述第二稳压降噪子电路70可以仅包括上述第六晶体管T6。
在上述第二稳压降噪子电路70可以仅包括上述第二电容C2的情况下，第二电容C2的一端直接连接到第一下拉控制子电路30的输出端，另一端连接到第一电压端VGL。需要说明的是，第一下拉控制子电路30的输出端是指，第一下拉控制子电路30中，在第一时钟信号端CK1的控制下，将第一控制电压端CN的电压输出至下拉节点PD的一端。示例的，如图7所示，第一下拉控制子电路30的输出端为第二晶体管T2的第二极。
在此情况下，当第二稳压降噪子电路70包括第二电容C2时，在第二电容C2的滤波作用下，第二电容C2可以对下拉节点PD的噪声杂波进行滤除，同时可以利用第二电容C2的自举作用保持下拉节点PD稳定。
当第二稳压降噪子电路70仅包括第六晶体管T6时，第六晶体管T6的栅极连接到第二电压端VGH，第一极连接到上述下拉控制子电路30的输出端，第二极连接到下拉节点PD。
此外，在第二稳压降噪子电路70包括第二电容C2和第六晶体管T6时，上述第二电容C2的一端与第六晶体管T6的第二极相连接，从而可以通过第六晶体管T6将第二电容C2的一端电连接到第一下拉控制子电路30的输出端。
在第二电压端VGH恒定输出高电平的控制下，第六晶体管T6作为单管传输门工作，一直处于导通状态。第一下拉控制子电路30输出的信号经第六晶体管T6传输至下拉节点PD，从而稳定下拉节点PD的电压，同时第六晶体管T6可以降低第一下拉控制子电路30的输出信号的杂波传输至下拉节点PD的几率，从而降低下拉节点PD的噪声杂波。
在本公开的一些实施例中，如图8所示，移位寄存器还可以包括放电子电路80，放电子电路80连接到下拉节点PD、复位信号端RESET(简称RST)。放电子电路80配置为在复位信号端RST的控制下，将复位信号端RST的电压输出至下拉节点PD。
以下对放电子电路80的具体电路结构进行举例说明。
在本公开的一些实施例中，如图9所示，放电子电路80包括第七晶体管T7，第七晶体管T7的栅极和第一极连接到复位信号端RST，第二极连接到下拉节点PD。
在此基础上，在下一图像帧开始扫描之前，向复位信号端RST输入高电平，在复位信号端RST的控制下，第七晶体管T7导通，通过第七晶体管T7将复位信号端RST输出的高电平传输至下拉节点PD，从而将下拉节点PD的电位拉高。
在下拉节点PD的控制下，第一输出下拉晶体管Q1和第二输出下拉晶体管Q2导通，从而通过第一输出下拉晶体管Q1和第二输出下拉晶体管Q2分别将第一信号输出端OTP1和第二信号输出端OTP2的电位下拉至第一电压端VGL。这样一来，可以在下一图像帧开始扫描之前，对移位寄存器的各个信号输出端的信号进行复位，以避免相邻图像帧的信号之间发生串扰。
此外，在本公开的一些实施例中，如图10所示，移位寄存器还可以包括第二输入子电路11和第三下拉控制子电路31。
第二输入子电路11连接到第二信号输入端INP2、第二控制电压端CNB、上拉节点PU。第一输入子电路10配置为在第二信号输入端INP2的控制下，将第二控制电压 端CNB的电压输出至上拉节点PU。
第三下拉控制子电路31连接到第二控制电压端CNB、第二时钟信号端CK2、下拉节点PD。第三下拉控制子电路31配置为在第二时钟信号端CK2的控制下，将第二控制电压端CNB的电压输出至下拉节点PD。
以下对第二输入子电路11和第三下拉控制子电路31的具体电路结构进行举例说明。
示例的，如图11所示，第二输入子电路11包括第八晶体管T8，第八晶体管T8的栅极连接到第二信号输入端INP2，第一极连接到第二控制电压端CNB，第二极连接到上拉节点PU。
第三下拉控制子电路31包括第九晶体管T9，第九晶体管T9的栅极连接到第二时钟信号端CK2，第一极连接到第二控制电压端CNB，第二极连接到下拉节点PD。
需要说明的是，可以以图11中第一控制电压端CN和第二控制电压端CNB作为正反扫的控制信号端。当CN＝1，CNB＝0时，具有多级上述移位寄存器的GOA电路可以对与该GOA电路相连接的多条栅线正向(从上到下)逐行扫描。
当CN＝0，CNB＝1时，具有多级上述移位寄存器的GOA电路可以对与该GOA电路相连接的多条栅线反向(从下到上)逐行扫描。
具有多级上述移位寄存器的GOA电路中。一级移位寄存器的第一信号输入端INP1连接到上一级移位寄存器的最后一级信号输出端OTP，第二信号输入端INP2连接到下一级移位寄存器的第一信号输出端OTP1。
以下以移位寄存器正向扫描为例，结合图12所示的时序电路对图11所示的移位寄存器的在一图像帧内的工作过程进行说明。其中。
正向扫描时，CN为高电平，CNB为低电平。向第一信号输入端INP1输入高电平，向第二信号输入端INP2输入低电平。在第二电压端VGH的控制下，第五晶体管T5和第六晶体管T6始终处于导通状态。
第一阶段P1，INP1＝1，CLK1＝0，CLK2＝0，CK1＝0，CK2＝0，PU＝1，PD＝0。
在此情况下，由于第一信号输入端INP1输出高电平，因此第一晶体管T1导通，从而将第一信号输入端INP1的高电平通过第五晶体管T5输出至上拉节点PU，并通过第一稳压电容CC1和第二稳压电容CC2对该高电平进行存储。第五晶体管T5可以降低第一晶体管T1输出信号的杂波传输至上拉节点PU的几率，从而降低上拉节点PU的噪声杂波。在第一电容C1的滤波作用下，第一电容C1可以对上拉节点PU的噪声杂波进行滤除，同时可以利用第一电容C1的自举作用保持上拉节点PU稳定。
在上拉节点PU的控制下，第一输出晶体管M1和第二输出晶体管M2导通，第一 输出时钟信号端CLK1输出的低电平通过第一输出晶体管M1传输至第一信号输出端OTP1。第二输出时钟信号端CLK2输出的低电平通过第二输出晶体管M2传输至第二信号输出端OTP2。
此外，在上拉节点PU的高电位的控制下，第三晶体管T3、第十晶体管T10导通，通过第三晶体管T3和第十晶体管T10将下拉节点PD的电位下拉至第一电压端VGL。
此外，由于第二信号输入端INP2输出低电平，因此第八晶体管T8处于截止状态。由于第一时钟信号端CK1输出低电平，因此第二晶体管T2处于截止状态。由于第二时钟信号端CK2输出低电平，因此第九晶体管T9处于截止状态。由于下拉节点PD的电位为低电平，因此第四晶体管T4、第一输出下拉晶体管Q1、第二输出下拉晶体管Q2处于截止状态。由于复位信号端RST输出低电平，因此第七晶体管T7处于截止状态。
综上所述，各个信号输出端，例如第一信号输出端OTP1和第二信号输出端OTP2在上述第一阶段P1均输出低电平。
第二阶段P2，INP1＝0，CLK1＝1，CLK2＝0，CK1＝0，CK2＝0，PU＝1，PD＝0。
在此情况下，由于第一信号输入端INP1输出低电平，因此第一晶体管T1处于截止状态。第一稳压电容CC1和第二稳压电容CC2将第一阶段P1存储的高电平对上拉节点PU进行充电，从而使得第一输出晶体管M1和第二输出晶体管M2保持导通状态。在此情况下，第一输出时钟信号端CLK1输出的高电平通过第一输出晶体管M1传输至第一信号输出端OTP1，第二输出时钟信号端CLK2输出的低电平通过第二输出晶体管M2传输至第二信号输出端OTP2。
此外，在第一稳压电容CC1和第二稳压电容CC2的自举作用下，上拉节点PU的电位进一步升高，以维持第一输出晶体管M1和第二输出晶体管M2处于导通的状态，从而使得第一输出时钟信号端CLK1的高电平能够作为栅极扫描信号持续稳定的输出至与第一信号输出端OTP1相连接的栅线上。此外，同第一阶段P1，第三晶体管T3处于导通状态，第二晶体管T2、第四晶体管T4、第八晶体管T8、第九晶体管T9、第一输出下拉晶体管Q1、第二输出下拉晶体管Q2、第七晶体管T7处于截止状态。
综上所述，第一信号输出端OTP1在第二阶段P2输出高电平，以向与第一信号输出端OTP1相连接的栅线输出栅极扫描信号。除第一信号输出端OTP1外，其他各个信号输出端，例如第二信号输出端OTP2输出低电平，即不输出栅极扫描信号。
第三阶段P3，INP1＝0，CLK1＝0，CLK2＝1，CK1＝0，CK2＝0，PU＝1，PD＝0。
在此情况下，由于第一信号输入端INP1输出低电平，因此第一晶体管T1截止。第一稳压电容CC1和第二稳压电容CC2将第一阶段P1存储的高电平对上拉节点PU 进行充电，从而使得第一输出晶体管M1和第二输出晶体管M2保持导通状态。在此情况下，第一输出时钟信号端CLK1输出的低电平通过第一输出晶体管M1传输至第一信号输出端OTP1，第二输出时钟信号端CLK2输出的高电平通过第二输出晶体管M2传输至第二信号输出端OTP2。
此外，在第一稳压电容CC1和第二稳压电容CC2的自举作用下，上拉节点PU的电位维持高电平，以维持第一输出晶体管M1和第二输出晶体管M2处于导通的状态，从而使得第二输出时钟信号端CLK2的高电平能够作为栅极扫描信号输出至与第二信号输出端OTP2相连接的栅线上。
此外，同第一阶段P1，第三晶体管T3处于导通状态，第二晶体管T2、第四晶体管T4、第七晶体管T7、第八晶体管T8、第九晶体管T9、第一输出下拉晶体管Q1、第二输出下拉晶体管Q2处于截止状态。
综上所述，第二信号输出端OTP2在第三阶段P3输出高电平，以向与第二信号输出端OTP2相连接的栅线输出栅极扫描信号。除第二信号输出端OTP2外，其他各个信号输出端，例如第一信号输出端OTP1输出低电平。
在此基础上，第三阶段P3中，如图12所示，当CLK1＝0时，此时第一输出时钟信号端CLK1输出的低电平传输至第一信号输出端OTP1，以对第一信号输出端OTP1进行复位。
第四阶段P4，INP1＝0，CLK1＝0，CLK2＝0，CK1＝1，CK2＝1，PU＝0，PD＝1。
在此情况下，由于第一时钟信号端CK1输出高电平，第二晶体管T2导通，将第一时钟信号端CK1的高电平输出至第六晶体管T6，并通过第六晶体管T6输出至下拉节点PD。其中，第六晶体管T6可以稳定下拉节点PD的电压，第六晶体管T6还可以降低第二晶体管T2的输出信号的杂波传输至下拉节点PD的几率，从而降低下拉节点PD的噪声杂波。同时在第二电容C2的滤波作用下，第二电容C2可以对下拉节点PD的噪声杂波进行滤除，且利用第二电容C1的自举作用可以保持下拉节点PD稳定。
在下拉节点PD的控制下，第四晶体管T4导通，通过第四晶体管T4将上拉节点PU的电位下拉至第一电压端VGL，以对上拉节点PU进行复位。
此外，在上述下拉节点PD的控制下，第一输出下拉晶体管Q1和第二输出下拉晶体管Q2导通，通过第一输出下拉晶体管Q1将第一信号输出端OTP1的电位下拉至第一电压端VGL，通过第二输出下拉晶体管Q2将第二信号输出端OTP2的电位下拉至第一电压端VGL，以对第一信号输出端OTP1、第二信号输出端OTP2分别进行复位。在上拉节点PU的控制下，第三晶体管T3、第一输出晶体管M1和第二输出晶体管M2截止。
接下来，可以在下一图像帧之前重复第四阶段P4，以使得下拉节点PD的电位保持高电平，并在下拉节点PD的控制下，拉低上拉节点PU的电位以使得第一输出晶体管M1和第二输出晶体管M2处于截止状态。
在此基础上，在下一图像帧开始扫描之前，向复位信号端RST输入高电平，第七晶体管T7导通，将复位信号端RST的高电平通过第七晶体管T7输出至下拉节点PD，在下拉节点PD的控制下，对上拉节点PU、第一信号输出端OTP1和第二信号输出端OTP2进行进一步复位，以避免相邻图像帧的信号之间发生串扰。
需要说明的是，当移位寄存器反向扫描时，向第一控制电压端CN输入低电平，向第二控制电压端CNB输入高电平，第一阶段P1时，在第二信号输入端INP2的控制下，将第二控制电压端CNB的电压输出至上拉节点PU；第四阶段P4时，向第二时钟信号端CK2输入高电平，在第二时钟信号端CK2的控制下，将第二控制电压端CNB的电压输出至下拉节点PD。第二阶段P2和第三阶段P3的工作原理和正向输出的工作原理相同，此处不再赘述。
此外，在相关技术中移位寄存器通过如图15所示包括10个晶体管和2个电容，以向两行栅线依次输出栅极扫描信号为例，此时需要包括两个级联的移位寄存器，即20个晶体管和2个电容。而本公开的一些实施例提供的一级移位寄存器就可以向至少两行栅线依次输出栅极扫描信号，相比于现有的移位寄存器，可以使用更少的晶体管个数，从而可以降低移位寄存器的功耗。
本公开的一些实施例提供了一种如图14a所示的栅极驱动电路，包括多个级联的如图1-图9提供的任一种移位寄存器，其中，第一级移位寄存器RS1的第一信号输入端INP1连接到起始信号端STV。
除了第一级移位寄存器RS1以外，每一级移位寄存器的第一信号输入端INP1连接到该级移位寄存器的上一级移位寄存器的最后一个信号输出端。
起始信号端STV配置为输出起始信号，该栅极驱动电路的第一级移位寄存器RS1在接收到上述起始信号后开始对栅线(G1、G2……Gn)进行逐行扫描。
需要说明的是，图14a是以每级移位寄存器包括两级信号输出端OTP为例进行的示意。具体的，第一级移位寄存器RS1的第一信号输入端INP1连接到起始信号端STV。
除了第一级移位寄存器RS1以外，每一级移位寄存器的第一信号输入端INP1连接到该级移位寄存器的上一级移位寄存器的第二信号输出端OTP2。
基于此，本公开的一些实施例提供了一种栅极驱动电路，包括多个级联的如图1-图9所示的任一种移位寄存器，具有与图1-图9所示的任意一种移位寄存器相同的结构和有益效果，由于前述实施例已经对上述移位寄存器的具体结构和有益效果进行了 说明，本公开对此不再赘述。
本公开的一些实施例还提供了一种栅极驱动电路，如图14b所示，包括多个级联的如图10或图11所示的任意一种移位寄存器。
其中，第一级移位寄存器RS1的第一信号输入端INP1连接到起始信号端STV。
除了第一级移位寄存器RS1以外，每一级移位寄存器的第一信号输入端INP1连接到该级移位寄存器的上一级移位寄存器的最后一个信号输出端。
除了最后一级移位寄存器RSn以外，每一级移位寄存器的第二信号输入端INP2连接到该级移位寄存器的下一级移位寄存器的第一个信号输出端OTP1。
最后一级移位寄存器RSn的第二信号输入端INP2连接到起始信号端STV。
其中，起始信号端STV配置为输出起始信号，该栅极驱动电路的第一级移位寄存器RS1在接收到上述起始信号后开始对栅线(G1、G2……Gn)进行正向逐行扫描。或者该栅极驱动电路的最后一级移位寄存器RSn在接收到上述起始信号后开始对栅线(G1、G2……Gn)进行反向逐行扫描。
需要说明的是，图14b是以每级移位寄存器包括两级信号输出端OTP为例进行的示意。具体的，第一级移位寄存器RS1的第一信号输入端INP1连接到起始信号端STV。
除了第一级移位寄存器RS1以外，每一级移位寄存器的第一信号输入端INP1连接到该级移位寄存器的上一级移位寄存器的第二信号输出端OTP2。
除了最后一级移位寄存器RSn以外，每一级移位寄存器的第二信号输入端INP2连接到该级移位寄存器的下一级移位寄存器的第一信号输出端OTP1。
最后一级移位寄存器RSn的第二信号输入端INP2连接到起始信号端STV。
基于此，本公开的一些实施例提供了一种栅极驱动电路，包括如图10或图11所示的任一种移位寄存器，该移位寄存器具有与图10或者图11所示的移位寄存器相同的结构和有益效果，由于前述实施例已经对上述移位寄存器的具体结构和有益效果进行了说明，本公开对此不再赘述。
本公开的一些实施例提供了一种显示装置，包括如上所述的任一种栅极驱动电路，具有与前述实施例提供的栅极驱动电路相同的结构和有益效果，由于前述实施例已经对该栅极驱动电路的结构和有益效果进行了详尽的描述，此处不再赘述。
本公开的一些实施例还提供了一种配置为驱动上述任意一种移位寄存器的方法，具体的一图像帧内，该驱动方法包括：
在如图3所示的第一阶段P1：
第一输入子电路10在第一信号输入端INP1的控制下，将第一控制电压端CN的电压输出至上拉节点PU。
第二下拉控制子电路40在上拉节点PU的控制下，将下拉节点PD的电压下拉至第一电压端VGL。各个输出子电路20存储上拉节点PU的信号，并在上拉节点PU的控制下，将各个输出时钟信号端CLK输出的时钟信号分别输出至各个输出子电路20各自所连接的信号输出端。此外，第一下拉控制子电路30和下拉子电路50均未开启。
当上述移位寄存器中各个子电路的结构如图2所示，且各个子电路中的晶体管均为N型晶体管时，其中，图2以移位寄存器包括两级输出子电路，即第一输出子电路21和第二输出子电路22为例进行示意。如图3所示，在该输入阶段P1中，第一输出时钟信号端CLK1和第二输出时钟信号端CLK2输入低电平，第一输入信号端INP1输入高电平，第一时钟信号端CK1输入低电平。此外，上拉节点PU为高电平，下拉节点PD为低电平，各个信号输出端输出低电平。
基于此，在该输入阶段P1中上述各个子电路中晶体管的通、断情况为：由于第一信号输入端INP1输出高电平，因此第一晶体管T1导通，从而将第一信号输入端INP1输出的高电平传输至上拉节点PU，并通过第一稳压电容CC1和第二稳压电容CC2对该高电平进行存储。在上拉节点PU的控制下，第一输出晶体管M1和第二输出晶体管M2导通，将第一输出时钟信号端CLK1输出的低电平通过第一输出晶体管M1传输至第一信号输出端OTP1，将第二输出时钟信号端CLK2输出的低电平通过第二输出晶体管M2传输至第二信号输出端OTP2。此外，在上拉节点PU高电位的控制下，第三晶体管T3导通，将下拉节点PD的电位下拉至第一电压端VGL，由于下拉节点PD的电位为低电平，因此第四晶体管T4处于截止状态。
此外，由于第一时钟信号端CK1输出低电平，因此第二晶体管T2处于截止状态。
在输出阶段：
各个输出子电路20将上一阶段存储的信号输出至上拉节点PU，在上拉节点PU的控制下，依次将各个输出时钟信号端CLK的信号输出至各个输出子电路20所连接的信号输出端，各个信号输出端依次输出栅极扫描信号。此外，在该阶段，第一下拉控制子电路40和下拉子电路50均未开启，第一输入子电路10无信号输出。
当上述移位寄存器中各个子电路的结构如图2所示，且各个子电路中的晶体管均为N型晶体管时，其中图2以移位寄存器包括两级输出子电路，即第一输出子电路21和第二输出子电路22为例进行示意。如图3所示，上述输出阶段包括第二阶段P2和第三阶段P3。
在此情况下，在如图3所示的第二阶段P2中，第一输出时钟信号端CLK1输入高电平，第二输出时钟信号端CLK2输入低电平，第一信号输入端INP1输入低电平，第一时钟信号端CK1输入低电平。此外，上拉节点PU为高电平，下拉节点PD为低电 平，第一信号输出端OTP1输出高电平，第二信号输出端OTP2输出低电平。
在如图3所示的第三阶段P3中，第一输出时钟信号端CLK1输入低电平，第二输出时钟信号端CLK2输入高电平，第一信号输入端INP1输入低电平，第一时钟信号端CK1输入低电平。此外，上拉节点PU为高电平，下拉节点PD为低电平，第一信号输出端OTP1输出低电平，以对第一信号输出端OTP1复位，第二信号输出端OTP2输出高电平。
基于此，在该第二阶段P2中上述各个子电路中晶体管的通、断情况为：由于第一信号输入端INP1输出低电平，因此第一晶体管T1处于截止状态。第一稳压电容CC1和第二稳压电容CC2将第一阶段P1存储的高电平对上拉节点PU进行充电，从而使得第一输出晶体管M1和第二输出晶体管M2保持导通状态。在此情况下，第一输出时钟信号端CLK1输出的高电平通过第一输出晶体管M1传输至第一信号输出端OTP1，第二输出时钟信号端CLK2输出的低电平通过第二输出晶体管M2传输至第二信号输出端OTP2。
此外，在第一稳压电容CC1和第二稳压电容CC2的自举作用下，上拉节点PU的电位进一步升高，以维持第一输出晶体管M1和第二输出晶体管M2处于导通的状态，从而使得第一输出时钟信号端CLK1的高电平能够作为栅极扫描信号输出至与第一信号输出端OTP1相连接的栅线上。此外，同第一阶段P1，第三晶体管T3处于导通状态，第二晶体管T2和第四晶体管T4处于截止状态。
在该第三阶段P3中上述各个子电路中晶体管的通断情况为：由于第一信号输入端INP1输出低电平，因此第一晶体管T1截止。第一稳压电容CC1和第二稳压电容CC2将第一阶段P1存储的高电平对上拉节点PU进行充电，从而使得第一输出晶体管M1和第二输出晶体管M2保持导通状态。在此情况下，第一输出时钟信号端CLK1的低电平通过第一输出晶体管M1输出至第一信号输出端OTP1，以对第一信号输出端OTP1进行复位，第二输出时钟信号端CLK2的高电平通过第二输出晶体管M2传输至第二信号输出端OTP2，从而对与该第二信号输出端OTP2相连接的栅线输出栅极扫描信号。
此外，在第一稳压电容CC1和第二稳压电容CC2的自举作用下，上拉节点PU的电位维持高电平，以维持第一输出晶体管M1和第二输出晶体管M2处于导通的状态，从而使得第二输出时钟信号端CLK2的高电平能够作为持续的栅极扫描信号输出至与第二信号输出端OTP2相连接的栅线上。此外，同第一阶段P1，第三晶体管T3处于导通状态，第二晶体管T2和第四晶体管T4处于截止状态。
在复位阶段，即如图3所示的第四阶段P4：
在第一时钟信号端CK1的控制下，第一下拉控制子电路30将第一控制电压端CN 的电压输出至下拉节点PD。下拉子电路50在下拉节点PD的控制下，将上拉节点PU的电压下拉至第一电压端VGL。此外第四阶段P4中，第一输入子电路10无信号输出，各个信号输出端无信号输出。
当上述移位寄存器中各个子电路的结构如图2所示，且各个子电路中的晶体管均为N型晶体管时，如图3所示，在第四阶段P4中，第一输出时钟信号端CLK1输入低电平，第二输出时钟信号端CLK2输入高电平，第一时钟信号端CK1输入高电平，第一信号输入端INP1输入低电平。此外，上拉节点PU为低电平，下拉节点PD为高电平，第一信号输出端OTP1输出低电平，第二信号输出端OTP2输出低电平。
基于此，在该第四阶段P4中上述各个子电路中晶体管的通、断情况为：由于第一时钟信号端CK1输出高电平，第二晶体管T2导通，通过第二晶体管T2将第一时钟信号端CK1的高电平输出至下拉节点PD。在下拉节点PD的控制下，第四晶体管T4导通，通过第四晶体管T4将上拉节点PU的电位下拉至第一电压端VGL，以对上拉节点PU进行复位。在上拉节点PU的控制下，第三晶体管T3和第一输出晶体管M1截止，以使第一信号输出端OTP1和第二信号输出端OUTPU T2不输出栅极扫描信号，从而对各个信号输出端进行复位。
接下来，可以在下一图像帧之前重复第四阶段P4，以使得下拉节点PD的电位保持高电平，并在下拉节点PD的控制下，拉低上拉节点PU的电位以使得输出晶体管M处于截止状态。
基于此，在一图像帧内，通过第一输入子电路10可以对上拉节点PU的电位进行控制，而该上拉节点PU可以控制各个输出子电路20将个输出时钟信号端CLK的时钟信号依次输出至各个信号输出端，以使得各个信号输出端在输出阶段能够分别对与各个信号输出端相连接的栅线依次输出栅极扫描信号。
此外，第一下拉控制子电路30和第二下拉控制子电路40能够控制下拉节点PD的电位，以将下拉节点PD的电位下拉至第一电压端VGL的电位；或者将下拉节点PD的电位拉高，以使得下拉节点PD能够控制下拉子电路50将上拉节点PU的电位下拉至第一电压端VGL的电位。
此外，在同一级移位寄存器中，当该移位寄存器的一个输出时钟信号端，例如CLK1的时钟信号为高电平时，接收该输出时钟信号端CLK1输出信号的第一输出子电路所连接的信号输出端OTP1输出栅极扫描信号。此时，其他输出时钟信号端，例如CLK2……CLKn输出的时钟信号为低电平，从而与第二输出子电路相连接的信号输出端OTP2……与第n输出子电路相连接的信号输出端OTPn等不输出栅极扫描信号，因此各个信号输出端可以分别向与该信号输出端相连的栅线输出栅极扫描信号。
这样一来，由于本公开的一些实施例提供的移位寄存器具有多级信号输出端，因此一级移位寄存器可以输出多级栅极扫描信号。在此情况下，一级移位寄存器无需仅向一行栅线输出栅极扫描信号，可以减少显示面板上GOA电路布图的面积，从而实现更窄边框的效果。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种移位寄存器，其中，包括第一输入子电路、第一下拉控制子电路、第二下拉控制子电路、下拉子电路以及n个输出子电路，其中n≥2，n为正整数；
    所述第一输入子电路连接到第一信号输入端、第一控制电压端、上拉节点，所述第一输入子电路配置为在所述第一信号输入端的控制下，将所述第一控制电压端的电压输出至所述上拉节点；
    每个所述输出子电路连接到所述上拉节点、信号输出端、输出时钟信号端，每个所述输出子电路配置为在所述上拉节点的控制下，将所述输出时钟信号端的信号输出至所述信号输出端；
    所述第一下拉控制子电路连接到所述第一控制电压端、第一时钟信号端、下拉节点，所述第一下拉控制子电路配置为在所述第一时钟信号端的控制下，将所述第一控制电压端的电压输出至所述下拉节点；
    所述第二下拉控制子电路连接到所述上拉节点、所述下拉节点、第一电压端，所述第二下拉控制子电路配置为在所述上拉节点的控制下，将所述下拉节点的电压下拉至所述第一电压；
    所述下拉子电路连接到所述上拉节点、所述下拉节点、所述第一电压端，所述下拉子电路配置为在所述下拉节点的控制下，将所述上拉节点的电压下拉至所述第一电压。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一输入子电路包括第一晶体管；
    所述第一晶体管的栅极连接到所述第一信号输入端，第一极连接到所述第一控制电压端，第二极连接到所述上拉节点。
  3. 根据权利要求1所述的移位寄存器，其中，每个所述输出子电路包括输出晶体管和稳压电容；
    所述输出晶体管的栅极连接到所述上拉节点，第一极连接到所述输出时钟信号端，第二极连接到所述信号输出端；
    所述稳压电容的一端连接到所述上拉节点，另一端连接到所述输出信号输出端。
  4. 根据权利要求1所述的移位寄存器，其中，所述第一下拉控制子电路包括第二晶体管；所述第二晶体管的栅极连接到所述第一时钟信号端，第一极连接到所述第一控制电压端，第二极连接到所述下拉节点；
    所述第二下拉控制子电路包括第三晶体管；所述第三晶体管的栅极连接到所述上拉节点，第一极连接到所述下拉节点，第二极连接到所述第一电压端；
    所述下拉子电路包括第四晶体管；所述第四晶体管的栅极连接到所述下拉节点，第一极连接到所述上拉节点，第二极连接到所述第一电压端。
  5. 根据权利要求1所述的移位寄存器，其中，所述下拉子电路还连接到各个所述信号输出端，所述下拉子电路还配置为在所述下拉节点的控制下，将所述信号输出端的电位拉低至所述第一电压端；
    所述下拉子电路还包括多个输出下拉晶体管；
    每个所述输出下拉晶体管的栅极连接到所述下拉节点，第一极连接到一信号输出端，第二极连接到所述第一电压端。
  6. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器还包括连接于所述第一输入子电路与所述上拉节点之间的第一稳压降噪子电路，所述第一稳压降噪子电路还连接到所述第一电压端，和/或，第二电压端；
    所述第一稳压降噪子电路配置为在所述第一电压端和/或所述第二电压端的控制下，对所述上拉节点的电压进行稳压降噪。
  7. 根据权利要求6所述的移位寄存器，其中，所述第一稳压降噪子电路包括第一电容，和/或，第五晶体管；
    所述第一电容的一端连接到所述第一输入子电路的输出端，另一端连接到所述第一电压端；
    所述第五晶体管的栅极连接到所述第二电压端，第一极连接到所述第一输入子电路的输出端，第二极连接到所述上拉节点。
  8. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器还包括连接于所述第一下拉控制子电路与所述下拉节点之间的第二稳压降噪子电路，所述第二稳压降噪子电路还连接到所述第一电压端、和/或第二电压端；
    所述第二稳压降噪子电路配置为在所述第一电压端和/或所述第二电压端的控制下，对所述下拉节点的电压进行稳压降噪。
  9. 根据权利要求8所述的移位寄存器，其中，所述第二稳压降噪子电路包括第二电容，和/或第六晶体管；
    所述第二电容的一端电连接到所述第一下拉控制子电路的输出端，另一端连接到所述第一电压端；
    所述第六晶体管的栅极连接到所述第二电压端，第一极连接到所述第一下拉控制子电路的输出端，第二极连接到所述下拉节点。
  10. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器还包括第二输入子电路；
    所述第二输入子电路连接到第二信号输入端、第二控制电压端、所述上拉节点，所述第一输入子电路配置为在所述第二信号输入端的控制下，将所述第二控制电压端的电压输出至所述上拉节点。
  11. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器还包括第三下拉控制子电路；
    所述第三下拉控制子电路连接到所述第二控制电压端、第二时钟信号端、所述下拉节点；所述第三下拉控制子电路配置为在所述第二时钟信号端的控制下，将所述第二控制电压端的电压输出至所述下拉节点。
  12. 根据权利要求10所述的移位寄存器，其中，所述第二输入子电路包括第八晶体管；
    所述第八晶体管的栅极连接到所述第二信号输入端，第一极连接到所述第二控制电压端，第二极连接到所述上拉节点。
  13. 根据权利要求10所述的移位寄存器，其中，所述第三下拉控制子电路包括第九晶体管；
    所述第九晶体管的栅极连接到所述第二时钟信号端，第一极连接到所述第二控制电压端，第二极连接到所述下拉节点。
  14. 一种栅极驱动电路，其中，包括多个级联的如权利要求1所述的移位寄存器；
    第一级移位寄存器的第一信号输入端连接到起始信号端；
    除了第一级移位寄存器以外，每一级移位寄存器的第一信号输入端连接到该级移位寄存器的上一级移位寄存器的最后一个信号输出端。
  15. 一种栅极驱动电路，其中，包括多个级联的如权利要求10所述的移位寄存器；
    第一级移位寄存器的第一信号输入端连接到起始信号端；
    除了第一级移位寄存器以外，每一级移位寄存器的第一信号输入端连接到该级移位寄存器的上一级移位寄存器的最后一个信号输出端；
    除了最后一级移位寄存器以外，每一级移位寄存器的第二信号输入端连接到该级移位寄存器的下一级移位寄存器的第一个信号输出端；
    最后一级移位寄存器的第二信号输入端连接到所述起始信号端。
  16. 一种显示装置，其中，包括如权利要求14所述的栅极驱动电路。
  17. 一种显示装置，其中，包括如权利要求15所述的栅极驱动电路。
  18. 一种配置为驱动如权利要求1所述的移位寄存器的方法，其中，一图像帧内，所述驱动方法包括：
    充电阶段，第一输入子电路在第一信号输入端的控制下，将第一控制电压端的电 压输出至上拉节点；第二下拉控制子电路在所述上拉节点的控制下，将下拉节点的电压下拉至所述第一电压端；
    各个输出子电路存储所述上拉节点的信号，并在所述上拉节点的控制下，将各个输出时钟信号端输出的信号分别输出至各个所述输出子电路所连接的信号输出端；
    输出阶段，所述各个输出子电路将上一阶段存储的信号输出至所述上拉节点，在所述上拉节点的控制下，依次将所述各个输出时钟信号端的信号输出至各个所述输出子电路所连接的信号输出端，各个信号输出端依次输出栅极扫描信号；
    复位阶段，在第一时钟信号端的控制下，第一下拉控制子电路将所述第一控制电压端的电压输出至所述下拉节点；
    下拉子电路在所述下拉节点的控制下，将所述上拉节点的电压下拉至所述第一电压端。
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