WO2020224154A1 - Goa电路和显示装置 - Google Patents

Goa电路和显示装置 Download PDF

Info

Publication number
WO2020224154A1
WO2020224154A1 PCT/CN2019/106293 CN2019106293W WO2020224154A1 WO 2020224154 A1 WO2020224154 A1 WO 2020224154A1 CN 2019106293 W CN2019106293 W CN 2019106293W WO 2020224154 A1 WO2020224154 A1 WO 2020224154A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
node
gate
drain
Prior art date
Application number
PCT/CN2019/106293
Other languages
English (en)
French (fr)
Inventor
薛炎
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020224154A1 publication Critical patent/WO2020224154A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a GOA (gate driver on array) circuit and a display device.
  • GOA gate driver on array
  • the horizontal scanning line of the display panel is driven by an external integrated circuit (IC).
  • the external integrated circuit can control the step-by-step turn-on of the row scanning lines at all levels, using GOA (gate driver on array) technology. That is, the array substrate row drive technology can integrate the row scan drive circuit on the substrate of the display panel, can reduce the number of external integrated circuits, thereby reducing the production cost of the display panel, and can realize the narrow frame of the display device.
  • IGZO indium gallium zinc oxide
  • IGZO indium gallium zinc oxide
  • the demultiplexer (Demux) GOA circuit is a method that can realize the narrow frame of the GOA circuit.
  • the current Demux GOA circuit needs to add multiple sets of clock signal sources with different pulse widths and amplitudes. Therefore, although the overall GOA is reduced The layout occupies space, but the number of signals is greatly increased, and the newly added signal lines also occupy a large part of the space.
  • the Demux GOA circuit needs to add multiple sets of clock signal sources with different pulse widths and amplitudes. Therefore, although the space occupied by the overall GOA layout is reduced, the number of signals is greatly increased, and the new signal lines also take up a lot Part of the space.
  • one purpose of the present disclosure is to provide a GOA (gate driver on array) circuit and a display device, which can drive three scan lines and use a set of clock signals.
  • the required thin film transistor (TFT) ) Is less in number and requires fewer signal lines to achieve a narrow frame of GOA circuit.
  • the GOA circuit includes multiple GOA circuit units cascaded. Let n be a natural number.
  • the nth level GOA unit responsible for outputting the nth level horizontal scan signal includes a pull-up unit, a pull-up control unit, a downstream unit, a pull-down unit, a pull-down sustain unit, and a bootstrap capacitor.
  • the pull-up unit is connected to the first node, the second node, the DC low voltage and a set of clock signals.
  • the set of clock signals includes a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal.
  • the pull-up control unit is connected to the first node, the second node, the first clock signal, the current stage transmission signal output terminal, and the previous stage transmission signal output terminal or start pulse trigger signal.
  • the download unit is connected to the first node, the current stage transmission signal output terminal, and a first direct current high voltage.
  • the pull-down unit is connected to the first node, the second node, the previous stage transmission signal output terminal, the next stage transmission signal output terminal, and the DC low voltage.
  • the pull-down maintaining unit is connected to the first node, the second node, the current stage transmission signal output terminal, the second direct current high voltage, and the direct current low voltage. Both ends of the bootstrap capacitor are respectively connected to the first node and the current stage transmission signal output terminal.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal of the set of clock signals are AC signals with the same waveform.
  • the pull-up control unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor.
  • the gate of the first thin film transistor is connected to the first clock signal, and the source and drain of the first thin film transistor are respectively connected to the second node and the previous stage signal output terminal or the Start pulse trigger signal.
  • the gate of the second thin film transistor is connected to the first clock signal, and the source and drain of the second thin film transistor are connected to the first node and the second node, respectively.
  • the gate of the third thin film transistor is connected to the first node, and the source and drain of the third thin film transistor are respectively connected to the current stage signal output terminal and the second node.
  • the source and drain of the first thin film transistor are respectively connected to the second node and the start pulse trigger signal.
  • the pull-up unit includes a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and a ninth thin film transistor.
  • the gate of the fourth thin film transistor is connected to the first node, and the source and drain of the fourth thin film transistor are respectively connected to the fourth clock signal and the 3n-th level horizontal scanning signal output terminal.
  • the gate of the fifth thin film transistor is connected to the first node, and the source and drain of the fifth thin film transistor are respectively connected to the third clock signal and the 3n-1 level horizontal scanning signal output terminal.
  • the gate of the sixth thin film transistor is connected to the first node, and the source and drain of the sixth thin film transistor are respectively connected to the second clock signal and the 3n-2th stage horizontal scanning signal output terminal.
  • the gate of the seventh thin film transistor is connected to the first clock signal, and the source and drain of the seventh thin film transistor are respectively connected to the 3n-th level horizontal scanning signal output terminal and the second node.
  • the gate of the eighth thin film transistor is connected to the fourth clock signal, and the source and drain of the eighth thin film transistor are respectively connected to the 3n-1 level horizontal scanning signal output terminal and the second node.
  • the gate of the ninth thin film transistor is connected to the third clock signal, and the source and drain of the ninth thin film transistor are respectively connected to the 3n-2th level horizontal scanning signal output terminal and the second node.
  • the downstream unit includes a tenth thin film transistor, the gate of the tenth thin film transistor is connected to the first node, and the source and drain of the tenth thin film transistor are respectively Connect the first direct current high voltage and the current stage transmission signal output terminal.
  • the pull-down unit includes an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, and a fourteenth thin film transistor.
  • the gate of the eleventh thin film transistor is connected to the upper-level signal output terminal, and the source and drain of the eleventh thin film transistor are respectively connected to the DC low voltage and the current-level signal The output terminal.
  • the gate of the twelfth thin film transistor is connected to the previous stage signal output terminal, and the source and drain of the twelfth thin film transistor are respectively connected to the current stage signal output terminal and the direct current low voltage.
  • the gate of the thirteenth thin film transistor is connected to the next-stage signal output terminal, and the source and drain of the thirteenth thin film transistor are respectively connected to the second node and the first node.
  • the gate of the fourteenth thin film transistor is connected to the next-stage signal output terminal, and the source and drain of the fourteenth thin film transistor are respectively connected to the DC low voltage and the second node.
  • the pull-down sustain unit includes a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, an eighteenth thin film transistor, a nineteenth thin film transistor, and a twentieth thin film transistor.
  • Transistor The gate of the fifteenth thin film transistor is connected to the third node, and the source and drain of the fifteenth thin film transistor are respectively connected to the second node and the first node.
  • the gate of the sixteenth thin film transistor is connected to the third node, and the source and drain of the sixteenth thin film transistor are respectively connected to the DC low voltage and the second node.
  • the gate of the seventeenth thin film transistor is connected to the second direct current high voltage, and the source and drain of the seventeenth thin film transistor are respectively connected to the gate of the eighteenth thin film transistor and the second direct current high voltage.
  • the gate of the eighteenth thin film transistor is connected to the source of the seventeenth thin film transistor, and the source and drain of the eighteenth thin film transistor are connected to the third node and the third node, respectively.
  • Two direct current high voltage is connected to the first node, and the source and drain of the nineteenth thin film transistor are respectively connected to the DC low voltage and the gate of the eighteenth thin film transistor .
  • the gate of the twentieth thin film transistor is connected to the first node, and the source and drain of the twentieth thin film transistor are respectively connected to the DC low voltage and the third node.
  • the GOA circuit is a GOA circuit made based on IGZO material.
  • the present disclosure also provides a display device including a GOA circuit.
  • the GOA circuit includes multiple GOA circuit units cascaded. Let n be a natural number.
  • the nth level GOA unit responsible for outputting the nth level horizontal scan signal includes a pull-up unit, a pull-up control unit, a downstream unit, a pull-down unit, a pull-down sustain unit, and a bootstrap capacitor.
  • the pull-up unit is connected to the first node, the second node, the DC low voltage and a set of clock signals.
  • the set of clock signals includes a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal.
  • the pull-up control unit is connected to the first node, the second node, the first clock signal, the current stage transmission signal output terminal, and the previous stage transmission signal output terminal or start pulse trigger signal.
  • the download unit is connected to the first node, the current stage transmission signal output terminal, and a first direct current high voltage.
  • the pull-down unit is connected to the first node, the second node, the previous stage transmission signal output terminal, the next stage transmission signal output terminal, and the DC low voltage.
  • the pull-down maintaining unit is connected to the first node, the second node, the current stage transmission signal output terminal, the second direct current high voltage, and the direct current low voltage. Both ends of the bootstrap capacitor are respectively connected to the first node and the current stage transmission signal output terminal.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal of the set of clock signals are AC signals with the same waveform.
  • the pull-up control unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor.
  • the gate of the first thin film transistor is connected to the first clock signal, and the source and drain of the first thin film transistor are respectively connected to the second node and the previous stage signal output terminal or the Start pulse trigger signal.
  • the gate of the second thin film transistor is connected to the first clock signal, and the source and drain of the second thin film transistor are connected to the first node and the second node, respectively.
  • the gate of the third thin film transistor is connected to the first node, and the source and drain of the third thin film transistor are respectively connected to the current stage signal output terminal and the second node.
  • the source and drain of the first thin film transistor are respectively connected to the second node and the start pulse trigger signal.
  • the pull-up unit includes a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and a ninth thin film transistor.
  • the gate of the fourth thin film transistor is connected to the first node, and the source and drain of the fourth thin film transistor are respectively connected to the fourth clock signal and the 3n-th level horizontal scanning signal output terminal.
  • the gate of the fifth thin film transistor is connected to the first node, and the source and drain of the fifth thin film transistor are respectively connected to the third clock signal and the 3n-1 level horizontal scanning signal output terminal.
  • the gate of the sixth thin film transistor is connected to the first node, and the source and drain of the sixth thin film transistor are respectively connected to the second clock signal and the 3n-2th stage horizontal scanning signal output terminal.
  • the gate of the seventh thin film transistor is connected to the first clock signal, and the source and drain of the seventh thin film transistor are respectively connected to the 3n-th level horizontal scanning signal output terminal and the second node.
  • the gate of the eighth thin film transistor is connected to the fourth clock signal, and the source and drain of the eighth thin film transistor are respectively connected to the 3n-1 level horizontal scanning signal output terminal and the second node.
  • the gate of the ninth thin film transistor is connected to the third clock signal, and the source and drain of the ninth thin film transistor are respectively connected to the 3n-2th level horizontal scanning signal output terminal and the second node.
  • the downstream unit includes a tenth thin film transistor, the gate of the tenth thin film transistor is connected to the first node, and the source and drain of the tenth thin film transistor are respectively Connect the first direct current high voltage and the current stage transmission signal output terminal.
  • the pull-down unit includes an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, and a fourteenth thin film transistor.
  • the gate of the eleventh thin film transistor is connected to the upper-level signal output terminal, and the source and drain of the eleventh thin film transistor are respectively connected to the DC low voltage and the current-level signal The output terminal.
  • the gate of the twelfth thin film transistor is connected to the previous stage signal output terminal, and the source and drain of the twelfth thin film transistor are respectively connected to the current stage signal output terminal and the direct current low voltage.
  • the gate of the thirteenth thin film transistor is connected to the next stage signal output terminal, and the source and drain of the thirteenth thin film transistor are respectively connected to the second node and the first node.
  • the gate of the fourteenth thin film transistor is connected to the next-stage signal output terminal, and the source and drain of the fourteenth thin film transistor are respectively connected to the DC low voltage and the second node.
  • the pull-down sustain unit includes a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, an eighteenth thin film transistor, a nineteenth thin film transistor, and a twentieth thin film transistor.
  • Transistor The gate of the fifteenth thin film transistor is connected to the third node, and the source and drain of the fifteenth thin film transistor are respectively connected to the second node and the first node.
  • the gate of the sixteenth thin film transistor is connected to the third node, and the source and drain of the sixteenth thin film transistor are respectively connected to the DC low voltage and the second node.
  • the gate of the seventeenth thin film transistor is connected to the second direct current high voltage, and the source and drain of the seventeenth thin film transistor are respectively connected to the gate of the eighteenth thin film transistor and the second direct current high voltage.
  • the gate of the eighteenth thin film transistor is connected to the source of the seventeenth thin film transistor, and the source and drain of the eighteenth thin film transistor are connected to the third node and the third node, respectively.
  • Two direct current high voltage is connected to the first node, and the source and drain of the nineteenth thin film transistor are respectively connected to the DC low voltage and the gate of the eighteenth thin film transistor .
  • the gate of the twentieth thin film transistor is connected to the first node, and the source and drain of the twentieth thin film transistor are respectively connected to the DC low voltage and the third node.
  • the GOA circuit is a GOA circuit made based on IGZO material.
  • the GOA circuit includes a plurality of GOA circuit units cascaded.
  • the nth level GOA unit responsible for outputting the nth level horizontal scan signal includes a pull-up unit, a pull-up control unit, a downstream unit, a pull-down unit, a pull-down sustain unit, and a bootstrap capacitor.
  • the pull-up unit is connected to the n-th level horizontal scanning signal output terminal and a set of clock signals.
  • the n-th level GOA unit can drive three row scan lines, can drive three row scan lines, and uses a set of clock signals. The number of thin film transistors required and the signal lines required are less, so that the GOA circuit is narrow. frame.
  • FIG. 1 shows a schematic diagram of the structure of a GOA circuit according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of the input source signal waveform of the GOA circuit according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of output waveforms of the nth GOA unit of the GOA circuit according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the GOA circuit of an embodiment of the present disclosure includes twenty thin film transistors (TFTs) and a capacitor Cbt, and the connection relationship between the circuits is shown in FIG. 1.
  • TFTs thin film transistors
  • VGH, VGHH and VGL are direct current (DC) power supplies
  • STV is a start pulse (start pulse) trigger signal, which is required to start the first-level GOA unit.
  • the specific waveform and potential relationship of each signal in the GOA circuit can be shown in Table 1 below. Nodes N, Q, QB, Cout(n-1), Cout(n), Cout(n+I), G(3n-2), G(3n-1), G(3n), etc. are important nodes in the circuit.
  • CK1, CK2, CK3, CK4 are a set of AC signals
  • Cout(n-1) is connected to the Cout(n) output signal of the previous stage
  • Cout(n+1) is connected to the Cout output signal of the next stage.
  • the Cout(n-1) of T11 in the first stage of the GOA circuit is connected to the STV signal.
  • FHD full high definition
  • the number of scan lines is 1080
  • the number of clock signals is 4 (CK1, CK2, CK3, and CK4)
  • the clock period is 60 milliseconds
  • the CK duty cycle is 25%
  • the number of STVs is one.
  • An embodiment of the present disclosure provides a GOA circuit.
  • the GOA circuit includes multiple GOA circuit units cascaded. Let n be a natural number.
  • the n-th GOA unit responsible for outputting the n-th horizontal scan signal includes a pull-up unit 10, a pull-up control unit 20, a download unit 30, a pull-down unit 40, a pull-down sustain unit 50, and a bootstrap capacitor Cbt.
  • the pull-up unit 10 is connected to the first node Q, the second node N, the DC low voltage VGL and a set of clock signals.
  • the set of clock signals includes a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4.
  • the pull-up control unit 20 is connected to the first node Q, the second node N, the first clock signal CK1, the current stage signal output terminal Cout(n), and the previous stage signal output terminal Cout(n-1) or start pulse trigger signal STV.
  • the download unit 30 is connected to the first node Q, the current-stage transmission signal output terminal Cout(n), and the first DC high voltage VGHH.
  • the pull-down unit 40 is connected to the first node Q, the second node N, the previous stage transmission signal output terminal Cout(n-1), and the next stage transmission signal output terminal Cout(n+1 ) And the DC low voltage VGL.
  • the pull-down maintaining unit 50 is connected to the first node Q, the second node N, the current stage transmission signal output terminal Cout(n), the second DC high voltage VGH and the DC low voltage VGL . Both ends of the bootstrap capacitor Cbt are respectively connected to the first node Q and the current stage transmission signal output terminal Cout(n).
  • the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 of the set of clock signals have the same waveform AC signal.
  • the pull-up control unit mainly raises the potential of the first node Q and controls the opening time of the pull-up unit 10.
  • the pull-up control unit 20 includes a first thin film transistor T11, a second thin film transistor T12, and a third thin film transistor T6.
  • the gate of the first thin film transistor T11 is connected to the first clock signal CK1, and the source and drain of the first thin film transistor T11 are respectively connected to the second node N and the previous stage signal output
  • the terminal Cout(n-1) or the start pulse triggers the signal STV.
  • the gate of the second thin film transistor T12 is connected to the first clock signal CK1, and the source and drain of the second thin film transistor T12 are connected to the first node Q and the second node N, respectively.
  • the gate of the third thin film transistor T6 is connected to the first node Q, and the source and drain of the third thin film transistor T6 are respectively connected to the current stage signal output terminal Cout(n) and the first node Q. Two node N.
  • the source and drain of the first thin film transistor T11 are respectively connected to the second node N and the start pulse trigger signal STV.
  • the pull-up unit 10 is mainly responsible for converting a clock signal into an output signal.
  • the pull-up unit 10 includes a fourth thin film transistor T21, a fifth thin film transistor T22, a sixth thin film transistor T23, a seventh thin film transistor T41, an eighth thin film transistor T42, and a ninth thin film transistor T43.
  • the gate of the fourth thin film transistor T21 is connected to the first node Q, and the source and drain of the fourth thin film transistor T21 are respectively connected to the fourth clock signal CK4 and the 3n-th level horizontal scanning signal output terminal G (3n).
  • the fourth thin film transistor T21 is responsible for converting the fourth clock signal CK4 into an output signal, that is, the 3n-th level horizontal scanning signal output terminal G(3n).
  • the gate of the fifth thin film transistor T22 is connected to the first node Q, and the source and drain of the fifth thin film transistor T22 are respectively connected to the third clock signal CK3 and the level 3n-1 horizontal scanning signal output End G(3n-1).
  • the fifth thin film transistor T22 is responsible for converting the third clock signal CK3 into an output signal, that is, the 3n-1 level horizontal scanning signal output terminal G(3n-1).
  • the gate of the sixth thin film transistor T23 is connected to the first node Q, and the source and drain of the sixth thin film transistor T23 are respectively connected to the second clock signal CK2 and the level 3n-2 horizontal scanning signal output Terminal G (3n-2).
  • the sixth thin film transistor T23 is responsible for converting the second clock signal CK2 into an output signal, that is, the 3n-2th level horizontal scanning signal output terminal G(3n-2).
  • the gate of the seventh thin film transistor T41 is connected to the first clock signal CK1, and the source and drain of the seventh thin film transistor T41 are respectively connected to the 3n-th level horizontal scanning signal output terminal G(3n) and the first clock signal CK1.
  • the second node N The gate of the eighth thin film transistor T42 is connected to the fourth clock signal CK4, and the source and drain of the eighth thin film transistor T42 are respectively connected to the 3n-1 level horizontal scanning signal output terminal G (3n- 1) and the second node N.
  • the gate of the ninth thin film transistor T43 is connected to the third clock signal CK3, and the source and drain of the ninth thin film transistor T43 are respectively connected to the 3n-2th level horizontal scanning signal output terminal G (3n- 2) and the second node N.
  • the downstream unit 30 mainly uses the current-stage transmission signal output terminal Cout(n) as the input signal of the next-stage GOA unit and the feedback signal of the previous-stage GOA unit .
  • the download unit 30 includes a tenth thin film transistor T24, the gate of the tenth thin film transistor T24 is connected to the first node Q, and the source and drain of the tenth thin film transistor T24 are respectively connected to the first node Q.
  • the pull-down unit 40 is mainly responsible for pulling down the potential of the first node Q and the output signal to a low potential at the first time.
  • the pull-down unit 40 includes an eleventh thin film transistor T31, a twelfth thin film transistor T44, a thirteenth thin film transistor T32, and a fourteenth thin film transistor T33.
  • the gate of the eleventh thin film transistor T31 is connected to the upper stage signal output terminal Cout(n-1), and the source and drain of the eleventh thin film transistor T31 are respectively connected to the DC low voltage VGL and the current stage transmission signal output terminal Cout(n).
  • the gate of the twelfth thin film transistor T44 is connected to the upper stage signal output terminal Cout(n-1), and the source and drain of the twelfth thin film transistor T44 are respectively connected to the current stage The signal output terminal Cout(n) and the DC low voltage VGL are transmitted.
  • the gate of the thirteenth thin film transistor T32 is connected to the next stage signal output terminal Cout(n+1), and the source and drain of the thirteenth thin film transistor T33 are respectively connected to the second node N and the first node Q.
  • the gate of the fourteenth thin film transistor T33 is connected to the next-stage signal output terminal Cout(n+1), and the source and drain of the fourteenth thin film transistor T33 are respectively connected to the DC low voltage VGL and the second node N.
  • the pull-down maintaining unit 50 is mainly responsible for maintaining the potential of the first node Q in the off state.
  • the pull-down sustain unit 50 includes a fifteenth thin film transistor T45, a sixteenth thin film transistor T46, a seventeenth thin film transistor T51, an eighteenth thin film transistor T52, a nineteenth thin film transistor T53, and a twentieth thin film transistor T54.
  • the gate of the fifteenth thin film transistor T45 is connected to the third node QB, and the source and drain of the fifteenth thin film transistor T45 are respectively connected to the second node N and the first node Q.
  • the gate of the sixteenth thin film transistor T46 is connected to the third node QB, and the source and drain of the sixteenth thin film transistor T46 are connected to the DC low voltage VGL and the second node N, respectively.
  • the gate of the seventeenth thin film transistor T51 is connected to the second DC high voltage VGH, and the source and drain of the seventeenth thin film transistor T51 are respectively connected to the gate and the gate of the eighteenth thin film transistor T52.
  • the gate of the eighteenth thin film transistor T52 is connected to the source of the seventeenth thin film transistor T51, and the source and drain of the eighteenth thin film transistor T52 are respectively connected to the third node QB And the second DC high voltage VGH.
  • the gate of the nineteenth thin film transistor T53 is connected to the first node Q, and the source and drain of the nineteenth thin film transistor T53 are respectively connected to the direct current low voltage VGL and the eighteenth thin film transistor T52 Of the gate.
  • the gate of the twentieth thin film transistor T54 is connected to the first node Q, and the source and drain of the twentieth thin film transistor T54 are respectively connected to the DC low voltage VGL and the third node QB.
  • Both ends of the bootstrap capacitor Cbt are respectively connected to the first node Q and the current stage transmission signal output terminal Cout(n). , responsible for the second rise of the potential of the first node Q, which is beneficial to the output of the current stage transmission signal output terminal Cout(n).
  • the GOA circuit is a GOA circuit made based on IGZO material.
  • FIG. 3 a schematic diagram of the output waveform of the n-th GOA unit of the GOA circuit of an embodiment of the present disclosure.
  • T1 stage the previous-stage transmission signal output terminal Cout(n-1) and the first clock signal CK1 are high, the first thin film transistor T11 and the second thin film transistor T12 are turned on, and the potential of the first node Q is raised To a high potential, the nineteenth thin film transistor T53, the twentieth thin film transistor T54, the fourth thin film transistor T21, the fifth thin film transistor T22, the sixth thin film transistor T23, and the tenth thin film transistor T24 are turned on, and the third node QB Decreased to a low potential, the twelfth thin film transistor T44, the fifteenth thin film transistor T45, and the sixteenth thin film transistor T46 are turned off, and the eleventh thin film transistor T31 is turned on.
  • the current stage transmission signal output terminal Cout(n) is low Since the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4 are at low potential, the 3n-2 level horizontal scanning signal output terminal G(3n-2) and the 3n-1 level horizontal scanning signal output The terminal G (3n-1) and the 3n-th level horizontal scanning signal output terminal G (3n) are at low potential.
  • T2 stage the previous-stage transmission signal output terminal Cout(n-1) and the first clock signal CK1 drop to a low level, the first thin film transistor T11, the second thin film transistor T12, and the eleventh thin film transistor are turned off, and the first A node Q is at a high potential, the nineteenth thin film transistor T53, the twentieth thin film transistor T54, the fourth thin film transistor T21, the fifth thin film transistor T22, the sixth thin film transistor T23, and the tenth thin film transistor T24 maintain an open state, The third node QB maintains a low potential, and the current stage signal output terminal Cout(n) rises to a high potential.
  • the potential of the first node Q is coupled to a higher potential
  • the second clock signal CK2 is at a high potential
  • the first clock signal CK1, the third clock signal CK3, and the fourth clock signal CK4 are at a low potential
  • the seventh thin film transistor T41, the eighth thin film transistor T42, and the ninth thin film transistor T43 is closed. Therefore, at this time, the level 3n-2 horizontal scanning signal output terminal G (3n-2) is at a high potential, and at the same time, the third thin film transistor T6 is turned on, and the potential of the second node N is raised to a high potential, reducing the Leakage of the first node Q.
  • Stage T3 The first node Q maintains a high level.
  • the third clock signal CK3 is at a high level, and the first clock signal CK1, the second clock signal CK2, and the fourth clock signal CK4 fall to a low level.
  • the thin film transistor T43 is turned on, the level 3n-2 horizontal scanning signal output terminal G (3n-2) drops to a low level, the 3n-1 level horizontal scanning signal output terminal G (3n-1) rises to a high level, the 3n level
  • the horizontal scanning signal output terminal G(3n) maintains a low level.
  • Stage T4 The first node Q maintains a high level.
  • the fourth clock signal CK4 is at a high level, and the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 fall to a low level, so the eighth
  • the thin film transistor T42 is turned on, the horizontal scanning signal output terminal G(3n-1) of the 3n-1 level drops to a low level, the horizontal scanning signal output terminal G(3n) of the 3n level rises to a high level, and the level 3n-2 horizontal scanning The signal output terminal G (3n-2).
  • T5 stage the first clock signal rises to a high potential, the first thin film transistor T11 and the second thin film transistor T12 are turned on, and at the same time, the next stage signal output terminal Cout(n+1) rises to a high potential, the thirteenth film The transistor T32 and the fourteenth thin film transistor T33 are turned on. Since the signal output terminal Cout(n-1) of the previous stage is at a low potential, the potential of the first node Q is quickly pulled down to a low potential.
  • the transistor T53 and the twentieth thin film transistor T54 are turned off, the potential of the third node QB is raised to a high potential, the twelfth thin film transistor T44, the fifteenth thin film transistor T45 and the sixteenth thin film transistor T46 are turned on, and the current stage passes The signal output terminal Cout(n) is pulled down to a low signal.
  • the potential maintenance capability of the first node Q is an important factor that limits the output of wide pulse signals from the IGZO (Indium Gallium Zinc Oxide)-GOA circuit.
  • the embodiments of the present disclosure propose a GOA circuit, which can be applied to IGZO-GOA circuits as well as The demultiplexer (Demux) GOA circuit can effectively maintain the Q point potential and realize the wide pulse GOA signal output. It can be applied to liquid crystal display (LCD), and can also be applied to organic light emitting diode (OLED) display.
  • the GOA circuit of the embodiment of the present disclosure can effectively solve the problem of maintaining the potential of the first node Q, and can realize wide-pulse GOA signal output.
  • the first-level GOA circuit of the embodiment of the present disclosure can drive three row scan lines, which reduces the footprint of the GOA circuit, and only requires one set of CK signals, which further reduces the number of signal lines and the space occupied by the layout, which is conducive to narrow display screens. Bordering.
  • the display device 200 includes a panel 220 and a GOA circuit 240 on one side of the panel 220.
  • the GOA circuit 240 is the GOA circuit described in any of the above embodiments.
  • the display device 200 may be an LCD or OLED display.
  • the GOA circuit includes a plurality of GOA circuit units cascaded.
  • the nth level GOA unit responsible for outputting the nth level horizontal scan signal includes a pull-up unit, a pull-up control unit, a downstream unit, a pull-down unit, a pull-down sustain unit, and a bootstrap capacitor.
  • the pull-up unit is connected to the n-th level horizontal scanning signal output terminal and a set of clock signals.
  • the n-th level GOA unit can drive three row scan lines, can drive three row scan lines, and uses a set of clock signals. The number of thin film transistors required and the signal lines required are less, so that the GOA circuit is narrow. frame.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种GOA电路和显示装置，该GOA电路包括级联的多个GOA电路单元，负责输出第n级水平扫描信号的第n级GOA单元包括上拉单元（10）、上拉控制单元（20）、下传单元（30）、下拉单元（40）、下拉维持单元（50）以及自举电容（Cbt）。该上拉单元（10）连接第n级水平扫描信号输出端以及一组时钟信号（CK1，CK2，CK3，CK4）。该第n级GOA单元能够实现GOA电路窄边框。

Description

GOA电路和显示装置 技术领域
本揭示涉及显示技术领域，特别涉及一种GOA(gate driver on array)电路和显示装置。
背景技术
目前显示面板的水平扫描线的驱动是由外接集成电路(integrated circuit,IC)来实现的，外接集成电路可以控制各级行扫描线的逐级开启，而采用GOA(gate driver on array)技术，即阵列基板行驱动技术，可以将行扫描驱动电路集成在显示面板的基板上，能够减少外接集成电路的数量，从而降低了显示面板的生产成本，并且能够实现显示装置的窄边框化。IGZO(indium gallium zinc oxide)，即铟镓锌氧化物，具有高的迁移率和良好的器件稳定性，目前广泛的应用于显示面板，然而，IGZO-GOA电路设计较为复杂，薄膜晶体管(thin film transistor,TFT)的数量较多，不利于显示面板的窄边框化，与GOA电路的设计初衷不符。分用器(demultiplexer,Demux)GOA电路是一种能够实现GOA电路窄边框的方法，然而目前Demux GOA电路需要新增多组不同脉宽与幅值的时钟信号源，因此，尽管减少了GOA整体版图所占空间，但是极大增加了信号的数量，并且新增信号线也占用很大一部分空间。
故，有需要提供一种GOA电路和显示装置，以解决现有技术存在的问题。
技术问题
目前Demux GOA电路需要新增多组不同脉宽与幅值的时钟信号源，因此，尽管减少了GOA整体版图所占空间，但是极大增加了信号的数量，并且新增信号线也占用很大一部分空间。
技术解决方案
为解决上述技术问题，本揭示的一目的在于提供GOA(gate driver on array)电路和显示装置，能够驱动三条行扫描线，且使用一组时钟信号，所需的薄膜晶体管(thin film transistor,TFT)的数量较少和所需的信号线较少，实现GOA电路窄边框。
为达成上述目的，本揭示提供一GOA电路。所述GOA电路包括级联的多个GOA电路单元。设n为自然数。负责输出第n级水平扫描信号的第n级GOA单元包括上拉单元、上拉控制单元、下传单元、下拉单元、下拉维持单元以及自举电容。所述上拉单元连接第一节点、第二节点、直流低电压以及一组时钟信号。所述组时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号。所述上拉控制单元连接所述第一节点、所述第二节点、所述第一时钟信号、当前级级传信号输出端以及前一级级传信号输出端或启动脉冲触发信号。所述下传单元连接所述第一节点、所述当前级级传信号输出端以及第一直流高电压。所述下拉单元连接所述第一节点、所述第二节点、所述前一级级传信号输出端、下一级级传信号输出端以及所述直流低电压。所述下拉维持单元连接所述第一节点、所述第二节点、所述当前级级传信号输出端、所述第二直流高电压以及所述直流低电 压。所述自举电容的两端分别连接所述第一节点和所述当前级级传信号输出端。
于本揭示其中的一实施例中，所述组时钟信号的所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号是波形相同的交流信号。
于本揭示其中的一实施例中，所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管。所述第一薄膜晶体管的栅极连接所述第一时钟信号，所述第一薄膜晶体管的源极和漏极分别连接所述第二节点和所述前一级级传信号输出端或所述启动脉冲触发信号。所述第二薄膜晶体管的栅极连接所述第一时钟信号，所述第二薄膜晶体管的源极和漏极分别连接所述第一节点和所述第二节点。所述第三薄膜晶体管的栅极连接所述第一节点，所述第三薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述第二节点。
于本揭示其中的一实施例中，当n＝1时，所述第一薄膜晶体管的所述源极和所述漏极分别连接所述第二节点和所述启动脉冲触发信号。
于本揭示其中的一实施例中，所述上拉单元包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管和第九薄膜晶体管。所述第四薄膜晶体管的栅极连接所述第一节点，所述第四薄膜晶体管的源极和漏极分别连接所述第四时钟信号和第3n级水平扫描信号输出端。所述第五薄膜晶体管的栅极连接所述第一节点，所述第五薄膜晶体管的源极和漏极分别连接所述第三时 钟信号和第3n-1级水平扫描信号输出端。所述第六薄膜晶体管的栅极连接所述第一节点，所述第六薄膜晶体管的源极和漏极分别连接所述第二时钟信号和第3n-2级水平扫描信号输出端。所述第七薄膜晶体管的栅极连接所述第一时钟信号，所述第七薄膜晶体管的源极和漏极分别连接所述第3n级水平扫描信号输出端和所述第二节点。所述第八薄膜晶体管的栅极连接所述第四时钟信号，所述第八薄膜晶体管的源极和漏极分别连接所述第3n-1级水平扫描信号输出端和所述第二节点。所述第九薄膜晶体管的栅极连接所述第三时钟信号，所述第九薄膜晶体管的源极和漏极分别连接所述第3n-2级水平扫描信号输出端和所述第二节点。
于本揭示其中的一实施例中，所述下传单元包括第十薄膜晶体管，所述第十薄膜晶体管的栅极连接所述第一节点，所述第十薄膜晶体管的源极和漏极分别连接所述第一直流高电压和所述当前级级传信号输出端。
于本揭示其中的一实施例中，所述下拉单元包括第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管和第十四薄膜晶体管。所述第十一薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十一薄膜晶体管的源极和漏极分别连接所述直流低电压和所述当前级级传信号输出端。所述第十二薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十二薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述直流低电压。所述第十三薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十三薄膜晶体管的源极和 漏极分别连接所述第二节点和所述第一节点。所述第十四薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十四薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点。
于本揭示其中的一实施例中，所述下拉维持单元包括第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管、第十八薄膜晶体管、第十九薄膜晶体管和第二十薄膜晶体管。所述第十五薄膜晶体管的栅极连接第三节点，所述第十五薄膜晶体管的源极和漏极分别连接所述第二节点和所述第一节点。所述第十六薄膜晶体管的栅极连接所述第三节点，所述第十六薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点。所述第十七薄膜晶体管的栅极连接所述第二直流高电压，所述第十七薄膜晶体管的源极和漏极分别连接所述第十八薄膜晶体管的栅极和所述第二直流高电压。所述第十八薄膜晶体管的所述栅极连接所述第十七薄膜晶体管的所述源极，所述第十八薄膜晶体管的源极和漏极分别连接所述第三节点和所述第二直流高电压。所述第十九薄膜晶体管的栅极连接所述第一节点，所述第十九薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第十八薄膜晶体管的所述栅极。所述第二十薄膜晶体管的栅极连接所述第一节点，所述第二十薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第三节点。
于本揭示其中的一实施例中，所述GOA电路为基于IGZO材料制备的GOA电路。
本揭示还提供一显示装置包括GOA电路。所述GOA电路包括 级联的多个GOA电路单元。设n为自然数。负责输出第n级水平扫描信号的第n级GOA单元包括上拉单元、上拉控制单元、下传单元、下拉单元、下拉维持单元以及自举电容。所述上拉单元连接第一节点、第二节点、直流低电压以及一组时钟信号。所述组时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号。所述上拉控制单元连接所述第一节点、所述第二节点、所述第一时钟信号、当前级级传信号输出端以及前一级级传信号输出端或启动脉冲触发信号。所述下传单元连接所述第一节点、所述当前级级传信号输出端以及第一直流高电压。所述下拉单元连接所述第一节点、所述第二节点、所述前一级级传信号输出端、下一级级传信号输出端以及所述直流低电压。所述下拉维持单元连接所述第一节点、所述第二节点、所述当前级级传信号输出端、所述第二直流高电压以及所述直流低电压。所述自举电容的两端分别连接所述第一节点和所述当前级级传信号输出端。
于本揭示其中的一实施例中，所述组时钟信号的所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号是波形相同的交流信号。
于本揭示其中的一实施例中，所述上拉控制单元包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管。所述第一薄膜晶体管的栅极连接所述第一时钟信号，所述第一薄膜晶体管的源极和漏极分别连接所述第二节点和所述前一级级传信号输出端或所述启动脉冲触发信号。所述第二薄膜晶体管的栅极连接所述第一时钟信号，所述第二 薄膜晶体管的源极和漏极分别连接所述第一节点和所述第二节点。所述第三薄膜晶体管的栅极连接所述第一节点，所述第三薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述第二节点。
于本揭示其中的一实施例中，当n＝1时，所述第一薄膜晶体管的所述源极和所述漏极分别连接所述第二节点和所述启动脉冲触发信号。
于本揭示其中的一实施例中，所述上拉单元包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管和第九薄膜晶体管。所述第四薄膜晶体管的栅极连接所述第一节点，所述第四薄膜晶体管的源极和漏极分别连接所述第四时钟信号和第3n级水平扫描信号输出端。所述第五薄膜晶体管的栅极连接所述第一节点，所述第五薄膜晶体管的源极和漏极分别连接所述第三时钟信号和第3n-1级水平扫描信号输出端。所述第六薄膜晶体管的栅极连接所述第一节点，所述第六薄膜晶体管的源极和漏极分别连接所述第二时钟信号和第3n-2级水平扫描信号输出端。所述第七薄膜晶体管的栅极连接所述第一时钟信号，所述第七薄膜晶体管的源极和漏极分别连接所述第3n级水平扫描信号输出端和所述第二节点。所述第八薄膜晶体管的栅极连接所述第四时钟信号，所述第八薄膜晶体管的源极和漏极分别连接所述第3n-1级水平扫描信号输出端和所述第二节点。所述第九薄膜晶体管的栅极连接所述第三时钟信号，所述第九薄膜晶体管的源极和漏极分别连接所述第3n-2级水平扫描信号输出端和所述第二节点。
于本揭示其中的一实施例中，所述下传单元包括第十薄膜晶体管，所述第十薄膜晶体管的栅极连接所述第一节点，所述第十薄膜晶体管的源极和漏极分别连接所述第一直流高电压和所述当前级级传信号输出端。
于本揭示其中的一实施例中，所述下拉单元包括第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管和第十四薄膜晶体管。所述第十一薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十一薄膜晶体管的源极和漏极分别连接所述直流低电压和所述当前级级传信号输出端。所述第十二薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十二薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述直流低电压。所述第十三薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十三薄膜晶体管的源极和漏极分别连接所述第二节点和所述第一节点。所述第十四薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十四薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点。
于本揭示其中的一实施例中，所述下拉维持单元包括第十五薄膜晶体管、第十六薄膜晶体管、第十七薄膜晶体管、第十八薄膜晶体管、第十九薄膜晶体管和第二十薄膜晶体管。所述第十五薄膜晶体管的栅极连接第三节点，所述第十五薄膜晶体管的源极和漏极分别连接所述第二节点和所述第一节点。所述第十六薄膜晶体管的栅极连接所述第三节点，所述第十六薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点。所述第十七薄膜晶体管的栅极连接所述第二直流 高电压，所述第十七薄膜晶体管的源极和漏极分别连接所述第十八薄膜晶体管的栅极和所述第二直流高电压。所述第十八薄膜晶体管的所述栅极连接所述第十七薄膜晶体管的所述源极，所述第十八薄膜晶体管的源极和漏极分别连接所述第三节点和所述第二直流高电压。所述第十九薄膜晶体管的栅极连接所述第一节点，所述第十九薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第十八薄膜晶体管的所述栅极。所述第二十薄膜晶体管的栅极连接所述第一节点，所述第二十薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第三节点。
于本揭示其中的一实施例中，所述GOA电路为基于IGZO材料制备的GOA电路。
有益效果
相较于现有技术，为解决上述技术问题，由于本揭示的实施例的所述GOA电路和所述显示装置中，GOA电路包括级联的多个GOA电路单元。负责输出第n级水平扫描信号的第n级GOA单元包括上拉单元、上拉控制单元、下传单元、下拉单元、下拉维持单元以及自举电容。所述上拉单元连接第n级水平扫描信号输出端以及一组时钟信号。所述第n级GOA单元能够驱动三条行扫描线，能够驱动三条行扫描线，且使用一组时钟信号，所需的薄膜晶体管的数量较少和所需的信号线较少，实现GOA电路窄边框。
附图说明
图1显示根据本揭示的一实施例的GOA电路的结构示意图；
图2显示根据本揭示的一实施例的GOA电路的输入源信号波形示意图；
图3显示根据本揭示的一实施例的GOA电路的第n级GOA单元的输出波形示意图；以及
图4显示根据本揭示的一实施例的显示装置的示意图。
本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1及图2,本揭示的一实施例的GOA电路包括二十个薄膜晶体管(thin film transistor,TFT)和一个电容Cbt，电路之间的连接关系如图1所示。VGH、VGHH和VGL是直流电源(direct current(DC)power supply)，STV是启动脉冲(start pulse)触发信号，为启动第一级GOA单元所需。GOA电路中各信号具体的波形与电位关系可以如下表1所示。节点N、Q、QB、Cout(n-l)、Cout(n)、Cout(n+I)、G(3n-2)、G(3n-1)、G(3n)等是电路中重要的节点。CK1、CK2，CK3，CK4为 一组交流讯号，Cout(n-1)连接前一级的Cout(n)输出信号，Cout(n+1)连接下一级的Cout输出信号。GOA电路第一级的T11的Cout(n-1)与STV信号相连。
表1
Figure PCTCN2019106293-appb-000001
应用本揭示的一实施例的面板的其他参数可以设置如下：对于例如全高清(full high definition,FHD)分辨率，行扫描线数量为1080，时钟信号数量(CK number)为4个(CK1、CK2、CK3和CK4)，时钟周期(CK period)为60毫秒，CK占空比(duty cycle)为25％，STV数量为1个。
本揭示的一实施例提供一GOA电路。所述GOA电路包括级联的多个GOA电路单元。设n为自然数。负责输出第n级水平扫描信号的第n级GOA单元包括上拉单元10、上拉控制单元20、下传单元30、下拉单元40、下拉维持单元50以及自举电容Cbt。
所述上拉单元10连接第一节点Q、第二节点N、直流低电压VGL 以及一组时钟信号。所述组时钟信号包括第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4。所述上拉控制单元20连接所述第一节点Q、所述第二节点N、所述第一时钟信号CK1、当前级级传信号输出端Cout(n)以及前一级级传信号输出端Cout(n-1)或启动脉冲触发信号STV。所述下传单元30连接所述第一节点Q、所述当前级级传信号输出端Cout(n)以及第一直流高电压VGHH。
所述下拉单元40连接所述第一节点Q、所述第二节点N、所述前一级级传信号输出端Cout(n-1)、下一级级传信号输出端Cout(n+1)以及所述直流低电压VGL。所述下拉维持单元50连接所述第一节点Q、所述第二节点N、所述当前级级传信号输出端Cout(n)、所述第二直流高电压VGH以及所述直流低电压VGL。所述自举电容Cbt的两端分别连接所述第一节点Q和所述当前级级传信号输出端Cout(n)。
于本揭示其中的一实施例中，所述组时钟信号的所述第一时钟信号CK1、所述第二时钟信号CK2、所述第三时钟信号CK3和所述第四时钟信号CK4是波形相同的交流信号。
于本揭示其中的一实施例中，所述上拉控制单元主要是拉升所述第一节点Q的电位并控制所述上拉单元10的打开时间。所述上拉控制单元20包括第一薄膜晶体管T11、第二薄膜晶体管T12和第三薄膜晶体管T6。所述第一薄膜晶体管T11的栅极连接所述第一时钟信号CK1，所述第一薄膜晶体管T11的源极和漏极分别连接所述第二节点N和所述前一级级传信号输出端Cout(n-1)或所述启动脉冲触发信号STV。所 述第二薄膜晶体管T12的栅极连接所述第一时钟信号CK1，所述第二薄膜晶体管T12的源极和漏极分别连接所述第一节点Q和所述第二节点N。所述第三薄膜晶体管T6的栅极连接所述第一节点Q，所述第三薄膜晶体管T6的源极和漏极分别连接所述当前级级传信号输出端Cout(n)和所述第二节点N。
于本揭示其中的一实施例中，当n＝1时，所述第一薄膜晶体管T11的所述源极和所述漏极分别连接所述第二节点N和所述启动脉冲触发信号STV。
于本揭示其中的一实施例中，所述上拉单元10主要负责将时钟信号转变为输出信号。所述上拉单元10包括第四薄膜晶体管T21、第五薄膜晶体管T22、第六薄膜晶体管T23、第七薄膜晶体管T41、第八薄膜晶体管T42和第九薄膜晶体管T43。所述第四薄膜晶体管T21的栅极连接所述第一节点Q，所述第四薄膜晶体管T21的源极和漏极分别连接所述第四时钟信号CK4和第3n级水平扫描信号输出端G(3n)。所述第四薄膜晶体管T21负责将所述第四时钟信号CK4转变为输出信号，即所述第3n级水平扫描信号输出端G(3n)。
所述第五薄膜晶体管T22的栅极连接所述第一节点Q，所述第五薄膜晶体管T22的源极和漏极分别连接所述第三时钟信号CK3和第3n-1级水平扫描信号输出端G(3n-1)。所述第五薄膜晶体管T22负责将所述第三时钟信号CK3转变为输出信号，即所述第3n-1级水平扫描信号输出端G(3n-1)。所述第六薄膜晶体管T23的栅极连接所述第一节点Q，所述第六薄膜晶体管T23的源极和漏极分别连接所述第二时钟信 号CK2和第3n-2级水平扫描信号输出端G(3n-2)。所述第六薄膜晶体管T23负责将所述第二时钟信号CK2转变为输出信号，即所述第3n-2级水平扫描信号输出端G(3n-2)。
所述第七薄膜晶体管T41的栅极连接所述第一时钟信号CK1，所述第七薄膜晶体管T41的源极和漏极分别连接所述第3n级水平扫描信号输出端G(3n)和所述第二节点N。所述第八薄膜晶体管T42的栅极连接所述第四时钟信号CK4，所述第八薄膜晶体管T42的源极和漏极分别连接所述第3n-1级水平扫描信号输出端G(3n-1)和所述第二节点N。所述第九薄膜晶体管T43的栅极连接所述第三时钟信号CK3，所述第九薄膜晶体管T43的源极和漏极分别连接所述第3n-2级水平扫描信号输出端G(3n-2)和所述第二节点N。
于本揭示其中的一实施例中，所述下传单元30主要是将所述当前级级传信号输出端Cout(n)作为下一级GOA单元的输入信号以及上一级GOA单元的反馈信号。所述下传单元30包括第十薄膜晶体管T24，所述第十薄膜晶体管T24的栅极连接所述第一节点Q，所述第十薄膜晶体管T24的源极和漏极分别连接所述第一直流高电压VGHH和所述当前级级传信号输出端Cout(n)。
于本揭示其中的一实施例中，所述下拉单元40主要是负责在第一时间将所述第一节点Q的电位与输出信号拉低为低电位。所述下拉单元40包括第十一薄膜晶体管T31、第十二薄膜晶体管T44、第十三薄膜晶体管T32和第十四薄膜晶体管T33。所述第十一薄膜晶体管T31的栅极连接所述上一级级传信号输出端Cout(n-1)，所述第十一薄膜晶体 管T31的源极和漏极分别连接所述直流低电压VGL和所述当前级级传信号输出端Cout(n)。所述第十二薄膜晶体管T44的栅极连接所述上一级级传信号输出端Cout(n-1)，所述第十二薄膜晶体管T44的源极和漏极分别连接所述当前级级传信号输出端Cout(n)和所述直流低电压VGL。
所述第十三薄膜晶体管T32的栅极连接所述下一级级传信号输出端Cout(n+1)，所述第十三薄膜晶体管T33的源极和漏极分别连接所述第二节点N和所述第一节点Q。所述第十四薄膜晶体管T33的栅极连接所述下一级级传信号输出端Cout(n+1)，所述第十四薄膜晶体管T33的源极和漏极分别连接所述直流低电压VGL和所述第二节点N。
于本揭示其中的一实施例中，所述下拉维持单元50主要是负责将所述第一节点Q的电位维持在关闭状态。所述下拉维持单元50包括第十五薄膜晶体管T45、第十六薄膜晶体管T46、第十七薄膜晶体管T51、第十八薄膜晶体管T52、第十九薄膜晶体管T53和第二十薄膜晶体管T54。所述第十五薄膜晶体管T45的栅极连接第三节点QB，所述第十五薄膜晶体管T45的源极和漏极分别连接所述第二节点N和所述第一节点Q。所述第十六薄膜晶体管T46的栅极连接所述第三节点QB，所述第十六薄膜晶体管T46的源极和漏极分别连接所述直流低电压VGL和所述第二节点N。
所述第十七薄膜晶体管T51的栅极连接所述第二直流高电压VGH，所述第十七薄膜晶体管T51的源极和漏极分别连接所述第十八薄膜晶体管T52的栅极和所述第二直流高电压VGH。所述第十八薄膜 晶体管T52的所述栅极连接所述第十七薄膜晶体管T51的所述源极，所述第十八薄膜晶体管T52的源极和漏极分别连接所述第三节点QB和所述第二直流高电压VGH。
所述第十九薄膜晶体管T53的栅极连接所述第一节点Q，所述第十九薄膜晶体管T53的源极和漏极分别连接所述直流低电压VGL和所述第十八薄膜晶体管T52的所述栅极。所述第二十薄膜晶体管T54的栅极连接所述第一节点Q，所述第二十薄膜晶体管T54的源极和漏极分别连接所述直流低电压VGL和所述第三节点QB。
所述自举电容Cbt的两端分别连接所述第一节点Q和所述当前级级传信号输出端Cout(n)。，负责所述第一节点Q的电位的二次抬升，这有利于所述当前级级传信号输出端Cout(n)的输出。
于本揭示其中的一实施例中，所述GOA电路为基于IGZO材料制备的GOA电路。
参照图3,本揭示的一实施例的GOA电路的第n级GOA单元的输出波形示意图，通过将图2所示的波形带入本揭示的一实施例的GOA电路，得到了非常好的信号输出。并且下面以单级GOA电路为例，说明电路的工作过程。
T1阶段：前一级级传信号输出端Cout(n-1)与第一时钟信号CK1为高电位，第一薄膜晶体管T11与第二薄膜晶体管T12打开，所述第一节点Q的电位被抬升至高电位，第十九薄膜晶体管T53、第二十薄膜晶体管T54、第四薄膜晶体管T21、第五薄膜晶体管T22、第六薄膜晶体管T23及所述第十薄膜晶体管T24打开，所述第三节点QB降为低 电位，第十二薄膜晶体管T44、第十五薄膜晶体管T45和第十六薄膜晶体管T46关闭，第十一薄膜晶体管T31打开，因此，当前级级传信号输出端Cout(n)为低电位，由于第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4为低电位，第3n-2级水平扫描信号输出端G(3n-2)、第3n-1级水平扫描信号输出端G(3n-1)及第3n级水平扫描信号输出端G(3n)为低电位。
T2阶段：前一级级传信号输出端Cout(n-1)与第一时钟信号CK1降为低电位，第一薄膜晶体管T11、第二薄膜晶体管T12与第十一薄膜晶体管关闭，所述第一节点Q为高电位，第十九薄膜晶体管T53、第二十薄膜晶体管T54、第四薄膜晶体管T21、第五薄膜晶体管T22、第六薄膜晶体管T23及所述第十薄膜晶体管T24维持打开状态，所述第三节点QB保持低电位，当前级级传信号输出端Cout(n)升为高电位，由于存储电容Cbt的存在，所述第一节点Q的电位被耦合(couple)至更高电位，此时，第二时钟信号CK2为高电位，第一时钟信号CK1、第三时钟信号CK3和第四时钟信号CK4为低电位，第七薄膜晶体管T41、第八薄膜晶体管T42和第九薄膜晶体管T43关闭。因此，此时第3n-2级水平扫描信号输出端G(3n-2)为高电位，同时，第三薄膜晶体管T6打开，所述第二节点N电位的被抬升至高电位，减少了所述第一节点Q的漏电。
T3阶段：所述第一节点Q维持高电位，此时，第三时钟信号CK3为高电位，第一时钟信号CK1、第二时钟信号CK2和第四时钟信号CK4降为低电位，因此第九薄膜晶体管T43打开，第3n-2级水平扫描 信号输出端G(3n-2)降为低电位，第3n-1级水平扫描信号输出端G(3n-1)升为高电位，第3n级水平扫描信号输出端G(3n)维持低电位。
T4阶段：所述第一节点Q维持高电位，此时，第四时钟信号CK4为高电位，第一时钟信号CK1、第二时钟信号CK2和第三时钟信号CK3降为低电位，因此第八薄膜晶体管T42打开，第3n-1级水平扫描信号输出端G(3n-1)降为低电位，第3n级水平扫描信号输出端G(3n)升为高电位，第3n-2级水平扫描信号输出端G(3n-2)。
T5阶段：第一时钟信号升为高电位，第一薄膜晶体管T11和第二薄膜晶体管T12打开，同时，下一级级传信号输出端Cout(n+1)升为高电位，第十三薄膜晶体管T32和第十四薄膜晶体管T33打开，由于前一级级传信号输出端Cout(n-1)为低电位，所述第一节点Q的电位被迅速拉低至低电位，第十九薄膜晶体管T53和第二十薄膜晶体管T54关闭，所述第三节点QB的电位被抬升至高电位，第十二薄膜晶体管T44、第十五薄膜晶体管T45和第十六薄膜晶体管T46打开，当前级级传信号输出端Cout(n)被拉低至低信号。
第一节点Q的电位维持能力是限制IGZO(铟镓锌氧化物)-GOA电路输出宽脉冲信号的重要因素，本揭示的实施例提出了GOA电路，可应用于IGZO-GOA电路，也可以应用于分用器(demultiplexer,Demux)GOA电路可以有效的维持Q点电位，实现宽脉冲GOA信号输出。可运用于液晶显示器(liquid crystal display,LCD)，也可以运用于有机发光二极管(organic light emitting diode,OLED)显示器。综上，本揭示的实施例的GOA电路可以有效的解决第一节点Q的电位维持问 题，能够实现宽脉冲GOA信号输出。本揭示的实施例的一级GOA电路能够驱动三条行扫描线，减少了GOA电路的版图占用空间，并且只需要一组CK讯号，进一步减少信号线数量及版图所占空间，有利于显示屏窄边框化。
参照图4，在一实施例中，显示装置200包括面板220和位于面板220一侧的GOA电路240。GOA电路240为上述任一实施例所述的GOA电路。显示装置200可以是LCD或OLED显示器。
由于本揭示的实施例的所述GOA电路和所述显示装置中，GOA电路包括级联的多个GOA电路单元。负责输出第n级水平扫描信号的第n级GOA单元包括上拉单元、上拉控制单元、下传单元、下拉单元、下拉维持单元以及自举电容。所述上拉单元连接第n级水平扫描信号输出端以及一组时钟信号。所述第n级GOA单元能够驱动三条行扫描线，能够驱动三条行扫描线，且使用一组时钟信号，所需的薄膜晶体管的数量较少和所需的信号线较少，实现GOA电路窄边框。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示)，即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个 被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (18)

  1. 一种GOA电路，包括多个级联的GOA单元，设n为自然数，负责输出第n级水平扫描信号的第n级GOA单元包括：
    上拉单元，所述上拉单元连接第一节点、第二节点、直流低电压以及一组时钟信号，所述组时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；
    上拉控制单元，所述上拉控制单元连接所述第一节点、所述第二节点、所述第一时钟信号、当前级级传信号输出端以及前一级级传信号输出端或启动脉冲触发信号；
    下传单元，所述下传单元连接所述第一节点、所述当前级级传信号输出端以及第一直流高电压；
    下拉单元，所述下拉单元连接所述第一节点、所述第二节点、所述前一级级传信号输出端、下一级级传信号输出端以及所述直流低电压；
    下拉维持单元，所述下拉维持单元连接所述第一节点、所述第二节点、所述当前级级传信号输出端、第二直流高电压以及所述直流低电压；以及
    自举电容，所述自举电容的两端分别连接所述第一节点和所述当前级级传信号输出端。
  2. 如权利要求1所述的GOA电路，其中所述组时钟信号的所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时 钟信号是波形相同的交流信号。
  3. 如权利要求1所述的GOA电路，其中所述上拉控制单元包括：
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接所述第一时钟信号，所述第一薄膜晶体管的源极和漏极分别连接所述第二节点和所述前一级级传信号输出端或所述启动脉冲触发信号；
    第二薄膜晶体管，所述第二薄膜晶体管的栅极连接所述第一时钟信号，所述第二薄膜晶体管的源极和漏极分别连接所述第一节点和所述第二节点；以及
    第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述第一节点，所述第三薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述第二节点。
  4. 如权利要求3所述的GOA电路，其中当n＝1时，所述第一薄膜晶体管的所述源极和所述漏极分别连接所述第二节点和所述启动脉冲触发信号。
  5. 如权利要求1所述的GOA电路，其中所述上拉单元包括：
    第四薄膜晶体管，所述第四薄膜晶体管的栅极连接所述第一节点，所述第四薄膜晶体管的源极和漏极分别连接所述第四时钟信号和第3n级水平扫描信号输出端；
    第五薄膜晶体管，所述第五薄膜晶体管的栅极连接所述第一节点，所述第五薄膜晶体管的源极和漏极分别连接所述第三时钟信号和第3n-1级水平扫描信号输出端；
    第六薄膜晶体管，所述第六薄膜晶体管的栅极连接所述第一节 点，所述第六薄膜晶体管的源极和漏极分别连接所述第二时钟信号和第3n-2级水平扫描信号输出端；
    第七薄膜晶体管，所述第七薄膜晶体管的栅极连接所述第一时钟信号，所述第七薄膜晶体管的源极和漏极分别连接所述第3n级水平扫描信号输出端和所述第二节点；
    第八薄膜晶体管，所述第八薄膜晶体管的栅极连接所述第四时钟信号，所述第八薄膜晶体管的源极和漏极分别连接所述第3n-1级水平扫描信号输出端和所述第二节点；以及
    第九薄膜晶体管，所述第九薄膜晶体管的栅极连接所述第三时钟信号，所述第九薄膜晶体管的源极和漏极分别连接所述第3n-2级水平扫描信号输出端和所述第二节点。
  6. 如权利要求1所述的GOA电路，其中所述下传单元包括第十薄膜晶体管，所述第十薄膜晶体管的栅极连接所述第一节点，所述第十薄膜晶体管的源极和漏极分别连接所述第一直流高电压和所述当前级级传信号输出端。
  7. 根据权利要求1所述的GOA电路，其中所述下拉单元包括：
    第十一薄膜晶体管，所述第十一薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十一薄膜晶体管的源极和漏极分别连接所述直流低电压和所述当前级级传信号输出端；
    第十二薄膜晶体管，所述第十二薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十二薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述直流低电压；
    第十三薄膜晶体管，所述第十三薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十三薄膜晶体管的源极和漏极分别连接所述第二节点和所述第一节点；以及
    第十四薄膜晶体管，所述第十四薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十四薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点。
  8. 根据权利要求1所述的GOA电路，其中所述下拉维持单元包括：
    第十五薄膜晶体管，所述第十五薄膜晶体管的栅极连接第三节点，所述第十五薄膜晶体管的源极和漏极分别连接所述第二节点和所述第一节点；
    第十六薄膜晶体管，所述第十六薄膜晶体管的栅极连接所述第三节点，所述第十六薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点；
    第十七薄膜晶体管，所述第十七薄膜晶体管的栅极连接所述第二直流高电压，所述第十七薄膜晶体管的源极和漏极分别连接第十八薄膜晶体管的栅极和所述第二直流高电压；
    所述第十八薄膜晶体管，所述第十八薄膜晶体管的所述栅极连接所述第十七薄膜晶体管的所述源极，所述第十八薄膜晶体管的源极和漏极分别连接所述第三节点和所述第二直流高电压；
    第十九薄膜晶体管，所述第十九薄膜晶体管的栅极连接所述第一节点，所述第十九薄膜晶体管的源极和漏极分别连接所述直流低电 压和所述第十八薄膜晶体管的所述栅极；以及
    第二十薄膜晶体管，所述第二十薄膜晶体管的栅极连接所述第一节点，所述第二十薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第三节点。
  9. 根据权利要求1所述的GOA电路，其中所述GOA电路为基于IGZO材料制备的GOA电路。
  10. 一种显示装置，包括：
    GOA电路，包括多个级联的GOA单元，设n为自然数，负责输出第n级水平扫描信号的第n级GOA单元包括：
    上拉单元，所述上拉单元连接第一节点、第二节点、直流低电压以及一组时钟信号，所述组时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；
    上拉控制单元，所述上拉控制单元连接所述第一节点、所述第二节点、所述第一时钟信号、当前级级传信号输出端以及前一级级传信号输出端或启动脉冲触发信号；
    下传单元，所述下传单元连接所述第一节点、所述当前级级传信号输出端以及第一直流高电压；
    下拉单元，所述下拉单元连接所述第一节点、所述第二节点、所述前一级级传信号输出端、下一级级传信号输出端以及所述直流低电压；
    下拉维持单元，所述下拉维持单元连接所述第一节点、所述第二节点、所述当前级级传信号输出端、第二直流高电压以及所述直流 低电压；以及
    自举电容，所述自举电容的两端分别连接所述第一节点和所述当前级级传信号输出端。
  11. 如权利要求10所述的显示装置，其中所述组时钟信号的所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号是波形相同的交流信号。
  12. 如权利要求10所述的显示装置，其中所述上拉控制单元包括：
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接所述第一时钟信号，所述第一薄膜晶体管的源极和漏极分别连接所述第二节点和所述前一级级传信号输出端或所述启动脉冲触发信号；
    第二薄膜晶体管，所述第二薄膜晶体管的栅极连接所述第一时钟信号，所述第二薄膜晶体管的源极和漏极分别连接所述第一节点和所述第二节点；以及
    第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述第一节点，所述第三薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述第二节点。
  13. 如权利要求12所述的显示装置，其中当n＝1时，所述第一薄膜晶体管的所述源极和所述漏极分别连接所述第二节点和所述启动脉冲触发信号。
  14. 如权利要求10所述的显示装置，其中所述上拉单元包括：
    第四薄膜晶体管，所述第四薄膜晶体管的栅极连接所述第一节 点，所述第四薄膜晶体管的源极和漏极分别连接所述第四时钟信号和第3n级水平扫描信号输出端；
    第五薄膜晶体管，所述第五薄膜晶体管的栅极连接所述第一节点，所述第五薄膜晶体管的源极和漏极分别连接所述第三时钟信号和第3n-1级水平扫描信号输出端；
    第六薄膜晶体管，所述第六薄膜晶体管的栅极连接所述第一节点，所述第六薄膜晶体管的源极和漏极分别连接所述第二时钟信号和第3n-2级水平扫描信号输出端；
    第七薄膜晶体管，所述第七薄膜晶体管的栅极连接所述第一时钟信号，所述第七薄膜晶体管的源极和漏极分别连接所述第3n级水平扫描信号输出端和所述第二节点；
    第八薄膜晶体管，所述第八薄膜晶体管的栅极连接所述第四时钟信号，所述第八薄膜晶体管的源极和漏极分别连接所述第3n-1级水平扫描信号输出端和所述第二节点；以及
    第九薄膜晶体管，所述第九薄膜晶体管的栅极连接所述第三时钟信号，所述第九薄膜晶体管的源极和漏极分别连接所述第3n-2级水平扫描信号输出端和所述第二节点。
  15. 如权利要求10所述的显示装置，其中所述下传单元包括第十薄膜晶体管，所述第十薄膜晶体管的栅极连接所述第一节点，所述第十薄膜晶体管的源极和漏极分别连接所述第一直流高电压和所述当前级级传信号输出端。
  16. 根据权利要求10所述的显示装置，其中所述下拉单元包括：
    第十一薄膜晶体管，所述第十一薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十一薄膜晶体管的源极和漏极分别连接所述直流低电压和所述当前级级传信号输出端；
    第十二薄膜晶体管，所述第十二薄膜晶体管的栅极连接所述上一级级传信号输出端，所述第十二薄膜晶体管的源极和漏极分别连接所述当前级级传信号输出端和所述直流低电压；
    第十三薄膜晶体管，所述第十三薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十三薄膜晶体管的源极和漏极分别连接所述第二节点和所述第一节点；以及
    第十四薄膜晶体管，所述第十四薄膜晶体管的栅极连接所述下一级级传信号输出端，所述第十四薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点。
  17. 根据权利要求10所述的显示装置，其中所述下拉维持单元包括：
    第十五薄膜晶体管，所述第十五薄膜晶体管的栅极连接第三节点，所述第十五薄膜晶体管的源极和漏极分别连接所述第二节点和所述第一节点；
    第十六薄膜晶体管，所述第十六薄膜晶体管的栅极连接所述第三节点，所述第十六薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第二节点；
    第十七薄膜晶体管，所述第十七薄膜晶体管的栅极连接所述第二直流高电压，所述第十七薄膜晶体管的源极和漏极分别连接第十八 薄膜晶体管的栅极和所述第二直流高电压；
    所述第十八薄膜晶体管，所述第十八薄膜晶体管的所述栅极连接所述第十七薄膜晶体管的所述源极，所述第十八薄膜晶体管的源极和漏极分别连接所述第三节点和所述第二直流高电压；
    第十九薄膜晶体管，所述第十九薄膜晶体管的栅极连接所述第一节点，所述第十九薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第十八薄膜晶体管的所述栅极；以及
    第二十薄膜晶体管，所述第二十薄膜晶体管的栅极连接所述第一节点，所述第二十薄膜晶体管的源极和漏极分别连接所述直流低电压和所述第三节点。
  18. 根据权利要求10所述的显示装置，其中所述GOA电路为基于IGZO材料制备的GOA电路。
PCT/CN2019/106293 2019-05-05 2019-09-18 Goa电路和显示装置 WO2020224154A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910366056.1 2019-05-05
CN201910366056.1A CN109961737A (zh) 2019-05-05 2019-05-05 Goa电路和显示装置

Publications (1)

Publication Number Publication Date
WO2020224154A1 true WO2020224154A1 (zh) 2020-11-12

Family

ID=67027030

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/106293 WO2020224154A1 (zh) 2019-05-05 2019-09-18 Goa电路和显示装置

Country Status (2)

Country Link
CN (1) CN109961737A (zh)
WO (1) WO2020224154A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109961737A (zh) * 2019-05-05 2019-07-02 深圳市华星光电半导体显示技术有限公司 Goa电路和显示装置
CN110299112B (zh) * 2019-07-18 2020-09-01 深圳市华星光电半导体显示技术有限公司 Goa电路
CN110379349B (zh) * 2019-07-22 2020-10-16 深圳市华星光电半导体显示技术有限公司 栅极驱动电路
CN110675828A (zh) 2019-09-10 2020-01-10 深圳市华星光电半导体显示技术有限公司 Goa电路
CN110969977A (zh) * 2019-12-02 2020-04-07 深圳市华星光电半导体显示技术有限公司 一种栅极驱动电路、其控制方法及显示装置
CN111223433B (zh) 2020-01-19 2021-01-15 深圳市华星光电半导体显示技术有限公司 一种goa电路和显示装置
CN111223452B (zh) 2020-03-18 2021-07-23 深圳市华星光电半导体显示技术有限公司 Goa电路
CN111477155A (zh) 2020-05-13 2020-07-31 武汉华星光电技术有限公司 驱动电路及显示面板
CN111986624B (zh) * 2020-08-04 2022-02-08 邵阳学院 一种低振荡的goa电路
CN112017584B (zh) * 2020-09-10 2022-07-12 武汉华星光电技术有限公司 移位寄存器单元、栅极驱动电路及显示面板
CN112053655B (zh) * 2020-10-10 2022-07-12 武汉华星光电技术有限公司 Goa电路及显示面板
CN112509511B (zh) * 2020-12-08 2022-07-12 深圳市华星光电半导体显示技术有限公司 显示装置
CN114743482B (zh) * 2022-03-28 2024-06-11 Tcl华星光电技术有限公司 基于goa的显示面板
CN114783337A (zh) * 2022-03-31 2022-07-22 Tcl华星光电技术有限公司 Goa电路以及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102109696A (zh) * 2010-12-30 2011-06-29 友达光电股份有限公司 液晶显示装置
CN105139816A (zh) * 2015-09-24 2015-12-09 深圳市华星光电技术有限公司 栅极驱动电路
CN105304044A (zh) * 2015-11-16 2016-02-03 深圳市华星光电技术有限公司 液晶显示设备及goa电路
US20160343335A1 (en) * 2014-12-31 2016-11-24 Shenzhen China Star Optoelectronics Technology Co. Ltd. Goa circuit and liquid crystal display device
CN107393473A (zh) * 2017-08-25 2017-11-24 深圳市华星光电半导体显示技术有限公司 Goa电路
CN109003588A (zh) * 2018-08-06 2018-12-14 深圳市华星光电半导体显示技术有限公司 液晶显示装置
CN109961737A (zh) * 2019-05-05 2019-07-02 深圳市华星光电半导体显示技术有限公司 Goa电路和显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9858880B2 (en) * 2015-06-01 2018-01-02 Shenzhen China Star Optoelectronics Technology Co., Ltd. GOA circuit based on oxide semiconductor thin film transistor
CN107705739B (zh) * 2017-07-11 2019-11-26 深圳市华星光电半导体显示技术有限公司 扫描驱动电路及显示装置
CN107154245B (zh) * 2017-07-17 2019-06-25 深圳市华星光电技术有限公司 一种栅极驱动电路及其驱动方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102109696A (zh) * 2010-12-30 2011-06-29 友达光电股份有限公司 液晶显示装置
US20160343335A1 (en) * 2014-12-31 2016-11-24 Shenzhen China Star Optoelectronics Technology Co. Ltd. Goa circuit and liquid crystal display device
CN105139816A (zh) * 2015-09-24 2015-12-09 深圳市华星光电技术有限公司 栅极驱动电路
CN105304044A (zh) * 2015-11-16 2016-02-03 深圳市华星光电技术有限公司 液晶显示设备及goa电路
CN107393473A (zh) * 2017-08-25 2017-11-24 深圳市华星光电半导体显示技术有限公司 Goa电路
CN109003588A (zh) * 2018-08-06 2018-12-14 深圳市华星光电半导体显示技术有限公司 液晶显示装置
CN109961737A (zh) * 2019-05-05 2019-07-02 深圳市华星光电半导体显示技术有限公司 Goa电路和显示装置

Also Published As

Publication number Publication date
CN109961737A (zh) 2019-07-02

Similar Documents

Publication Publication Date Title
WO2020224154A1 (zh) Goa电路和显示装置
CN111223433B (zh) 一种goa电路和显示装置
CN110299112B (zh) Goa电路
CN107909971B (zh) Goa电路
WO2019210830A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2019037299A1 (zh) Goa电路
WO2018120330A1 (zh) 栅极驱动电路以及液晶显示装置
WO2021203508A1 (zh) Goa电路、显示面板
WO2017096658A1 (zh) 基于ltps半导体薄膜晶体管的goa电路
WO2019080626A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN107689221B (zh) Goa电路
WO2019090875A1 (zh) Goa电路
US20180211626A1 (en) Driving methods and driving devices of gate driver on array (goa) circuit
WO2017096704A1 (zh) 基于ltps半导体薄膜晶体管的goa电路
US11107381B2 (en) Shift register and method for driving the same, gate driving circuit and display device
WO2020151128A1 (zh) Goa电路及显示装置
WO2019179521A1 (zh) 移位寄存器电路及驱动方法、栅极驱动电路、显示装置
WO2020224240A1 (zh) 一种goa电路、显示面板及显示装置
US11355067B2 (en) Array substrate
WO2020224133A1 (zh) 一种goa电路、显示面板及显示装置
WO2021012313A1 (zh) 栅极驱动电路
WO2020220480A1 (zh) Goa 电路
US10386663B2 (en) GOA circuit and liquid crystal display device
WO2020015138A1 (zh) 一种goa电路及液晶显示装置
US11151943B1 (en) Gate driver on array circuit

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19928272

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19928272

Country of ref document: EP

Kind code of ref document: A1