WO2015051643A1 - 电平转换模块、阵列基板及显示装置 - Google Patents

电平转换模块、阵列基板及显示装置 Download PDF

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Publication number
WO2015051643A1
WO2015051643A1 PCT/CN2014/078762 CN2014078762W WO2015051643A1 WO 2015051643 A1 WO2015051643 A1 WO 2015051643A1 CN 2014078762 W CN2014078762 W CN 2014078762W WO 2015051643 A1 WO2015051643 A1 WO 2015051643A1
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Prior art keywords
level
tft
signal
drain
gate
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PCT/CN2014/078762
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English (en)
French (fr)
Inventor
郑亮亮
何剑
金婷婷
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US14/422,340 priority Critical patent/US9583059B2/en
Publication of WO2015051643A1 publication Critical patent/WO2015051643A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a level conversion module, an array substrate, and a display device. Background technique
  • Flat-panel displays such as liquid crystal displays, plasma displays, 0LED (organic light-emitting diode) displays, etc.
  • LCD liquid crystal displays
  • 0LED organic light-emitting diode
  • Consumer electronics such as television have gradually replaced traditional cathode ray tube displays and become the mainstream of displays.
  • timing As shown in FIG. 1 , in a conventional display panel, such as a driving structure of a liquid crystal panel, timing
  • a signal such as polarity (POL) is applied to the source driver chip to generate a data line charge signal loaded on the thin film transistor (TFT) to provide a start pulse signal (STV) / clock signal (CPV) / output enable signal (0E)
  • the gate drive chip is controlled to control the turning on and off of a thin film transistor (TFT) in each pixel circuit.
  • the internal structure of the gate drive chip is shown in Figure 2.
  • the logic circuit is based on the start pulse signal (STV, such as STV1 and STV2) / clock signal (CPV) / output enable signal (0E) / left or right shift Instructing the signal (L/R), etc., the control shift register sequentially outputs the gate line strobe signals of each row, and the output of the shift register is enhanced by the level conversion module (in the form of an IC integrated in the gate driving chip)
  • the output buffer is outputted row by row to each of the row gate lines (G1, G2, ... Gn), thereby sequentially strobing/scanning the respective gate lines.
  • the GOA (Ga te On Array) technology is one of the gate driving technologies of a display panel (such as a liquid crystal panel).
  • the basic concept is to integrate the gate driving circuit of the liquid crystal panel on the array substrate. Forming a scan drive for the liquid crystal panel.
  • the G0A technology not only eliminates the bonding area of the gate driving circuit and the fan-out wiring space, but also realizes a narrow bezel design, which can achieve a two-sided symmetrical aesthetic design.
  • Figure 3 shows a gate drive architecture for the prior art G0A.
  • the source driver chip since the level conversion module (Leve l Shif t Modu le ) is designed inside the source driver chip (in the form of an IC module integrated in the source driver chip, non-TFT structure), the source driver chip must be High-voltage process; In addition, the T-C0N chip and the source driver chip are integrated into the same chip (that is, the T-C0N and the source driver chip are the same chip), and the timing circuit of the gate drive circuit is included, which also makes The source driver chip must use a high voltage process, resulting in an increase in design cost.
  • I VGH I + I VGL I in the source drive signal can not be too high, so that the TFT turn-on voltage output to the G0A unit is low, resulting in the problem that the G0A unit cannot be fully opened or even started at low temperatures. , which in turn leads to insufficient charging or even charging.
  • the technical problem to be solved by the present invention is to provide a level conversion module, an array substrate, and a display device, which can avoid the design cost increase caused by the integration of the level conversion circuit inside the source driving chip and the low temperature of the G0A unit cannot be started. problem.
  • the present invention provides a level shifting circuit, comprising: a first level positive phase input terminal, a first level inverting input terminal, a second level positive phase output terminal, and a second level inverse a phase output terminal, a level state transfer unit, and a second level drive unit; the level state transfer unit receiving the first level positive phase input terminal and The first level is input to the first level of the input terminal, and the input high level state of the first level is transmitted to the second level driving unit; the second level driving unit is based on the input a high level state of the first level, outputting a second level of the corresponding state to the second level positive phase output terminal and the second level inversion output terminal, wherein the first level and the second level The levels are not equal.
  • the level state transfer unit includes:
  • a first signal positive phase input unit configured to receive a positive phase level signal input by the first level positive phase input terminal and output a level signal of the same phase
  • a first signal inverting input unit configured to receive an inverted level signal input by the first level inverting input terminal and output a level signal of the same phase
  • a first state interlocking unit that receives a level signal from the first signal positive phase input unit and the first signal inversion input unit, and maintains a high and low state of the level signal by an interlocking structure and is positive
  • the phase level signal and the inverted level signal are output separately.
  • the second level driving unit includes:
  • a second signal positive phase input unit configured to receive a positive phase level signal output by the first state interlocking unit and output a level signal of the same phase
  • a second signal inversion input unit configured to receive an inverted level signal output by the first state interlock unit and output a level signal of the same phase
  • a second state interlocking unit that receives a level signal from the second signal positive phase input unit and the second signal inversion input unit, and maintains a high and low state of the level signal by an interlocking structure and is positive
  • the forms of the phase second level signal and the inverted second level signal are respectively output.
  • the first signal positive phase input unit includes: a first TFT and a second TFT, wherein a source of the first TFT and a source of the second TFT are both connected to a first voltage, and the drain of the first TFT a pole is connected to the gate of the second TFT, and a gate of the first TFT is connected to the first level positive phase input terminal;
  • the first signal inversion input unit includes: a third TFT and a fourth TFT, wherein the a source of the third TFT and a source of the fourth TFT are both connected to a first voltage, a drain of the third TFT is connected to a gate of the fourth TFT, and a gate of the third TFT is connected to the a first level inverting input;
  • the first state interlocking unit includes: a fifth TFT and a sixth TFT, a gate of the fifth TFT is connected to a drain of the fourth TFT, and a source of the fifth TFT is connected to the first a drain of the second TFT, a gate of the sixth TFT is connected to a drain of the second TFT, a source of the sixth TFT is connected to a drain of the fourth TFT, and a fifth TFT
  • the drain and the drain of the sixth TFT are both connected to a negative voltage.
  • the second signal positive phase input unit includes: a seventh TFT and an eighth TFT, a gate of the seventh TFT is connected to a drain of the second TFT, and a drain of the seventh TFT is connected to a gate of the eighth TFT, a source of the seventh TFT and the eighth TFT are both connected to a second voltage, and a drain of the eighth TFT is connected to the second level positive phase output terminal;
  • the second signal inversion input unit includes: a ninth TFT and a tenth TFT, a gate of the ninth TFT is connected to a drain of the fourth TFT, and a drain of the ninth TFT is connected to the tenth a gate of the TFT, a source of the ninth TFT and the tenth TFT are both connected to a second voltage, and a drain of the tenth TFT is connected to the second level inverting output terminal;
  • the second state interlocking unit includes: an eleventh TFT and a twelfth TFT, a gate of the eleventh TFT is connected to a drain of the tenth TFT, and a source connection of the eleventh TFT To a drain of the eighth TFT, a gate of the twelfth TFT is connected to a drain of the eighth TFT, and a source of the twelfth TFT is connected to a drain of the tenth TFT, The drain of the eleventh TFT and the drain of the twelfth TFT are both connected to a negative voltage.
  • the first signal positive phase input unit includes: a first PTFT, a drain of the first PTFT is connected to a first voltage, and a gate of the first PTFT is connected to the first level positive phase input end ;
  • the first signal inverting input unit includes: a second PTFT, a drain of the second PTFT is connected to a first voltage, and a gate of the second PTFT is connected to the first level inverting input end;
  • the first state interlocking unit includes: a first NTFT and a second NTFT, a gate of the first NTFT is connected to a source of the second PTFT, and a source of the first NTFT is connected to the first a source of a PTFT, a gate of the second NTFT is connected to a source of the first PTFT, a source of the second NTFT is connected to a source of the second PTFT, the first NTFT
  • the drain and the drain of the second NTFT are both connected to a negative voltage.
  • the second signal positive phase input unit includes: a fourth NTFT, a gate of the fourth NTFT is connected to a source of the first PTFT, and a source of the fourth NTFT is connected to the second a positive phase output terminal, the drain of the fourth NTFT is connected to a negative voltage;
  • the second signal inversion input unit includes: a third NTFT, a gate of the third NTFT is connected to a source of the second PTFT, and a source of the third NTFT is connected to the second level a phase output end, the drain of the third NTFT is connected to a negative voltage;
  • the second state interlocking unit includes: a third PTFT and a fourth PTFT, a gate of the third PTFT is connected to a source of the fourth NTFT, and a source of the third PTFT is connected to the first a source of the third NTFT, a gate of the fourth PTFT is connected to a source of the third NTFT, a source of the fourth PTFT is connected to a source of the fourth NTFT, and a third PTFT is The drains and the drains of the fourth PTFT are each connected to a second voltage.
  • first level is lower than the second level.
  • the present invention also provides an array substrate comprising the level shifting circuit of any of the above.
  • the present invention also provides a display device comprising the above array substrate.
  • the level conversion circuit is formed by using a thin film transistor, so that the level conversion circuit can be integrated on the array substrate, which can not only avoid the level conversion circuit conversion circuit integrated in the source driving chip, because the IC process
  • the resulting low level of I VGH I + I VGL I caused the problem that the G0A unit could not be started at a low temperature.
  • DRAWINGS 1 is a schematic diagram of a driving structure of a liquid crystal panel in the prior art
  • FIG. 2 is an internal architecture diagram of a gate driving chip in the prior art, wherein a level converting module is integrated inside the gate driving chip;
  • FIG. 3 is a schematic diagram of a driving structure of a G0A panel in the prior art (only the source driving chip and the gate driving chip are shown), wherein the gate driving chip is disposed on the array substrate of the display panel;
  • FIG. 4 is a schematic diagram of a driving structure of a G0A panel according to an embodiment of the present invention, wherein a gate driving chip and a level converting circuit are disposed on an array substrate of the display panel;
  • FIG. 5 is a schematic structural diagram of a level conversion circuit according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural diagram of a level conversion circuit according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic diagram of a level transition state according to an embodiment of the present invention. detailed description
  • the level shift circuit of the present invention is composed of a thin film transistor.
  • the level conversion circuit is fabricated by using a thin film transistor on the array substrate, and can be made by the panel manufacturer according to requirements (for example, whether the process condition of the array substrate is N-type doping or P-type doping, the position of the G0A unit in the PANEL is The near-end or the far-end is used to fabricate the level-shifting circuit, so that the problem of increasing the design cost caused by the high-voltage process of the source driver chip can be solved.
  • FIG. 4 is a driving architecture diagram of a G0A panel of the present invention, in which a level conversion module of the prior art is integrated on an array substrate of a display panel in the form of a TFT circuit.
  • the timing control (T-C0N) chip when the timing control (T-C0N) chip outputs a low-voltage logic timing signal to the G0A (Ga te On Array) panel, the low-voltage logic timing signal of the T-C0N output is first integrated on the array substrate and implemented by a thin film transistor.
  • the level shifting circuit converts into a phase-consistent high-voltage timing signal, and then supplies the phase-aligned high-voltage timing signal to the G0A panel for the gate driving circuit to control the opening and closing of the thin film transistors in each pixel circuit. Therefore, the T-C0N chip can completely use the low-voltage process, thereby reducing the system design cost.
  • the gate control signal supplied by the T-C0N to the G0A panel changes from the existing high voltage to the low voltage, the corresponding timing signal pendulum Width reduction, EMI ( E lec t ro Magnet ic Interference ) Noise is also reduced. .
  • the level conversion circuit includes: a first level positive phase input terminal, a first level inversion input terminal, a second level positive phase output terminal, a second level inversion output terminal, a level state transfer unit, and Second level drive unit.
  • the level state transfer unit receives a first level input through the first level positive phase input terminal and the first level inverting input terminal, and transmits the input high level state of the first level to a second level driving unit; the second level driving unit outputs a second level of the corresponding state to the second level positive phase output terminal and the first according to the input high level state of the first level a two-level inverting output, wherein the first level is not equal to the second level.
  • the level state transfer unit includes:
  • a first signal positive phase input unit for receiving a positive phase level signal input by the first level positive phase input terminal and outputting a level signal of the same phase
  • a first signal inverting input unit configured to receive an inverted phase level signal input by the first level inverting input terminal and output a level signal of the same phase
  • a first state interlocking unit configured to respectively receive a level signal output by the first signal positive phase input unit and the first signal inversion input unit, and maintain a high and low state of the level signal through an interlock structure It is unchanged and is output separately in the form of a positive phase signal and an inverted level signal.
  • the second level driving unit includes:
  • a second signal positive phase input unit for receiving a positive phase level signal output by the first state interlocking unit and outputting a level signal of the same phase
  • a second signal inverting input unit configured to receive an inverted level signal output by the first state interlocking unit and output a level signal of the same phase
  • a second state interlocking unit configured to respectively receive the level signals output by the second signal positive phase input unit and the second signal inverting input unit, and maintain the high and low states of the level signal through an interlock structure It is unchanged and output in the form of a positive phase second level signal and an inverted second level signal, respectively. Since the level shifting module is typically used to boost the level, the second level (ie, the output level) is typically higher than the first level (ie, the input level).
  • VINA is a first level positive phase input terminal for inputting a positive phase level
  • VINB is a first level inversion input terminal for inputting an inversion level
  • 0UTA is a second level positive phase output for outputting a second positive phase level
  • 0UTB is a second level inverting output for outputting a second inverted level
  • VDD is the first voltage
  • VGH is the second voltage
  • VEE is the negative voltage.
  • the first signal positive phase input unit includes: a first TFTM1 and a second TFT M2.
  • the source of the first TFT M1 and the source of the second TFT M2 are both connected to the first voltage VDD, the drain of the first TFT M1 is connected to the gate of the second TFT M2, and the gate of the first TFT M1 is connected To the first level positive phase input terminal VINA.
  • the first signal inversion input unit includes: a third TFT M3 and a fourth TFT M4.
  • the source of the third TFT M3 and the source of the fourth TFT M4 are both connected to the first voltage VDD, the drain of the third TFT M3 is connected to the gate of the fourth TFT M4, and the gate of the third TFT M3 is connected to the A level inverting input VINB.
  • the first state interlocking unit includes: a fifth TFT M5 and a sixth TFT M6.
  • the gate of the fifth TFT M5 is connected to the drain of the fourth TFT M4, the source of the fifth TFT M5 is connected to the drain of the second TFT M2, and the gate of the sixth TFT M6 is connected to the drain of the second TFT M2.
  • the source of the sixth TFT M6 is connected to the drain of the fourth TFT M4, and the drains of the fifth TFT M5 and the drain of the sixth TFT M6 are both connected to the negative voltage VEE.
  • the gate of the first TFT M1 can be used as the first level The positive phase input terminal VINA
  • the drain of the second TFTM2 is used as a first level positive phase output terminal for transmitting the high and low states of the level input through the first level positive phase input terminal VINA to the second level driving unit.
  • the gate of the third TFT M3 can be used as the first level inverting input terminal VINB
  • the drain of the fourth TFT M4 can be used as the first level inverting output terminal for inputting the power input through the first level inverting input terminal VINB.
  • the flat high and low states are passed to the second level drive unit.
  • the first state interlocking unit composed of the fifth TFTM5 and the sixth TFTM6 is for holding the first level positive phase output terminal (point A in FIG. 5) and the first level inverting output terminal (point B in FIG. 5). Flat state.
  • the second signal positive phase input unit includes: a seventh TFT M7 and an eighth TFT M8.
  • the gate of the TFT M7 is connected to the drain of the second TFT M2, the drain of the seventh TFT M7 is connected to the gate of the eighth TFT M8, and the sources of the seventh TFT M7 and the eighth TFT M8 are both connected to the second voltage. VGH, the drain of the eighth TFT M8 is connected to the second level positive phase output terminal OUTA.
  • the second signal inversion input unit includes: a ninth TFT M9 and a tenth TFT M10.
  • the gate of the ninth TFT M9 is connected to the drain of the fourth TFT M4, the drain of the ninth TFT M9 is connected to the gate of the tenth TFT M10, and the sources of the ninth TFT M9 and the tenth TFT M10 are connected to the The second voltage VGH, the drain of the tenth TFT M10 is connected to the second level inverting output terminal OUTB.
  • the second state interlocking unit includes: an eleventh TFT Mi l and a twelfth TFT M12.
  • the gate of the eleventh TFT Mi l is connected to the drain of the tenth TFT M10
  • the source of the eleventh TFT Mi l is connected to the drain of the eighth TFT M8
  • the gate of the twelfth TFT M12 is connected to the a drain of the eighth TFT M8
  • a source of the twelfth TFT M12 is connected to a drain of the tenth TFT M10
  • a drain of the eleventh TFT Mi1 and a drain of the twelfth TFT M12 are connected to a negative voltage VEE.
  • the gate of the seventh TFT M7 can be used as a receiving end for receiving the level of the first level positive phase output terminal (point A in FIG. 5), and the eighth
  • the drain of the TFT M8 serves as the second level positive phase output terminal OUTA.
  • the gate of the ninth TFT M9 can be used as a level to receive the first level inverted output terminal (point B in FIG. 5).
  • the drain of the tenth TFT M10 is used as the second level inverting output terminal OUTB.
  • a second state interlocking unit composed of the eleventh TFT Mi1 and the twelfth TFT M12 is for maintaining a level state of the output of the second level positive phase output terminal and the second level inverting output terminal.
  • the level shifting state of the level shift circuit of this embodiment is as shown in FIG. Specifically, a signal having an opposite phase is input to the first level positive phase input terminal VINA and the first level inverting input terminal VI NB.
  • the first level positive phase input terminal VINA is at a high level
  • the first level inverting input terminal VINB When the level is low, the first TFT M1 and the second TFT M2 are turned on, and the third TFT M3 and the fourth TFT M4 are turned off, at which point A is at a high level, the sixth TFT M6 is turned on, and point B is at a low level.
  • the fifth TFT M5 is turned off, so that point A is maintained at a high level.
  • the seventh TFT M7 and the eighth TFT M8 are turned on, the second level positive phase output terminal OUTA is high level, the twelfth TFT M12 is turned on, and the second level inverting output terminal OUTB is Low level, the eleventh TFT Mi l is turned off, so that the second level positive phase output terminal OUTA maintains a high level.
  • the first level positive phase input terminal VINA is at a low level
  • the first level inverting input terminal VINB is at a high level
  • the third TFT M3 and the fourth TFT M4 are turned on, and point B is at a high level
  • fifth TFT M5 is turned on, so that point A is low level
  • sixth TFT M6 is turned off, and point B is maintained at a high level
  • ninth TFT M9 and tenth TFT M10 are turned on
  • second power The flat inverting output terminal OUTB is at a high level
  • the eleventh TFT Mi l is turned on, so that the second level positive phase output terminal OUTA is low level
  • the twelfth TFT M12 is turned off, and the second level inverting output terminal OUTB is maintained. High level.
  • the level conversion circuit is formed by using a thin film transistor, so that the level conversion circuit can be integrated on the array substrate, which can not only avoid the problem that the design cost of the level conversion circuit integrated in the source driving chip is increased, but also Solved the problem that the level conversion circuit is integrated in the source driver chip due to the IC process
  • the source driving chip since the source driving chip internally uses a low voltage process of 6V or less, and the gate driving circuit uses a high voltage process of 30V or 32V, the source driving chip of the built-in level converting circuit Due to the sequential circuit including the gate drive circuit, it is also necessary to use a high voltage process of 30V or 32V.
  • the level conversion circuit is provided on the array substrate, so that the source driving chip only needs to use a low voltage process of 6V or less.
  • VINA is a first level positive phase input terminal for inputting a positive phase level
  • VINB is a first level inversion input terminal for inputting an inversion level
  • 0UTA is a second level positive phase output for outputting a second positive phase level
  • 0UTB is a second level inverting output for outputting a second inverted level
  • VDD is the first voltage
  • VGH is the second voltage
  • VEE is the negative voltage.
  • PTFT P-channel thin film transistor
  • NTFT N-channel thin film transistor
  • the first signal positive phase input unit includes: a first PTFT PM1 having a drain connected to a first voltage VDD, and a gate of the first PTFT PM1 connected to a first level positive phase input terminal VINA.
  • the first signal inverting input unit comprises: a second PTFT PM2, the second PTFT PM2 drain is connected to the first voltage VDD, and the gate of the second PTFT PM2 is connected to the first level inverting input terminal VINB.
  • the first state interlocking unit includes: a first NTFT NM1 and a second NTFT MN2.
  • a gate of the first NTFT MN1 is connected to a source of the second PTFT PM2
  • a source of the first NTFT MN1 is connected to a source of the first PTFT PM1
  • a gate of the second NTFT NM2 is connected to the first
  • the source of the PTFT PM1 the source of the second NTFT NM2 is connected to the source of the second PTFT PM2.
  • the drain of the first NTFT MN 1 and the drain of the second NTFT MN 2 are both connected to the negative voltage VEE.
  • the gate of the first PTFT PM1 can be used as the first level positive phase input terminal VINA, and the source is used as the first level positive phase output terminal (point B in FIG. 6) for The level of the level of the positive phase input of the VINA input is passed to Second level drive unit.
  • the gate of the second PTFT PM2 can be used as the first level inverting input terminal VI NB , and the source is used as the first level inverting output terminal (point A in FIG. 6 ) for inputting through the first level inverting input terminal VINB
  • the level of the level is passed to the second level driving unit.
  • the first state interlocking unit composed of the first NTFTNM1 and the second NTFTNM2 is for holding the first level positive phase output terminal (point B in FIG. 6) and the first level inverting output terminal (point A in FIG. 6). Flat state.
  • the second signal positive phase input unit comprises: a fourth NTFT MN4, the gate of the fourth NTFT MN4 is connected to the source of the first PTFT PM1, and the source of the fourth NTFT MN4 is connected to the second level positive phase output terminal 0UTA, the drain of the fourth NTFT is connected to the negative voltage VEE.
  • the second signal inversion input unit includes: a third NTFT NM3, a gate of the third NTFT 3 is connected to a source of the second PTFT PM2, and a source of the third NTFT 3 is connected to the second level inverting output OUTB The drain of the third NTFT is connected to the negative voltage VEE.
  • the second state interlocking unit includes: a third PTFT PM3 and a fourth PTFT PM4.
  • the gate of the third PTFT PM3 is connected to the source of the fourth NTFT MN4, the source of the third PTFT PM3 is connected to the source of the third NTFT MN3, and the gate of the fourth PTFT PM4 is connected to the third NTFT NM3
  • the source, the source of the fourth PTFT PM4 is connected to the source of the fourth NTFT MN4.
  • the drain of the third PTFT PM3 and the drain of the fourth PTFT PM4 are both connected to the second voltage VGH.
  • the gate of the fourth NTFT 4 can be used as a receiving end for receiving a level of the first level positive phase output terminal (point B in FIG. 6), and the source is used as the second power.
  • the normal phase output terminal is 0UTA.
  • the gate of the third NTFT MN 3 can be used as the receiving end of the level to which the first level inverted output terminal (point A in Fig. 6) is received, and the source serves as the second level inverted output terminal 0UTB.
  • a second state interlocking unit composed of the third PTFT PM3 and the fourth PTFT PM4 is for maintaining the level state of the output of the second level positive phase output terminal and the second level inverting output terminal.
  • the working principle is similar to the embodiment, and the level shifting state of the level shifting circuit is also the same as As shown in FIG. 7, specifically, when the first level positive phase input terminal VINA is at a low level, the first level inverting input terminal VINB is at a high level, the first PTFT PM1 is turned on, and the B point is at a high level, the second NTFTNM2 is turned on, A is low, the first NTFTNM1 is turned off, and B is maintained at a high level; the fourth NTFT MN4 is turned on, the second level positive phase output terminal OUTA is low level, and the third PTFTPM 3 is turned The second level inverting output terminal OUTB is at a high level, and the fourth PTFTPM4 is turned off to maintain the second level positive phase output terminal OUTA at a low level.
  • the first level positive phase input terminal VINA When the first level positive phase input terminal VINA is at a high level, the first level inverting input terminal VINB is at a low level, the second PTFT PM2 is turned on, the A point is at a high level, the first NTFTNM1 is turned on, and the B point is low. Level, the second NTFTNM2 is turned off, and the A point is maintained at a high level; the third NTFT ⁇ 3 is turned on, the second level inverted output terminal OUTB is at a low level, and the fourth PTFTPM4 is turned on, and the second level positive phase output terminal 0UTA is high, the third PTFTPM3 is turned off, and the second level inverting output terminal OUTB is maintained at a low level.
  • the level shifting circuit of the present invention can also be combined with a timing control chip to implement a shutdown artifact removal function.
  • the timing control chip detects that the system power is lower than a certain set value, the level of the first level positive phase input terminal VINA outputted to the G0A unit is pulled high, so that the second level positive phase output terminal OUTA is kept high.
  • the shutdown afterimage removal function can be realized.
  • the present invention also provides an array substrate comprising the level conversion circuit of the first embodiment or the second embodiment.
  • the present invention also provides a display device comprising the above array substrate.
  • the display device can be: LCD panel, electronic paper, 0LED panel, mobile phone, tablet, TV, monitor, laptop, digital photo frame, navigator, etc. Any product or component with display function.

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Abstract

一种电平转换电路、阵列基板和显示装置，其中电平转换电路包括：第一电平正相输入端、第一电平反相输入端、第二电平正相输出端、第二电平反相输出端、电平状态传递单元和第二电平驱动单元；所述电平状态传递单元接收所述第一电平正相输入端以及所述第一电平反相输入端输入的第一电平，并将所述输入电平的高低状态传递至第二电平驱动单元；所述第二电平驱动单元根据所述输入电平的高低状态，输出相应状态的第二电平至所述第二电平正相输出端以及所述第二电平反相输出端，其中所述第一电平与所述第二电平不相等。

Description

说 明 书 电平转换模块、 阵列基板及显示装置 技术领域
本发明涉及显示技术领域， 尤其涉及一种电平转换模块、 一种阵 列基板及一种显示装置。 背景技术
平面显示器， 例如液晶显示器、 等离子体显示器、 0LED (有机发 光二极管）显示器等， 具有高画质、 体积小、 重量轻及应用范围广等 优点， 因此被广泛应用于移动电话、 笔记本电脑、 显示器以及电视等 消费性电子产品，并已经逐渐取代传统的阴极射线管显示器而成为显 示器的主流。
如图 1所示， 传统显示面板、 例如液晶面板的驱动架构中， 时序
/极性（ POL )等信号给源极驱动芯片以生成加载在薄膜晶体管（ TFT ) 上的数据线充电信号， 提供起始脉冲信号（STV ) /时钟信号（CPV ) / 输出使能信号 ( 0E )给栅极驱动芯片以控制各像素电路中的薄膜晶体 管 （TFT ) 的开启和关闭。 所述栅极驱动芯片的内部架构如图 2所示， 逻辑电路根据起始脉冲信号 ( STV,如 STV1和 STV2 ) /时钟信号 ( CPV ) /输出使能信号 （0E ) /左移或右移指示信号 （L/R )等， 控制移位寄 存器依次输出各行栅线选通信号，移位寄存器的输出经电平转换模块 (以 IC的形式集成在栅极驱动芯片中 )的增强后， 通过输出緩冲器而 逐行输出到各行栅线 （Gl , G2 , ... ... Gn ) 中， 从而依次选通 /扫描各 行栅线。
GOA ( Ga te On Array , 栅极驱动集成于阵列基板上）技术是显示 面板（例如液晶面板）的栅极驱动技术之一， 其基本概念是将液晶面 板的栅极驱动电路集成在阵列基板上， 形成对液晶面板的扫描驱动。 与传统驱动技术相比， G0A技术不仅省去了栅极驱动电路的焊接 ( bonding ) 区域以及扇出 （ fan-out )布线空间， 而且实现了窄边框 设计， 可以做到两边对称的美观设计。 图 3给出了现有技术中的 G0A 的一种栅极驱动架构。 该方案中， 由于电平转换模块（Leve l Shif t Modu le )设计在源极驱动芯片内部（以 IC模块的形式集成在源极驱动 芯片内， 非 TFT结构）， 使得源极驱动芯片必须釆用高压制程； 此外， T-C0N芯片与源极驱动芯片集成到同一个芯片中（即 T-C0N和源极驱动 芯片为同一芯片）， 并包含了栅极驱动电路的时序电路， 这也使得源 极驱动芯片必须釆用高压制程， 从而导致设计成本上升。 此外， 受限 于芯片制程， 源极驱动信号中 I VGH I + I VGL I不能过高， 使得输出给 G0A 单元的 TFT开启电压较低，导致 G0A单元在低温下无法完全打开甚至无 法启动的问题， 进而导致充电不充分甚至无法充电。 此外， 现有技术 中还有釆用外置电平转换芯片的 G0A驱动架构， 该架构中， 由于外置 的电平转换模块输出给 G0A的信号， 如 STV、 CLKn等的电位较高， 且频 率较高， 而电平转换模块和面板之间无法加入防电磁干扰器件， 从而 导致电磁干扰问题的风险极高，同时该种设计也会导致面板厂商的设 计成本上升。 发明内容
(一）要解决的技术问题
本发明要解决的技术问题是： 提供一种电平转换模块、 阵列基板 及显示装置，其能够避免电平转换电路集成于源极驱动芯片内部带来 的设计成本上升和 G0A单元低温无法启动的问题。
(二）技术方案
为解决上述问题，本发明提供了一种电平转换电路，其特征在于， 包括： 第一电平正相输入端、 第一电平反相输入端、 第二电平正相输 出端、第二电平反相输出端、电平状态传递单元和第二电平驱动单元； 所述电平状态传递单元接收通过所述第一电平正相输入端以及 所述第一电平反相输入端输入的第一电平，并将输入的所述第一电平 的高低状态传递至第二电平驱动单元；所述第二电平驱动单元根据输 入的所述第一电平的高低状态，输出相应状态的第二电平至所述第二 电平正相输出端以及所述第二电平反相输出端，其中所述第一电平与 所述第二电平不相等。
其中， 所述电平状态传递单元包括：
第一信号正相输入单元，用于接收所述第一电平正相输入端输入 的正相电平信号并输出相同相位的电平信号；
第一信号反相输入单元，用于接收所述第一电平反相输入端输入 的反相电平信号并输出相同相位的电平信号；
第一状态互锁单元，从所述第一信号正相输入单元和所述第一信 号反相输入单元接收电平信号，通过互锁结构维持所述电平信号的高 低状态不变并以正相电平信号和反相电平信号的形式分别输出。
其中， 所述第二电平驱动单元包括：
第二信号正相输入单元，用于接收所述第一状态互锁单元输出的 正相电平信号并输出相同相位的电平信号；
第二信号反相输入单元，用于接收所述第一状态互锁单元输出的 反相电平信号并输出相同相位的电平信号；
第二状态互锁单元，从所述第二信号正相输入单元和所述第二信 号反相输入单元接收电平信号，通过互锁结构维持所述电平信号的高 低状态不变并以正相第二电平信号和反相第二电平信号的形式分别 输出。
其中， 所述第一信号正相输入单元包括： 第一 TFT和第二 TFT , 所述第一 TFT的源极和第二 TFT的源极均连接至第一电压，所述第一 TFT的漏极连接至所述第二 TFT的栅极， 所述第一 TFT的栅极连接至 所述第一电平正相输入端；
所述第一信号反相输入单元包括： 第三 TFT和第四 TFT , 所述第 三 TFT的源极和第四 TFT的源极均连接至第一电压，所述第三 TFT的 漏极连接至所述第四 TFT的栅极，所述第三 TFT的栅极连接至所述第 一电平反相输入端；
所述第一状态互锁单元包括：第五 TFT和第六 TFT ,所述第五 TFT 的栅极连接至所述第四 TFT的漏极，所述第五 TFT的源极连接至所述 第二 TFT的漏极， 所述第六 TFT的栅极连接至所述第二 TFT的漏极， 所述第六 TFT的源极连接至所述第四 TFT的漏极，所述第五 TFT的漏 极和所述第六 TFT的漏极均接负压。
其中， 所述第二信号正相输入单元包括： 第七 TFT和第八 TFT , 所述第七 TFT的栅极连接至所述第二 TFT的漏极，所述第七 TFT的漏 极连接至所述第八 TFT的栅极，所述第七 TFT和第八 TFT的源极均连 接至第二电压，所述第八 TFT的漏极连接至所述第二电平正相输出端； 所述第二信号反相输入单元包括： 第九 TFT和第十 TFT , 所述第 九 TFT的栅极连接至所述第四 TFT的漏极，所述第九 TFT的漏极连接 至所述第十 TFT的栅极，所述第九 TFT和第十 TFT的源极均连接至第 二电压， 所述第十 TFT的漏极连接至所述第二电平反相输出端；
所述第二状态互锁单元包括： 第十一 TFT和第十二 TFT , 所述第 十一 TFT的栅极连接至所述第十 TFT的漏极，所述第十一 TFT的源极 连接至所述第八 TFT的漏极，所述第十二 TFT的栅极连接至所述第八 TFT的漏极， 所述第十二 TFT的源极连接至所述第十 TFT的漏极， 所 述第十一 TFT的漏极和所述第十二 TFT的漏极均接负压。
其中， 所述第一信号正相输入单元包括： 第一 PTFT , 所述第一 PTFT的漏极连接至第一电压， 所述第一 PTFT的栅极连接至所述第一 电平正相输入端；
所述第一信号反相输入单元包括： 第二 PTFT , 所述第二 PTFT漏 极连接至第一电压， 所述第二 PTFT的栅极连接至所述第一电平反相 输入端； 所述第一状态互锁单元包括： 第一 NTFT和第二 NTFT , 所述第一 NTFT的栅极连接至所述第二 PTFT的源极， 所述第一 NTFT的源极连 接至所述第一 PTFT 的源极， 所述第二 NTFT 的栅极连接至所述第一 PTFT的源极， 所述第二 NTFT的源极连接至所述第二 PTFT的源极， 所述第一 NTFT的漏极和所述第二 NTFT的漏极均连接至负压。
其中， 所述第二信号正相输入单元包括： 第四 NTFT , 所述第四 NTFT的栅极连接至所述第一 PTFT的源极， 所述第四 NTFT的源极连 接至所述第二电平正相输出端， 所述第四 NTFT的漏极接负压；
所述第二信号反相输入单元包括： 第三 NTFT , 所述第三 NTFT的 栅极连接至所述第二 PTFT的源极，所述第三 NTFT的源极连接至所述 第二电平反相输出端， 所述第三 NTFT的漏极接负压；
所述第二状态互锁单元包括： 第三 PTFT和第四 PTFT , 所述第三 PTFT的栅极连接至所述第四 NTFT的源极， 所述第三 PTFT的源极连 接至所述第三 NTFT 的源极， 所述第四 PTFT 的栅极连接至所述第三 NTFT的源极， 所述第四 PTFT的源极连接至所述第四 NTFT的源极， 所述第三 PTFT的漏极和第四 PTFT的漏极均连接至第二电压。
其中， 所述第一电平低于所述第二电平。
本发明还提供了一种阵列基板， 包括上述任一所述的电平转换电 路。
本发明还提供了一种显示装置， 包括上述的阵列基板。
(三）有益效果
本发明实施例中， 通过利用薄膜晶体管来组成电平转换电路， 使 得电平转换电路可以集成到阵列基板上，不仅可以规避电平转换电路 转换电路集成于源极驱动芯片的方案中由于 IC制程导致的 I VGH I + I VGL I较低导致的 G0A单元低温无法启动的问题。 附图说明 图 1为现有技术中的一种液晶面板的驱动架构图； 图 2为现有技术中的栅极驱动芯片的内部架构图， 其中电平转换 模块集成在栅极驱动芯片内部；
图 3为现有技术中的 G0A面板的驱动架构图（只示出了源极驱动芯 片和栅极驱动芯片）， 其中栅极驱动芯片设置在显示面板的阵列基板 上；
图 4为本发明实施例的一种 G0A面板的驱动架构图，其中栅极驱动 芯片和电平转换电路设置在显示面板的阵列基板上；
图 5为本发明实施例一的电平转换电路的结构示意图；
图 6为本发明实施例二的电平转换电路的结构示意图；
图 7为本发明实施例的电平转换状态示意图。 具体实施方式
本发明电平转换电路由薄膜晶体管构成。通过在阵列基板上釆用 薄膜晶体管来制成电平转换电路，并可以由面板厂商根据需求（比如， 阵列基板的工艺条件是 N型掺杂还是 P型掺杂， G0A单元在 PANEL的 位置是近端还是远端等）来制作电平转换电路， 从而可以解决源极驱 动芯片釆用高压制程而导致的设计成本上升的问题。
如图 4所示为本发明的 G0A面板的驱动架构图，其中将现有技术 中的电平转换模块以 TFT电路的形式集成在显示面板的阵列基板上。 本发明中， 当时序控制 （T-C0N ) 芯片输出低压逻辑时序信号给 G0A ( Ga te On Array ) 面板时， T-C0N 输出的低压逻辑时序信号首先通 过集成在阵列基板上并通过薄膜晶体管实现的电平转换电路转换成 相位一致的高压时序信号， 然后将该相位一致的高压时序信号供给 G0A面板， 以用于栅极驱动电路控制各像素电路中的薄膜晶体管的开 启与关闭。 因此， T-C0N芯片完全可以釆用低压制程， 从而实现系统 设计成本的降低，同时由于 T-C0N提供给 G0A面板的栅极控制信号由 现有的高压变成低压， 因此相应的时序信号摆幅降低， EMI ( E lec t ro Magnet ic Interference )噪声也得以降低。。
本发明实施例提供的电平转换电路包括： 第一电平正相输入端、 第一电平反相输入端、 第二电平正相输出端、 第二电平反相输出端、 电平状态传递单元和第二电平驱动单元。所述电平状态传递单元接收 通过所述第一电平正相输入端以及所述第一电平反相输入端输入的 第一电平，并将输入的所述第一电平的高低状态传递至第二电平驱动 单元； 所述第二电平驱动单元根据输入的所述第一电平的高低状态， 输出相应状态的第二电平至所述第二电平正相输出端以及所述第二 电平反相输出端， 其中所述第一电平与所述第二电平不相等。
其中， 电平状态传递单元包括：
第一信号正相输入单元，用于接收第一电平正相输入端输入的正 相电平信号并输出相同相位的电平信号；
第一信号反相输入单元，用于接收第一电平反相输入端输入的反 相电平信号并输出相同相位的电平信号；
第一状态互锁单元，用于分别接收所述第一信号正相输入单元和 所述第一信号反相输入单元输出的电平信号，并通过互锁结构维持所 述电平信号的高低状态不变并以正相电平信号和反相电平信号的形 式分别输出。
其中， 第二电平驱动单元包括：
第二信号正相输入单元，用于接收第一状态互锁单元输出的正相 电平信号并输出相同相位的电平信号；
第二信号反相输入单元，用于接收第一状态互锁单元输出的反相 电平信号并输出相同相位的电平信号；
第二状态互锁单元，用于分别接收所述第二信号正相输入单元和 所述第二信号反相输入单元输出的电平信号，并通过互锁结构维持所 述电平信号的高低状态不变并以正相第二电平信号和反相第二电平 信号的形式分别输出。 由于电平转换模块通常用于增强电平， 因此第二电平（即， 输出 电平）通常高于第一电平 （即， 输入电平）。
下面结合附图及具体实施例对本发明进行进一步的详细说明。应 理解的是， 以下实施例仅作为示例用来对本发明进行说明， 而并非用 于限制本发明。 实施例一
本实施例的具体电路结构如图 5所示， VINA为第一电平正相输 入端， 用于输入正相电平， VINB 为第一电平反相输入端， 用于输入 反相电平。 0UTA 为第二电平正相输出端， 用于输出第二正相电平， 0UTB为第二电平反相输出端， 用于输出第二反相电平。 VDD为第一电 压， VGH为第二电压， VEE为负压。
本实施例的电平状态传递单元中：
第一信号正相输入单元包括： 第一 TFTM1和第二 TFT M2。 第一 TFT Ml的源极和第二 TFT M2的源极均连接至第一电压 VDD, 第一 TFT Ml的漏极连接至第二 TFT M2的栅极， 所述第一 TFT Ml的栅极连接 至第一电平正相输入端 VINA。
第一信号反相输入单元包括： 第三 TFT M3和第四 TFT M4。 第三 TFT M3的源极和第四 TFT M4的源极均连接至第一电压 VDD, 第三 TFT M3的漏极连接至第四 TFT M4的栅极， 第三 TFT M3的栅极连接至第 一电平反相输入端 VINB。
第一状态互锁单元包括：第五 TFT M5和第六 TFT M6。第五 TFT M5 的栅极连接至第四 TFT M4 的漏极， 第五 TFT M5 的源极连接至第二 TFT M2的漏极， 第六 TFT M6的栅极连接至第二 TFT M2的漏极， 第 六 TFT M6的源极连接至第四 TFT M4的漏极， 第五 TFT M5的漏极和 第六 TFT M6的漏极均接至负压 VEE。
该电平状态传递单元中，可以将第一 TFTM1的栅极作为第一电平 正相输入端 VINA, 将第二 TFTM2 的漏极作为第一电平正相输出端， 用于将通过第一电平正相输入端 VINA输入的电平的高低状态传递至 第二电平驱动单元。可以将第三 TFTM3的栅极作为第一电平反相输入 端 VINB, 将第四 TFT M4的漏极作为第一电平反相输出端， 用于将通 过第一电平反相输入端 VINB输入的电平的高低状态传递至第二电平 驱动单元。由第五 TFTM5和第六 TFTM6构成的第一状态互锁单元用于 保持第一电平正相输出端（图 5中 A点）和第一电平反相输出端 (图 5中 B点） 的电平状态。
本实施例的第二电平驱动单元中：
第二信号正相输入单元包括： 第七 TFT M7和第八 TFT M8。 第七
TFT M7的栅极连接至第二 TFT M2的漏极， 第七 TFT M7的漏极连接 至第八 TFT M8的栅极， 第七 TFT M7和第八 TFT M8的源极均连接至 第二电压 VGH,第八 TFT M8的漏极连接至第二电平正相输出端 0UTA。
第二信号反相输入单元包括： 第九 TFT M9和第十 TFT M10。 第 九 TFT M9的栅极连接至第四 TFT M4的漏极， 第九 TFT M9的漏极连 接至第十 TFT M10的栅极， 第九 TFT M9和第十 TFT M10的源极均连 接至第二电压 VGH, 第十 TFT M10的漏极连接至第二电平反相输出端 0UTB。
第二状态互锁单元包括： 第十一 TFT Mi l和第十二 TFT M12。 第 十一 TFT Mi l的栅极连接至第十 TFT M10的漏极， 第十一 TFT Mi l的 源极连接至第八 TFT M8的漏极， 第十二 TFT Ml 2的栅极连接至第八 TFT M8的漏极， 第十二 TFT Ml 2的源极连接至第十 TFT M10的漏极， 第十一 TFT Mi l的漏极和第十二 TFT Ml 2的漏极均接至负压 VEE。
该第二电平驱动单元中， 可以将第七 TFT M7的栅极作为接收第 一电平正相输出端（图 5中 A点）传递过来的电平的接收端， 将第八
TFT M8的漏极作为第二电平正相输出端 0UTA。 可以将第九 TFT M9的 栅极作为接收第一电平反相输出端（图 5中 B点）传递过来的电平的 接收端， 将第十 TFT M10的漏极作为第二电平反相输出端 0UTB。 由 第十一 TFT Mi l和第十二 TFT M12构成的第二状态互锁单元用于保持 第二电平正相输出端和第二电平反相输出端输出的电平状态。
该电路具体工作原理如下：
本实施例的电平转换电路的电平转换状态如图 7所示。 具体地， 向第一电平正相输入端 VINA与第一电平反相输入端 V I NB输入相位相 反的信号， 当第一电平正相输入端 VINA为高电平时， 第一电平反相 输入端 VINB为低电平， 第一 TFT M1和第二 TFT M2导通， 第三 TFT M3 和第四 TFT M4截止， 此时 A点为高电平， 第六 TFT M6导通， B点为 低电平， 第五 TFT M5截止， 使得 A点维持高电平。 由于 A点为高电 平， 第七 TFT M7和第八 TFT M8导通， 第二电平正相输出端 0UTA为 高电平，第十二 TFT M12导通，第二电平反相输出端 0UTB为低电平， 第十一 TFT Mi l截止， 从而第二电平正相输出端 0UTA维持高电平。 反之， 当第一电平正相输入端 VINA为低电平时， 第一电平反相输入 端 VINB为高电平， 第三 TFT M3和第四 TFT M4导通， B点为高电平， 第五 TFT M5导通， 从而 A点为低电平， 第六 TFT M6截止， 使得 B点 维持高电平； 由于 B点为高电平， 第九 TFT M9和第十 TFT M10导通， 第二电平反相输出端 0UTB为高电平， 第十一 TFT Mi l导通， 从而第 二电平正相输出端 0UTA为低电平， 第十二 TFT M12截止， 维持第二 电平反相输出端 0UTB为高电平。
本实施例通过利用薄膜晶体管来组成电平转换电路 ,使得电平转 换电路可以集成到阵列基板上，不仅可以规避电平转换电路集成于源 极驱动芯片带来的设计成本上升的问题，而且能够解决电平转换电路 集成于源极驱动芯片的方案中由于 IC 制程导致的| ¥011 | + | ¥0 |较低 导致的 G0A单元低温无法启动的问题。
而且， 由于源极驱动芯片内部釆用 6V以下低压制程， 而栅极驱 动电路釆用 30V或 32V高压制程， 内置电平转换电路的源极驱动芯片 由于包含了栅极驱动电路的时序电路， 因此也需要釆用 30V或 32V的 高压制程。 本实施例将电平转换电路提供在阵列基板上， 从而使得源 极驱动芯片仅需釆用 6V以下的低压制程即可。 实施例二
本实施例的具体电路结构如图 6所示， VINA为第一电平正相输 入端， 用于输入正相电平， VINB 为第一电平反相输入端， 用于输入 反相电平。 0UTA 为第二电平正相输出端， 用于输出第二正相电平， 0UTB为第二电平反相输出端， 用于输出第二反相电平。 VDD为第一电 压， VGH为第二电压， VEE为负压。为描述简洁起见， 本文的描述中， 以 PTFT表示 P沟道的薄膜晶体管，以 NTFT表示 N沟道的薄膜晶体管。
本实施例的电平状态传递单元中：
第一信号正相输入单元包括： 第一 PTFT PM1 , 第一 PTFT PM1的 漏极连接至第一电压 VDD, 第一 PTFT PM1 的栅极连接至第一电平正 相输入端 VINA。
第一信号反相输入单元包括： 第二 PTFT PM2 , 第二 PTFT PM2漏 极连接至第一电压 VDD, 第二 PTFT PM2 的栅极连接至第一电平反相 输入端 VINB。
所述第一状态互锁单元包括： 第一 NTFT NM1和第二 NTFT 丽 2。 第一 NTFT丽 1的栅极连接至所述第二 PTFT PM2的源极，第一 NTFT丽 1 的源极连接至第一 PTFT PM 1的源极， 第二 NTFT NM2的栅极连接至第 一 PTFT PM1的源极， 第二 NTFT NM2的源极连接至第二 PTFT PM2的 源极。 第一 NTFT 丽 1 的漏极和第二 NTFT 丽 2 的漏极均连接至负压 VEE。
该电平状态传递单元中， 可以将第一 PTFT PM1的栅极作为第一 电平正相输入端 VINA ,源极作为第一电平正相输出端（图 6中 B点）， 用于将通过第一电平正相输入端 VINA输入的电平的高低状态传递至 第二电平驱动单元。可以将第二 PTFTPM2的栅极作为第一电平反相输 入端 VI NB , 源极作为第一电平反相输出端 （图 6中 A点）， 用于将通 过第一电平反相输入端 VINB输入的电平的高低状态传递至第二电平 驱动单元。由第一 NTFTNM1和第二 NTFTNM2构成的第一状态互锁单元 用于保持第一电平正相输出端（图 6中 B点）和第一电平反相输出端 (图 6中 A点） 的电平状态。
本实施例的第二电平驱动单元中：
第二信号正相输入单元包括： 第四 NTFT丽 4 , 第四 NTFT丽 4的 栅极连接至第一 PTFT PM1的源极， 第四 NTFT丽 4的源极连接至第二 电平正相输出端 0UTA , 第四 NTFT的漏极接至负压 VEE。
第二信号反相输入单元包括： 第三 NTFT NM3 , 第三 NTFT 丽 3的 栅极连接至第二 PTFT PM2的源极， 第三 NTFT丽 3的源极连接至第二 电平反相输出端 0UTB , 第三 NTFT的漏极接至负压 VEE。
第二状态互锁单元包括： 第三 PTFT PM3和第四 PTFT PM4。 第三 PTFT PM3的栅极连接至第四 NTFT 丽 4的源极， 第三 PTFT PM3的源 极连接至第三 NTFT 丽 3 的源极， 第四 PTFT PM4 的栅极连接至第三 NTFT NM3的源极， 第四 PTFT PM4的源极连接至第四 NTFT 丽 4的源 极。 第三 PTFT PM3的漏极和第四 PTFT PM4的漏极均连接至第二电压 VGH。
该第二电平驱动单元中， 可以将第四 NTFT 丽 4的栅极作为接收 第一电平正相输出端（图 6中 B点）传递过来的电平的接收端， 源极 作为第二电平正相输出端 0UTA。 可以将第三 NTFT 丽 3的栅极作为接 收第一电平反相输出端（图 6中 A点）传递过来的电平的接收端， 源 极作为第二电平反相输出端 0UTB。 由第三 PTFTPM3和第四 PTFTPM4 构成的第二状态互锁单元用于保持第二电平正相输出端和第二电平 反相输出端输出的电平状态。
工作原理与实施例类似，其电平转换电路的电平转换状态同样如 图 7所示， 具体地， 当第一电平正相输入端 VINA为低电平时， 第一 电平反相输入端 VINB为高电平，第一 PTFTPM1导通， B点为高电平， 第二 NTFTNM2导通， A点为低电平， 第一 NTFTNM1截止， 维持 B点为 高电平； 第四 NTFT丽 4导通， 第二电平正相输出端 0UTA为低电平， 第三 PTFTPM 3导通 ,第二电平反相输出端 0UTB为高电平，第四 PTFTPM4 截止， 维持第二电平正相输出端 0UTA为低电平。 当第一电平正相输 入端 VINA为高电平时， 第一电平反相输入端 VINB为低电平， 第二 PTFTPM2导通， A点为高电平， 第一 NTFTNM1导通， B点为低电平， 第二 NTFTNM2截止， 维持 A点为高电平； 第三 NTFT 丽 3导通， 第二 电平反相输出端 0UTB为低电平， 第四 PTFTPM4导通， 第二电平正相 输出端 0UTA为高电平， 第三 PTFTPM3截止， 维持第二电平反相输出 端 0UTB为低电平。
本实施例能够实现与实施例一相同的技术效果， 此处不再赘述。 本发明的电平转换电路还可以配合时序控制芯片来实现关机残 影消除功能。 当时序控制芯片检测到系统电源低于某一设定值时， 将 输出给 G0A单元的第一电平正相输入端 VINA的电平拉高， 使得第二 电平正相输出端 0UTA保持高电平， 配合带静电环的 G0A阵列基板残 影消除设计， 从而可以实现关机残影消除功能。
本发明还提供了一种阵列基板， 包括上述实施例一或实施例二中 的电平转换电路。
本发明还提供了一种显示装置， 包括上述的阵列基板。 该显示装 置可以是： 液晶面板、 电子纸、 0LED 面板、 手机、 平板电脑、 电视 机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的 产品或部件。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关 技术领域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明 的范畴， 本发明的专利保护范围应由权利要求限定。

Claims

权 利 要 求 书
1、 一种电平转换电路， 其特征在于， 包括： 第一电平正相输入 端、 第一电平反相输入端、 第二电平正相输出端、 第二电平反相输出 端、 电平状态传递单元和第二电平驱动单元；
所述电平状态传递单元接收通过所述第一电平正相输入端以及 所述第一电平反相输入端输入的第一电平，并将输入的所述第一电平 的高低状态传递至第二电平驱动单元；所述第二电平驱动单元根据输 入的所述第一电平的高低状态，输出相应状态的第二电平至所述第二 电平正相输出端以及所述第二电平反相输出端，其中所述第一电平与 所述第二电平不相等。
2、 如权利要求 1所述的电平转换电路， 其特征在于， 所述电平 状态传递单元包括：
第一信号正相输入单元，用于接收所述第一电平正相输入端输入 的正相电平信号并输出相同相位的电平信号；
第一信号反相输入单元，用于接收所述第一电平反相输入端输入 的反相电平信号并输出相同相位的电平信号；
第一状态互锁单元，从所述第一信号正相输入单元和所述第一信 号反相输入单元接收电平信号，通过互锁结构维持所述电平信号的高 低状态不变并以正相电平信号和反相电平信号的形式分别输出。
3、 如权利要求 2所述的电平转换电路， 其特征在于， 所述第二 电平驱动单元包括：
第二信号正相输入单元，用于接收所述第一状态互锁单元输出的 正相电平信号并输出相同相位的电平信号；
第二信号反相输入单元，用于接收所述第一状态互锁单元输出的 反相电平信号并输出相同相位的电平信号； 第二状态互锁单元，从所述第二信号正相输入单元和所述第二信 号反相输入单元接收电平信号，通过互锁结构维持所述电平信号的高 低状态不变并以正相第二电平信号和反相第二电平信号的形式分别 输出。
4、 如权利要求 3所述的电平转换电路， 其特征在于， 所述第一 信号正相输入单元包括： 第一 TFT和第二 TFT , 所述第一 TFT的源极 和第二 TFT的源极均连接至第一电压，所述第一 TFT的漏极连接至所 述第二 TFT的栅极，所述第一 TFT的栅极连接至所述第一电平正相输 入端；
所述第一信号反相输入单元包括： 第三 TFT和第四 TFT , 所述第 三 TFT的源极和第四 TFT的源极均连接至第一电压，所述第三 TFT的 漏极连接至所述第四 TFT的栅极，所述第三 TFT的栅极连接至所述第 一电平反相输入端；
所述第一状态互锁单元包括：第五 TFT和第六 TFT ,所述第五 TFT 的栅极连接至所述第四 TFT的漏极，所述第五 TFT的源极连接至所述 第二 TFT的漏极， 所述第六 TFT的栅极连接至所述第二 TFT的漏极， 所述第六 TFT的源极连接至所述第四 TFT的漏极，所述第五 TFT的漏 极和所述第六 TFT的漏极均接负压。
5、 如权利要求 4所述的电平转换电路， 其特征在于， 所述第二 信号正相输入单元包括： 第七 TFT和第八 TFT , 所述第七 TFT的栅极 连接至所述第二 TFT 的漏极， 所述第七 TFT的漏极连接至所述第八 TFT的栅极， 所述第七 TFT和第八 TFT的源极均连接至第二电压， 所 述第八 TFT的漏极连接至所述第二电平正相输出端；
所述第二信号反相输入单元包括： 第九 TFT和第十 TFT , 所述第 九 TFT的栅极连接至所述第四 TFT的漏极，所述第九 TFT的漏极连接 至所述第十 TFT的栅极，所述第九 TFT和第十 TFT的源极均连接至第 二电压， 所述第十 TFT的漏极连接至所述第二电平反相输出端； 所述第二状态互锁单元包括： 第十一 TFT和第十二 TFT , 所述第 十一 TFT的栅极连接至所述第十 TFT的漏极，所述第十一 TFT的源极 连接至所述第八 TFT的漏极，所述第十二 TFT的栅极连接至所述第八 TFT的漏极， 所述第十二 TFT的源极连接至所述第十 TFT的漏极， 所 述第十一 TFT的漏极和所述第十二 TFT的漏极均接负压。
6、 如权利要求 3所述的电平转换电路， 其特征在于， 所述第一 信号正相输入单元包括： 第一 PTFT , 所述第一 PTFT的漏极连接至第 一电压， 所述第一 PTFT的栅极连接至所述第一电平正相输入端； 所述第一信号反相输入单元包括： 第二 PTFT , 所述第二 PTFT漏 极连接至第一电压， 所述第二 PTFT的栅极连接至所述第一电平反相 输入端；
所述第一状态互锁单元包括： 第一 NTFT和第二 NTFT , 所述第一 NTFT的栅极连接至所述第二 PTFT的源极， 所述第一 NTFT的源极连 接至所述第一 PTFT 的源极， 所述第二 NTFT 的栅极连接至所述第一 PTFT的源极， 所述第二 NTFT的源极连接至所述第二 PTFT的源极， 所述第一 NTFT的漏极和所述第二 NTFT的漏极均连接至负压。
7、 如权利要求 6所述的电平转换电路， 其特征在于， 所述第二 信号正相输入单元包括： 第四 NTFT , 所述第四 NTFT的栅极连接至所 述第一 PTFT的源极，所述第四 NTFT的源极连接至所述第二电平正相 输出端， 所述第四 NTFT的漏极接负压；
所述第二信号反相输入单元包括： 第三 NTFT , 所述第三 NTFT的 栅极连接至所述第二 PTFT的源极，所述第三 NTFT的源极连接至所述 第二电平反相输出端， 所述第三 NTFT的漏极接负压； 所述第二状态互锁单元包括： 第三 PTFT和第四 PTFT , 所述第三 PTFT的栅极连接至所述第四 NTFT的源极， 所述第三 PTFT的源极连 接至所述第三 NTFT 的源极， 所述第四 PTFT 的栅极连接至所述第三 NTFT的源极， 所述第四 PTFT的源极连接至所述第四 NTFT的源极， 所述第三 PTFT的漏极和第四 PTFT的漏极均连接至第二电压。
8、如权利要求 1-7中任一项所述的电平转换电路，其特征在于， 所述第一电平低于所述第二电平。
9、 一种阵列基板， 其特征在于， 包括如权利要求 Γ8中任一所 述的电平转换电路。
1 0、 一种显示装置， 其特征在于， 包括如权利要求 9所述的阵列 基板。
PCT/CN2014/078762 2013-10-12 2014-05-29 电平转换模块、阵列基板及显示装置 WO2015051643A1 (zh)

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