WO2021174607A1 - Goa 驱动电路、显示面板及显示装置 - Google Patents

Goa 驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2021174607A1
WO2021174607A1 PCT/CN2020/080975 CN2020080975W WO2021174607A1 WO 2021174607 A1 WO2021174607 A1 WO 2021174607A1 CN 2020080975 W CN2020080975 W CN 2020080975W WO 2021174607 A1 WO2021174607 A1 WO 2021174607A1
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WIPO (PCT)
Prior art keywords
node
pull
module
goa
signal
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PCT/CN2020/080975
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English (en)
French (fr)
Inventor
周永祥
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武汉华星光电技术有限公司
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Priority to US16/772,782 priority Critical patent/US11328640B1/en
Publication of WO2021174607A1 publication Critical patent/WO2021174607A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display driving technology, and more specifically, to a GOA driving circuit, a display panel, and a display device.
  • TFT thin film transistor
  • PMOS type
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • GOA circuits are divided into NMOS circuits, PMOS circuits and CMOS circuits.
  • NMOS circuits do not need to perform the P-doping process, which is of great benefit to improving yield and reducing costs. Therefore, the development of stable NMOS circuits has become the common goal of the majority of developers.
  • an embodiment of the present invention provides a GOA driving circuit, which includes a plurality of cascaded GOA units, wherein the GOA unit includes:
  • the forward scanning control module is used to control the GOA drive circuit to perform forward scanning according to the constant voltage high potential signal
  • the node signal control module is used to control the GOA drive circuit to output a low-potential gate drive signal in the non-working phase
  • the output control module is used to control the output of the gate drive signal of the current level according to the clock signal of the current level
  • the voltage stabilizing module is used to maintain the level of the first node
  • the first pull-down module is used to pull down the level of the first node
  • the second pull-down module is used to pull down the level of the second node
  • the third pull-down module is used to pull down the level of the gate drive signal of the GOA unit of the current stage
  • the fourth pull-down module is used to pull down the level of the gate drive signal of the current stage when the GOA drive circuit is in the working stage according to the global signal;
  • the switch module is electrically connected between the third pull-down module and the node signal control module, and is used to maintain the level of the second node when the first node is in the charging stage according to the gate drive signal of the GOA unit of the next stage.
  • an embodiment of the present invention also provides a display panel including a GOA driving circuit;
  • the GOA driving circuit includes a plurality of cascaded GOA units;
  • the GOA unit includes:
  • the forward scanning control module is used to control the GOA drive circuit to perform forward scanning according to the constant voltage high potential signal
  • the node signal control module is used to control the GOA drive circuit to output a low-potential gate drive signal in the non-working phase
  • the output control module is used to control the output of the gate drive signal of the current level according to the clock signal of the current level
  • the voltage stabilizing module is used to maintain the level of the first node
  • the first pull-down module is used to pull down the level of the first node
  • the second pull-down module is used to pull down the level of the second node
  • the third pull-down module is used to pull down the level of the gate drive signal of the GOA unit of the current stage
  • the fourth pull-down module is used to pull down the level of the gate drive signal of the current stage when the GOA drive circuit is in the working stage according to the global signal;
  • the switch module is electrically connected between the third pull-down module and the node signal control module, and is used to maintain the level of the second node when the first node is in the charging stage according to the gate drive signal of the GOA unit of the next stage.
  • an embodiment of the present invention also provides a display device including a display panel; the display panel includes a GOA driving circuit; the GOA driving circuit includes a plurality of cascaded GOA units;
  • the GOA unit includes:
  • the forward scanning control module is used to control the GOA drive circuit to perform forward scanning according to the constant voltage high potential signal
  • the node signal control module is used to control the GOA drive circuit to output a low-potential gate drive signal in the non-working phase
  • the output control module is used to control the output of the gate drive signal of the current level according to the clock signal of the current level
  • the voltage stabilizing module is used to maintain the level of the first node
  • the first pull-down module is used to pull down the level of the first node
  • the second pull-down module is used to pull down the level of the second node
  • the third pull-down module is used to pull down the level of the gate drive signal of the GOA unit of the current stage
  • the fourth pull-down module is used to pull down the level of the gate drive signal of the current stage when the GOA drive circuit is in the working stage according to the global signal;
  • the switch module is electrically connected between the third pull-down module and the node signal control module, and is used to maintain the level of the second node when the first node is in the charging stage according to the gate drive signal of the GOA unit of the next stage.
  • the GOA drive circuit there is no need to add a reverse scan control module, a pull-up module, and a reset module, and only two CK signals are needed to complete the normal stage transfer work.
  • the GOA drive circuit is simplified and further reduced By increasing the GOA width, narrow bezels can be achieved.
  • the first CK signal is used to raise the potential of the first node
  • the second CK signal is used to raise the potential of the second node.
  • Figure 1 is a schematic diagram of the structure of a traditional GOA circuit
  • Fig. 2 is a schematic diagram of the structure of the N-th level GOA unit in a conventional GOA circuit
  • Figure 3 is a schematic diagram of the structure of the N+2 level GOA unit in the conventional GOA circuit
  • FIG. 4 is a timing diagram of the GOA circuit of the display panel of the traditional 4CK architecture
  • FIG. 5 is a schematic diagram of the first structure of the GOA driving circuit in an embodiment
  • FIG. 6 is a schematic diagram of the second structure of the GOA driving circuit in an embodiment.
  • the traditional GOA circuit is a 14T2C architecture (including 14 thin film transistors (NT1-NT14) and 2 capacitors (C1 and C2)).
  • the thin film transistor NT1-NT10, two capacitors and their networks constitute the basic circuit working structure;
  • the thin film transistor NT11 and the thin film transistor NT12 are formed in the All gate On module (that is, the pull-up module);
  • the thin film transistor NT13 forms the All Gate Off module ( Fourth pull-down module);
  • NT14 constitutes the Reset module (ie reset module);
  • the thin film transistor NT1 and the thin film transistor NT2 constitute the forward and reverse scanning control module, which has the function of forward and reverse scanning.
  • the forward scanning control signal U2D is high and reverse When the scan control signal D2U is at a low level, it scans line by line from top to bottom. On the contrary, if the forward scan control signal U2D is at a low level, and the reverse scan control signal D2U is at a high level, it scans line by line from bottom to top.
  • the circuit includes m cascaded GOA units, and the n-th GOA unit includes: forward and backward scanning control module 100, node signal control module 200, output control module 300, voltage stabilizing module 400, and first pull-down module 500, the second pull-down module 600, the third pull-down module 700, the fourth pull-down module 800, the pull-up module 900, the reset module 110, and the first capacitor C1 and the second capacitor C2, where m ⁇ n ⁇ 1.
  • the forward and reverse scanning control module 100 is used for controlling the GOA circuit to perform forward scanning or reverse scanning according to the forward scanning control signal U2D or the reverse scanning control signal D2U.
  • the node signal control module 200 is used to control the GOA unit of the current stage to output a low potential gate in the non-working stage according to the n+1th stage clock signal CK(n+1) and the n-1th stage clock signal CK(n-1).
  • the output control module 300 is used to control the output of the gate drive signal of the current stage according to the clock signal CK(n) of the current stage; the voltage stabilizing module 400 is used to maintain the level of the first node Q; the first pull-down The module 500 is used to pull down the level of the first node Q; the second pull-down module 600 is used to pull down the level of the second node P; the third pull-down module 700 is used to pull down the gate drive signal G( n) level; the fourth pull-down module 800 is used to pull down the level of the gate drive signal G(n) of the current level when the display panel is in the second working state according to the second global signal GAS2.
  • the pull-up module 900 is used for controlling the GOA unit of this stage to output a high-level gate driving signal when the display panel is in the first working state according to the first global signal GAS1.
  • the reset module 110 is used to reset the second node according to the reset signal.
  • the first working state is during the black screen touch operation or when the power is abnormally cut off. It can be understood that when the display panel is in the first working state, the first global signal GAS1 is at a high level, and all GOA units output high-level gate drive signals.
  • the second working state is a display touch operation period, at which time the second global signal GAS2 is at a high level.
  • the GOA drive architecture can adopt Interlace (interlace) architecture or dual drive architecture, and the GOA circuit uses 2 basic units as the smallest repeating unit to cycle. As shown in Figures 2 and 3, the nth-level GOA unit and the n+2th-level GOA unit can jointly form a GOA repeating unit.
  • the first clock signal CK1 to the fourth clock signal CK4 when the nth stage clock signal of the nth stage GOA unit is the first clock signal CK1, the nth stage The n+1th level clock signal of the GOA unit is the second clock signal CK2, and the n-1th level clock signal of the nth level GOA unit is the 4th clock signal CK4.
  • the n+2th level GOA unit is the nth level clock
  • the signal is the third clock signal CK3
  • the n+1th level clock signal of the n+2 level GOA unit is the 4th clock signal
  • the n-1 level clock signal of the n+2 level GOA unit is the second clock signal . It can be understood that if the node signal control module 200 of the nth level GOA unit is connected to the second and fourth clock signals, and the output control module 300 is connected to the first clock signal, then the n+1 level GOA unit
  • the node signal control module 200 is connected to the first and third clock signals, and the output control module 300 is connected to the second clock signal.
  • the duty cycle of the 4 CK signals can be 25% or less; the display panel can also use the 6CK or 8CK architecture, and the minimum repeating unit is 3 or 4 basic units, and the basic principle is similar to that of the 4CK architecture.
  • FIG. 4 shows a timing diagram of the GOA circuit corresponding to the display panel of the 4CK architecture; STVL and STVR are start signals, and the first global signal GAS1 and the second global signal GAS2 are both low when the display panel is working normally.
  • the second global signal GAS2 changes from a low level to a high level during the display period T1 (display period) into a touch period T2 (touch period).
  • the first global signal GAS1 is at TP
  • a high-level signal is superimposed on the low-level signal during the Term period (that is, the T2 period)
  • a high-level signal is superimposed on the high-level signal during the TP Term (that is, the T2 period) of the second global signal GAS2.
  • GATE_1 to GATE_4 respectively represent the first to fourth scan signals, which correspond to the gate drive signals of the first to fourth levels of GOA units, respectively.
  • the output control module 300 of the first-level GOA unit is connected to the first clock signal
  • the output control module 300 of the second-level GOA unit is connected to the second clock signal.
  • the output control module 300 of the third-level GOA unit is connected to the third clock signal
  • the output control module 300 of the fourth-level GOA unit is connected to the fourth clock signal. Therefore, when CK1 is high, G(1) is High level, so GATE_1 is also high. The rest of GATE_2 and GATE_4 are similar.
  • the scan line pauses the input of the scan signal, that is, the GOA unit corresponding to the scan line at the pause pauses output.
  • G(n-2) and U2D of the GOA unit are high.
  • the Q point is at a high potential.
  • the thin film transistor NT2 is in the off state, there will still be a certain leakage current, which reduces the stage transfer stability of the GOA circuit and affects the working stability of the GOA unit.
  • the traditional GOA circuit also has a reset module with a specific reset function, an abnormal power off (APO) mode, and the All gate off mode of the TP device.
  • this GOA architecture uses a large number of TFTs and a large number of CK signal lines.
  • the GOA circuit structure is complex, the GOA width is large, and the GOA width compression rate is low.
  • a GOA driving circuit which includes a plurality of cascaded GOA units, wherein the GOA unit includes:
  • the forward scanning control module 510 is used for controlling the GOA driving circuit to perform forward scanning according to the constant voltage high potential signal VGH;
  • the node signal control module 520 is used to control the GOA drive circuit to output a low-level gate drive signal in the non-working phase;
  • the output control module 530 is used to control the output of the gate drive signal of the current level according to the clock signal CK(n) of the current level;
  • the voltage stabilizing module 540 is used to maintain the level of the first node
  • the first pull-down module 550 is used to pull down the level of the first node
  • the second pull-down module 560 is used to pull down the level of the second node
  • the third pull-down module 570 is used to pull down the level of the gate drive signal of the GOA unit of the current stage
  • the fourth pull-down module 580 is used to pull down the level of the gate drive signal of the current stage when the GOA drive circuit is in the working stage according to the global signal;
  • the switch module 590 is electrically connected between the third pull-down module 570 and the node signal control module 520, and is used to maintain the power of the second node when the first node is in the charging phase according to the gate drive signal of the GOA unit of the next stage. flat.
  • the forward scan control module 510 is connected to the input end of the voltage stabilization module 540, the output end of the voltage stabilization module 540 is connected to the control end of the output control module 530; the node signal control module 520 is connected to the input end of the switch module 590, the switch module
  • the output terminal of 590 is connected to the control terminal of the third pull-down module 570; the input terminal of the third pull-down module 570 is used to connect the low potential signal VGL, and the output terminal is connected to the output terminal of the output control module 530; the control terminal of the second pull-down module 560
  • Connect the forward scanning control module 510 the input terminal is used to connect the low potential signal VGL, the output terminal is connected to the node signal control module 520; the control terminal of the first pull-down module 550 is connected to the control terminal of the third pull-down module 570, and the input terminal is used When the low-potential signal VGL is connected, the output terminal is connected to the forward scanning control module 510; the control terminal of the control terminal
  • the forward scanning control module 510 controls the GOA drive circuit to perform forward scanning according to the constant voltage high potential signal VGH, and the node signal control module 520 controls the GOA drive circuit to output a low potential gate drive signal in the non-working phase; voltage stabilization module 540 Used to maintain the level of the first node; the first pull-down module 550 is used to pull down the level of the first node; the second pull-down module 560 is used to pull down the level of the second node; the third pull-down module 570 is used to pull down the current The level of the gate drive signal of the GOA unit; the fourth pull-down module 580 is used to pull down the level of the gate drive signal of the current stage according to the global signal when the GOA drive circuit is in the working stage; the switch module 590 is used to according to the next stage The gate drive signal of the GOA unit maintains the level of the second node when the first node is in the charging stage; and the output control module 540 controls the output of the gate drive signal of the current stage according to the clock signal of
  • the reset module only works in the first frame, and each node will automatically reset when displayed later, so the actual effect is small.
  • there is no need to add a reverse scan control module and then The GOA circuit can be further simplified.
  • each embodiment of the GOA drive circuit described above there is no need to add a reverse scan control module, a pull-up module, and a reset module, and only two CK signals are needed to complete the normal stage transfer work, which reduces the number of signal lines used, and at the same time
  • the GOA driving circuit is simplified, the GOA width is further reduced, and a narrow frame can be realized.
  • the first CK signal is used to raise the potential of the first node
  • the second CK signal is used to raise the potential of the second node.
  • the GOA unit further includes a first charge storage module, wherein one end of the first charge storage module is connected to the first node, and the other end is used to connect a low-potential signal.
  • the first charge storage module can be used to store the charge of the first node.
  • the GOA unit further includes a second charge storage module, wherein one end of the second charge storage module is connected between the first pull-down module and the third pull-down module, and the other end is used to connect a low-potential signal.
  • the first charge storage module can be used to store the charge of the second node.
  • a GOA driving circuit including a plurality of cascaded GOA units, where the GOA unit includes a forward scanning control module 610, a node signal control module 620, and an output control module 630, the voltage stabilizing module 640, the first pull-down module 650, the second pull-down module 660, the third pull-down module 670, the fourth pull-down module 680, and are electrically connected between the third pull-down module 670 and the node signal control module 620 Switch module 690.
  • the GOA unit includes a forward scanning control module 610, a node signal control module 620, and an output control module 630, the voltage stabilizing module 640, the first pull-down module 650, the second pull-down module 660, the third pull-down module 670, the fourth pull-down module 680, and are electrically connected between the third pull-down module 670 and the node signal control module 620 Switch module 690.
  • the GOA unit also includes a first capacitor C1; the first capacitor C1 can be used to store the charge of the first node; one end of the first capacitor C1 is connected to the first node, and the other end of the first capacitor C1 is used to connect a constant voltage low potential signal VGL.
  • the first node Q is the connection point between the forward scanning control module 610 and the voltage stabilizing module 340.
  • the first capacitor C1 can store the charge of the first node, and the first capacitor C1 It can also be used to supply power to the first node, which is beneficial to the G(n) output of the GOA unit.
  • the switch module 690 includes a fifteenth thin film transistor NT15; the source of the fifteenth thin film transistor NT15 is connected to the second node, the drain is connected to the third pull-down module 670, and the gate is connected to the third pull-down module 670. Used to connect to the gate drive signal of the next-level GOA unit.
  • the second node (P) is a connection point between the node signal control module 620, the switch module 690, and the second pull-down module 660.
  • the fifteenth thin film transistor NT15 may be an NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) type TFT (Thin Film Transistor, thin film transistor) device.
  • NMOS N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor
  • TFT Thi Film Transistor, thin film transistor
  • the drain of the fifteenth thin film transistor NT15 is connected to the third pull-down module 670, and the gate of the fifteenth thin film transistor NT15 is connected to the next stage
  • the gate drive signal G(n+1) of the GOA unit Since the gate of the fifteenth thin film transistor NT15 is controlled by G(n+1), the charging stage of the second node and the first node can be staggered. Influence, and after this level is passed, raise the second node.
  • the fifteenth thin film transistor can be used to control the pull-up of the second node to avoid conflicts with the charging phase of the first node.
  • the forward scan control module 610 includes a first thin film transistor NT1; the gate of the first thin film transistor NT1 is used to connect to the gate drive signal G(n -1)
  • the source is connected to the positive DC scanning control signal VGH, and the drain is connected to the voltage regulator module.
  • the first thin film transistor NT1 may be an NMOS type TFT device.
  • the first The drain of a thin film transistor NT1 is connected to the voltage stabilizing module 640, which can realize the progressive scanning from the top to the bottom of the panel, which simplifies the structure of the GOA drive circuit, does not affect the normal GOA function, and further reduces the width of the GOA .
  • the node signal control module 620 includes an eighth thin film transistor NT8; the gate of the eighth thin film transistor NT8 is used to access the next-stage clock signal (CK(n+1)), The source is connected to a constant voltage high potential signal (VGH), and the drain is connected to the second node.
  • CK(n+1) next-stage clock signal
  • VGH constant voltage high potential signal
  • the eighth thin film transistor NT8 may be an NMOS type TFT device.
  • the gate of the eighth thin film transistor NT8 is used to connect to the next-stage clock signal (CK(n+1))
  • the source of the eighth thin film transistor NT8 is connected to the constant voltage high potential signal (VGH)
  • VGH constant voltage high potential signal
  • the second pull-down module 660 includes a sixth thin film transistor NT6; the gate of the sixth thin film transistor NT6 is connected to the drain of the first thin film transistor NT1, and the source is connected to a constant voltage low For the potential signal VGL, the drain is connected to the second node.
  • the sixth thin film transistor NT6 may be an NMOS type TFT device.
  • the gate of the sixth thin film transistor NT6 is connected to the drain of the first thin film transistor NT1
  • the source of the sixth thin film transistor NT6 is connected to the constant voltage low potential signal VGL
  • the drain of the sixth thin film transistor NT6 is connected to the The two nodes are connected, and the level of the second node can be pulled down by the sixth thin film transistor NT6.
  • the first pull-down module 650 includes a fifth thin film transistor NT5; the gate of the fifth thin film transistor NT5 is connected to the third pull-down module 670, the drain is connected to the first node, and the source The pole is connected to the constant voltage low potential signal VGL.
  • the fifth thin film transistor NT5 may be an NMOS type TFT device.
  • the drain of the fifth thin film transistor NT5 is connected to the first node, and the source of the fifth thin film transistor NT5 is connected to the constant voltage low potential signal VGL , And then the level of the first node can be pulled down by the fifth thin film transistor NT5.
  • the output control module 630 includes a ninth thin film transistor NT9; the gate of the ninth thin film transistor NT9 is connected to the voltage stabilizing module 640, and the source is connected to the clock signal CK(n) of the current stage. , The drain is connected to the third pull-down module 670.
  • the ninth thin film transistor NT9 may be an NMOS type TFT device.
  • the gate of the ninth thin film transistor NT9 is connected to the voltage stabilizing module 640, the source of the ninth thin film transistor NT9 is connected to the clock signal CK(n) of the current stage, and the drain of the ninth thin film transistor NT9 is connected to the third pull-down
  • the module 670 and the output control module 630 can control the output of the gate drive signal of the current level according to the clock signal CK(n) of the current level.
  • the fourth pull-down module 680 includes a fourteenth thin film transistor NT14; the gate of the fourteenth thin film transistor NT14 is used to connect to the drain connection of the global signal GAS2, and the source is connected to The drain of the constant voltage low potential signal VGL is connected to the drain of the output control module 630.
  • the fourteenth thin film transistor NT14 may be an NMOS type TFT device.
  • the gate of the fourteenth thin film transistor NT14 is connected to the drain connection of the global signal GAS2
  • the source of the fourteenth thin film transistor NT14 is connected to the constant voltage low potential signal VGL
  • the drain of the fourteenth thin film transistor NT14 is connected
  • the drain of the output control module 630 is connected, and the fourth pull-down module 680 can pull down the level of the gate drive signal of the current stage when the GOA drive circuit is in the working stage according to the global signal GAS2;
  • the global signal (GAS2) is pulled high, the fourteenth thin film transistor is turned on, VGH jumps to VGL, and the voltage is pulled low, so that the first node and the second node are closed to achieve no interference
  • GAS2 global signal
  • the third pull-down module 670 includes a tenth thin film transistor NT10; the gate of the tenth thin film transistor NT10 is connected to the gate of the fifth thin film transistor NT5, and the source of the tenth thin film transistor NT10 is connected to Input the constant voltage low potential signal VGL, the drain of the tenth thin film transistor NT10 is connected to the drain of the ninth thin film transistor NT9, and the gate driving signal G(n) of the current stage can be pulled down through the tenth thin film transistor NT10.
  • the voltage stabilizing module 640 includes a seventh thin film transistor NT7; the gate of the seventh thin film transistor NT7 is connected to the constant voltage high potential signal VGH, and the source of the seventh thin film transistor NT7 is connected to the first At node Q, the drain of the seventh thin film transistor NT7 is connected to the gate of the ninth thin film transistor NT9, and the level of the first node Q can be maintained by the seventh thin film transistor NT7.
  • the GOA unit further includes a second capacitor C2; the second capacitor C2 can be used to store the charge of the second node; one end of the second capacitor C2 is connected to the drain of the fifteenth thin film transistor NT15 , The other end of the second capacitor C2 is used to connect the constant voltage low potential signal VGL.
  • the second capacitor C2 can store the charge of the second node
  • the second capacitor C2 can also be used to supply power to the second node, which is beneficial to the G(n) output of the GOA unit.
  • the GOA drive circuit of the present application does not need to add a reverse scan control module, a pull-up module, and a reset module. It only needs to use 2 CK signals to complete the normal stage transfer work, while simplifying the GOA drive circuit and further reducing GOA width, which in turn can achieve a narrow frame.
  • the first CK signal is used to raise the potential of the first node
  • the second CK signal is used to raise the potential of the second node.
  • a display panel is also provided, and the display panel includes the GOA driving circuit as described above.
  • the display panel can be a liquid crystal display panel, or an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display panel.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • the GOA drive circuit's gate line-by-line normal opening function is realized, and the GOA width is greatly reduced to achieve a narrow frame. Design, and the process risk and stability are also improved, so that the efficiency and stability are improved.
  • a display device including the above-mentioned display panel.
  • the display device can be, but is not limited to, a mobile phone, a TV, and a tablet computer.
  • the display device by using fewer thin film transistors and only using 2 CK signals, the number of signal lines is reduced, and the gate-by-line normal opening function of the GOA driving circuit is realized, and the GOA is greatly reduced. Width, the design of narrow frame is realized, and the process risk and stability are also improved, so that the efficiency and stability are improved.

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Abstract

提供了一种GOA驱动电路、显示面板及显示装置。该GOA驱动电路包括多个级联的GOA单元，GOA单元包括输出控制模块（530），稳压模块（540），第一下拉模块（550），第二下拉模块（560），第三下拉模块（570），第四下拉模块（580），正向扫描控制模块（510），节点信号控制模块（520）以及开关模块（590）。只需用到2个CK信号，减少了信号线数量，极大地降低GOA宽度，实现窄边框的设计。

Description

GOA驱动电路、显示面板及显示装置 技术领域
本申请涉及显示驱动技术领域，更具体地说，涉及一种GOA驱动电路、显示面板及显示装置。
 背景技术
当今社会科技迅猛发展，手机、电脑和电视等电子产品广泛应用于生活中的各个方面。因此，液晶显示面板和OLED显示面板等电子显示屏被广泛采用，而Gate Driver On Array（GOA）电路是显示面板中的一个重要组成部分。它是在阵列基板上制作薄膜晶体管（TFT）作为开关，从而将栅级驱动制作在阵列基板上，实现栅极的逐行扫描。
根据面板内采用的薄膜晶体管（TFT）类型，可以分为NMOS型，PMOS型，以及CMOS。类似的，根据采用的TFT类型，GOA电路分为NMOS电路，PMOS电路以及CMOS电路。比于CMOS电路，NMOS电路无需进行P掺杂这一工序，对于提高良率以及降低成本都大有裨益，因此开发稳定的NMOS电路成为广大研发人员的共同目标。
随着全面屏成为一种潮流趋势，这就对手机，平板电脑和电视等的边框提出了越来越高的要求，因此压缩GOA的宽度成为降低左右border的一种常见手段。
 技术问题
在实现过程中，发明人发现传统技术中至少存在如下问题：传统的GOA电路结构复杂，GOA宽度大，GOA的宽度压缩率低。
 技术解决方案
基于此，有必要传统的GOA电路结构复杂，GOA宽度大，GOA的宽度压缩率低的问题，提供一种GOA驱动电路、显示面板及显示装置。
为了实现上述目的，本发明实施例提供了一种GOA驱动电路，包括多个级联的GOA单元，其中，GOA单元包括：
正向扫描控制模块，用于根据恒压高电位信号控制GOA驱动电路进行正向扫描；
节点信号控制模块，用于控制GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；
输出控制模块，用于根据本级时钟信号控制本级栅极驱动信号的输出；
稳压模块，用于维持第一节点的电平；
第一下拉模块，用于下拉第一节点的电平；
第二下拉模块，用于下拉第二节点的电平；
第三下拉模块，用于下拉本级GOA单元的栅极驱动信号的电平；
第四下拉模块，用于根据全局信号在GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
开关模块，电性连接在第三下拉模块与节点信号控制模块之间，用于根据下一级GOA单元的栅极驱动信号，在第一节点处于充电阶段时维持第二节点的电平。
另一方面，本发明实施例还提供了一种显示面板，包括GOA驱动电路；GOA驱动电路包括多个级联的GOA单元；
其中，GOA单元包括：
正向扫描控制模块，用于根据恒压高电位信号控制GOA驱动电路进行正向扫描；
节点信号控制模块，用于控制GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；
输出控制模块，用于根据本级时钟信号控制本级栅极驱动信号的输出；
稳压模块，用于维持第一节点的电平；
第一下拉模块，用于下拉第一节点的电平；
第二下拉模块，用于下拉第二节点的电平；
第三下拉模块，用于下拉本级GOA单元的栅极驱动信号的电平；
第四下拉模块，用于根据全局信号在GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
开关模块，电性连接在第三下拉模块与节点信号控制模块之间，用于根据下一级GOA单元的栅极驱动信号，在第一节点处于充电阶段时维持第二节点的电平。
另一方面，本发明实施例还提供了一种显示装置，包括显示面板；显示面板包括GOA驱动电路；GOA驱动电路包括多个级联的GOA单元；
其中，GOA单元包括：
正向扫描控制模块，用于根据恒压高电位信号控制GOA驱动电路进行正向扫描；
节点信号控制模块，用于控制GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；
输出控制模块，用于根据本级时钟信号控制本级栅极驱动信号的输出；
稳压模块，用于维持第一节点的电平；
第一下拉模块，用于下拉第一节点的电平；
第二下拉模块，用于下拉第二节点的电平；
第三下拉模块，用于下拉本级GOA单元的栅极驱动信号的电平；
第四下拉模块，用于根据全局信号在GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
开关模块，电性连接在第三下拉模块与节点信号控制模块之间，用于根据下一级GOA单元的栅极驱动信号，在第一节点处于充电阶段时维持第二节点的电平。
 有益效果
上述的GOA驱动电路的各实施例中，无需增加反向扫描控制模块、上拉模块和复位模块，只需要采用2个CK信号即可完成正常级传工作，同时简化了GOA驱动电路，进一步降低了GOA宽度，进而能够实现窄边框。其中，第一CK信号用于拉高第一节点电位，第二CK信号用于拉高第二节点电位。通过增加开关模块，进而能够避免第一节点充电阶段，与第二节点发生竞争冲突，能够实现第二节点与第一节点充电阶段错开，互不影响。本申请通过采用较少的薄膜晶体管，并且只需用到2个CK信号，减少信号线数量，极大地降低GOA宽度，实现窄边框的设计。制程风险和稳定性也得到提高，使得效率和稳定性提高。
 附图说明
下面将结合附图及实施例对本申请作进一步说明，附图中：
图1为传统GOA电路的结构示意图；
图2为传统GOA电路中的第N级GOA单元的结构示意图；
图3为传统GOA电路中的第N+2级GOA单元的结构示意图；
图4为传统4CK架构的显示面板的GOA电路的时序图；
图5为一个实施例中GOA驱动电路的第一结构示意图；
图6为一个实施例中GOA驱动电路的第二结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
为了对本申请的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本申请的具体实施方式。
如图1所示，传统的GOA电路为14T2C架构（包括14个薄膜晶体管（NT1-NT14）和2个电容（C1和C2））。其中，薄膜晶体管NT1-NT10、两个电容及其网络，构成基本电路工作架构；薄膜晶体管NT11和薄膜晶体管NT12构成在All gate On模块（即上拉模块）；薄膜晶体管NT13构成All Gate Off模块（第四下拉模块）；NT14构成Reset模块（即复位模块）；薄膜晶体管NT1和薄膜晶体管NT2构成正反向扫描控制模块，具有正反扫功能，正向扫描控制信号U2D为高电平，反向扫描控制信号D2U为低电平则由上向下逐行扫描，反之，正向扫描控制信号U2D为低电平，反向扫描控制信号D2U为高电平，则由下向上逐行扫描。
具体地，该电路包括m个级联的GOA单元，第n级GOA单元包括：正反向扫描控制模块100、节点信号控制模块200、输出控制模块300、稳压模块400、第一下拉模块500、第二下拉模块600、第三下拉模块700、第四下拉模块800、上拉模块900、复位模块110以及第一电容C1和第二电容C2，其中m≥n≥1。
正反向扫描控制模块100，用于根据正向扫描控制信号U2D或反向扫描控制信号D2U控制GOA电路进行正向扫描或反向扫描。节点信号控制模块200，用于根据第n+1级时钟信号CK(n+1)和第n-1级时钟信号CK(n-1)控制本级GOA单元在非工作阶段输出低电位的栅极驱动信号；输出控制模块300，用于根据本级时钟信号CK(n)控制本级栅极驱动信号的输出；稳压模块400，用于维持第一节点Q的电平；第一下拉模块500，用于下拉所述第一节点Q的电平；第二下拉模块600，用于下拉第二节点P的电平；第三下拉模块700，用于下拉本级栅极驱动信号G(n)的电平；第四下拉模块800用于根据第二全局信号GAS2在显示面板处于第二工作状态时下拉本级栅极驱动信号G(n)的电平。上拉模块900、用于根据第一全局信号GAS1在显示面板处于第一工作状态时控制本级GOA单元输出高电平的栅极驱动信号。复位模块110，用于根据复位信号对第二节点进行复位。第一工作状态为黑屏触控工作期间或者异常断电时。可以理解的，当显示面板处于第一工作状态时，第一全局信号GAS1为高电平，所有GOA单元都输出高电平的栅极驱动信号。第二工作状态为显示触控工作期间，此时第二全局信号GAS2为高电平。
当显示面板处于正向扫描状态时，U2D为高电平，D2U为低电平，此时GOA电路则由上向下逐行扫描。反之，当显示面板处于反向扫描状态时，U2D为低电平，D2U为高电平，此时GOA电路则由下向上逐行扫描。
当显示面板为4CK架构时，GOA 驱动架构可以采用Interlace（交错）架构或者双驱架构，GOA电路以2个基本单元为最小重复单元进行循环。如图2和3所示，第n级GOA单元和第n+2级GOA单元可以共同构成一个GOA重复单元。结合图4，GOA电路中共有4个时钟信号CK；第1时钟信号CK1至第4条时钟信号CK4，当第n级GOA单元的第n级时钟信号为第1时钟信号CK1时，第n级GOA单元的第n+1级时钟信号为第2时钟信号CK2，第n级GOA单元的第n-1级时钟信号为第4时钟信号CK4，当第n+2级GOA单元的第n级时钟信号为第3时钟信号CK3时，第n+2级GOA单元的第n+1级时钟信号为第4时钟信号，第n+2级GOA单元的第n-1级时钟信号为第2时钟信号。可以理解的，如果第n级GOA单元的节点信号控制模块200对应接入的是第2和第4时钟信号，输出控制模块300接入的是第1时钟信号，那么第n+1级GOA单元的节点信号控制模块200接入的就是第1条和第3条时钟信号，输出控制模块300接入的是第2时钟信号。
需要说明的是，4个CK信号的占空比可以是25%或以下；显示面板也可使用6CK或8CK架构，最小重复单元为3或4个基本单元，基本原理与4CK架构的类似。
图4所示为4CK架构的显示面板对应的GOA电路的时序图；STVL、STVR为启动信号，第一全局信号GAS1和第二全局信号GAS2在显示面板正常工作时都为低电平。第二全局信号GAS2在显示期间T1（显示期间）转换为触控期间T2（触控期间）由低电平变为高电平。进一步的，第一全局信号GAS1在TP Term期间（即T2期间）在低电平信号上叠加一个高电平信号，第二全局信号GAS2在TP Term期间（即T2期间）在高电平信号上叠加一个高电平信号。
其中GATE_1至GATE_4分别表示第1至4条扫描信号，分别对应第1至4级GOA单元的栅极驱动信号。
可以理解的，如果第1级GOA单元的输出控制模块300接入的是第1时钟信号，第2级GOA单元输出控制模块300接入的是第2时钟信号。第3级GOA单元的输出控制模块300接入的是第3时钟信号，第4级GOA单元输出控制模块300接入的是第4时钟信号，因此当CK1为高点平时，G(1)为高电平，因而GATE_1也为高电平。其余GATE_2与GATE_4与此类似。
如图1所示，在TP Term期间，扫描线暂停输入扫描信号，也即暂停处对应扫描线的GOA单元暂停输出，此时该GOA单元的G(n-2)以及U2D为高电平，Q点处于高电位，然而虽然薄膜晶体管NT2处于断开状态，但是也会存在一定的漏电流，降低了GOA电路的级传稳定性，影响了GOA单元的工作稳定性。
可知，传统GOA电路，除了正常GOA级传功能外，还具有具体复位功能的复位模块，异常断电（Abnormal Power Off ，APO）模式，以及TP器件的All gate off模式。但是这个GOA架构所采用的TFT数量较多，并且CK信号线数量也较多，进而GOA电路结构复杂，GOA宽度大，GOA的宽度压缩率低。
为了传统的GOA电路结构复杂，GOA宽度大，GOA的宽度压缩率低的问题。在一个实施例中，如图5所示，提供了一种GOA驱动电路，包括多个级联的GOA单元，其中，GOA单元包括：
正向扫描控制模块510，用于根据恒压高电位信号VGH控制GOA驱动电路进行正向扫描；
节点信号控制模块520，用于控制GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；
输出控制模块530，用于根据本级时钟信号CK（n）控制本级栅极驱动信号的输出；
稳压模块540，用于维持第一节点的电平；
第一下拉模块550，用于下拉第一节点的电平；
第二下拉模块560，用于下拉第二节点的电平；
第三下拉模块570，用于下拉本级GOA单元的栅极驱动信号的电平；
第四下拉模块580，用于根据全局信号在GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
开关模块590，电性连接在第三下拉模块570与节点信号控制模块520之间，用于根据下一级GOA单元的栅极驱动信号，在第一节点处于充电阶段时维持第二节点的电平。
具体地，基于正向扫描控制模块510连接稳压模块540的输入端，稳压模块540的输出端连接输出控制模块530的控制端；节点信号控制模块520连接开关模块590的输入端，开关模块590的输出端连接第三下拉模块570的控制端；第三下拉模块570的输入端用于接入低电位信号VGL，输出端连接输出控制模块530的输出端；第二下拉模块560的控制端连接正向扫描控制模块510，输入端用于接入低电位信号VGL，输出端连接节点信号控制模块520；第一下拉模块550的控制端连接第三下拉模块570的控制端，输入端用于接入低电位信号VGL，输出端连接正向扫描控制模块510；第四下拉模块580的控制端用于接入全局信号GAS2，输入端用于接入低电位信号VGL，输出端连接输出控制模块530的输出端。
正向扫描控制模块510根据恒压高电位信号VGH控制GOA驱动电路进行正向扫描，通过节点信号控制模块520来控制GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；稳压模块540用来维持第一节点的电平；第一下拉模块550用来下拉第一节点的电平；第二下拉模块560用来下拉第二节点的电平；第三下拉模块570用来下拉本级GOA单元的栅极驱动信号的电平；第四下拉模块580用来根据全局信号在GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；开关模块590用来根据下一级GOA单元的栅极驱动信号，在第一节点处于充电阶段时维持第二节点的电平；进而输出控制模块540根据本级时钟信号控制本级栅极驱动信号的输出，实现GOA单元的正常级传工作。
进一步的，由于在显示面板实际使用过程中极少发生异常断电的现象，并且异常断电时开机会重新复位，画面正常显示，不影响正常的GOA功能。上述实施例中，无需增加上拉模块，进而精简了GOA电路。
在显示面板实际使用过程中，只需要从一个方向进行扫描，通常GOA开启都是从面板上部到下部的逐行开启，反扫功能更多用于检测的时候，或正扫模块发生异常，用于替代正扫。上述实施例中，无需增加反向扫描控制模块，进而进一步的简化电路架构，实现窄边框。
在显示面板实际使用过程中，复位模块只在第一帧的时候起作用，后面显示的时候各个节点会自动复位，因此实际作用较小，上述实施例中，无需增加反向扫描控制模块，进而可进一步的简化GOA电路。
上述的GOA驱动电路的各实施例中，无需增加反向扫描控制模块、上拉模块和复位模块，只需要采用2个CK信号即可完成正常级传工作，降低了使用的信号线数量，同时简化了GOA驱动电路，进一步降低了GOA宽度，进而能够实现窄边框。其中，第一CK信号用于拉高第一节点电位，第二CK信号用于拉高第二节点电位。通过增加开关模块，进而能够避免第一节点充电阶段，与第二节点发生竞争冲突，能够实现第二节点与第一节点充电阶段错开，互不影响。本申请通过采用较少的薄膜晶体管，并且只需用到2个CK信号，减少了信号线数量，极大地降低GOA宽度，实现窄边框的设计。制程风险和稳定性也得到提高，使得效率和稳定性提高。
在一个示例中，GOA单元还包括第一电荷存储模块，其中，第一电荷存储模块的一端与第一节点连接，另一端用于接入低电位信号。第一电荷存储模块可用来存储第一节点的电荷。
在一个示例中，GOA单元还包括第二电荷存储模块，其中，第二电荷存储模块的一端连接在第一下拉模块与第三下拉模块之间，另一端用于接入低电位信号。第一电荷存储模块可用来存储第二节点的电荷。
在一个实施例中，如图6所示，提供了一种GOA驱动电路，包括多个级联的GOA单元，其中，GOA单元包括正向扫描控制模块610，节点信号控制模块620，输出控制模块630，稳压模块640，第一下拉模块650，第二下拉模块660，第三下拉模块670，第四下拉模块680，以及电性连接在第三下拉模块670与节点信号控制模块620之间开关模块690。GOA单元还包括第一电容C1；第一电容C1可用于存储第一节点的电荷；第一电容C1的一端与第一节点连接，第一电容C1的另一端用于接入恒压低电位信号VGL。其中，第一节点Q为正向扫描控制模块610与稳压模块340之间的连接点。
具体地，基于第一电容C1的一端连接第一节点，第一电容C1的另一端用于接入恒压低电位信号VGL，进而第一电容C1可存储第一节点的电荷，第一电容C1还可用来向第一节点供电，有利于GOA单元的G（n）输出。
在一个实施例中，如图6所示，开关模块690包括第十五薄膜晶体管NT15；第十五薄膜晶体管NT15的源极与第二节点连接，漏极与第三下拉模块670连接，栅极用于接入下一级GOA单元的栅极驱动信号。其中，第二节点（P）为节点信号控制模块620、开关模块690和第二下拉模块660之间的连接点。
其中，第十五薄膜晶体管NT15可以是NMOS（N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体）型TFT（Thin Film Transistor，薄膜晶体管）器件。
具体地，基于第十五薄膜晶体管NT15的源极与第二节点连接，第十五薄膜晶体管NT15的漏极与第三下拉模块670连接，第十五薄膜晶体管NT15的栅极接入下一级GOA单元的栅极驱动信号G（n+1），由于第十五薄膜晶体管NT15的栅极是由G（n+1）控制，从而能够实现第二节点与第一节点充电阶段错开，互不影响，且在本级级传之后，再拉高第二节点。
上述实施例中，通过增加了一个第十五薄膜晶体管，进而可通过第十五薄膜晶体管控制第二节点的上拉，避免与第一节点的充电阶段发生冲突。
在一个实施例中，如图6所示，正向扫描控制模块610包括第一薄膜晶体管NT1；第一薄膜晶体管NT1的栅极用于接入上一级GOA单元的栅极驱动信号G（n-1），源极接入正向直流扫描控制信号VGH，漏极与稳压模块连接。
其中，第一薄膜晶体管NT1可以是NMOS型TFT器件。
具体地，基于第一薄膜晶体管NT1的栅极接入上一级GOA单元的栅极驱动信号G（n-1），第一薄膜晶体管NT1的源极接入正向直流扫描控制信号VGH，第一薄膜晶体管NT1的漏极与稳压模块640连接，进而能够实现面板上部到下部的逐行扫描开启，简化了GOA驱动电路结构，在不影响正常的GOA功能，同时进一步的降低了GOA的宽度。
在一个实施例中，如图6所示，节点信号控制模块620包括第八薄膜晶体管NT8；第八薄膜晶体管NT8的栅极用于接入下一级时钟信号（CK（n+1）），源极接入恒压高电位信号（VGH），漏极与第二节点连接。
其中，第八薄膜晶体管NT8可以是NMOS型TFT器件。
具体地，基于第八薄膜晶体管NT8的栅极用于接入下一级时钟信号（CK（n+1）），第八薄膜晶体管NT8的源极接入恒压高电位信号（VGH），第八薄膜晶体管NT8的漏极与第二节点连接，进而在第八薄膜晶体管NT8导通时，能够向第二节点供电。
在一个实施例中，如图6所示，第二下拉模块660包括第六薄膜晶体管NT6；第六薄膜晶体管NT6的栅极与第一薄膜晶体管NT1的漏极连接，源极接入恒压低电位信号VGL，漏极与第二节点连接。
其中，第六薄膜晶体管NT6可以是NMOS型TFT器件。
具体地，基于第六薄膜晶体管NT6的栅极与第一薄膜晶体管NT1的漏极连接，第六薄膜晶体管NT6的源极接入恒压低电位信号VGL，第六薄膜晶体管NT6的漏极与第二节点连接，进而可通过第六薄膜晶体管NT6下拉第二节点的电平。
在一个实施例中，如图6所示，第一下拉模块650包括第五薄膜晶体管NT5；第五薄膜晶体管NT5的栅极与第三下拉模块670连接，漏极与第一节点连接，源极接入恒压低电位信号VGL。
其中，第五薄膜晶体管NT5可以是NMOS型TFT器件。
具体地，基于第五薄膜晶体管NT5的栅极与第三下拉模块670连接，第五薄膜晶体管NT5的漏极与第一节点连接，第五薄膜晶体管NT5的源极接入恒压低电位信号VGL，进而可通过第五薄膜晶体管NT5下拉第一节点的电平。
在一个实施例中，如图6所示，输出控制模块630包括第九薄膜晶体管NT9；第九薄膜晶体管NT9的栅极与稳压模块640连接，源极接入本级时钟信号CK（n），漏极与第三下拉模块670连接。
其中，第九薄膜晶体管NT9可以是NMOS型TFT器件。
具体地，基于第九薄膜晶体管NT9的栅极与稳压模块640连接，第九薄膜晶体管NT9的源极接入本级时钟信号CK（n），第九薄膜晶体管NT9的漏极连接第三下拉模块670，进而输出控制模块630可根据本级时钟信号CK（n），控制本级栅极驱动信号的输出。
在一个实施例中，如图6所示，第四下拉模块680包括第十四薄膜晶体管NT14；第十四薄膜晶体管NT14的栅极用于接入全局信号GAS2的漏极连接，源极接入恒压低电位信号VGL，漏极与输出控制模块630的漏极连接。
其中，第十四薄膜晶体管NT14可以是NMOS型TFT器件。
具体地，基于第十四薄膜晶体管NT14的栅极接入全局信号GAS2的漏极连接，第十四薄膜晶体管NT14的源极接入恒压低电位信号VGL，第十四薄膜晶体管NT14的漏极连接输出控制模块630的漏极，进而第四下拉模块680可根据全局信号GAS2，在GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
进一步的，在TP Term（触控）阶段，全局信号（GAS2）拉高，第十四薄膜晶体管打开，VGH跳变成VGL，电压拉低，从而第一节点和第二节点关闭，实现不干扰第十四薄膜晶体管的输出。
在一个示例中，如图6所示，第三下拉模块670包括第十薄膜晶体管NT10；第十薄膜晶体管NT10的栅极连接第五薄膜晶体管NT5的栅极，第十薄膜晶体管NT10的源极接入恒压低电位信号VGL，第十薄膜晶体管NT10的漏极连接第九薄膜晶体管NT9的漏极，进而可通过第十薄膜晶体管NT10可下拉本级栅极驱动信号G（n）。
在一个示例中，如图6所示，稳压模块640包括第七薄膜晶体管NT7；第七薄膜晶体管NT7的栅极接入恒压高电位信号VGH，第七薄膜晶体管NT7的源极连接第一节点Q，第七薄膜晶体管NT7的漏极连接第九薄膜晶体管NT9的栅极，进而可通过第七薄膜晶体管NT7可维持第一节点Q的电平。
在一个示例中，如图6所示，GOA单元还包括第二电容C2；第二电容C2可用于存储第二节点的电荷；第二电容C2的一端与第十五薄膜晶体管NT15的漏极连接，第二电容C2的另一端用于接入恒压低电位信号VGL。
具体地，基于第二电容C2的一端与第十五薄膜晶体管NT15的漏极连接，第二电容C2的另一端接入恒压低电位信号VGL，进而第二电容C2可存储第二节点的电荷，第二电容C2还可用来向第二节点供电，有利于GOA单元的G（n）输出。
具体而言，本申请的GOA驱动电路无需增加反向扫描控制模块、上拉模块和复位模块，只需要采用2个CK信号即可完成正常级传工作，同时简化了GOA驱动电路，进一步降低了GOA宽度，进而能够实现窄边框。其中，第一CK信号用于拉高第一节点电位，第二CK信号用于拉高第二节点电位。通过增加第十五薄膜晶体管，进而能够避免第一节点充电阶段，与第二节点发生竞争冲突，能够实现第二节点与第一节点充电阶段错开，互不影响。本申请通过采用较少的薄膜晶体管，并且只需用到2个CK信号，极大地降低GOA宽度，实现窄边框的设计。制程风险和稳定性也得到提高，使得效率和稳定性提高。
在一个实施例中，还提供了一种显示面板，该显示面板包括如上述任意一项的GOA驱动电路。
其中，该显示面板可以是液晶显示面板，还可以是OLED（Organic Light-Emitting Diode，有机发光二极管）显示面板。
上述的显示面板实施例中，通过采用较少的薄膜晶体管，并且只需用到2个CK信号，在实现GOA驱动电路的gate逐行正常打开功能，同时极大地降低GOA宽度，实现窄边框的设计，且制程风险和稳定性也得到提高，使得效率和稳定性提高。
关于显示面板的具体限定可以参见上文中对于GOA驱动电路的限定，在此不再赘述。
在一个实施例中，还提供了一种显示装置，包括如上述的显示面板。
其中，显示装置可以但不限于是手机，电视和平板电脑。
上述的显示装置实施例中，通过采用较少的薄膜晶体管，并且只需用到2个CK信号，降低了信号线数量，在实现GOA驱动电路的gate逐行正常打开功能，同时极大地降低GOA宽度，实现窄边框的设计，且制程风险和稳定性也得到提高，使得效率和稳定性提高。
关于显示装置的具体限定可以参见上文中对于显示面板以及GOA驱动电路的限定，在此不再赘述。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种GOA驱动电路，其特征在于其中，包括多个级联的GOA单元，其中，所述GOA单元包括：
    正向扫描控制模块，用于根据恒压高电位信号控制所述GOA驱动电路进行正向扫描；
    节点信号控制模块，用于控制所述GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；
    输出控制模块，用于根据本级时钟信号控制本级栅极驱动信号的输出；
    稳压模块，用于维持第一节点的电平；
    第一下拉模块，用于下拉所述第一节点的电平；
    第二下拉模块，用于下拉第二节点的电平；
    第三下拉模块，用于下拉本级所述GOA单元的栅极驱动信号的电平；
    第四下拉模块，用于根据全局信号在所述GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
    开关模块，电性连接在所述第三下拉模块与所述节点信号控制模块之间，用于根据下一级所述GOA单元的栅极驱动信号，在所述第一节点处于充电阶段时维持所述第二节点的电平。
  2. 根据权利要求1所述的GOA驱动电路，其中其特征在于，所述GOA单元还包括：
    第一电容，用于存储所述第一节点的电荷；所述第一电容的一端与所述第一节点连接，所述第一电容的另一端用于接入恒压低电位信号；
    其中，所述第一节点为所述正向扫描控制模块与所述稳压模块之间的连接点。
  3. 根据权利要求1所述的GOA驱动电路，其中其特征在于，所述开关模块包括第十五薄膜晶体管；
    所述第十五薄膜晶体管的源极与所述第二节点连接，漏极与所述第三下拉模块连接，栅极用于接入下一级所述GOA单元的栅极驱动信号；
    其中，所述第二节点为所述节点信号控制模块、所述开关模块和所述第二下拉模块之间的连接点。
  4. 根据权利要求3所述的GOA驱动电路，其中其特征在于，所述正向扫描控制模块包括第一薄膜晶体管；所述第一薄膜晶体管的栅极用于接入上一级所述GOA单元的栅极驱动信号，源极接入所述正向直流扫描控制信号，漏极与所述稳压模块连接；
    所述节点信号控制模块包括第八薄膜晶体管；所述第八薄膜晶体管的栅极用于接入下一级时钟信号，源极接入所述恒压高电位信号，漏极与所述第二节点连接。
  5. 根据权利要求4所述的GOA驱动电路，其中其特征在于，所述第二下拉模块包括第六薄膜晶体管；
    所述第六薄膜晶体管的栅极与所述第一薄膜晶体管的漏极连接，源极接入恒压低电位信号，漏极与所述第二节点连接。
  6. 根据权利要求4所述的GOA驱动电路，其中其特征在于，所述第一下拉模块包括第五薄膜晶体管；
    所述第五薄膜晶体管的栅极与所述第三下拉模块连接，漏极与所述第一节点连接，源极接入恒压低电位信号。
  7. 根据权利要求1所述的GOA驱动电路，其中其特征在于，所述输出控制模块包括第九薄膜晶体管；
    所述第九薄膜晶体管的栅极与所述稳压模块连接，源极接入本级时钟信号，漏极与所述第三下拉模块连接。
  8. 根据权利要求7所述的GOA驱动电路，其中其特征在于，所述第四下拉模块包括第十四薄膜晶体管；
    所述第十四薄膜晶体管的栅极用于接入所述全局信号的漏极连接，源极接入恒压低电位信号，漏极与所述输出控制模块的漏极连接。
  9. 一种显示面板，其特征在于其中，包括如权利要求1至8中任意一项所述的GOA驱动电路；所述GOA驱动电路包括多个级联的GOA单元；
    其中，所述GOA单元包括：
    正向扫描控制模块，用于根据恒压高电位信号控制所述GOA驱动电路进行正向扫描；
    节点信号控制模块，用于控制所述GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；
    输出控制模块，用于根据本级时钟信号控制本级栅极驱动信号的输出；
    稳压模块，用于维持第一节点的电平；
    第一下拉模块，用于下拉所述第一节点的电平；
    第二下拉模块，用于下拉第二节点的电平；
    第三下拉模块，用于下拉本级所述GOA单元的栅极驱动信号的电平；
    第四下拉模块，用于根据全局信号在所述GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
    开关模块，电性连接在所述第三下拉模块与所述节点信号控制模块之间，用于根据下一级所述GOA单元的栅极驱动信号，在所述第一节点处于充电阶段时维持所述第二节点的电平。
  10. 一种显示装置，其特征在于其中，包括如权利要求9所述的显示液晶面板；所述显示面板包括GOA驱动电路；
    所述GOA驱动电路包括多个级联的GOA单元；
    其中，所述GOA单元包括：
    正向扫描控制模块，用于根据恒压高电位信号控制所述GOA驱动电路进行正向扫描；
    节点信号控制模块，用于控制所述GOA驱动电路在非工作阶段输出低电位的栅极驱动信号；
    输出控制模块，用于根据本级时钟信号控制本级栅极驱动信号的输出；
    稳压模块，用于维持第一节点的电平；
    第一下拉模块，用于下拉所述第一节点的电平；
    第二下拉模块，用于下拉第二节点的电平；
    第三下拉模块，用于下拉本级所述GOA单元的栅极驱动信号的电平；
    第四下拉模块，用于根据全局信号在所述GOA驱动电路处于工作阶段时下拉本级栅极驱动信号的电平；
    开关模块，电性连接在所述第三下拉模块与所述节点信号控制模块之间，用于根据下一级所述GOA单元的栅极驱动信号，在所述第一节点处于充电阶段时维持所述第二节点的电平。
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