WO2021022478A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2021022478A1
WO2021022478A1 PCT/CN2019/099443 CN2019099443W WO2021022478A1 WO 2021022478 A1 WO2021022478 A1 WO 2021022478A1 CN 2019099443 W CN2019099443 W CN 2019099443W WO 2021022478 A1 WO2021022478 A1 WO 2021022478A1
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WIPO (PCT)
Prior art keywords
signal
circuit
node
shift register
terminal
Prior art date
Application number
PCT/CN2019/099443
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English (en)
French (fr)
Inventor
宗少雷
孙伟
王洁琼
孙继刚
李付强
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/099443 priority Critical patent/WO2021022478A1/zh
Priority to CN201980001274.3A priority patent/CN110582805A/zh
Publication of WO2021022478A1 publication Critical patent/WO2021022478A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, in particular to a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • the gate driver on array (GOA) technology used for display driving is to fabricate a gate driver circuit on an array substrate to realize the function of scanning pixels line by line.
  • the gate driving circuit may include a plurality of cascaded shift registers. The scan signal is output from the shift register to drive the pixels, and the cascade signal can be output at the same time to drive the next-stage shift register, thereby sequentially driving the entire display device for display.
  • the embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • a shift register including a start circuit and a shift register circuit.
  • the startup circuit is configured to provide one of the startup input signal from the startup input signal terminal and the startup control signal from the startup control signal terminal to the shift register circuit as an input signal via the first node according to the startup selection signal from the startup selection signal terminal.
  • the shift register circuit is configured to provide a scan driving signal through the output terminal according to the input signal and the first clock signal from the first clock signal terminal.
  • the start circuit is configured to store and maintain the start set signal from the start set signal terminal according to the start input signal in the first stage.
  • the startup circuit is configured to provide the startup control signal to the shift register circuit as an input signal via the first node according to the held startup set signal in the second stage.
  • the start circuit includes a start input circuit, a start holding circuit, a start output circuit, and a start selection circuit.
  • the start input circuit is configured to provide the start set signal to the second node according to the start input signal.
  • the start and hold circuit is configured to store and maintain the start set signal.
  • the start output circuit is configured to provide the start control signal to the shift register circuit as an input signal via the first node according to the held start set signal.
  • the start selection circuit is configured to provide a start input signal to the shift register via the first node as the input signal according to the start selection signal.
  • the startup circuit further includes a startup reset circuit configured to reset the second node according to the startup reset signal from the startup reset signal terminal.
  • the activation input circuit includes a first transistor, the control electrode of the first transistor is coupled to the activation input signal terminal, the first electrode of the first transistor is coupled to the activation setting signal terminal, and the first transistor The second pole is coupled to the second node.
  • the startup and hold circuit includes a first capacitor, the first pole of the capacitor is coupled to the second node, and the second pole of the capacitor is coupled to the first node.
  • the output sub-circuit includes a second transistor, the control electrode of the second transistor is coupled to the second node, the first electrode of the second transistor is coupled to the start control signal terminal, and the first electrode of the second transistor is The two poles are coupled to the first node.
  • the activation selection circuit includes a third transistor, the control electrode of the third transistor is coupled to the activation selection signal terminal, the first electrode of the third transistor is coupled to the activation input signal terminal, and the The second pole is coupled to the first node.
  • the start-up reset circuit includes a fourth transistor, the control electrode of the fourth transistor is coupled to the start-up reset signal terminal, the first electrode of the fourth transistor is coupled to the second node, and the second node of the fourth transistor is The two poles are coupled to the first voltage terminal.
  • the shift register circuit includes an input circuit, an output circuit, a pull-down control circuit, a pull-down circuit, a display reset circuit, and a blanking reset circuit.
  • the input circuit is coupled to the second node, the third node and the first control signal terminal, and is configured to provide the first control signal to the third node according to the input signal.
  • the output circuit is coupled to the third node, the first clock signal terminal and the output terminal, and is configured to provide a scan driving signal via the output terminal according to the voltage of the third node and the first clock signal from the first clock signal terminal.
  • the pull-down control circuit is coupled to the second clock signal terminal, the fourth node, the third node, the first voltage terminal and the output terminal, and is configured to convert the first voltage from the first voltage terminal according to the voltage of the third node and the voltage of the output terminal.
  • the voltage signal is provided to the fourth node to control the voltage of the fourth node, and is configured to control the voltage of the fourth node according to the second clock signal from the second clock signal terminal.
  • the pull-down circuit is coupled to the third node, the fourth node, the first voltage terminal, and the output terminal, and is configured to provide the first voltage signal to the third node and the output terminal according to the voltage of the fourth node to control the third node And the voltage at the output.
  • the display reset circuit is coupled to the display reset signal terminal, the third node, and the second control signal terminal, and is configured to provide the second control signal from the second control signal terminal to the third node according to the display reset signal from the display reset signal terminal , To reset the third node; and the blanking reset circuit is coupled to the third node, the first voltage terminal and the blanking reset signal terminal, and is configured to reset the first voltage according to the blanking reset signal from the blanking reset signal terminal The signal is provided to the third node to reset the third node.
  • the shift register circuit further includes an anti-leakage circuit, the anti-leakage circuit is coupled to the third clock signal terminal, and the output circuit is coupled to the third node via the anti-leakage circuit.
  • the leakage prevention circuit is configured to prevent the output circuit from leaking through the third node according to the third clock signal from the third clock signal terminal.
  • the shift register circuit further includes a touch circuit, which is coupled to the touch control signal terminal, the output terminal and the first voltage terminal, and is configured to switch the touch signal from the touch signal terminal
  • the first voltage signal is provided to the output terminal to control the display driving signal provided by the output terminal.
  • a driving method for driving the shift register according to any one of the first aspects.
  • the method includes: the start circuit provides one of the start input signal and the start control signal to the shift register circuit as an input signal via the first node according to the start selection signal; and the shift register circuit generates the scan driving signal according to the input signal.
  • the method further includes: in the first stage, the startup circuit stores the startup setting signal according to the startup selection signal and the startup input signal; and in the second stage, the startup circuit stores the startup setting signal according to the stored startup setting signal
  • the start control signal is provided to the shift register circuit as an input signal via the first node, and the shift register circuit generates a scan driving signal according to the input signal.
  • the method further includes: in the first stage, the activation input circuit provides the activation setting signal to the activation retention circuit via the second node according to the activation selection signal, and the activation retention circuit stores and maintains activation A set signal; and in the second stage, the start output circuit provides the start control signal to the shift register circuit as an input signal via the first node according to the held start set signal, and the shift register circuit generates a scan drive signal according to the input signal .
  • a gate driving circuit including a plurality of shift registers according to any one of the first aspects.
  • the output terminal of the Nth stage shift register is coupled to the start signal input terminal of the N+1th stage shift register, where N is a positive integer.
  • the gate driving circuit further includes an activation selection signal line and an activation control signal line.
  • the start selection signal line is coupled to the start selection signal end of each shift register to provide a start selection signal.
  • the start control signal line is coupled to the start control signal end of each shift register to provide a start control signal.
  • the gate driving circuit further includes a start-set signal line and a start-reset signal line.
  • the start setting signal line is coupled to the start setting signal end of each shift register to provide a start setting signal.
  • the start reset signal line is coupled with the start reset signal end of each shift register to provide a start reset signal.
  • the gate driving circuit further includes a first clock signal line, a second clock signal line, a blanking reset signal line, a third clock signal line, and a touch signal line.
  • the first clock signal line is coupled to the first clock signal terminal of the shift register of odd-numbered stages to provide a first clock signal, and is coupled to the second clock signal terminal of the shift register of even-numbered stages to provide a second clock signal.
  • the second clock signal line is coupled to the first clock signal terminal of the even-numbered shift register to provide a first clock signal, and is coupled to the second clock signal terminal of the odd-numbered shift register to provide a second clock signal .
  • the blanking reset signal line is coupled to the blanking reset signal end of each shift register to provide a blanking reset signal.
  • the third clock signal line is coupled to the third clock signal terminal of each shift register to provide a third clock signal.
  • the touch signal line is coupled to the touch signal end of each shift register to provide a touch signal.
  • the output terminal of the N+1th stage shift register is coupled to the display reset signal terminal of the Nth stage shift register, where N is a positive integer.
  • an array substrate including the gate driving circuit according to any one of the third aspects.
  • a display device including the array substrate according to the fourth aspect.
  • Fig. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure
  • Fig. 3 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 5 shows a timing diagram of various signals in the working process of the shift register shown in FIG. 2.
  • the currently applied GOA does not have any node start and stop function, which makes display products in a fixed GOA cascade structure only start from the first level GOA.
  • the first stage outputs the scanning drive signal until the last stage GOA completes the output.
  • this usually requires sending a black picture to the non-display area in the display area, and each level of GOA still maintains the output scanning drive. This not only leads to a large waste of GOA resources, but also increases equipment power consumption.
  • each level of GOA needs to be driven in sequence, it is impossible to start any level of GOA.
  • the shift register provided by the embodiment of the present disclosure can drive pixels to display row by row starting from any designated row, thereby achieving the purpose of displaying any designated display area.
  • the embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • the embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • Fig. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register 10 may include a startup circuit 100 and a shift register circuit 200. It will be described in detail below with reference to the drawings.
  • the startup circuit 100 may send one of the startup input signal STV from the startup input signal terminal and the startup control signal CSTV from the startup control signal terminal via the first node according to the startup selection signal EN from the startup selection signal terminal. K is supplied to the shift register circuit 200 as an input signal.
  • the activation circuit 100 is coupled to the activation selection signal terminal to receive the activation selection signal EN.
  • the start circuit 100 is coupled to the start input signal terminal to receive the start input signal STV.
  • the start circuit 100 is coupled to the start control signal terminal to receive the start control signal.
  • the shift register circuit 200 may provide a scan driving signal through the output terminal OUTPUT according to the input signal and the first clock signal CK from the first clock signal terminal.
  • the shift register circuit 200 is coupled to the first node K to receive the input signal.
  • the shift register circuit 200 is coupled to the first clock signal terminal to receive the first clock signal CK.
  • the shift register 200 is coupled to the output terminal OUTPUT to output the first clock signal CK through the output terminal OUTPUT as a scan driving signal.
  • the start circuit 100 may store and maintain the start set signal SSTV from the start set signal terminal according to the start input signal STV in the first stage.
  • the startup circuit 100 may also provide the startup control signal CSTV via the first node K to the shift register circuit 200 as an input signal according to the held startup set signal SSTV in the second stage.
  • the start circuit 100 is coupled to the start setting signal terminal to receive the start setting signal SSTV.
  • the starting circuit 100 includes a starting input circuit 110, a starting holding circuit 120, a starting output circuit 130, and a starting selection circuit 140. It will be described in detail below with reference to the drawings.
  • the start input circuit 110 may provide the start set signal SSTV to the second node L according to the start input signal STV.
  • the start input circuit 110 is coupled to the start input signal terminal to receive the start input signal STV.
  • the activation input circuit 110 is coupled to the activation setting signal terminal to receive the activation setting signal SSTV. Based on the received start input signal STV, the received start set signal SSTV is provided to the second node L.
  • the activation holding circuit 120 may store and maintain the activation set signal SSTV.
  • the startup and hold circuit 120 is coupled to the second node L and the first node K, and the startup and hold circuit 120 stores and maintains the voltage difference between the second node L and the first node K.
  • the first node K is in a floating state due to no signal input and the coupled load is large, the first node K is considered to be a low level.
  • the voltage of the second node L is the start set signal SSTV, therefore, the start and hold circuit 120 stores and holds the start set signal SSTV.
  • the start output circuit 130 may provide the start control signal CSTV via the first node K to the shift register circuit 200 as an input signal according to the held start set signal SSTV.
  • the start output circuit 130 is coupled to the start control signal terminal to receive the start control signal CSTV.
  • the start output circuit 130 is coupled to the first node K and the second node L to provide the start control signal CSTV to the first node K based on the voltage of the second node L, that is, the held start set signal SSTV, thereby providing It is given to the shift register circuit 200 as an input signal.
  • the activation selection circuit 140 may provide the activation input signal STV via the first node K to the shift register circuit 200 as an input signal according to the activation selection signal EN. In an embodiment, the activation selection circuit 140 may be coupled to the activation selection signal terminal to receive the activation selection signal EN.
  • the start selection circuit 140 is coupled to the start input signal terminal to receive the start input signal STV.
  • the startup selection circuit 140 is coupled to the first node K. The start selection circuit 140 provides the received start input signal STV to the first node K based on the received start selection signal EN, and provides it to the shift register circuit 200 as an input signal.
  • the startup circuit 100 further includes a startup reset circuit 150.
  • the startup reset circuit 150 can reset the second node L according to the startup reset signal RSTV from the startup reset signal terminal.
  • the startup reset circuit 150 is coupled to the startup reset signal terminal to receive the startup reset signal RSTV.
  • the startup reset circuit 150 is coupled to the first voltage terminal to receive the first voltage VGL.
  • the first voltage terminal can provide a low-level signal, that is, the first voltage VGL is a low-level signal.
  • the startup reset circuit 150 is coupled to the second node L.
  • the startup reset circuit 150 may provide the received first voltage VGL to the second node L based on the received startup reset signal RSTV, and pull down the voltage of the second node L, thereby resetting the second node L.
  • the shift register circuit 200 may include an input circuit 210, an output circuit 220, a pull-down control circuit 230, a pull-down circuit 240, a display reset circuit 250, and a blanking reset circuit 260. It will be described in detail below with reference to the drawings.
  • the input circuit 210 is coupled to the first node K, the third node P and the first control signal terminal, and can provide the first control signal CN to the third node P according to the input signal. It should be understood that although FIG. 1 also shows an anti-leakage circuit 270 coupled between the third node P and the output circuit 210, the anti-leakage circuit 270 is optional rather than necessary.
  • the input circuit 210 is coupled to the first control signal terminal to receive the first control signal CN.
  • the first control signal terminal can provide a high level signal, that is, the first control signal CN is high level.
  • the input circuit 210 outputs the received first control signal CN to the third node P (ie, the pull-up node) under the control of the voltage of the first node K.
  • the first control signal terminal provides a high level, that is, the first control signal CN is a high level.
  • the output circuit 220 is coupled to the third node P, the first clock signal terminal and the output terminal OUTPUT, and is configured to output the first clock signal CK from the first clock signal terminal according to the voltage of the third node P and the first clock signal terminal.
  • the terminal OUTPUT outputs a scan driving signal.
  • the output circuit 220 is coupled to the first clock signal terminal to receive the first clock signal CK. Under the control of the voltage of the third node P, the output circuit 220 provides the received first clock signal CK to the output terminal OUTPUT as a scan driving signal.
  • each output circuit is coupled with a corresponding clock signal.
  • Each output circuit can output a corresponding driving signal according to the voltage of the third node P and the corresponding clock signal.
  • the pull-down control circuit 230 is coupled to the second clock signal terminal, the fourth node Q, the third node P, the first voltage terminal and the output terminal OUTPUT.
  • the pull-down control circuit 230 can provide the first voltage signal VGL or the second clock signal CKB from the first voltage terminal to the voltage of the third node P, the voltage of the output terminal OUTPUT, and the second clock signal CKB from the second clock signal terminal.
  • the fourth node Q is used to control the voltage of the fourth node Q.
  • the pull-down control circuit 230 is coupled to the second clock signal terminal to receive the second clock signal CKB.
  • the pull-down control circuit 230 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the pull-down control circuit 230 provides the received second clock signal CKB to the fourth node Q based on the received second clock signal CKB.
  • the pull-down control circuit 230 may provide the received first voltage signal VGL to the fourth node Q based on the voltage of the third node P to pull down the voltage of the fourth node Q.
  • the pull-down control circuit 230 may also provide the received first voltage signal VGL to the fourth node Q based on the voltage of the output terminal OUTPUT to pull down the voltage of the fourth node Q.
  • the pull-down circuit 240 is coupled to the third node P, the fourth node Q, the first voltage terminal, and the output terminal OUTPUT, and can provide the first voltage signal VGL to the third node according to the voltage of the fourth node Q P and the output terminal OUTPUT to control the voltage of the third node P and the output terminal OUTPUT.
  • the pull-down circuit 240 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the pull-down circuit 240 Under the control of the voltage of the fourth node Q, the pull-down circuit 240 provides the received first voltage signal VGL to the third node P and the output terminal OUTPUT, and pulls down the voltages of the third node P and the output terminal OUTPUT, thereby controlling the third node P and the output terminal OUTPUT.
  • the display reset circuit 250 is coupled to the display reset signal terminal, the third node P, and the second control signal terminal, and can control the second control signal terminal from the second control signal terminal according to the display reset signal STD from the display reset signal terminal.
  • the signal CNB is provided to the third node P to reset the third node P.
  • the display reset circuit 250 may be coupled to the display reset signal terminal to receive the display reset signal STD.
  • the display reset circuit 250 may be coupled to the second control signal terminal to receive the second control signal CNB.
  • the second control signal terminal provides a low level, that is, the second control signal CNB is a low level.
  • the display reset circuit 250 may provide the received second control signal CNB to the third node P under the control of the received display reset signal STD, thereby pulling down the voltage of the third node P and resetting the third node P .
  • the blanking reset circuit 260 is coupled to the third node P, the first voltage terminal, and the blanking reset signal terminal, and can provide the first voltage signal VGL to the blanking reset signal REST from the blanking reset signal terminal The third node P to reset the third node P.
  • the blanking reset circuit 260 may be coupled to the blanking reset signal terminal to receive the blanking reset signal REST.
  • the blanking reset circuit 260 may be coupled to the first voltage terminal to receive the first voltage VGL.
  • the blanking reset circuit 260 can provide the received first voltage signal VGL (low level) to the third node P under the control of the received blanking reset signal REST, thereby pulling down the voltage of the third node P , To reset the third node P.
  • the shift register circuit 200 may further include an anti-leakage circuit 270.
  • the leakage prevention circuit 270 is coupled to the third clock signal terminal, and the output circuit 220 is coupled to the third node P via the leakage prevention circuit 270.
  • the leakage prevention circuit 270 can also prevent the output circuit 220 from leaking through the third node P according to the third clock signal CLK from the third clock signal terminal.
  • the leakage prevention circuit 270 is coupled to the third clock signal terminal to receive the third clock signal CLK.
  • the leakage prevention circuit 270 may be coupled to the output circuit 220 via the fifth node R. According to the received third clock signal CLK, the leakage prevention circuit 270 provides the voltage of the third node P to the output circuit 220 via the fifth node R.
  • the leakage prevention circuit 270 prevents the charge of the fifth node R from leaking through the third node P according to the received third clock signal CLK.
  • the shift register circuit 200 further includes a touch circuit 280.
  • the touch circuit 280 is coupled to the touch control signal terminal, the output terminal OUTPUT and the first voltage terminal, and can provide the first voltage signal VGL to the output terminal OUTPUT according to the touch signal TOUCHEN from the touch signal terminal to control The display drive signal output by the output terminal OUTPUT.
  • the touch circuit 280 is coupled to the touch control signal terminal to receive the touch signal TOUCHEN.
  • the touch circuit 280 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the touch circuit 280 can provide the received first voltage signal VGL to the output terminal OUTPUT based on the received touch signal TOUCHEN, pull down the voltage of the output terminal OUTPUT, and the scan driving signal is at a low level, thereby responding to the scan driving signal Take control.
  • the shift register 10 is configured to drive the display device for forward scanning as an example for description.
  • the output terminal of the Nth stage shift register can be coupled to the start signal input terminal of the N+1 stage shift register, and the output terminal of the N+1th stage shift register can be coupled to the display of the Nth stage shift register.
  • Reset signal terminal where N is a positive integer.
  • the first control signal CN is configured to be a high level
  • the second control signal CNB is configured to be a low level. But this cannot limit the protection scope of the present disclosure.
  • the shift register may also be configured to drive the display device to perform reverse scanning.
  • the output terminal of the N+1th stage shift register can also be coupled to the start signal input terminal of the Nth stage shift register, and the output terminal of the Nth stage shift register can also be coupled to the N+1th stage shift register.
  • the display reset signal terminal where N is a positive integer.
  • the first control signal CN may also be configured to be a low level, and the second control signal CNB may also be configured to be a high level.
  • the shift register 10 in FIG. 1 shows a pull-down control circuit 230, a pull-down circuit 240, a display reset circuit 250, a blanking reset circuit 260, an anti-leakage circuit 270, and a touch circuit 280
  • the above examples do not limit the protection scope of the present disclosure.
  • the skilled person can choose to use or not use one or more of the above-mentioned circuits according to the situation.
  • Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • FIG. 2 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register is, for example, the shift register 10 shown in FIG. 1.
  • the shift register may include a first transistor T1 to a thirteenth transistor T13 and a first capacitor C1 to a third capacitor C3.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the gate of the transistor can be called the gate.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage
  • the turn-off voltage is a high-level voltage
  • the turn-on voltage is a high-level voltage
  • the turn-off voltage is a low-level voltage
  • the transistors used in the shift register provided in the embodiments of the present disclosure are all N-type transistors as examples.
  • the embodiments of the present disclosure include but are not limited thereto.
  • at least part of the transistors in the shift register may also adopt P-type transistors.
  • the startup input circuit 110 includes a first transistor T1.
  • the control electrode of the first transistor T1 is coupled to the start input signal terminal to receive the start input signal STV.
  • the first pole of the first transistor T1 is coupled to the start setting signal terminal to receive the start setting signal SSTV.
  • the second electrode of the first transistor T1 is coupled to the second node L.
  • the first transistor T1 when the start input signal STV is at a high level, the first transistor T1 is turned on, and the received start set signal SSTV is provided to the second node L.
  • the holding circuit 120 includes a first capacitor C1.
  • the first pole of the first capacitor C1 is coupled to the second node L.
  • the second pole of the first capacitor C1 is coupled to the first node K.
  • the voltage difference between the start set signal SSTV and the first node K can be stored. As described above with reference to FIG. 1, the first node K is suspended, and the voltage of the first node K is low.
  • the start setting signal SSTV provided to the second node is at a high level
  • the voltage difference between the two poles of the first capacitor C1 is the start setting signal SSTV, and the first capacitor C1 is charged.
  • the second node L When the second node L is suspended and the first node K is at a high level, the second node L is at a higher level due to the bootstrap effect of the first capacitor C1.
  • the voltage difference between the two poles of the first capacitor C1 is maintained as the activation set signal SSTV.
  • the start output circuit 130 includes a second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the second node L.
  • the first electrode of the second transistor T2 is coupled to the start control signal terminal to receive the start control signal CSTV.
  • the second electrode of the second transistor T2 is coupled to the first node K.
  • the second transistor T2 when the voltage of the second node L is at a high level, the second transistor T2 is turned on, thereby providing the received start control signal CSTV to the first node K as an input signal of the shift register circuit 200.
  • the startup selection circuit 140 includes a third transistor T3.
  • the control electrode of the third transistor T3 is coupled to the start selection signal terminal to receive the start selection signal EN.
  • the first pole of the third transistor T3 is coupled to the start input signal terminal to receive the start input signal STV.
  • the second electrode of the third transistor T3 is coupled to the first node K.
  • the third transistor T3 when the enable selection signal EN is at a high level, the third transistor T3 is turned on, and the received high-level enable input signal STV is provided to the first node K as the input signal of the shift register circuit 200 .
  • the enable selection signal EN is at a low level, the third transistor T3 is turned off. At this time, the start control signal CSTV provided to the first node K as described above can be used as the input signal of the shift register circuit 200.
  • the startup reset circuit 150 includes a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is coupled to the start reset signal terminal to receive the start reset signal RSTV.
  • the first electrode of the fourth transistor T4 is coupled to the second node L.
  • the second electrode of the fourth transistor T4 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the fourth transistor T4 when the start-up reset signal RSTV is at a high level, the fourth transistor T4 is turned on, and the first voltage signal VGL is provided to the second node L, and the voltage of the second node L is lowered, so that the second node L Perform a reset.
  • the input circuit 210 includes a fifth transistor T5.
  • the control electrode of the fifth transistor T5 is coupled to the first node K to receive the input signal.
  • the first electrode of the fifth transistor T5 is coupled to the first control signal terminal to receive the first control signal CN (high level).
  • the second electrode of the fifth transistor T5 is coupled to the third node P.
  • the fifth transistor T5 when the input signal is at a high level, the fifth transistor T5 is turned on to provide the received first control signal CN with a high level to the third node P.
  • the output circuit 220 includes a sixth transistor T6 and a second capacitor C2.
  • the control electrode of the sixth transistor T6 is coupled to the third node P.
  • the first pole of the sixth transistor T6 is coupled to the first clock signal terminal to receive the first clock signal CK.
  • the second electrode of the sixth transistor T6 is coupled to the output terminal OUTPUT.
  • the first pole of the second capacitor C2 is coupled to the third node P.
  • the second pole of the second capacitor C2 is coupled to the output terminal OUTPUT.
  • the sixth transistor T6 when the third node P is at a high level, the sixth transistor T6 is turned on, and the received first clock signal CK is provided to the output terminal OUTPUT as a scan driving signal.
  • the pull-down control circuit 230 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a third capacitor C3.
  • the control electrode and the first electrode of the seventh transistor T7 are coupled to the second clock signal terminal to receive the second clock signal CKB.
  • the second electrode of the seventh transistor T7 is coupled to the fourth node Q.
  • the control electrode of the eighth transistor T8 is coupled to the third node P.
  • the first electrode of the eighth transistor T8 is coupled to the fourth node Q.
  • the second electrode of the eighth transistor T8 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the control electrode of the ninth transistor T9 is coupled to the output terminal OUTPUT.
  • the first electrode of the ninth transistor T9 is coupled to the fourth node Q.
  • the second electrode of the ninth transistor T9 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the first pole of the third capacitor C3 is coupled to the fourth node Q.
  • the second pole of the third capacitor C3 is coupled to the first voltage terminal.
  • the seventh transistor T7 is turned on to provide the received second clock signal CKB to the fourth node Q.
  • the eighth transistor T8 is turned on to provide the received first voltage signal VGL (low level) to the fourth node Q.
  • the ninth transistor T9 is turned on to provide the received first voltage signal VGL (low level) to the fourth node Q.
  • the pull-down circuit 240 includes a tenth transistor T10 and an eleventh transistor T11.
  • the control electrode of the tenth transistor T10 is coupled to the fourth node Q.
  • the first electrode of the tenth transistor T10 is coupled to the third node P.
  • the second electrode of the tenth transistor T10 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the control electrode of the eleventh transistor T11 is coupled to the fourth node Q.
  • the first pole of the eleventh transistor T11 is coupled to the output terminal OUTPUT.
  • the second electrode of the eleventh transistor T11 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the tenth transistor T10 and the eleventh transistor T11 are both turned on, and the received first voltage signal VGL (low level) is provided to the third node P, respectively. And the output terminal OUTPUT to lower the voltage of the third node P and the output terminal OUTPUT.
  • the display reset circuit 250 includes a twelfth transistor T12.
  • the control electrode of the twelfth transistor T12 is coupled to the display reset signal terminal to receive the display reset signal STD.
  • the first electrode of the twelfth transistor T12 is coupled to the third node P.
  • the second electrode of the twelfth transistor T12 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the twelfth transistor T12 when the display reset signal STD is at a high level, the twelfth transistor T12 is turned on to provide the received first voltage signal VGL (low level) to the third node P, and pull down the third node P , To reset the third node P.
  • the blanking reset circuit 260 includes a thirteenth transistor T13.
  • the control electrode of the thirteenth transistor T13 is coupled to the blanking reset signal terminal to receive the blanking reset signal REST.
  • the first electrode of the thirteenth transistor T13 is coupled to the third node P.
  • the second electrode of the thirteenth transistor T13 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the thirteenth transistor T13 when the blanking reset signal REST is at a high level, the thirteenth transistor T13 is turned on, and the received first voltage signal VGL (low level) is provided to the third node P, and the third node is pulled down. P to reset the third node P.
  • the shift register circuit 200 may further include an anti-leakage circuit 270.
  • the leakage prevention circuit 270 includes a fourteenth transistor T14.
  • the control electrode of the fourteenth transistor T14 is coupled to the third clock signal terminal to receive the third clock signal CLK.
  • the first electrode of the fourteenth transistor T14 is coupled to the third node P.
  • the second electrode of the fourteenth transistor T14 is coupled to the fifth node R.
  • the fourteenth transistor T14 When the third clock signal CLK is at a high level, the fourteenth transistor T14 is turned on, and the voltage of the third node P is provided to the output circuit 220 via the fifth node R. When the third clock signal CLK is at a low level, the fourteenth transistor T14 is turned off to prevent the charge of the fifth node R from leaking through the third node P.
  • the shift register circuit 200 may further include a touch circuit 280.
  • the touch circuit 280 includes a fifteenth transistor T15.
  • the control electrode of the fifteenth transistor T15 is coupled to the contact control signal terminal to receive the touch signal TOUCHEN.
  • the first pole of the fifteenth transistor T15 is coupled to the output terminal OUTPUT.
  • the second electrode of the fifteenth transistor T15 is coupled to the first voltage terminal to receive the first voltage signal VGL.
  • the fifteenth transistor T15 when the touch signal TOUCHEN is at a high level, the fifteenth transistor T15 is turned on to provide the received first voltage signal VGL (low level) to the output terminal OUTPUT, pull down the output terminal OUTPUT, and scan The driving signal is low level, thereby controlling the scanning driving signal.
  • FIG. 3 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • the shift register may be any applicable shift register based on the embodiment of the present disclosure.
  • step 310 the startup circuit 100 provides one of the startup input signal STV and the startup control signal CSTV via the first node K to the shift register circuit 200 as an input signal according to the startup selection signal EN.
  • the shift register corresponding to the row of pixels performs the following steps:
  • the startup circuit 100 stores the startup setting according to the startup selection signal EN and the startup input signal STV Signal SSTV.
  • the startup circuit 100 provides the startup control signal CSTV via the first node K to the shift register circuit 200 as an input signal according to the stored startup set signal SSTV.
  • the start input circuit 100 provides the start setting signal SSTV to the start holding circuit 120 via the second node L according to the start selection signal STV, and the start holding circuit 120 stores and holds the start setting signal SSTV;
  • the start output circuit 130 provides the start control signal CSTV via the first node K to the shift register circuit 200 as an input signal according to the held start set signal SSTV.
  • the startup circuit 100 corresponding to the row receives a low-level startup selection signal EN and a high-level startup input signal during the display period D1 of the first stage. STV.
  • the high level start set signal SSTV is provided to the second node L.
  • the high-level start-set signal SSTV is stored and held by the holding circuit 120.
  • the startup circuit 100 corresponding to the pixel in the i-th row receives a high-level startup control signal CSTV during the display period D2 of the second stage.
  • the start-up output circuit 130 Based on the maintained high-level start-set signal SSTV, the start-up output circuit 130 provides the received high-level start control signal CSTV to the first node K, thereby providing it to the corresponding shift register circuit 200 as an input signal .
  • step 320 the shift register circuit 200 generates a scan driving signal according to the high-level input signal.
  • the shift register circuit 200 under the control of the received high-level input signal, the shift register circuit 200 provides the first clock signal CK to the output terminal OUTPUT as a display driving signal.
  • FIG. 4 shows a schematic diagram of a gate driving circuit 40 according to an embodiment of the present disclosure.
  • the gate driving circuit 40 may include a plurality of shift registers. Any one or more shift registers may adopt the structure of the shift register 10 provided in the embodiments of the present disclosure or a modification thereof.
  • FIG. 4 only schematically shows the first three shift registers, that is, the first shift register SR_1 corresponding to the first row of pixels, the second shift register SR_2 corresponding to the second row of pixels, and the third shift register.
  • the third shift register SR_3 corresponding to the row pixels.
  • the output terminal of the Nth stage shift register is coupled to the start input signal terminal of the N+1th stage shift register, where N is a positive integer.
  • the start input signal terminal of the first shift register appliance SR_1 receives the start input signal STV_1 from the start input signal line INPUT.
  • the output terminal OUTPUT_1 of the first shift register SR_1 is coupled to the start input signal terminal of the second shift register SR_2 to provide the start input signal STV_2.
  • the output terminal OUTPUT_2 of the second shift register SR_2 is coupled to the start input signal terminal of the shift register SR_3 to provide the start input signal STV_3.
  • the gate driving circuit 40 further includes an activation selection signal line CLK_A and an activation control signal line CLK_B.
  • the start selection signal line CLK_A is coupled to the start selection signal ends of the three shift registers to provide the start selection signal EN.
  • the start control signal line CLK_B is coupled to the start control signal ends of the three shift registers to provide the start control signal CSTV.
  • the gate driving circuit 40 may further include a start-set signal line CLK_C and a start-reset signal line CLK_D.
  • the start setting signal line CLK_C is coupled to the start setting signal ends of the three shift registers to provide the start setting signal SSTV.
  • the start reset signal line CLK_D is coupled to the start reset signal terminals of the three shift registers to provide the start reset signal RSTV.
  • the gate driving circuit 40 also includes a first clock signal line CLK_E, a second clock signal line CLK_F, and a blanking reset signal line CLK_G.
  • the first clock signal line CLK_E is coupled to the first clock signal terminal of the shift register of the odd-numbered stage to provide the first clock signal CK, and is coupled to the second clock signal terminal of the shift register of the even-numbered stage to provide the second clock signal The clock signal CKB.
  • the second clock signal line CLK_F is coupled to the first clock signal terminal of the even-numbered shift register to provide the first clock signal CK, and is coupled to the second clock signal terminal of the odd-numbered shift register to provide the second clock Signal CKB.
  • the first clock signal line CLK_E is coupled to the first clock signal terminal of the first shift register SR_1 and the third shift register SR_3 to provide the first clock signal CK.
  • the first clock signal line CLK_E is coupled to the second clock signal terminal of the second shift register SR_2 to provide the second clock signal CKB.
  • the second clock signal line CLK_F is coupled to the first clock signal terminal of the second shift register SR_2 to provide the first clock signal CK.
  • the second clock signal line CLK_F is coupled to the second clock signal end of the first shift register SR_1 and the third shift register SR_3 to provide the second clock signal CKB.
  • the blanking reset signal line CLK_G is coupled to the blanking reset signal terminals of the three shift registers to provide a blanking reset signal RSET.
  • the output terminal of the N+1th stage shift register is coupled to the display reset signal terminal of the Nth stage shift register, where N is a positive integer.
  • the output terminal OUTPUT_2 of the second shift register SR_2 is coupled to the display reset signal terminal of the first shift register SR_1 to provide a display reset signal STD_1.
  • the output terminal OUTPUT_3 of the third shift register SR_3 is coupled to the display reset signal terminal of the second shift register SR_2 to provide a display reset signal STD_2.
  • the shift register in the gate driving circuit 40 has, for example, the circuit structure of the shift register shown in FIG. 2.
  • Fig. 5 shows a signal timing diagram of the gate driving circuit 40 starting from the second row of pixels to display row by row.
  • the first clock signal line CLK_E provides the first clock signal CK to the first shift register SR_1 and the third shift register SR_3.
  • the second clock signal line CLK_F provides the second clock signal CKB to the first shift register SR_1 and the third shift register SR_3.
  • the start input signal line INPUT provides the start input signal STV to the first shift register SR_1.
  • the start setting signal line CLK_C provides the start setting signal SSTV to the three shift registers.
  • the start control signal line CLK_B provides the start control signal CSTV to the three shift registers.
  • the start selection signal line CLK_A provides the start selection signal EN to the three shift registers.
  • the start reset signal line CLK_D provides the start reset signal RSTV to the three shift registers.
  • the signals VK, VL, VP, and VQ respectively represent the voltage signals of the first node K_2, the second node L_2, the third node P_2, and the fourth node Q_2 of the second shift register SR_2 in the gate driving circuit 40.
  • the output signals OUT_1, OUT_2, and OUT_3 represent the output terminals OUTPUT_1, OUTPUT_2 of the first shift register SR_1, the second shift register SR_2, and the third shift register SR_3 corresponding to the pixels of the first row, the second row, and the third row, respectively.
  • OUTPUT_3 output signal It is understandable that the signal voltage in the signal timing diagram shown in FIG. 5 is only schematic, and does not represent a true voltage value.
  • the first stage and the second stage respectively include a display period (D1 and D2) and a blanking period (B1 and B2).
  • the blanking period refers to a period in which the display device does not perform display refresh. During this period, the gate drive circuit no longer provides a display drive signal for refreshing the displayed image, and the display device still displays the image displayed in the previous display period.
  • both the blanking reset signal line CLK_G and the start reset signal line CLK_D provide high-level signals. Therefore, the thirteenth transistor T13 and the fourth transistor T4 in the three shift registers are both turned on. Thus, the first voltage VGL (low level) is supplied to the second node L and the third node P to pull down the voltages of the second node L and the third node P. Thus, the second node L and the third node P of the three shift registers are reset.
  • the first stage starts, and both the blanking reset signal line CLK_G and the start reset signal line CLK_D become low-level signals.
  • the thirteenth transistor T13 and the fourth transistor T4 are turned off.
  • the second shift register SR_2 and related shift registers in the gate driving circuit 40 will be described in detail below.
  • the display device starts displaying sequentially from the pixels in the first row, and the start circuit 100 corresponding to the pixels in the second row stores and holds the start set signal SSTV.
  • the shift register SR_1 receives A high level start input signal STV_1, a high level start selection signal EN and a low level start set signal SSTV.
  • the first transistor T1 is turned on, and the received low-level start setting signal SSTV is provided to the second node L_1, and the voltage of the second node L_1 is low.
  • the third transistor T3 is turned on, and the received high-level start input signal STV_1 is provided to the first node K_1.
  • the voltage difference between the two poles of the first capacitor C1 is the voltage difference between the low level and the high level, and the first capacitor C1 is reversely charged.
  • the voltage of the first node K_1 is at a high level
  • the fifth transistor T5 is turned on
  • the first control signal CN of a high level is provided to the third node P_1
  • the voltage of the third node P_1 is at a high level. This high level is stored and maintained by the second capacitor C2.
  • the shift register SR_1 receives the first clock signal CK at a high level. Under the bootstrap action of the second capacitor C2, the voltage of the third node P_1 is further pulled up. Under the higher level control of the third node P_1, the sixth transistor T6 is turned on.
  • the shift register SR_1 outputs a high-level scan driving signal OUT_1 through the output terminal OUTPUT_1.
  • the high-level scan driving signal OUT_1 can be used to drive the pixels in the first row of the display device, and can also be used as the start input signal STV_2 of the second shift register appliance SR_2.
  • the second shift register appliance SR_2 receives a high-level start input signal STV_2 and a high-level start set signal SSTV.
  • the first transistor T1 is turned on, and the received high-level start setting signal SSTV is provided to the second node L_2, and the voltage of the second node L_2 is high.
  • the second transistor T2 is turned on, the received low-level start control signal CSTV is provided to the first node K_2, and the voltage of the first node K_2 is low. Therefore, the received high-level start-set signal SSTV is stored and maintained by the first capacitor C1. Since the voltage of the first node K_2 is low level, the fifth transistor T5 is turned off, and the voltage of the third node P_2 is low level, the output terminal OUTPUT_2 provides a low level display driving signal OUT_2.
  • the start input signal STV_3 of the third shift register appliance SR_3 is low.
  • the third transistor T3 is turned on, the low-level start input signal STV_3 is provided to the first node K_3, and the voltage of the first node K_3 is low.
  • the second node L_3 is at a low level, the voltage difference between the two poles of the first capacitor C1 is 0 volts, and the first capacitor C1 is not charged.
  • the output terminal OUTPUT_3 provides a low-level display driving signal OUT_3.
  • the blanking reset signal line CLK_G provides a high-level signal. Therefore, the thirteenth transistor T13 in the three shift registers is turned on. Thus, the first voltage signal VGL (low level) is provided to the third node P to pull the voltage of the third node P low. Thus, the third node P of the three shift registers is reset.
  • the display device sequentially displays the pixels from the second row.
  • the second shift register appliance SR_2 receives the high-level start control signal CSTV. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node L_2 is further pulled up. Under the control of the higher level of the second node L_2, the second transistor T2 is turned on, the received high-level start control signal CSTV is provided to the first node K_2, and the voltage of the first node K_2 is high .
  • the fifth transistor T5 is turned on, the high-level first control signal CN is provided to the third node P_2, and the voltage of the third node P_2 is high. This high level is stored and maintained by the second capacitor C2.
  • the first shift register SR_1 receives the high-level start control signal CSTV.
  • the first node K_1 is in a floating state, and the first node K_1 is coupled with a large load, so the first node K_1 is at a low level. Since the voltage difference between the two poles of the first capacitor C1 is a voltage difference between a low level and a high level, the voltage of the second node L_1 is a lower level. Under the control of the lower level of the second node L_1, the second transistor T2 is turned off, the high-level start control signal CSTV cannot be provided to the first node K_1, and the first node K_1 is low.
  • the third shift register SR_3 receives the high-level start control signal CSTV.
  • the first node K_3 is also in a floating state and the first node K_3 is coupled with a large load, so the first node K_3 is also at a low level. Since the voltage difference between the two poles of the first capacitor C1 is 0V, the voltage of the second node L_3 is low. Under the control of the low level of the second node L_3, the second transistor T2 is turned off, the high-level start control signal CSTV cannot be provided to the first node K_3, and the first node K_3 is low.
  • the second shift register SR_2 receives the high-level first clock signal CK. Under the bootstrap action of the second capacitor C2, the voltage of the third node P_2 is further pulled up. Under the higher level control of the third node P_2, the sixth transistor T6 is turned on, and the received high level first clock signal CK is provided to the output terminal OUTPUT_2. Therefore, the second shift register SR_2 outputs a high-level scan driving signal OUT_2.
  • the high-level scan driving signal OUT_2 can be used to drive the pixels in the second row, and can also be used as the start input signal STV_3 of the third shift register SR_3.
  • the third shift register SR_3 it receives the high-level start selection signal EN.
  • the third transistor T3 is turned on, the received high-level start input signal STV_3 is provided to the first node K_3, and the voltage of the first node K_3 is high.
  • the fifth transistor T5 is turned on, and the first control signal CN of the high level is provided to the third node P_3. This high level is stored and maintained by the second capacitor C2.
  • the first clock signal CK received by the second shift register SR_2 becomes a low level. Since the voltage difference between the two poles of the second capacitor C2 is at a high level, the voltage of the third node P_2 becomes a high level.
  • the third shift register SR_3 receives the high-level first clock signal CK.
  • the sixth transistor T6 is turned on, and the third shift register SR_3 outputs a high-level scan driving signal OUT_3.
  • This process is similar to the second shift register SR_2 outputting the high-level scan driving signal OUT_2 in the fifth period, and will not be repeated here.
  • the scan drive signal OUT_3 can be used to drive the third row of pixels, can also be used as the start input signal STV_4 (not shown) of the fourth shift register SR_4 (not shown), and can also be used as the display of the second shift register SR_2 Reset signal STD_2.
  • the second shift register SR_2 receives a high-level display reset signal STD_2.
  • the twelfth transistor T12 is turned on, the low-level first voltage VGL is provided to the third node P_3, and the voltage of the third node P_3 is pulled down, thereby resetting the third node P_3.
  • the blanking reset signal line CLK_G and the start reset signal line CLK_D provide high-level signals. Therefore, the thirteenth transistor T13 and the fourth transistor T4 in the three shift registers are turned on.
  • the first voltage signal VGL low level
  • the third node P and the second node L of the three shift registers are reset.
  • the second stage includes only one display period and one blanking period as an example, this is not a limitation.
  • the second stage may also include M display periods and blanking periods. During the period, where M is a positive integer.
  • M is a positive integer.
  • the second stage includes multiple display periods and blanking periods, only the third node P is reset during the first to M-1th blanking periods, and the third node P is reset during the Mth blanking period. And the second node L are reset.
  • the blanking reset signal line CLK_G provides a high-level signal to reset the third node P of the shift registers of each stage.
  • the blanking reset signal line CLK_G and the start reset signal line CLK_D provide high-level signals to reset the third node P and the second node L of the shift registers of each level. This process is similar to the foregoing process of resetting the third node P and the second node L in the second blanking period B2, and will not be repeated here.
  • the above-mentioned principle of driving from a specified row is described by sequentially driving pixels from the second row, but the present disclosure does not limit this.
  • the high-level duration of the set signal SSTV and the activation The duration of the low level of the selection signal EN is the same.
  • the duration of the high level of the enable input signal STV corresponding to the pixel in the i-th row falls within the duration of the high level of the enable set signal SSTV and the duration of the low level of the enable selection signal EN, and The rising or falling edge is at the same point in time.
  • the duration of the high level of the enable control signal CSTV is the same as the duration of the low level of the enable selection signal EN.
  • the high-level first clock signal CK is output through the output terminal OUTPUT of the i-th stage shift register as a scan drive signal.
  • the embodiments of the present disclosure also provide an array substrate.
  • the array substrate may include a gate driving circuit according to an embodiment of the present disclosure.
  • embodiments of the present disclosure also provide a display device including the above-mentioned array substrate.
  • the display device may be any product or component with display function, such as a liquid crystal panel, a liquid crystal TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. .

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Abstract

一种移位寄存器（10，SR_1，SR_2，SR_3）及其驱动方法、栅极驱动电路（40）和显示装置。移位寄存器（10，SR_1，SR_2，SR_3）包括启动电路（100）和移位寄存电路（200）。其中，启动电路（100）被配置为根据来自启动选择信号端的启动选择信号（EN）将来自启动输入信号端的启动输入信号（STV，STV_1，STV_2，STV_3）和来自启动控制信号端的启动控制信号（CSTV）中的一者经由第一节点（K）提供给移位寄存电路（200）作为输入信号。其中，移位寄存电路（200）被配置为根据输入信号，生成扫描驱动信号（OUT_1，OUT _2，OUT _3）。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开涉及显示技术领域，具体地，涉及移位寄存器及其驱动方法、栅极驱动电路、阵列基板以及显示装置。
背景技术
随着显示技术的发展，出现了平板显示、柔性显示、折叠显示、卷曲显示等多种显示技术。目前，用于显示驱动的阵列基板驱动(Gate Driver on Array，简称GOA)技术将栅极驱动电路制作在阵列基板上，实现对像素逐行扫描的功能。栅极驱动电路可包括多个级联的移位寄存器。从移位寄存器输出扫描信号以驱动像素，并可同时输出级联信号以驱动下一级移位寄存器，从而顺序驱动整个显示装置进行显示。
发明内容
本公开的实施例提供了移位寄存器及其驱动方法、栅极驱动电路、阵列基板以及显示装置。
根据本公开的第一方面，提供了一种移位寄存器，该移位寄存器包括启动电路和移位寄存电路。启动电路被配置为根据来自启动选择信号端的启动选择信号将来自启动输入信号端的启动输入信号和来自启动控制信号端的启动控制信号中的一者经由第一节点提供给移位寄存电路作为输入信号。移位寄存电路被配置为根据输入信号和来自第一时钟信号端的第一时钟信号，通过输出端提供扫描驱动信号。
在本公开的实施例中，启动电路被配置为在第一阶段根据启动输入信号，存储并保持来自启动置位信号端的启动置位信号。启动电路被配置为在第二阶段根据所保持的启动置位信号，将启动控制信号经由第一节点提供给移位寄存电路作为输入信号。
在本公开的实施例中，启动电路包括启动输入电路、启动保持电路、 启动输出电路以及启动选择电路。启动输入电路被配置为根据启动输入信号，将启动置位信号提供给第二节点。启动保持电路被配置为存储并保持启动置位信号。启动输出电路被配置为根据所保持的启动置位信号，将启动控制信号经由第一节点提供给移位寄存电路作为输入信号。以及启动选择电路被配置为根据启动选择信号，将启动输入信号经由第一节点提供给所述移位寄存器作为所述输入信号。
在本公开的实施例中，启动电路还包括启动复位电路，该启动复位电路被配置为根据来自启动复位信号端的启动复位信号对第二节点进行复位。
在本公开的实施例中，启动输入电路包括第一晶体管，该第一晶体管的控制极耦接启动输入信号端，该第一晶体管的第一极耦接启动置位信号端，该第一晶体管的第二极耦接第二节点。
在本公开的实施例中，启动保持电路包括第一电容，该电容的第一极耦接第二节点，该电容的第二极耦接第一节点。
在本公开的实施例中，输出子电路包括第二晶体管，该第二晶体管的控制极耦接第二节点，该第二晶体管的第一极耦接启动控制信号端，该第二晶体管的第二极耦接第一节点。
在本公开的实施例中，启动选择电路包括第三晶体管，该第三晶体管的控制极耦接启动选择信号端，该第三晶体管的第一极耦接启动输入信号端，该第三晶体管的第二极耦接第一节点。
在本公开的实施例中，启动复位电路包括第四晶体管，该第四晶体管的控制极耦接启动复位信号端，该第四晶体管的第一极耦接第二节点，该第四晶体管的第二极耦接第一电压端。
在本公开的实施例中，移位寄存电路包括输入电路、输出电路、下拉控制电路、下拉电路、显示复位电路、消隐复位电路。输入电路耦接第二节点、第三节点和第一控制信号端，并被配置为根据输入信号，将第一控制信号提供给第三节点。输出电路耦接第三节点、第一时钟信号端和输出端，并被配置为根据第三节点的电压和来自第一时钟信号端的第一时钟信号经由输出端提供扫描驱动信号。下拉控制电路耦接第二时钟信号端、第 四节点、第三节点、第一电压端和输出端，并被配置为根据第三节点的电压和输出端的电压，将来自第一电压端的第一电压信号提供给第四节点，以控制第四节点的电压，以及被配置为根据来自第二时钟信号端的第二时钟信号控制所述第四节点的电压。下拉电路耦接第三节点、第四节点、第一电压端以及输出端，并被配置为根据第四节点的电压，将第一电压信号提供给第三节点和输出端，以控制第三节点和输出端的电压。显示复位电路耦接显示复位信号端、第三节点以及第二控制信号端，并被配置为根据来自显示复位信号端的显示复位信号，将来自第二控制信号端的第二控制信号提供给第三节点，以对第三节点进行复位；以及消隐复位电路耦接第三节点、第一电压端以及消隐复位信号端，并被配置为根据来自消隐复位信号端的消隐复位信号将第一电压信号提供给第三节点，以对第三节点进行复位。
在本公开的实施例中，移位寄存电路进一步包括防漏电电路，该防漏电电路耦接第三时钟信号端，输出电路经由该防漏电电路耦接第三节点。该防漏电电路被配置为根据来自第三时钟信号端的第三时钟信号，防止输出电路经由第三节点漏电。
在本公开的实施例中，移位寄存电路进一步包括触控电路，该触控电路耦接触控信号端、输出端和第一电压端，并被配置为根据来自触控信号端的触控信号将第一电压信号提供给输出端，以控制输出端提供的显示驱动信号。
根据本公开的第二方面，提供了一种用于驱动如第一方面中任一项所述的移位寄存器的驱动方法。该方法包括：启动电路根据启动选择信号将启动输入信号和启动控制信号中的一者经由第一节点提供给移位寄存电路作为输入信号；以及移位寄存电路根据输入信号生成扫描驱动信号。
在本公开的实施例中，该方法还包括：在第一阶段，启动电路根据启动选择信号和启动输入信号存储启动置位信号；以及在第二阶段，启动电路根据所存储的启动置位信号将启动控制信号经由第一节点提供给移位寄存电路作为输入信号，移位寄存电路根据输入信号生成扫描驱动信号。
在本公开的实施例中，该方法还包括：在第一阶段，启动输入电路根据启动选择信号将所述启动置位信号经由第二节点提供给启动保持电路，该启动保持电路存储并保持启动置位信号；以及在第二阶段，启动输出电路根据所保持的启动置位信号将启动控制信号经由第一节点提供给移位寄存电路作为输入信号，移位寄存电路根据输入信号生成扫描驱动信号。
根据本公开的第三方面，提供了一种栅极驱动电路，该栅极驱动电路包括多个如第一方面中任一项所述的移位寄存器。第N级移位寄存器的输出端耦接第N+1级移位寄存器的启动信号输入端，其中，N为正整数。
在本公开的实施例中，栅极驱动电路还包括启动选择信号线和启动控制信号线。该启动选择信号线与各个移位寄存器的启动选择信号端耦接以提供启动选择信号。该启动控制信号线与各个移位寄存器的启动控制信号端耦接以提供启动控制信号。
在本公开的实施例中，栅极驱动电路还包括启动置位信号线和启动复位信号线。该启动置位信号线与各个移位寄存器的启动置位信号端耦接以提供启动置为信号。该启动复位信号线与各个移位寄存器的启动复位信号端耦接以提供启动复位信号。
在本公开的实施例中，栅极驱动电路还包括第一时钟信号线、第二时钟信号线、消隐复位信号线、第三时钟信号线以及触控信号线。该第一时钟信号线与奇数级的移位寄存器的第一时钟信号端耦接以提供第一时钟信号，并且与偶数级的移位寄存器的第二时钟信号端耦接以第二时钟信号。该第二时钟信号线与偶数级的移位寄存器的第一时钟信号端耦接以提供第一时钟信号，并且与奇数级的移位寄存器的第二时钟信号端耦接以提供第二时钟信号。该消隐复位信号线与各个移位寄存器的消隐复位信号端耦接以提供消隐复位信号。该第三时钟信号线与各个移位寄存器的第三时钟信号端耦接以提供第三时钟信号。该触控信号线与各个移位寄存器的触控信号端耦接以提供触控信号。以及第N+1级移位寄存器的输出端耦接第N级移位寄存器的显示复位信号端，其中，N为正整数。
根据本公开的第四方面，提供了一种阵列基板，该阵列基板包括第三 方面中任一项所述的栅极驱动电路。
根据本公开的第五方面，提供了一种显示装置，该显示装置包括如第四方面所述的阵列基板。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。在附图中：
图1示出了根据本公开的实施例的移位寄存器的示意性框图；
图2示出了根据本公开的实施例的移位寄存器的示例性电路图；
图3示出了根据本公开的实施例的用于驱动移位寄存器的方法的示意性流程图；
图4示出了根据本公开的实施例的栅极驱动电路的示意图；以及
图5示出了如图2所示的移位寄存器的工作过程中各信号的时序图。
具体实施方式
为了使本公开的实施例的技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“耦接”等类似的词 语并非限定于物理的或者机械的连接，而是可以包括电性的连接，并且可以是直接连接也可以通过中间介质间接连接。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在平板显示、柔性显示、折叠显示、卷曲显示等显示领域，目前所应用的GOA并不具备任意节点启停功能，使得显示产品在固定的GOA级联结构中只能从第一级GOA开始逐级输出扫描驱动信号，直至最后一级GOA完成输出。在一些显示领域，诸如折叠显示和卷曲显示等，不可避免地存在进行局部显示的需求。然而，这通常需要向显示区中的非显示区域发送黑画面，而各级GOA仍然保持输出扫描驱动。这不仅导致GOA资源大量浪费，而且会增加设备功耗。此外，由于各级GOA需要依次驱动，因而也不能实现对任意级的GOA的启动。
为了解决这一技术问题，本公开的实施例提供的移位寄存器可以从任意指定行开始驱动像素逐行进行显示，从而实现显示任意指定显示区域的目的。
本公开的实施例提供了移位寄存器及其驱动方法、栅极驱动电路、阵列基板以及显示装置。下面结合附图对本公开的实施例及其示例进行详细说明。
图1示出了根据本公开的实施例的移位寄存器的示意性框图。如图1所示，移位寄存器10可包括启动电路100和移位寄存电路200。下面参照附图，对其进行详细描述。
在本公开的实施例中，启动电路100可以根据来自启动选择信号端的启动选择信号EN将来自启动输入信号端的启动输入信号STV和来自启动控制信号端的启动控制信号CSTV中的一者经由第一节点K提供给移位寄存电路200作为输入信号。在实施例中，启动电路100与启动选择信号端耦接，以接收启动选择信号EN。启动电路100与启动输入信号端耦接，以接收启动输入信号STV。启动电路100与启动控制信号端耦接，以接收启动控制信号。
移位寄存电路200可以根据输入信号和来自第一时钟信号端的第一时钟信号CK，通过输出端OUTPUT提供扫描驱动信号。在实施例中，移位寄存电路200与第一节点K耦接，以接收输入信号。移位寄存电路200与第一时钟信号端耦接，以接收第一时钟信号CK。移位寄存器200与输出端OUTPUT耦接，以将第一时钟信号CK通过输出端OUTPUT输出，作为扫描驱动信号。
进一步地，在本公开的实施例中，启动电路100可以在第一阶段根据启动输入信号STV，存储并保持来自启动置位信号端的启动置位信号SSTV。启动电路100还可以在第二阶段根据所保持的启动置位信号SSTV，将启动控制信号CSTV经由第一节点K提供给移位寄存电路200作为输入信号。在实施例中，启动电路100与启动置位信号端耦接，以接收启动置位信号SSTV。
进一步地，在本公开的实施例中，启动电路100包括启动输入电路110、启动保持电路120、启动输出电路130以及启动选择电路140。下面参照附图，对其进行详细描述。
在实施例中，启动输入电路110可以根据启动输入信号STV，将启动置位信号SSTV提供给第二节点L。在实施例中，启动输入电路110与启动输入信号端耦接，以接收启动输入信号STV。启动输入电路110与启动置位信号端耦接，以接收启动置位信号SSTV。基于所接收的启动输入信号STV，将所接收启动置位信号SSTV提供给第二节点L。
在实施例中，启动保持电路120可以存储并保持启动置位信号SSTV。在实施例中，启动保持电路120与第二节点L和第一节点K耦接，启动保持电路120存储并保持第二节点L与第一节点K之间的电压差。在第一节点K因没有信号输入而处于悬空状态且耦接的负载较大时，第一节点K被考虑为低电平。然而，第二节点L的电压为启动置位信号SSTV，因此，启动保持电路120存储并保持启动置位信号SSTV。
在实施例中，启动输出电路130可以根据所保持的启动置位信号SSTV，将启动控制信号CSTV经由第一节点K提供给移位寄存电路200作为输入 信号。在实施例中，启动输出电路130与启动控制信号端耦接，以接收启动控制信号CSTV。启动输出电路130与第一节点K和第二节点L耦接，以基于第二节点L的电压，即所保持的启动置位信号SSTV，将启动控制信号CSTV提供给第一节点K，从而提供给移位寄存电路200作为输入信号。
在实施例中，启动选择电路140可以根据启动选择信号EN，将启动输入信号STV经由第一节点K提供给移位寄存电路200作为输入信号。在实施例中，启动选择电路140可以与启动选择信号端耦接，以接收启动选择信号EN。启动选择电路140与启动输入信号端耦接，以接收启动输入信号STV。启动选择电路140与第一节点K耦接。启动选择电路140基于所接收的启动选择信号EN，从而将所接收的启动输入信号STV提供给第一节点K，提供给移位寄存电路200作为输入信号。
附加地，在本公开的实施例中，启动电路100还包括启动复位电路150。在实施例中，启动复位电路150可以根据来自启动复位信号端的启动复位信号RSTV对第二节点L进行复位。启动复位电路150与启动复位信号端耦接，以接收启动复位信号RSTV。启动复位电路150与第一电压端耦接，以接收第一电压VGL。在实施例中，第一电压端可提供低电平信号，即，第一电压VGL是低电平。启动复位电路150与第二节点L耦接。启动复位电路150可以基于所接收的启动复位信号RSTV，将所接收的第一电压VGL提供给第二节点L，将第二节点L的电压拉低，从而对第二节点L进行复位。
进一步地，在本公开的实施例中，移位寄存电路200可以包括输入电路210、输出电路220、下拉控制电路230、下拉电路240、显示复位电路250以及消隐复位电路260。下面参照附图，对其进行详细描述。
在实施例中，输入电路210耦接第一节点K、第三节点P和第一控制信号端，并且可以根据输入信号，将第一控制信号CN提供给第三节点P。应理解，虽然在图1中还示出了耦接在第三节点P与输出电路210之间的防漏电电路270，但该防漏电电路270是可选的而非是必需的。在实施例 中，输入电路210耦接第一控制信号端，以接收第一控制信号CN。在本公开的实施例中，第一控制信号端可提供高电平信号，即第一控制信号CN是高电平。输入电路210在第一节点K的电压的控制下，将所接收的第一控制信号CN输出给第三节点P(即，上拉节点)。在实施例中，第一控制信号端提供高电平，即第一控制信号CN为高电平。
在实施例中，输出电路220耦接第三节点P、第一时钟信号端和输出端OUTPUT，并被配置为根据第三节点P的电压和来自第一时钟信号端的第一时钟信号CK经由输出端OUTPUT输出扫描驱动信号。在实施例中，输出电路220耦接第一时钟信号端，以接收第一时钟信号CK。在第三节点P的电压的控制下，输出电路220将所接收的第一时钟信号CK提供给输出端OUTPUT，作为扫描驱动信号。
在本公开的实施例中，本领域技术人员可理解的是输出端的数量不限于一个，也可以是多个。对应地，每个输出电路与对应的时钟信号耦接。每个输出电路可根据第三节点P的电压和对应的时钟信号输出对应的驱动信号。
在实施例中，下拉控制电路230耦接第二时钟信号端、第四节点Q、第三节点P、第一电压端和输出端OUTPUT。下拉控制电路230可以根据第三节点P的电压、输出端OUTPUT的电压以及来自第二时钟信号端的第二时钟信号CKB，将来自第一电压端的第一电压信号VGL或第二时钟信号CKB提供给第四节点Q，以控制第四节点Q的电压。在实施例中，下拉控制电路230与第二时钟信号端耦接，以接收第二时钟信号CKB。下拉控制电路230与第一电压端耦接，以接收第一电压信号VGL。下拉控制电路230基于所接收的第二时钟信号CKB，将所接收的第二时钟信号CKB提供给第四节点Q。下拉控制电路230可以基于第三节点P的电压，将所接收的第一电压信号VGL提供给第四节点Q，以拉低第四节点Q的电压。下拉控制电路230还可以基于输出端OUTPUT的电压，将所接收的第一电压信号VGL提供给第四节点Q，以拉低第四节点Q的电压。
在实施例中，下拉电路240耦接第三节点P、第四节点Q、第一电压 端以及输出端OUTPUT，并且可以根据第四节点Q的电压，将第一电压信号VGL提供给第三节点P和输出端OUTPUT，以控制第三节点P和输出端OUTPUT的电压。在实施例中，下拉电路240耦接第一电压端，以接收第一电压信号VGL。下拉电路240在第四节点Q的电压的控制下，将所接收的第一电压信号VGL提供给第三节点P和输出端OUTPUT，拉低第三节点P和输出端OUTPUT的电压，从而控制第三节点P和输出端OUTPUT的电压。
在实施例中，显示复位电路250耦接显示复位信号端、第三节点P以及第二控制信号端，并且可以根据来自显示复位信号端的显示复位信号STD，将来自第二控制信号端的第二控制信号CNB提供给第三节点P，以对第三节点P进行复位。在实施例中，显示复位电路250可以耦接显示复位信号端，以接收显示复位信号STD。显示复位电路250可以耦接第二控制信号端，以接收第二控制信号CNB。在实施例中，第二控制信号端提供低电平，即第二控制信号CNB为低电平。显示复位电路250可以在所接收的显示复位信号STD的控制下将所接收的第二控制信号CNB提供给第三节点P，从而将第三节点P的电压拉低，对第三节点P进行复位。
在实施例中，消隐复位电路260耦接第三节点P、第一电压端以及消隐复位信号端，并且可以根据来自消隐复位信号端的消隐复位信号REST将第一电压信号VGL提供给第三节点P，以对第三节点P进行复位。在实施例中，消隐复位电路260可以耦接消隐复位信号端，以接收消隐复位信号REST。消隐复位电路260可以耦接第一电压端，以接收第一电压VGL。消隐复位电路260可以在所接收的消隐复位信号REST的控制下，将所接收的第一电压信号VGL(低电平)提供到第三节点P，从而将第三节点P的电压拉低，对第三节点P进行复位。
附加地，移位寄存电路200还可以包括防漏电电路270。在实施例中，防漏电电路270耦接第三时钟信号端，输出电路220经由防漏电电路270耦接第三节点P。防漏电电路270还可以根据来自第三时钟信号端的第三时钟信号CLK，防止输出电路220经由第三节点P发生漏电。在实施例中， 防漏电电路270与第三时钟信号端耦接，以接收第三时钟信号CLK。防漏电电路270可以经由第五节点R与输出电路220耦接。根据所接收的第三时钟信号CLK，防漏电电路270将第三节点P的电压经由第五节点R提供给输出电路220。并且防漏电电路270根据所接收的第三时钟信号CLK，防止第五节点R的电荷经由第三节点P泄漏。
附加地，移位寄存电路200还包括触控电路280。在实施例中，触控电路280耦接触控信号端、输出端OUTPUT和第一电压端，并且可以根据来自触控信号端的触控信号TOUCHEN将第一电压信号VGL提供给输出端OUTPUT，以控制输出端OUTPUT输出的显示驱动信号。在实施例中，触控电路280耦接触控信号端，以接收触控信号TOUCHEN。触控电路280耦接第一电压端，以接收第一电压信号VGL。触控电路280可以基于所接收的触控信号TOUCHEN，将所接收的第一电压信号VGL提供给输出端OUTPUT，拉低输出端OUTPUT的电压，扫描驱动信号为低电平，从而对扫描驱动信号进行控制。
本公开的实施例中，尽管图1所示的移位寄存器10中，以被配置为驱动显示装置进行正向扫描移位寄存器10为示例进行说明。其中，第N级移位寄存器的输出端可以耦接第N+1级移位寄存器的启动信号输入端，第N+1级移位寄存器的输出端可以耦接第N级移位寄存器的显示复位信号端，其中，N为正整数。第一控制信号CN被配置为高电平，第二控制信号CNB被配置为低电平。但这不能限制本公开的保护范围。在实施例中，移位寄存器也可以被配置为驱动显示装置进行反向扫描。其中，第N+1级移位寄存器的输出端也可以耦接第N级移位寄存器的启动信号输入端，第N级移位寄存器的输出端也可以耦接第N+1级移位寄存器的显示复位信号端，其中，N为正整数。第一控制信号CN也可以被配置为低电平，第二控制信号CNB也可以被配置为高电平。
本领域技术人员可以理解，尽管图1中的移位寄存器10示出了下拉控制电路230、下拉电路240、显示复位电路250、消隐复位电路260、防漏电电路270以及触控电路280，然而上述示例并不能限制本公开的保护范 围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
以下通过示例性电路结构来对本公开的实施例提供的移位寄存器进行描述。图2示出了根据本公开的实施例的移位寄存器的示例性电路图。移位寄存器例如是图1中所示的移位寄存器10。如图2所示，移位寄存器可以包括第一晶体管T1至第十三晶体管T13以及第一电容C1至第三电容C3。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其它特性相同的开关器件。本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。晶体管的栅极可被称为控制极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，导通电压为低电平电压，关断电压为高电平电压。当晶体管为N型晶体管时，导通电压为高电平电压，关断电压为低电平电压。
另外，需要说明的是，本公开的实施例中提供的移位寄存器中采用的晶体管均是以N型晶体管为例进行说明的。本公开的实施例包括但不限于此，例如移位寄存器中的至少部分晶体管也可以采用P型晶体管。
如图2所示，启动输入电路110包括第一晶体管T1。第一晶体管T1的控制极与启动输入信号端耦接以接收启动输入信号STV。第一晶体管T1的第一极耦接启动置位信号端，以接收启动置位信号SSTV。第一晶体管T1的第二极与第二节点L耦接。在实施例中，当启动输入信号STV为高电平时，第一晶体管T1导通，将所接收的启动置位信号SSTV提供给第二节点L。
保持电路120包括第一电容C1。第一电容C1的第一极耦接第二节点L。第一电容C1的第二极耦接第一节点K。可以存储启动置位信号SSTV 与第一节点K之间的电压差。如上述参考图1所述，第一节点K悬空，以及第一节点K的电压为低电平。在实施例中，当提供给第二节点的启动置位信号SSTV为高电平时，第一电容C1的两极的电压差为启动置位信号SSTV，第一电容C1充电。当第二节点L悬空且第一节点K为高电平时，由于第一电容C1的自举作用，第二节点L为更高电平。第一电容C1的两极的电压差保持为启动置位信号SSTV。
启动输出电路130包括第二晶体管T2。第二晶体管T2的控制极与第二节点L耦接。第二晶体管T2的第一极与启动控制信号端耦接，以接收启动控制信号CSTV。第二晶体管T2的第二极与第一节点K耦接。在实施例中，当第二节点L的电压为高电平时，第二晶体管T2导通，从而将所接收的启动控制信号CSTV提供给第一节点K，作为移位寄存电路200的输入信号。
启动选择电路140包括第三晶体管T3。第三晶体管T3的控制极耦接启动选择信号端，以接收启动选择信号EN。第三晶体管T3的第一极耦接启动输入信号端，以接收启动输入信号STV。第三晶体管T3的第二极与第一节点K耦接。在实施例中，当启动选择信号EN为高电平时，第三晶体管T3导通，将所接收的高电平的启动输入信号STV提供给第一节点K，作为移位寄存电路200的输入信号。在实施例中，当启动选择信号EN为低电平时，第三晶体管T3关断。此时，如上所述提供给第一节点K的启动控制信号CSTV可以作为移位寄存电路200的输入信号。
启动复位电路150包括第四晶体管T4。第四晶体管T4的控制极耦接启动复位信号端，以接收启动复位信号RSTV。第四晶体管T4的第一极耦接第二节点L。第四晶体管T4的第二极耦接第一电压端，以接收所述第一电压信号VGL。在实施例中，当启动复位信号RSTV为高电平时，第四晶体管T4导通，将第一电压信号VGL提供给第二节点L，拉低第二节点L的电压，从而对第二节点L进行复位。
输入电路210包括第五晶体管T5。第五晶体管T5的控制极与第一节点K耦接，以接收输入信号。第五晶体管T5的第一极耦接第一控制信号 端，以接收第一控制信号CN(高电平)。第五晶体管T5的第二极耦接第三节点P。在实施例中，当输入信号为高电平时，第五晶体管T5导通，将所接收的高电平的第一控制信号CN提供给第三节点P。
输出电路220包括第六晶体管T6和第二电容C2。第六晶体管T6的控制极与第三节点P耦接。第六晶体管T6的第一极耦接第一时钟信号端，以接收第一时钟信号CK。第六晶体管T6的第二极耦接输出端OUTPUT。第二电容C2的第一极与第三节点P耦接。第二电容C2的第二极与输出端OUTPUT耦接。在实施例中，当第三节点P为高电平时，第六晶体管T6导通，将所接收的第一时钟信号CK提供给输出端OUTPUT，作为扫描驱动信号。
下拉控制电路230包括第七晶体管T7、第八晶体管T8、第九晶体管T9和第三电容C3。第七晶体管T7的控制极和第一极与第二时钟信号端耦接，以接收第二时钟信号CKB。第七晶体管T7的第二极与第四节点Q耦接。第八晶体管T8的控制极与第三节点P耦接。第八晶体管T8的第一极与第四节点Q耦接。第八晶体管T8的第二极与第一电压端耦接，以接收第一电压信号VGL。第九晶体管T9的控制极与输出端OUTPUT耦接。第九晶体管T9的第一极与第四节点Q耦接。第九晶体管T9的第二极与第一电压端耦接，以接收第一电压信号VGL。第三电容C3的第一极与第四节点Q耦接。第三电容C3的第二极与第一电压端耦接。在实施例中，当第二时钟信号CKB为高电平时，第七晶体管T7导通，将所接收的第二时钟信号CKB提供给第四节点Q。在实施例中，当第三节点P的电压为高电平时，第八晶体管T8导通，将所接收的第一电压信号VGL(低电平)提供给第四节点Q。在实施例中，输出端OUTPUT的电压为高电平时，第九晶体管T9导通，将所接收的第一电压信号VGL(低电平)提供给第四节点Q。
下拉电路240包括第十晶体管T10和第十一晶体管T11。第十晶体管T10的控制极与第四节点Q耦接。第十晶体管T10的第一极与第三节点P耦接。第十晶体管T10的第二极与第一电压端耦接，以接收第一电压信号 VGL。第十一晶体管T11的控制极与第四节点Q耦接。第十一晶体管T11的第一极与输出端OUTPUT耦接。第十一晶体管T11的第二极与第一电压端耦接，以接收第一电压信号VGL。在实施例中，当第四节点Q为高电平时，第十晶体管T10和第十一晶体管T11均导通，将所接收的第一电压信号VGL(低电平)分别提供给第三节点P和输出端OUTPUT，以拉低第三节点P和输出端OUTPUT的电压。
显示复位电路250包括第十二晶体管T12。第十二晶体管T12的控制极耦接显示复位信号端，以接收显示复位信号STD。第十二晶体管T12的第一极耦接第三节点P。第十二晶体管T12的第二极与第一电压端耦接，以接收第一电压信号VGL。在实施例中，当显示复位信号STD为高电平时，第十二晶体管T12导通，将所接收的第一电压信号VGL(低电平)提供给第三节点P，拉低第三节点P，以对第三节点P进行复位。
消隐复位电路260包括第十三晶体管T13。第十三晶体管T13的控制极与消隐复位信号端耦接，以接收消隐复位信号REST。第十三晶体管T13的第一极耦接第三节点P。第十三晶体管T13的第二极与第一电压端耦接，以接收第一电压信号VGL。在实施例中，当消隐复位信号REST为高电平时，第十三晶体管T13导通，将所接收的第一电压信号VGL(低电平)提供给第三节点P，拉低第三节点P，以对第三节点P进行复位。
为了使显示装置的公共电极在显示期间和消隐期间为显示功能提供电力，而在触控期间为触控功能提供电力，并且防止移位寄存电路200发生漏电，在本公开的另一些实施例中，移位寄存电路200还可包括防漏电电路270。防漏电电路270包括第十四晶体管T14。第十四晶体管T14的控制极与第三时钟信号端耦接，以接收第三时钟信号CLK。第十四晶体管T14的第一极与第三节点P耦接。第十四晶体管T14的第二极与第五节点R耦接。当第三时钟信号CLK为高电平时，第十四晶体管T14导通，将第三节点P的电压经由第五节点R提供输出电路220。当第三时钟信号CLK为低电平时，第十四晶体管T14关断，防止第五节点R的电荷经由第三节点P泄漏。
在本公开的另一些实施例中，移位寄存电路200还可包括触控电路280。触控电路280包括第十五晶体管T15。第十五晶体管T15的控制极耦接触控信号端，以接收触控信号TOUCHEN。第十五晶体管T15的第一极耦接输出端OUTPUT。第十五晶体管T15的第二极与第一电压端耦接，以接收第一电压信号VGL。在实施例中，当触控信号TOUCHEN为高电平时，第十五晶体管T15导通，将所接收的第一电压信号VGL(低电平)提供给输出端OUTPUT，拉低输出端OUTPUT，扫描驱动信号为低电平，从而控制扫描驱动信号。
此外，本公开的实施例还提供了用于驱动移位寄存器的方法。图3示出了根据本公开的实施例的用于驱动移位寄存器的方法的示意性流程图。移位寄存器可以是基于本公开的实施例的任何可适用的移位寄存器。
在步骤310，启动电路100根据启动选择信号EN将启动输入信号STV和启动控制信号CSTV中的一者经由第一节点K提供给移位寄存电路200作为输入信号。
进一步地，在选定从某一行像素开始进行显示时，与该行像素对应的移位寄存器进行如下步骤：在第一阶段，启动电路100根据启动选择信号EN和启动输入信号STV存储启动置位信号SSTV。在第二阶段，启动电路100根据所存储的启动置位信号SSTV将启动控制信号CSTV经由第一节点K提供给移位寄存电路200作为输入信号。
进一步地，在第一阶段，启动输入电路100根据启动选择信号STV将启动置位信号SSTV经由第二节点L提供给启动保持电路120，启动保持电路120存储并保持启动置位信号SSTV；在第二阶段，启动输出电路130根据所保持的启动置位信号SSTV，将启动控制信号CSTV经由第一节点K提供给移位寄存电路200作为输入信号。
在实施例中，当选择从第i行像素开始进行显示时，与该行对应的启动电路100在第一阶段的显示期间D1接收低电平的启动选择信号EN和高电平的启动输入信号STV。在高电平的启动输入信号STV的控制下，高电平的启动置位信号SSTV被提供给第二节点L。此高电平的启动置位信 号SSTV被保持电路120存储并保持。与第i行像素对应的启动电路100在第二阶段的显示期间D2接收高电平的启动控制信号CSTV。基于所保持的高电平的启动置位信号SSTV，启动输出电路130将所接收的高电平的启动控制信号CSTV提供给第一节点K，从而提供给相应的移位寄存电路200作为输入信号。
在步骤320，移位寄存电路200根据高电平的输入信号生成扫描驱动信号。在实施例中，在所接收的高电平的输入信号的控制下，移位寄存电路200将第一时钟信号CK提供给输出端OUTPUT，作为显示驱动信号。
本领域技术人员可以理解，以上各步骤虽然按顺序描述，但并不构成对方法顺序的限定，本公开的实施例也可以以任何其它合适顺序实施。
本公开的实施例还提供了由移位寄存器构成的栅极驱动电路。图4示出了根据本公开的实施例的栅极驱动电路40的示意图。如图4所示，栅极驱动电路40可包括多个移位寄存器。任意一个或多个移位寄存器可以采用本公开的实施例提供的移位寄存器10的结构或其变型。图4中仅示意性的示出了前三个移位寄存器，即，与第一行像素对应的第一移位寄存器SR_1、与第二行像素对应的第二移位寄存器SR_2、与第三行像素对应的第三移位寄存器SR_3。
根据本公开的实施例，第N级移位寄存器的输出端耦接第N+1级移位寄存器的启动输入信号端，其中，N为正整数。如图4所示，第一移位寄存电器SR_1的启动输入信号端从启动输入信号线INPUT接收启动输入信号STV_1。第一移位寄存器SR_1的输出端OUTPUT_1与第二移位寄存器SR_2的启动输入信号端耦接，以提供启动输入信号STV_2。第二移位寄存器SR_2的输出端OUTPUT_2与移位寄存器SR_3的启动输入信号端耦接，以提供启动输入信号STV_3。
在本公开的实施例中，栅极驱动电路40还包括启动选择信号线CLK_A和启动控制信号线CLK_B。启动选择信号线CLK_A与三个移位寄存器的启动选择信号端耦接，以提供启动选择信号EN。启动控制信号线CLK_B与三个移位寄存器的启动控制信号端耦接，以提供启动控制信号CSTV。
栅极驱动电路40还可包括启动置位信号线CLK_C和启动复位信号线CLK_D。启动置位信号线CLK_C与三个移位寄存器的启动置位信号端耦接，以提供启动置位信号SSTV。启动复位信号线CLK_D与三个移位寄存器的启动复位信号端耦接，以提供启动复位信号RSTV。
栅极驱动电路40还包括第一时钟信号线CLK_E、第二时钟信号线CLK_F和消隐复位信号线CLK_G。第一时钟信号线CLK_E所与奇数级的移位寄存器的第一时钟信号端耦接以提供第一时钟信号CK，并且与偶数级的移位寄存器的第二时钟信号端耦接以提供第二时钟信号CKB。第二时钟信号线CLK_F与偶数级的移位寄存器的第一时钟信号端耦接以提供第一时钟信号CK，并且与奇数级的移位寄存器的第二时钟信号端耦接以提供第二时钟信号CKB。在实施例中，第一时钟信号线CLK_E与第一移位寄存器SR_1和第三移位寄存器SR_3的第一时钟时钟信号端耦接，以提供第一时钟信号CK。第一时钟信号线CLK_E与第二移位寄存器SR_2的第二时钟信号端耦接，以提供第二时钟信号CKB。第二时钟信号线CLK_F与第二移位寄存器SR_2的第一时钟信号端耦接，以提供第一时钟信号CK。第二时钟信号线CLK_F与第一移位寄存器SR_1和第三移位寄存器SR_3的第二时钟时钟信号端耦接，以提供第二时钟信号CKB。消隐复位信号线CLK_G与三个移位寄存器的消隐复位信号端耦接，以提供消隐复位信号RSET。
此外，第N+1级移位寄存器的输出端耦接第N级移位寄存器的显示复位信号端，其中，N为正整数。如图4所示，第二移位寄存器SR_2的输出端OUTPUT_2耦接第一移位寄存器SR_1的显示复位信号端，提供显示复位信号STD_1。第三移位寄存电器SR_3的输出端OUTPUT_3耦接第二移位寄存器SR_2的显示复位信号端，提供显示复位信号STD_2。
下面结合图5中的信号时序图，对图4中所示的栅极驱动电路40的工作过程进行说明。在实施例中，栅极驱动电路40中的移位寄存器例如具有图2所示的移位寄存器的电路结构。
图5示出了栅极驱动电路40从第二行像素开始逐行进行显示的信号 时序图。第一时钟信号线CLK_E向第一移位寄存器SR_1和第三移位寄存器SR_3提供第一时钟信号CK。第二时钟信号线CLK_F向第一移位寄存器SR_1和第三移位寄存器SR_3提供第二时钟信号CKB。启动输入信号线INPUT向第一移位寄存器SR_1提供启动输入信号STV。启动置位信号线CLK_C向三个移位寄存器提供启动置位信号SSTV。启动控制信号线CLK_B向三个移位寄存器提供启动控制信号CSTV。启动选择信号线CLK_A向三个移位寄存器提供启动选择信号EN。启动复位信号线CLK_D向三个移位寄存器提供启动复位信号RSTV。信号VK、VL、VP和VQ分别表示栅极驱动电路40中第二移位寄存器SR_2的第一节点K_2、第二节点L_2、第三节点P_2和第四节点Q_2的电压信号。输出信号OUT_1、OUT_2和OUT_3表示分别与第一行、第二行和第三行像素对应的第一移位寄存器SR_1、第二移位寄存器SR_2和第三移位寄存器SR_3的输出端OUTPUT_1、OUTPUT_2和OUTPUT_3输出的输出信号。可以理解的是，图5所示的信号时序图中的信号电压只是示意性的，不代表真实电压值。
如图5所示，第一阶段和第二阶段分别包括显示期间(D1和D2)和消隐期间(B1和B2)。应理解，在本公开的实施例中，消隐期间指的是显示装置不进行显示刷新的阶段。在此期间，栅极驱动电路不再提供用于刷新显示图像的显示驱动信号，显示装置仍然显示上一显示期间所显示的图像。
在第一阶段开启前，消隐复位信号线CLK_G和启动复位信号线CLK_D均提供高电平信号。因此，三个移位寄存器中的第十三晶体管T13和第四晶体管T4均导通。由此，将第一电压VGL(低电平)提供给第二节点L和第三节点P，以将第二节点L和第三节点P的电压拉低。由此，对三个移位寄存器的第二节点L和第三节点P进行复位。
然后，第一阶段开始，消隐复位信号线CLK_G和启动复位信号线CLK_D均变为低电平信号。第十三晶体管T13和第四晶体管T4关断。
以下对栅极驱动电路40中的第二移位寄存器SR_2及相关移位寄存器进行详细描述。
在第一阶段的显示期间D1，显示装置从第一行像素开始进行顺序显示，与第二行像素对应的启动电路100存储并保持启动置位信号SSTV，在第1时段，移位寄存器SR_1接收高电平的启动输入信号STV_1、高电平的启动选择信号EN和低电平的启动置位信号SSTV。第一晶体管T1导通，所接收的低电平的启动置位信号SSTV被提供给第二节点L_1，第二节点L_1的电压为低电平。第三晶体管T3导通，所接收的高电平的启动输入信号STV_1被提供给第一节点K_1。第一电容C1两极之间的电压差为低电平与高电平之间的电压差，第一电容C1被反向充电。第一节点K_1的电压为高电平，第五晶体管T5导通，高电平的第一控制信号CN被提供给第三节点P_1，第三节点P_1的电压为高电平。此高电平由第二电容C2存储并保持。
在第2时段，移位寄存器SR_1接收高电平的第一时钟信号CK。在第二电容C2的自举作用下，第三节点P_1的电压被进一步拉高。在第三节点P_1的更高电平的控制下，第六晶体管T6导通。移位寄存器SR_1经由输出端OUTPUT_1输出高电平的扫描驱动信号OUT_1。高电平的扫描驱动信号OUT_1可以用于驱动显示装置中的第一行像素，也可以作为第二移位寄存电器SR_2的启动输入信号STV_2。
另外，在第2时段，第二移位寄存电器SR_2接收高电平的启动输入信号STV_2和高电平的启动置位信号SSTV。第一晶体管T1导通，所接收的高电平的启动置位信号SSTV被提供给第二节点L_2，第二节点L_2的电压为高电平。第二晶体管T2导通，所接收的低电平的启动控制信号CSTV被提供给第一节点K_2，第一节点K_2的电压为低电平。因此，所接收的高电平的启动置位信号SSTV由第一电容C1存储并保持。由于第一节点K_2的电压为低电平，第五晶体管T5关断，第三节点P_2的电压为低电平，因此输出端OUTPUT_2提供低电平的显示驱动信号OUT_2。
由于第二移位寄存电器SR_2的输出端OUTPUT_2与第三移位寄存电器SR_3的启动输入信号端耦接，因此第三移位寄存电器SR_3的启动输入信号STV_3为低电平。第三晶体管T3导通，低电平的启动输入信号STV_3 被提供给第一节点K_3，第一节点K_3的电压为低电平。第二节点L_3为低电平，第一电容C1两极的电压差为0伏，第一电容C1未被充电。由于第一节点K_3的电压为低电平，第五晶体管T5关断，第三节点P_3的电压为低电平，因此输出端OUTPUT_3提供低电平的显示驱动信号OUT_3。
然后，进入第一阶段的消隐期间B1，在此期间对移位寄存电路进行复位。在第3时段，消隐复位信号线CLK_G提供高电平信号。因此，三个移位寄存器中的第十三晶体管T13导通。由此，将第一电压信号VGL(低电平)提供给第三节点P，以将第三节点P的电压拉低。由此，对三个移位寄存器的第三节点P进行复位。
在第二阶段的显示阶段D2，显示装置从第二行像素开始顺序进行显示。在第4时段，第二移位寄存电器SR_2接收高电平的启动控制信号CSTV。由于第一电容C1的自举作用，第二节点L_2的电压被进一步拉高。在第二节点L_2的更高电平的控制下，第二晶体管T2导通，所接收的高电平的启动控制信号CSTV被提供给第一节点K_2，第一节点K_2的电压为高电平。第五晶体管T5导通，高电平的第一控制信号CN被提供给第三节点P_2，第三节点P_2的电压为高电平。此高电平由第二电容C2存储并保持。
此时，第一移位寄存器SR_1接收高电平的启动控制信号CSTV。此时第一节点K_1处于悬空状态，且第一节点K_1耦接负载较大，因此第一节点K_1为低电平。由于第一电容C1两极的电压差为低电平与高电平之间的电压差，因此第二节点L_1的电压为更低电平。在第二节点L_1的更低电平的控制下，第二晶体管T2关断，高电平的启动控制信号CSTV不能提供给第一节点K_1，第一节点K_1为低电平。
此时，第三移位寄存器SR_3接收高电平的启动控制信号CSTV。此时第一节点K_3也处于悬空状态且第一节点K_3耦接负载较大，因此第一节点K_3也为低电平。由于第一电容C1两极的电压差为0伏，因此第二节点L_3的电压为低电平。在第二节点L_3的低电平的控制下，第二晶体管T2关断，高电平的启动控制信号CSTV不能提供给第一节点K_3，第一节点K_3为低电平。
在第5时段，第二移位寄存器SR_2接收高电平的第一时钟信号CK。在第二电容C2的自举作用下，第三节点P_2的电压被进一步拉高。在第三节点P_2的更高电平的控制下，第六晶体管T6导通，所接收的高电平的第一时钟信号CK被提供给输出端OUTPUT_2。因此，第二移位寄存器SR_2输出高电平的扫描驱动信号OUT_2。高电平的扫描驱动信号OUT_2可以用于驱动第二行像素，也可以作为第三移位寄存器SR_3的启动输入信号STV_3。
此时，对于第三移位寄存器SR_3，其接收高电平的启动选择信号EN。第三晶体管T3导通，所接收的高电平的启动输入信号STV_3被提供给第一节点K_3，第一节点K_3的电压为高电平。在第一节点K_3的高电平的控制下，第五晶体管T5导通，高电平的第一控制信号CN被提供给第三节点P_3。此高电平由第二电容C2存储并保持。
在第6时段，第二移位寄存器SR_2所接收的第一时钟信号CK变为低电平。由于第二电容C2两极的电压差为高电平，因此第三节点P_2的电压变为高电平。
在第7时段，第三移位寄存器SR_3接收高电平的第一时钟信号CK。第六晶体管T6导通，第三移位寄存器SR_3输出高电平的扫描驱动信号OUT_3。此过程与在第5时段所述的第二移位寄存器SR_2输出高电平的扫描驱动信号OUT_2类似，在此不再赘述。扫描驱动信号OUT_3可以用于驱动第三行像素，也可以作为第四移位寄存器SR_4(未示出)的启动输入信号STV_4(未示出)，还可以作为第二移位寄存器的SR_2的显示复位信号STD_2。
此时，第二移位寄存器SR_2接收高电平的显示复位信号STD_2。第十二晶体管T12导通，低电平的第一电压VGL被提供给第三节点P_3，第三节点P_3的电压被拉低，从而对第三节点P_3进行复位。
进入第二阶段的消隐期间B2，此时对三个移位寄存器进行复位。在第8时段，消隐复位信号线CLK_G和启动复位信号线CLK_D提供高电平信号。因此，三个移位寄存器中的第十三晶体管T13和第四晶体管T4导通。 由此，将第一电压信号VGL(低电平)提供给第三节点P和第二节点L，以将第三节点P和第二节点L的电压拉低。由此，对三个移位寄存器的第三节点P和第二节点L进行复位。
需要说明的是，尽管在本公开的实施例中，以第二阶段仅包括一个显示期间和一个消隐期间为例，但这不作为限制，第二阶段还可以包括M个显示期间和消隐期间，其中，M为正整数。在第二阶段包括多个显示期间和消隐期间的情况下，在第一至第M-1个消隐期间仅对第三节点P进行复位，在第M个消隐期间对第三节点P和第二节点L进行复位。进一步地，在第一至第M-1个消隐期间，消隐复位信号线CLK_G提供高电平信号，对各级移位寄存器的第三节点P进行复位。在第M个消隐期间，消隐复位信号线CLK_G和启动复位信号线CLK_D提供高电平信号，对各级移位寄存器第三节点P和第二节点L进行复位。此过程与上述在第二消隐期间B2中对第三节点P和第二节点L进行复位的过程类似，在此不再赘述。
另外，上述从指定行开始驱动的原理是以从第二行像素开始进行顺序驱动进行说明的，然而本公开对此不作限定。在本公开的实施例中，当需要从显示装置的第i行(不是第一行和最后一行)像素进行显示时，在第一阶段，启动置位信号SSTV的高电平的持续期间和启动选择信号EN的低电平的持续期间相同。进一步地，与第i行像素对应的启动输入信号STV的高电平的持续期间落入启动置位信号SSTV的高电平的持续期间和启动选择信号EN的低电平的持续期间内，且上升沿或下降沿处于同一时间点。存储并保持第i级移位寄存器的启动置位信号SSTV。然后在第二阶段，启动控制信号CSTV的高电平的持续期间与启动选择信号EN的低电平的持续期间相同。基于所存储的启动置位信号SSTV，将高电平的第一时钟信号CK通过第i级移位寄存器的输出端OUTPUT输出，作为扫描驱动信号。从而，驱动第i行像素进行显示，并使得之后的其它行顺序显示。
另一方面，本公开的实施例还提供了阵列基板。阵列基板可包括根据本公开的实施例的栅极驱动电路。此外，本公开的实施例还提供了包括上述阵列基板的显示装置。在实施例中，显示装置可以为液晶面板、液晶电 视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变型。本公开的保护范围由所附权利要求限定。

Claims (21)

  1. 一种移位寄存器，包括启动电路和移位寄存电路，其中，
    所述启动电路被配置为根据来自启动选择信号端的启动选择信号将来自启动输入信号端的启动输入信号和来自启动控制信号端的启动控制信号中的一者经由第一节点提供给所述移位寄存电路作为输入信号；以及
    所述移位寄存电路被配置为根据所述输入信号和来自第一时钟信号端的第一时钟信号，通过输出端提供扫描驱动信号。
  2. 根据权利要求1所述的移位寄存器，
    其中，所述启动电路被配置为在第一阶段根据所述启动输入信号，存储并保持来自启动置位信号端的启动置位信号；
    其中，所述启动电路被配置为在第二阶段根据所保持的启动置位信号，将启动控制信号经由所述第一节点提供给所述移位寄存电路作为所述输入信号。
  3. 根据权利要求2所述的移位寄存器，所述启动电路包括启动输入电路、启动保持电路、启动输出电路以及启动选择电路，其中，
    所述启动输入电路被配置为根据所述启动输入信号，将所述启动置位信号提供给第二节点；
    所述启动保持电路被配置为存储并保持所述启动置位信号；
    所述启动输出电路被配置为根据所保持的启动置位信号，将所述启动控制信号经由所述第一节点提供给所述移位寄存电路作为所述输入信号；以及
    所述启动选择电路被配置为根据所述启动选择信号，将所述启动输入信号经由所述第一节点提供给所述移位寄存电路作为所述输入信号。
  4. 根据权利要求3所述的移位寄存器，所述启动电路还包括启动复位电路，其中，所述启动复位电路被配置为根据来自启动复位信号端的启动复位信号对所述第二节点进行复位。
  5. 根据权利要求3所述的移位寄存器，所述启动输入电路包括第一晶体管，其中，所述第一晶体管的控制极耦接所述启动输入信号端，所述第 一晶体管的第一极耦接所述启动置位信号端，所述第一晶体管的第二极耦接所述第二节点。
  6. 根据权利要求3所述的移位寄存器，所述启动保持电路包括第一电容，其中，所述电容的第一极耦接所述第二节点，所述电容的第二极耦接所述第一节点。
  7. 根据权利要求3所述的移位寄存器，所述启动输出电路包括第二晶体管，其中，所述第二晶体管的控制极耦接所述第二节点，所述第二晶体管的第一极耦接所述启动控制信号端，所述第二晶体管的第二极耦接所述第一节点。
  8. 根据权利要求3所述的移位寄存器，所述启动选择电路包括第三晶体管，其中，所述第三晶体管的控制极耦接所述启动选择信号端，所述第三晶体管的第一极耦接所述启动输入信号端，所述第三晶体管的第二极耦接所述第一节点。
  9. 根据权利要求4所述的移位寄存器，所述启动复位电路包括第四晶体管，其中，所述第四晶体管的控制极耦接所述启动复位信号端，所述第四晶体管的第一极耦接所述第二节点，所述第四晶体管的第二极耦接第一电压端。
  10. 根据权利要求2所述的移位寄存器，其中，所述移位寄存电路包括：输入电路、输出电路、下拉控制电路、下拉电路、显示复位电路、消隐复位电路；
    其中，所述输入电路耦接所述第一节点、第三节点和第一控制信号端，并被配置为根据所述输入信号，将所述第一控制信号提供给所述第三节点；
    其中，所述输出电路耦接所述第三节点、第一时钟信号端和所述输出端，并被配置为根据所述第三节点的电压和来自所述第一时钟信号端的第一时钟信号经由所述输出端提供所述扫描驱动信号；
    其中，所述下拉控制电路耦接第二时钟信号端、第四节点、所述第三节点、第一电压端和所述输出端，并被配置为根据所述第三节点的电压和所述输出端的电压，将来自所述第一电压端的第一电压信号提供给所述第 四节点，以控制所述第四节点的电压；以及被配置为根据来自所述第二时钟信号端的第二时钟信号控制所述第四节点的电压；
    其中，所述下拉电路耦接所述第三节点、所述第四节点、所述第一电压端以及所述输出端，并被配置为根据所述第四节点的电压，将所述第一电压信号提供给所述第三节点和所述输出端，以控制所述第三节点和所述输出端的电压；
    其中，所述显示复位电路耦接显示复位信号端、所述第三节点以及第二控制信号端，并被配置为根据来自所述显示复位信号端的显示复位信号，将来自所述第二控制信号端的第二控制信号提供给所述第三节点，以对所述第三节点进行复位；以及
    其中，所述消隐复位电路耦接所述第三节点、所述第一电压端以及消隐复位信号端，并被配置为根据来自所述消隐复位信号端的消隐复位信号将所述第一电压信号提供给所述第三节点，以对所述第三节点进行复位。
  11. 根据权利要求10所述的移位寄存器，其中，所述移位寄存电路进一步包括防漏电电路，其中，
    所述防漏电电路耦接第三时钟信号端，所述输出电路经由所述防漏电电路耦接所述第三节点，并且
    所述防漏电电路被配置为根据来自所述第三时钟信号端的第三时钟信号，防止所述输出电路经由所述第三节点发生漏电。
  12. 根据权利要求10或权利要求11所述的移位寄存器，所述移位寄存电路进一步包括触控电路，其中，
    所述触控电路耦接触控信号端、所述输出端和所述第一电压端，并被配置为根据来自所述触控信号端的触控信号将所述第一电压信号提供给所述输出端，以控制所述输出端提供的所述显示驱动信号。
  13. 一种用于驱动根据权利要求1-12中任一项所述的移位寄存器的驱动方法，包括：
    启动电路根据启动选择信号将启动输入信号和启动控制信号中的一者经由第一节点提供给移位寄存电路作为输入信号；以及
    所述移位寄存电路根据所述输入信号生成扫描驱动信号。
  14. 根据权利要求13所述的方法，所述方法还包括：
    在第一阶段，所述启动电路根据所述启动选择信号和所述启动输入信号存储启动置位信号；以及
    在第二阶段，所述启动电路根据所存储的启动置位信号将启动控制信号经由所述第一节点提供给所述移位寄存电路作为所述输入信号，所述移位寄存电路根据所述输入信号生成所述扫描驱动信号。
  15. 根据权利要求14所述的方法，所述方法，还包括：
    在所述第一阶段，启动输入电路根据所述启动选择信号将所述启动置位信号经由第二节点提供给启动保持电路，所述启动保持电路存储并保持所述启动置位信号；以及
    在所述第二阶段，所述启动输出电路根据所保持的启动置位信号将所述启动控制信号经由所述第一节点提供给所述移位寄存电路作为所述输入信号，所述移位寄存电路根据所述输入信号生成所述扫描驱动信号。
  16. 一种栅极驱动电路，包括多个如权利要求1至12中任一项所述的移位寄存器，其中，第N级移位寄存器的输出端耦接第N+1级移位寄存器的启动信号输入端，其中，N为正整数。
  17. 根据权利要求16所述的栅极驱动电路，还包括启动选择信号线和启动控制信号线，其中
    所述启动选择信号线与各个移位寄存器的启动选择信号端耦接以提供启动选择信号；以及
    所述启动控制信号线与各个移位寄存器的启动控制信号端耦接以提供启动控制信号。
  18. 根据权利要求16所述的栅极驱动电路，还包括启动置位信号线和启动复位信号线，其中，
    所述启动置位信号线与各个移位寄存器的启动置位信号端耦接以提供启动置为信号；以及
    所述启动复位信号线与各个移位寄存器的启动复位信号端耦接以提供 启动复位信号。
  19. 根据权利要求17所述的栅极驱动电路，还包括第一时钟信号线、第二时钟信号线、消隐复位信号线以及触控信号线，其中，
    所述第一时钟信号线与奇数级的移位寄存器的第一时钟信号端耦接以提供第一时钟信号，并且与偶数级的移位寄存器的第二时钟信号端耦接以提供第二时钟信号；
    所述第二时钟信号线与偶数级的移位寄存器的所述第一时钟信号端耦接以提供所述第一时钟信号，并且与奇数级的移位寄存器的所述第二时钟信号端耦接以提供所述第二时钟信号；
    所述消隐复位信号线与各个移位寄存器的消隐复位信号端耦接以提供消隐复位信号；
    所述第三时钟信号线与各个移位寄存器的第三时钟信号端耦接以提供第三时钟信号；
    所述触控信号线与各个移位寄存器的触控信号端耦接以提供触控信号；以及
    第N+1级移位寄存器的输出端耦接第N级移位寄存器的显示复位信号端，其中，N为正整数。
  20. 一种阵列基板，包括根据权利要求16-19中任一项所述的栅极驱动电路。
  21. 一种显示装置，包括根据权利要求20所述的阵列基板。
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