WO2020140321A1 - Goa扫描电路和液晶显示装置 - Google Patents

Goa扫描电路和液晶显示装置 Download PDF

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Publication number
WO2020140321A1
WO2020140321A1 PCT/CN2019/076819 CN2019076819W WO2020140321A1 WO 2020140321 A1 WO2020140321 A1 WO 2020140321A1 CN 2019076819 W CN2019076819 W CN 2019076819W WO 2020140321 A1 WO2020140321 A1 WO 2020140321A1
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WIPO (PCT)
Prior art keywords
film transistor
thin film
terminal
goa
path
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PCT/CN2019/076819
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English (en)
French (fr)
Inventor
吕晓文
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020140321A1 publication Critical patent/WO2020140321A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto

Definitions

  • the present disclosure relates to the field of display technology, in particular to a GOA (gate driver on array) scanning circuit and a liquid crystal display device.
  • GOA gate driver on array
  • LCD Liquid crystal display
  • PDA personal Digital assistant
  • digital camera computer screen or laptop screen, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module (backlight module) module).
  • the working principle of the liquid crystal display panel is to infuse liquid crystal molecules between the thin film transistor array substrate and the color filter substrate, and apply a driving voltage to the two substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module Come out to produce the picture.
  • each pixel is electrically connected to a thin film transistor, the gate of the thin film transistor is connected to the horizontal scanning line, the drain is connected to the data line in the vertical direction, and the source is connected to the pixel electrode.
  • the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly performed by an external integrated circuit board (integrated circuit, IC), the external IC can control the charging and discharging of the horizontal scanning lines at all levels.
  • GOA gate driver on array
  • GOA technology is the array substrate row drive technology, which can use the original array manufacturing process of the liquid crystal display panel to make the horizontal scanning line drive circuit on the substrate around the display area, so that it can replace the external IC to complete the horizontal scanning line drive.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product costs, and can make LCD panels more suitable for making narrow-frame or non-frame display products.
  • the present disclosure provides a GOA scanning circuit, including a plurality of cascaded GOA circuit units, each GOA circuit unit including:
  • a bidirectional input module including a first thin-film transistor and a second thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the stage 4 signal of the lower four-level GOA circuit unit, and the control terminal of the second thin-film transistor is connected to the upper four The signal of the stage GOA circuit unit, wherein the first path terminal of the first thin film transistor is used to input a first constant voltage, the second path terminal of the first thin film transistor is connected to the first node, and the second thin film The first path terminal of the transistor is used to input a second constant voltage, and the second path terminal of the second thin film transistor is connected to the first node;
  • An output module connected to the first node and used for outputting the cascade signal of the current GOA circuit unit and outputting the scan signal of the current GOA circuit unit according to the potential of the first node;
  • Pull-down module connected to the first node and used to output a first clock signal according to the potential of the first node
  • the output module includes a third thin film transistor and a fourth thin film transistor, the control terminal of the third thin film transistor and the control terminal of the fourth thin film transistor are both connected to the first node, and the third thin film transistor
  • the first path end is used to output a second clock signal
  • the second path end of the third thin-film transistor is used to output the stage-transmitted signal of the GOA circuit unit of the current stage
  • the first path of the fourth thin-film transistor The terminal is used to output the second clock signal
  • the second path terminal of the fourth thin film transistor is used to output the scan signal of the GOA circuit unit of the current stage;
  • the first clock signal and the second clock signal are inverted.
  • the pull-down module includes a fifth thin-film transistor and a sixth thin-film transistor. Both the control terminal of the fifth thin-film transistor and the control terminal of the sixth thin-film transistor are used to output the A first clock signal, a first path end of the fifth thin film transistor is connected to the first node, a second path end of the fifth thin film transistor is connected to a first stabilized voltage, and a first of the sixth thin film transistor The path end is used to output the scan signal of the GOA circuit unit at the current stage, and the second path end of the sixth thin film transistor is connected to a second stabilized voltage.
  • each GOA circuit unit further includes a seventh thin film transistor and an eighth thin film transistor, a first path end of the seventh thin film transistor is connected to the first node, and the seventh thin film The second path end of the transistor is connected to the first regulated voltage, the first path end of the eighth thin film transistor is used to output the scan signal of the GOA circuit unit of the current stage, and the first The second channel end is connected to the second regulated voltage.
  • each GOA circuit unit further includes a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor and a twelfth thin film transistor, the control terminal and the first A channel terminal outputs a low-frequency clock signal.
  • the second channel terminal of the ninth thin film transistor is connected to the first channel terminal of the tenth thin film transistor, and the control terminal of the tenth thin film transistor is connected to the first node.
  • the second path terminal of the tenth thin film transistor is connected to the second regulated voltage
  • the control terminal of the eleventh thin film transistor is connected to the second channel terminal of the ninth thin film transistor and the tenth thin film transistor
  • the first channel end of the first channel, the first channel end of the eleventh thin film transistor outputs the low frequency clock signal
  • the second channel end of the eleventh thin film transistor is connected to the control of the seventh thin film transistor End
  • the control end of the twelfth thin film transistor is connected to the control end of the tenth thin film transistor
  • the first channel end of the twelfth thin film transistor is connected to the second of the eleventh thin film transistor
  • a channel terminal and the control terminal of the seventh thin film transistor, and a second channel terminal of the twelfth thin film transistor is connected to the second regulated voltage.
  • control terminals of the first thin film transistor to the twelfth thin film transistor are all gates, and the first channel of the first thin film transistor to the twelfth thin film transistor The terminals are all source electrodes, and the second channel terminals of the first thin film transistor to the twelfth thin film transistor are all drain electrodes.
  • the disclosure also provides a GOA scanning circuit, including a plurality of cascaded GOA circuit units, and each GOA circuit unit includes:
  • a bidirectional input module including a first thin-film transistor and a second thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the stage 4 signal of the lower four-level GOA circuit unit, and the control terminal of the second thin-film transistor is connected to the upper four The signal of the stage GOA circuit unit, wherein the first path terminal of the first thin film transistor is used to input a first constant voltage, the second path terminal of the first thin film transistor is connected to the first node, and the second thin film The first path terminal of the transistor is used to input a second constant voltage, and the second path terminal of the second thin film transistor is connected to the first node;
  • An output module connected to the first node and used for outputting the cascade signal of the current GOA circuit unit and outputting the scan signal of the current GOA circuit unit according to the potential of the first node;
  • the pull-down module is connected to the first node and used to output a first clock signal according to the potential of the first node.
  • the output module includes a third thin film transistor and a fourth thin film transistor, the control terminal of the third thin film transistor and the control terminal of the fourth thin film transistor are both connected to the first Node, the first path end of the third thin-film transistor is used to output a second clock signal, and the second path end of the third thin-film transistor is used to output the stage-transmitted signal of the GOA circuit unit of the current stage, so The first path terminal of the fourth thin film transistor is used to output the second clock signal, and the second path terminal of the fourth thin film transistor is used to output the scan signal of the GOA circuit unit of the current stage.
  • the pull-down module includes a fifth thin-film transistor and a sixth thin-film transistor. Both the control terminal of the fifth thin-film transistor and the control terminal of the sixth thin-film transistor are used to output the A first clock signal, a first path end of the fifth thin film transistor is connected to the first node, a second path end of the fifth thin film transistor is connected to a first stabilized voltage, and a first of the sixth thin film transistor The path end is used to output the scan signal of the GOA circuit unit at the current stage, and the second path end of the sixth thin film transistor is connected to a second stabilized voltage.
  • each GOA circuit unit further includes a seventh thin film transistor and an eighth thin film transistor, a first path end of the seventh thin film transistor is connected to the first node, and the seventh thin film The second path end of the transistor is connected to the first regulated voltage, the first path end of the eighth thin film transistor is used to output the scan signal of the GOA circuit unit of the current stage, and the first The second channel end is connected to the second regulated voltage.
  • each GOA circuit unit further includes a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor and a twelfth thin film transistor, the control terminal and the first A channel terminal outputs a low-frequency clock signal.
  • the second channel terminal of the ninth thin film transistor is connected to the first channel terminal of the tenth thin film transistor, and the control terminal of the tenth thin film transistor is connected to the first node.
  • the second path terminal of the tenth thin film transistor is connected to the second regulated voltage
  • the control terminal of the eleventh thin film transistor is connected to the second channel terminal of the ninth thin film transistor and the tenth thin film transistor
  • the first channel end of the first channel, the first channel end of the eleventh thin film transistor outputs the low frequency clock signal
  • the second channel end of the eleventh thin film transistor is connected to the control of the seventh thin film transistor End
  • the control end of the twelfth thin film transistor is connected to the control end of the tenth thin film transistor
  • the first channel end of the twelfth thin film transistor is connected to the second of the eleventh thin film transistor
  • a channel terminal and the control terminal of the seventh thin film transistor, and a second channel terminal of the twelfth thin film transistor is connected to the second regulated voltage.
  • the first clock signal and the second clock signal are inverted.
  • control terminals of the first thin film transistor to the twelfth thin film transistor are all gates.
  • the first channel terminals of the first thin film transistor to the twelfth thin film transistor are all sources.
  • the second channel terminals of the first thin film transistor to the twelfth thin film transistor are all drains.
  • the present disclosure also provides a liquid crystal display device including a GOA scanning circuit.
  • the GOA scanning circuit includes a plurality of cascaded GOA circuit units, and each GOA circuit unit includes:
  • a bidirectional input module including a first thin-film transistor and a second thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the stage 4 signal of the lower four-level GOA circuit unit, and the control terminal of the second thin-film transistor is connected to the upper four The signal of the stage GOA circuit unit, wherein the first path terminal of the first thin film transistor is used to input a first constant voltage, the second path terminal of the first thin film transistor is connected to the first node, and the second thin film The first path terminal of the transistor is used to input a second constant voltage, and the second path terminal of the second thin film transistor is connected to the first node;
  • An output module connected to the first node and used for outputting the cascade signal of the current GOA circuit unit and outputting the scan signal of the current GOA circuit unit according to the potential of the first node;
  • the pull-down module is connected to the first node and used to output a first clock signal according to the potential of the first node.
  • the output module includes a third thin film transistor and a fourth thin film transistor, the control terminal of the third thin film transistor and the control terminal of the fourth thin film transistor are both connected to the first Node, the first path end of the third thin-film transistor is used to output a second clock signal, and the second path end of the third thin-film transistor is used to output the stage-transmitted signal of the GOA circuit unit of the current stage, so The first path terminal of the fourth thin film transistor is used to output the second clock signal, and the second path terminal of the fourth thin film transistor is used to output the scan signal of the GOA circuit unit of the current stage.
  • the pull-down module includes a fifth thin-film transistor and a sixth thin-film transistor. Both the control terminal of the fifth thin-film transistor and the control terminal of the sixth thin-film transistor are used to output the A first clock signal, a first path end of the fifth thin film transistor is connected to the first node, a second path end of the fifth thin film transistor is connected to a first stabilized voltage, and a first of the sixth thin film transistor The path end is used to output the scan signal of the GOA circuit unit at the current stage, and the second path end of the sixth thin film transistor is connected to a second stabilized voltage.
  • each GOA circuit unit further includes a seventh thin film transistor and an eighth thin film transistor, a first path end of the seventh thin film transistor is connected to the first node, and the seventh thin film The second path end of the transistor is connected to the first regulated voltage, the first path end of the eighth thin film transistor is used to output the scan signal of the GOA circuit unit of the current stage, and the first The second channel end is connected to the second regulated voltage.
  • each GOA circuit unit further includes a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor and a twelfth thin film transistor, the control terminal and the first A channel terminal outputs a low-frequency clock signal.
  • the second channel terminal of the ninth thin film transistor is connected to the first channel terminal of the tenth thin film transistor, and the control terminal of the tenth thin film transistor is connected to the first node.
  • the second path terminal of the tenth thin film transistor is connected to the second regulated voltage
  • the control terminal of the eleventh thin film transistor is connected to the second channel terminal of the ninth thin film transistor and the tenth thin film transistor
  • the first channel end of the first channel, the first channel end of the eleventh thin film transistor outputs the low frequency clock signal
  • the second channel end of the eleventh thin film transistor is connected to the control of the seventh thin film transistor End
  • the control end of the twelfth thin film transistor is connected to the control end of the tenth thin film transistor
  • the first channel end of the twelfth thin film transistor is connected to the second of the eleventh thin film transistor
  • a channel terminal and the control terminal of the seventh thin film transistor, and a second channel terminal of the twelfth thin film transistor is connected to the second regulated voltage.
  • the first clock signal and the second clock signal are inverted.
  • the present disclosure provides a GOA (gate driver on array) scanning circuit and a liquid crystal display device.
  • the GOA scanning circuit includes a plurality of cascaded GOA circuit units.
  • Each GOA circuit unit includes the bidirectional input module, the output module, and the pull-down module.
  • the bidirectional input module includes the first thin film transistor and the second thin film transistor.
  • the pull-down module is connected to the first node and used to output the first clock signal according to the potential of the first node.
  • the embodiments of the present disclosure can achieve a bidirectional scanning function, and require fewer thin film transistors and signal lines, which is advantageous for a narrow bezel or no bezel design.
  • FIG. 1 shows a schematic structural diagram of a scanning circuit unit of a GOA scanning circuit according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a GOA scanning circuit according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic structural diagram of a GOA scanning circuit according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of a liquid crystal display device according to an embodiment of the present disclosure.
  • a GOA scanning circuit includes a plurality of cascaded GOA circuit units.
  • Each GOA circuit unit includes a bidirectional input module 10, an output module 12, and a pull-down module 14.
  • the bidirectional input module 10 includes a first thin film transistor T1 and a second thin film transistor T2.
  • the control terminal of the first thin film transistor T1 is connected to the stage transmission signal STn-4 of the next four stage GOA circuit unit.
  • the control terminal of the second thin film transistor T2 is connected to the cascade signal STn+4 of the four-stage GOA circuit unit.
  • the first path terminal of the first thin film transistor T1 is used to input the first constant voltage VGH1.
  • the second path terminal of the first thin film transistor T1 is connected to the first node Q.
  • the first path terminal of the second thin film transistor T2 is used to input a second constant voltage VGH2.
  • the second path end of the second thin film transistor T2 is connected to the first node Q.
  • the output module 12 is connected to the first node Q and is used to output the staged signal STn of the GOA circuit unit of the current stage and the scan signal Gn of the GOA circuit unit of the current stage according to the potential of the first node Q.
  • the pull-down module 14 is connected to the first node Q and used to output a first clock signal XCK according to the potential of the first node Q.
  • the pull-down module 14 Since the pull-down module 14 outputs the first clock signal XCK, that is, the pull-down module 14 pulls down using the first clock signal XCK, the pull-down signal (ie, the first clock signal XCK) has no directionality, and there is no need to add a signal line and provide an inversion Scanning thin film transistor.
  • the GOA circuit unit of this embodiment has a simple circuit and fewer newly added signal lines, and can be used in a GOA circuit with bidirectional transmission requirements to increase the compatibility of the GOA circuit.
  • the bidirectional input module 10 uses two bidirectional input members (ie, the first thin-film transistor T1 and the second thin-film transistor T2), and uses the first thin-film transistor T1 during the reverse scanning, and the stage-transmitted signal STn- of the upper four-stage GOA circuit unit 4 and the first constant voltage VGH1 input, the second thin film transistor T2 is also used during reverse scanning, the staged signal STn+4 of the lower four-stage GOA circuit unit and the second constant voltage VGH2 input, in order to prevent two bidirectional input components (That is, the first thin-film transistor T1 and the second thin-film transistor T2) interfere with each other.
  • the first thin-film transistor T1 and the second thin-film transistor T2 uses two bidirectional input members (ie, the first thin-film transistor T1 and the second thin-film transistor T2), and uses the first thin-film transistor T1 during the reverse scanning, and the stage-transmitted signal STn- of the upper four-stage GOA circuit unit 4 and the first constant voltage VGH1 input, the second thin film
  • the second thin-film transistor T2 may be triggered by the stage transmission signal STn+4 of the next four-stage GOA circuit unit, causing the output module 12 to output erroneously.
  • Add a constant voltage signal When the inverting input of the first constant voltage VGH1 is used, the second constant voltage VGH2 is given to the low signal to ensure that the second thin film transistor T2 is turned off without risk of triggering.
  • the GOA circuit unit of this embodiment has a simple circuit and fewer newly added signal lines, and can be used in a GOA circuit with bidirectional transmission requirements to increase the compatibility of the GOA circuit.
  • the current-level GOA circuit unit is, for example, the n-th level GOA circuit unit, n is a positive integer and n is greater than 1.
  • the order of the GOA circuit unit from the first stage to the nth stage provides scanning signals G1 ⁇ Gn to the corresponding pixel unit in turn, and in the reverse scanning, the order of the GOA circuit unit from the nth stage to the first stage Scan signals Gn ⁇ G1 are sequentially provided to the corresponding pixel units.
  • the output module 12 includes a third thin film transistor T3 and a fourth thin film transistor T4.
  • the control terminal of the third thin film transistor T3 and the control terminal of the fourth thin film transistor T4 are both connected to the first node Q, the first path terminal of the third thin film transistor T3 is used to output the second clock signal CK, and the third thin film transistor T3
  • the two-path end is used to output the staged signal STn of the GOA circuit unit at the current stage.
  • the first path terminal of the fourth thin film transistor T4 is used to output the second clock signal CK, and the second path terminal of the fourth thin film transistor T4 is used to output the scan signal Gn of the GOA circuit unit of the current stage.
  • the pull-down module 14 includes a fifth thin film transistor T5 and a sixth thin film transistor T6.
  • the control terminal of the fifth thin film transistor T5 and the control terminal of the sixth thin film transistor T6 are used to output the first clock signal XCK.
  • the first path terminal of the fifth thin film transistor T5 is connected to the first node Q, and the second path terminal of the fifth thin film transistor T5 is connected to the first stabilized voltage VSSQ.
  • the first path terminal of the sixth thin film transistor T6 is used to output the scan signal Gn of the GOA circuit unit of the current stage, and the second path terminal of the sixth thin film transistor T6 is connected to the second regulated voltage VSSG.
  • the control terminal of the fifth thin film transistor T5 and the control terminal of the sixth thin film transistor T6 of the pull-down module 14 are both used to output the first clock signal XCK, that is, the control terminal of the fifth thin film transistor T5 of the pull-down module 14 and the sixth thin film transistor
  • the control terminal of T6 uses the first clock signal XCK to pull down. Therefore, the pull-down signal (that is, the first clock signal XCK) has no directionality, and there is no need to add a signal line and a thin film transistor to provide reverse scanning.
  • the first path terminal of the third thin film transistor T3 and the first path terminal of the fourth thin film transistor T4 of the output module 12 are both used to output the second clock signal CK, because the second clock signal CK and the first clock signal XCK are Reverse signal, no interference problem of reverse scanning, which is beneficial to bidirectional scanning.
  • each GOA circuit unit further includes a seventh thin film transistor T7 and an eighth thin film transistor T8.
  • the first path terminal of the seventh thin film transistor T7 is connected to the first node Q, and the second path terminal of the seventh thin film transistor T7 is connected to the first stabilized voltage VSSQ.
  • the first path terminal of the eighth thin film transistor T8 is used to output the scan signal Gn of the GOA circuit unit of the current stage, and the second path terminal of the eighth thin film transistor T8 is connected to the second stabilized voltage VSSG.
  • each GOA circuit unit further includes a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, and a twelfth thin film transistor T12.
  • Both the control terminal and the first path terminal of the ninth thin film transistor T9 output a low-frequency clock signal LC, and the second path terminal of the ninth thin film transistor T9 is connected to the first path terminal of the tenth thin film transistor T10.
  • the control terminal of the tenth thin film transistor T10 is connected to the first node Q, and the second path terminal of the tenth thin film transistor T10 is connected to the second regulated voltage VSSG.
  • the control terminal of the eleventh thin film transistor T11 is connected to the second channel terminal of the ninth thin film transistor T9 and the first channel terminal of the tenth thin film transistor T10.
  • the first channel terminal of the eleventh thin film transistor T11 outputs a low frequency clock signal LC
  • the second channel terminal of the eleventh thin film transistor T11 is connected to the control terminal of the seventh thin film transistor T7.
  • the control terminal of the twelfth thin film transistor T12 is connected to the control terminal of the tenth thin film transistor T10, and the first channel terminal of the twelfth thin film transistor T12 is connected to the control of the second channel terminal of the eleventh thin film transistor T11 and the seventh thin film transistor T7 Terminal, the second channel terminal of the twelfth thin film transistor T12 is connected to the second regulated voltage VSSG.
  • first constant voltage VGH1 and the second constant voltage VGH2 are equal in magnitude, and the first constant voltage VGH1 and the second constant voltage VGH2 may be connected to the same signal line VGH.
  • first constant voltage VGH1 may be greater than the second constant voltage VGH2 to maintain the voltage difference Vgs between the drain and source of the first thin film transistor T1 during the non-output period greater than 0, thereby reducing leakage.
  • the first to twelfth thin film transistors T1 to T12 are all P-type thin film transistors. In other embodiments, the first to twelfth thin film transistors T1 to T12 are all N-type thin film transistors.
  • control terminals of the first to twelfth thin film transistors T1 to T12 are all gates.
  • the first channel terminals of the first to twelfth thin film transistors T1 to T12 are all sources.
  • the second channel terminals of the first to twelfth thin film transistors T1 to T12 are all drains.
  • the first clock signal XCK and the second clock signal CK are inverted.
  • the upload start signal that is, the second trigger signal STV2 and the second constant voltage VGH2 are used to continue transmission from top to bottom.
  • the first trigger signal STV1 and the first constant voltage are transmitted.
  • the low potential of VGH1 ensures that the inverted transmission signal will not interfere.
  • the reverse transmission is used from bottom to top, the first trigger signal STV1 and the first constant voltage VGH1 are used.
  • the second trigger signal STV2 and the second constant voltage VGH2 are given to the low level VSS to prevent interference.
  • the settings of the first constant voltage VGH1 and the second constant voltage VGH2 can control the outputs of the first thin film transistor T1 and the second thin film transistor T2, only one trigger signal can be used By using the first constant voltage VGH1 and the second constant voltage VGH2 to control the forward or reverse transmission of the high-low circuit, a signal line can be saved, and the circuit design is simpler.
  • the forward and reverse scanning signals of the analog GOA scanning circuit are output, and both forward and reverse scanning can output signals normally.
  • the liquid crystal display device 20 includes a liquid crystal panel 22 and a GOA scanning circuit 24 on the side of the liquid crystal panel 22.
  • the GOA scanning circuit 24 is the GOA scanning circuit described in any of the above embodiments.
  • the GOA scanning circuit includes a plurality of cascaded GOA circuit units.
  • Each GOA circuit unit includes the bidirectional input module, the output module, and the pull-down module.
  • the bidirectional input module includes the first thin film transistor and the second thin film transistor.
  • the pull-down module is connected to the first node and used to output the first clock signal according to the potential of the first node.

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Abstract

一种GOA扫描电路和液晶显示装置。GOA扫描电路包括级联的多个GOA电路单元。每个GOA电路单元包括双向输入模块（10）、输出模块（12）以及下拉模块（14）。双向输入模块（10）包括第一薄膜晶体管（T1）和第二薄膜晶体管（T2）。下拉模块（14）与第一节点（Q）连接且用于根据第一节点（Q）的电位输出第一时钟信号（XCK）。GOA扫描电路能实现双向扫描功能，且所需的薄膜晶体管和信号线较少。

Description

GOA扫描电路和液晶显示装置 技术领域
本揭示涉及显示技术领域，特别涉及一种GOA(gate driver on array)扫描电路和液晶显示装置。
 背景技术
液晶显示器(liquid crystal display，LCD)具有机身薄及省电等优点，得到了广泛的应用。例如应用于液晶电视、移动电话、个人数字助理(personal digital assistant, PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板与彩色滤光片基板之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管，薄膜晶体管的栅极连接至水平扫描线，漏极连接至垂直方向的数据线，源极则连接至像素电极。在水平扫描线上施加足够的电压，使得电性连接至该条水平扫描线上的所有薄膜晶体管打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板的水平扫描线的驱动主要由外接的集成电路板(integrated circuit, IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA(gate driver on array)技术即阵列基板行驱动技术，可以运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
现有的GOA扫描电路需要的薄膜晶体管较多，且使用的信号线较多，导致非有效显示区占用较多，不利于窄边框或者无边框设计。
故，有需要提供一种GOA扫描电路和液晶显示装置，以解决现有技术存在的问题。
 技术问题
现有的GOA扫描电路需要的薄膜晶体管较多，且使用的信号线较多，导致非有效显示区占用较多，不利于窄边框或者无边框设计。
 技术解决方案
为解决上述技术问题，本揭示提供一GOA扫描电路，包括级联的多个GOA电路单元，每个GOA电路单元包括:
双向输入模块，包括第一薄膜晶体管和第二薄膜晶体管，其中所述第一薄膜晶体管的控制端连接下四级GOA电路单元的级传信号，以及所述第二薄膜晶体管的控制端连接上四级GOA电路单元的级传信号，其中所述第一薄膜晶体管的第一通路端用于输入第一恒定电压，所述第一薄膜晶体管的第二通路端连接第一节点，所述第二薄膜晶体管的第一通路端用于输入第二恒定电压，以及所述第二薄膜晶体管的第二通路端连接所述第一节点;
输出模块，与所述第一节点连接且用于根据所述第一节点的电位输出本级GOA电路单元的级传信号和输出所述本级GOA电路单元的扫描信号;以及
下拉模块，与所述第一节点连接且用于根据所述第一节点的电位输出第一时钟信号;
其中所述输出模块包括第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管的控制端和所述第四薄膜晶体管的控制端均连接所述第一节点，所述第三薄膜晶体管的第一通路端用于输出第二时钟信号，所述第三薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述级传信号，所述第四薄膜晶体管的第一通路端用于输出所述第二时钟信号，所述第四薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述扫描信号;
其中所述第一时钟信号与所述第二时钟信号反相。
于本揭示其中的一实施例中，所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管，所述第五薄膜晶体管的控制端和所述第六薄膜晶体管的控制端均用于输出所述第一时钟信号，所述第五薄膜晶体管的第一通路端连接所述第一节点，所述第五薄膜晶体管的第二通路端连接第一稳压电压，所述第六薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第六薄膜晶体管的第二通路端连接第二稳压电压。
于本揭示其中的一实施例中，每个GOA电路单元还包括第七薄膜晶体管和第八薄膜晶体管，所述第七薄膜晶体管的第一通路端连接所述第一节点，所述第七薄膜晶体管的第二通路端连接所述第一稳压电压，所述第八薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第八薄膜晶体管的第二通路端连接所述第二稳压电压。
于本揭示其中的一实施例中，每个GOA电路单元还包括第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第十二薄膜晶体管，所述第九薄膜晶体管的控制端和第一通路端均输出低频时钟信号，所述第九薄膜晶体管的第二通路端连接所述第十薄膜晶体管的第一通路端，所述第十薄膜晶体管的控制端连接所述第一节点，所述第十薄膜晶体管的第二通路端连接所述第二稳压电压，所述第十一薄膜晶体管的控制端连接所述第九薄膜晶体管的所述第二通道端和所述第十薄膜晶体管的所述第一通道端，所述第十一薄膜晶体管的第一通路端输出所述低频时钟信号，所述第十一薄膜晶体管的第二通道端连接所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的控制端连接所述第十薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第一通道端连接所述第十一薄膜晶体管的所述第二通道端和所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第二通道端连接所述第二稳压电压。
于本揭示其中的一实施例中，所述第一薄膜晶体管至第十二薄膜晶体管的所述控制端均为栅极，所述第一薄膜晶体管至第十二薄膜晶体管的所述第一通道端均为源极，所述第一薄膜晶体管至第十二薄膜晶体管的所述第二通道端均为漏极。
本揭示还提供一GOA扫描电路，包括级联的多个GOA电路单元，每个GOA电路单元包括:
双向输入模块，包括第一薄膜晶体管和第二薄膜晶体管，其中所述第一薄膜晶体管的控制端连接下四级GOA电路单元的级传信号，以及所述第二薄膜晶体管的控制端连接上四级GOA电路单元的级传信号，其中所述第一薄膜晶体管的第一通路端用于输入第一恒定电压，所述第一薄膜晶体管的第二通路端连接第一节点，所述第二薄膜晶体管的第一通路端用于输入第二恒定电压，以及所述第二薄膜晶体管的第二通路端连接所述第一节点;
输出模块，与所述第一节点连接且用于根据所述第一节点的电位输出本级GOA电路单元的级传信号和输出所述本级GOA电路单元的扫描信号;以及
下拉模块，与所述第一节点连接且用于根据所述第一节点的电位输出第一时钟信号。
于本揭示其中的一实施例中，所述输出模块包括第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管的控制端和所述第四薄膜晶体管的控制端均连接所述第一节点，所述第三薄膜晶体管的第一通路端用于输出第二时钟信号，所述第三薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述级传信号，所述第四薄膜晶体管的第一通路端用于输出所述第二时钟信号，所述第四薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述扫描信号。
于本揭示其中的一实施例中，所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管，所述第五薄膜晶体管的控制端和所述第六薄膜晶体管的控制端均用于输出所述第一时钟信号，所述第五薄膜晶体管的第一通路端连接所述第一节点，所述第五薄膜晶体管的第二通路端连接第一稳压电压，所述第六薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第六薄膜晶体管的第二通路端连接第二稳压电压。
于本揭示其中的一实施例中，每个GOA电路单元还包括第七薄膜晶体管和第八薄膜晶体管，所述第七薄膜晶体管的第一通路端连接所述第一节点，所述第七薄膜晶体管的第二通路端连接所述第一稳压电压，所述第八薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第八薄膜晶体管的第二通路端连接所述第二稳压电压。
于本揭示其中的一实施例中，每个GOA电路单元还包括第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第十二薄膜晶体管，所述第九薄膜晶体管的控制端和第一通路端均输出低频时钟信号，所述第九薄膜晶体管的第二通路端连接所述第十薄膜晶体管的第一通路端，所述第十薄膜晶体管的控制端连接所述第一节点，所述第十薄膜晶体管的第二通路端连接所述第二稳压电压，所述第十一薄膜晶体管的控制端连接所述第九薄膜晶体管的所述第二通道端和所述第十薄膜晶体管的所述第一通道端，所述第十一薄膜晶体管的第一通路端输出所述低频时钟信号，所述第十一薄膜晶体管的第二通道端连接所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的控制端连接所述第十薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第一通道端连接所述第十一薄膜晶体管的所述第二通道端和所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第二通道端连接所述第二稳压电压。
于本揭示其中的一实施例中，所述第一时钟信号与所述第二时钟信号反相。
于本揭示其中的一实施例中，所述第一薄膜晶体管至第十二薄膜晶体管的所述控制端均为栅极。
于本揭示其中的一实施例中，所述第一薄膜晶体管至第十二薄膜晶体管的所述第一通道端均为源极。
于本揭示其中的一实施例中，所述第一薄膜晶体管至第十二薄膜晶体管的所述第二通道端均为漏极。
本揭示还提供一液晶显示装置，包括GOA扫描电路，所述GOA扫描电路，包括级联的多个GOA电路单元，每个GOA电路单元包括:
双向输入模块，包括第一薄膜晶体管和第二薄膜晶体管，其中所述第一薄膜晶体管的控制端连接下四级GOA电路单元的级传信号，以及所述第二薄膜晶体管的控制端连接上四级GOA电路单元的级传信号，其中所述第一薄膜晶体管的第一通路端用于输入第一恒定电压，所述第一薄膜晶体管的第二通路端连接第一节点，所述第二薄膜晶体管的第一通路端用于输入第二恒定电压，以及所述第二薄膜晶体管的第二通路端连接所述第一节点;
输出模块，与所述第一节点连接且用于根据所述第一节点的电位输出本级GOA电路单元的级传信号和输出所述本级GOA电路单元的扫描信号;以及
下拉模块，与所述第一节点连接且用于根据所述第一节点的电位输出第一时钟信号。
于本揭示其中的一实施例中，所述输出模块包括第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管的控制端和所述第四薄膜晶体管的控制端均连接所述第一节点，所述第三薄膜晶体管的第一通路端用于输出第二时钟信号，所述第三薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述级传信号，所述第四薄膜晶体管的第一通路端用于输出所述第二时钟信号，所述第四薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述扫描信号。
于本揭示其中的一实施例中，所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管，所述第五薄膜晶体管的控制端和所述第六薄膜晶体管的控制端均用于输出所述第一时钟信号，所述第五薄膜晶体管的第一通路端连接所述第一节点，所述第五薄膜晶体管的第二通路端连接第一稳压电压，所述第六薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第六薄膜晶体管的第二通路端连接第二稳压电压。
于本揭示其中的一实施例中，每个GOA电路单元还包括第七薄膜晶体管和第八薄膜晶体管，所述第七薄膜晶体管的第一通路端连接所述第一节点，所述第七薄膜晶体管的第二通路端连接所述第一稳压电压，所述第八薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第八薄膜晶体管的第二通路端连接所述第二稳压电压。
于本揭示其中的一实施例中，每个GOA电路单元还包括第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第十二薄膜晶体管，所述第九薄膜晶体管的控制端和第一通路端均输出低频时钟信号，所述第九薄膜晶体管的第二通路端连接所述第十薄膜晶体管的第一通路端，所述第十薄膜晶体管的控制端连接所述第一节点，所述第十薄膜晶体管的第二通路端连接所述第二稳压电压，所述第十一薄膜晶体管的控制端连接所述第九薄膜晶体管的所述第二通道端和所述第十薄膜晶体管的所述第一通道端，所述第十一薄膜晶体管的第一通路端输出所述低频时钟信号，所述第十一薄膜晶体管的第二通道端连接所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的控制端连接所述第十薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第一通道端连接所述第十一薄膜晶体管的所述第二通道端和所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第二通道端连接所述第二稳压电压。
于本揭示其中的一实施例中，所述第一时钟信号与所述第二时钟信号反相。
 有益效果
相较于现有技术，为解决上述技术问题，本揭示提供GOA(gate driver on array)扫描电路和液晶显示装置，所述GOA扫描电路包括级联的多个GOA电路单元。每个GOA电路单元包括所述双向输入模块、所述输出模块以及所述下拉模块。所述双向输入模块包括所述第一薄膜晶体管和所述第二薄膜晶体管。所述下拉模块与所述第一节点连接且用于根据所述第一节点的电位输出所述第一时钟信号。本揭示的实施例能实现双向扫描功能，且所需的薄膜晶体管和信号线较少，利于窄边框或无边框设计。
 附图说明
图1显示根据本揭示的一实施例的GOA扫描电路的一个扫描电路单元的结构示意图；
图2显示根据本揭示的一实施例的GOA扫描电路的结构示意图；
图3显示根据本揭示的一实施例的GOA扫描电路的结构示意图；以及
图4显示根据本揭示的一实施例的液晶显示装置的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1，本揭示的一实施例的GOA扫描电路包括级联的多个GOA电路单元。每个GOA电路单元包括双向输入模块10、输出模块12以及下拉模块14。双向输入模块10包括第一薄膜晶体管T1和第二薄膜晶体管T2。第一薄膜晶体管T1的控制端连接下四级GOA电路单元的级传信号STn-4。第二薄膜晶体管T2的控制端连接上四级GOA电路单元的级传信号STn+4。第一薄膜晶体管T1的第一通路端用于输入第一恒定电压VGH1。第一薄膜晶体管T1的第二通路端连接第一节点Q。第二薄膜晶体管T2的第一通路端用于输入第二恒定电压VGH2。第二薄膜晶体管T2的第二通路端连接第一节点Q。输出模块12与第一节点Q连接且用于根据第一节点Q的电位输出本级GOA电路单元的级传信号STn和输出本级GOA电路单元的扫描信号Gn。下拉模块14与第一节点Q连接且用于根据第一节点Q的电位输出第一时钟信号XCK。
由于下拉模块14输出第一时钟信号XCK，即下拉模块14使用第一时钟信号XCK下拉，因此下拉讯号(即第一时钟信号XCK)无方向性，不需要新增信号线和新增提供反相扫描的薄膜晶体管。本实施例的GOA电路单元的电路简单，新增讯号线少，可用于具有双向传输需求的GOA 电路中，增加GOA 电路的兼容性。
另外，双向输入模块10使用两个双向输入构件(即第一薄膜晶体管T1和第二薄膜晶体管T2)，反相扫描时使用第一薄膜晶体管T1, 上四级GOA电路单元的级传信号STn-4和第一恒定电压VGH1输入，反相扫描时还使用第二薄膜晶体管T2, 下四级GOA电路单元的级传信号STn+4和第二恒定电压VGH2输入，为防止两个双向输入构件(即第一薄膜晶体管T1和第二薄膜晶体管T2)相互干扰，例如反相扫描时，第二薄膜晶体管T2可能在下四级GOA电路单元的级传信号STn+4时触发，导致输出模块12误输出，增加一个恒定电压讯号。当使用第一恒定电压VGH1反相输入时，将第二恒定电压VGH2 给低讯号，保证第二薄膜晶体管T2关闭，无触发风险。
本实施例的GOA电路单元的电路简单，新增讯号线少，可用于具有双向传输需求的GOA 电路中，增加GOA 电路的兼容性。
具体地，本级GOA电路单元例如为第n级GOA电路单元，n为正整数且n大于1。在正向扫描时，从第1级到第n级GOA电路单元的顺序依次向对应的像素单元提供扫描信号G1〜Gn，反相扫描时，从第n级到第1级GOA电路单元的顺序依次向对应的像素单元提供扫描信号Gn〜G1。
具体地，输出模块12包括第三薄膜晶体管T3和第四薄膜晶体管T4。第三薄膜晶体管T3的控制端和第四薄膜晶体管T4的控制端均连接第一节点Q，第三薄膜晶体管T3的第一通路端用于输出第二时钟信号CK，第三薄膜晶体管T3的第二通路端用于输出本级GOA电路单元的级传信号STn。第四薄膜晶体管T4的第一通路端用于输出第二时钟信号CK，第四薄膜晶体管T4的第二通路端用于输出本级GOA电路单元的扫描信号Gn。
具体地，下拉模块14包括第五薄膜晶体管T5和第六薄膜晶体管T6。第五薄膜晶体管T5的控制端和第六薄膜晶体管T6的控制端均用于输出第一时钟信号XCK。第五薄膜晶体管T5的第一通路端连接第一节点Q，第五薄膜晶体管T5的第二通路端连接第一稳压电压VSSQ。第六薄膜晶体管T6的第一通路端用于输出本级GOA电路单元的扫描信号Gn，第六薄膜晶体管T6的第二通路端连接第二稳压电压VSSG。
由于下拉模块14的第五薄膜晶体管T5的控制端和第六薄膜晶体管T6的控制端均用于输出第一时钟信号XCK，即下拉模块14的第五薄膜晶体管T5的控制端和第六薄膜晶体管T6的控制端均使用第一时钟信号XCK下拉，因此下拉讯号(即第一时钟信号XCK)无方向性，不需要新增信号线和新增提供反相扫描的薄膜晶体管。另外，输出模块12的第三薄膜晶体管T3的第一通路端及第四薄膜晶体管T4的第一通路端均用于输出第二时钟信号CK，因第二时钟信号CK和第一时钟信号XCK是反相讯号，无反相扫描干扰问题，利于双向扫描。
具体地，每个GOA电路单元还包括第七薄膜晶体管T7和第八薄膜晶体管T8。第七薄膜晶体管T7的第一通路端连接第一节点Q，第七薄膜晶体管T7的第二通路端连接第一稳压电压VSSQ。第八薄膜晶体管T8的第一通路端用于输出本级GOA电路单元的扫描信号Gn，第八薄膜晶体管T8的第二通路端连接第二稳压电压VSSG。
具体地，每个GOA电路单元还包括第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11和第十二薄膜晶体管T12。第九薄膜晶体管T9的控制端和第一通路端均输出低频时钟信号LC，第九薄膜晶体管T9的第二通路端连接第十薄膜晶体管T10的第一通路端。第十薄膜晶体管T10的控制端连接第一节点Q，第十薄膜晶体管T10的第二通路端连接第二稳压电压VSSG。第十一薄膜晶体管T11的控制端连接第九薄膜晶体管T9的第二通道端和第十薄膜晶体管T10的第一通道端，第十一薄膜晶体管T11的第一通路端输出低频时钟信号LC，第十一薄膜晶体管T11的第二通道端连接第七薄膜晶体管T7的控制端。第十二薄膜晶体管T12的控制端连接第十薄膜晶体管T10的控制端，第十二薄膜晶体管T12的第一通道端连接第十一薄膜晶体管T11的第二通道端和第七薄膜晶体管T7的控制端，第十二薄膜晶体管T12的第二通道端连接第二稳压电压VSSG。
具体地，第一恒定电压VGHl和第二恒定电压VGH2的大小相等，第一恒定电压VGHl和第二恒定电压VGH2可以是连接同一信号线VGH。在其他实施例中，第一恒定电压VGHl可以大于第二恒定电压VGH2，以保持在非输出期间第一薄膜晶体管Tl的漏极与源极之间的压差Vgs大于0，从而减小漏电。
具体地，第一至第十二薄膜晶体管Tl〜T12均为P型薄膜晶体管。在其他实施例中，第一至第十二薄膜晶体管Tl〜T12均为Ｎ型薄膜晶体管。
具体地，第一至第十二薄膜晶体管Tl〜T12的控制端均为栅极。第一至第十二薄膜晶体管Tl〜T12的第一通道端均为源极。第一至第十二薄膜晶体管Tl〜T12的第二通道端均为漏极。
具体地，第一时钟信号XCK与第二时钟信号CK反相。
参照图1及2，在一实施例中，使用上传起始讯号，即第二触发信号STV2和第二恒定电压VGH2，从上往下续传，此时第一触发信号STV1和第一恒定电压VGH1低电位保证反相传输讯号不会干扰。当使用反相从下往上续传时，使用第一触发信号STV1和第一恒定电压VGH1，此时第二触发信号STV2和第二恒定电压VGH2给低准位VSS，防止干扰。
参照图1及3，在一实施例中，因为第一恒定电压VGH1和第二恒定电压VGH2的设定可控制第一薄膜晶体管Tl和第二薄膜晶体管T2的输出，所以可以只用一个触发信号，以第一恒定电压VGH1和第二恒定电压VGH2高低控制电路正向传输还是反相传输，可以节省一根讯号线，电路设计也更加简单。
在一实施例中，模拟GOA扫描电路模的正反向扫描信号输出，其正反向扫描均能正常输出讯号。
参照图4，在一实施例中，液晶显示装置20包括液晶面板22和位于液晶面板22一侧的GOA扫描电路24。GOA扫描电路24为上述任一实施例所述的GOA扫描电路。
由于本揭示的实施例的所述GOA扫描电路和所述液晶显示装置中，所述GOA扫描电路包括级联的多个GOA电路单元。每个GOA电路单元包括所述双向输入模块、所述输出模块以及所述下拉模块。所述双向输入模块包括所述第一薄膜晶体管和所述第二薄膜晶体管。所述下拉模块与所述第一节点连接且用于根据所述第一节点的电位输出所述第一时钟信号。本揭示的实施例能实现双向扫描功能，且所需的薄膜晶体管和信号线较少，利于窄边框或无边框设计。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (20)

  1. 一种GOA扫描电路，包括级联的多个GOA电路单元，每个GOA电路单元包括:
    双向输入模块，包括第一薄膜晶体管和第二薄膜晶体管，其中所述第一薄膜晶体管的控制端连接下四级GOA电路单元的级传信号，以及所述第二薄膜晶体管的控制端连接上四级GOA电路单元的级传信号，其中所述第一薄膜晶体管的第一通路端用于输入第一恒定电压，所述第一薄膜晶体管的第二通路端连接第一节点，所述第二薄膜晶体管的第一通路端用于输入第二恒定电压，以及所述第二薄膜晶体管的第二通路端连接所述第一节点;
    输出模块，与所述第一节点连接且用于根据所述第一节点的电位输出本级GOA电路单元的级传信号和输出所述本级GOA电路单元的扫描信号;以及
    下拉模块，与所述第一节点连接且用于根据所述第一节点的电位输出第一时钟信号;
    其中所述输出模块包括第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管的控制端和所述第四薄膜晶体管的控制端均连接所述第一节点，所述第三薄膜晶体管的第一通路端用于输出第二时钟信号，所述第三薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述级传信号，所述第四薄膜晶体管的第一通路端用于输出所述第二时钟信号，所述第四薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述扫描信号;
    其中所述第一时钟信号与所述第二时钟信号反相。
  2. 如权利要求1所述的GOA扫描电路，其中所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管，所述第五薄膜晶体管的控制端和所述第六薄膜晶体管的控制端均用于输出所述第一时钟信号，所述第五薄膜晶体管的第一通路端连接所述第一节点，所述第五薄膜晶体管的第二通路端连接第一稳压电压，所述第六薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第六薄膜晶体管的第二通路端连接第二稳压电压。
  3. 如权利要求2所述的GOA扫描电路，其中每个GOA电路单元还包括第七薄膜晶体管和第八薄膜晶体管，所述第七薄膜晶体管的第一通路端连接所述第一节点，所述第七薄膜晶体管的第二通路端连接所述第一稳压电压，所述第八薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第八薄膜晶体管的第二通路端连接所述第二稳压电压。
  4. 如权利要求3所述的GOA扫描电路，其中每个GOA电路单元还包括第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第十二薄膜晶体管，所述第九薄膜晶体管的控制端和第一通路端均输出低频时钟信号，所述第九薄膜晶体管的第二通路端连接所述第十薄膜晶体管的第一通路端，所述第十薄膜晶体管的控制端连接所述第一节点，所述第十薄膜晶体管的第二通路端连接所述第二稳压电压，所述第十一薄膜晶体管的控制端连接所述第九薄膜晶体管的所述第二通道端和所述第十薄膜晶体管的所述第一通道端，所述第十一薄膜晶体管的第一通路端输出所述低频时钟信号，所述第十一薄膜晶体管的第二通道端连接所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的控制端连接所述第十薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第一通道端连接所述第十一薄膜晶体管的所述第二通道端和所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第二通道端连接所述第二稳压电压。
  5. 根据权利要求4所述的GOA扫描电路，其中所述第一薄膜晶体管至第十二薄膜晶体管的所述控制端均为栅极，所述第一薄膜晶体管至第十二薄膜晶体管的所述第一通道端均为源极，所述第一薄膜晶体管至第十二薄膜晶体管的所述第二通道端均为漏极。
  6. 一种GOA扫描电路，包括级联的多个GOA电路单元，每个GOA电路单元包括:
    双向输入模块，包括第一薄膜晶体管和第二薄膜晶体管，其中所述第一薄膜晶体管的控制端连接下四级GOA电路单元的级传信号，以及所述第二薄膜晶体管的控制端连接上四级GOA电路单元的级传信号，其中所述第一薄膜晶体管的第一通路端用于输入第一恒定电压，所述第一薄膜晶体管的第二通路端连接第一节点，所述第二薄膜晶体管的第一通路端用于输入第二恒定电压，以及所述第二薄膜晶体管的第二通路端连接所述第一节点;
    输出模块，与所述第一节点连接且用于根据所述第一节点的电位输出本级GOA电路单元的级传信号和输出所述本级GOA电路单元的扫描信号;以及
    下拉模块，与所述第一节点连接且用于根据所述第一节点的电位输出第一时钟信号。
  7. 如权利要求6所述的GOA扫描电路，其中所述输出模块包括第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管的控制端和所述第四薄膜晶体管的控制端均连接所述第一节点，所述第三薄膜晶体管的第一通路端用于输出第二时钟信号，所述第三薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述级传信号，所述第四薄膜晶体管的第一通路端用于输出所述第二时钟信号，所述第四薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述扫描信号。
  8. 如权利要求7所述的GOA扫描电路，其中所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管，所述第五薄膜晶体管的控制端和所述第六薄膜晶体管的控制端均用于输出所述第一时钟信号，所述第五薄膜晶体管的第一通路端连接所述第一节点，所述第五薄膜晶体管的第二通路端连接第一稳压电压，所述第六薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第六薄膜晶体管的第二通路端连接第二稳压电压。
  9. 如权利要求8所述的GOA扫描电路，其中每个GOA电路单元还包括第七薄膜晶体管和第八薄膜晶体管，所述第七薄膜晶体管的第一通路端连接所述第一节点，所述第七薄膜晶体管的第二通路端连接所述第一稳压电压，所述第八薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第八薄膜晶体管的第二通路端连接所述第二稳压电压。
  10.     如权利要求9所述的GOA扫描电路，其中每个GOA电路单元还包括第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第十二薄膜晶体管，所述第九薄膜晶体管的控制端和第一通路端均输出低频时钟信号，所述第九薄膜晶体管的第二通路端连接所述第十薄膜晶体管的第一通路端，所述第十薄膜晶体管的控制端连接所述第一节点，所述第十薄膜晶体管的第二通路端连接所述第二稳压电压，所述第十一薄膜晶体管的控制端连接所述第九薄膜晶体管的所述第二通道端和所述第十薄膜晶体管的所述第一通道端，所述第十一薄膜晶体管的第一通路端输出所述低频时钟信号，所述第十一薄膜晶体管的第二通道端连接所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的控制端连接所述第十薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第一通道端连接所述第十一薄膜晶体管的所述第二通道端和所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第二通道端连接所述第二稳压电压。
  11.      如权利要求7所述的GOA扫描电路，其中所述第一时钟信号与所述第二时钟信号反相。
  12. 根据权利要求9所述的GOA扫描电路，其中所述第一薄膜晶体管至第十二薄膜晶体管的所述控制端均为栅极。
  13. 根据权利要求12所述的GOA扫描电路，其中所述第一薄膜晶体管至第十二薄膜晶体管的所述第一通道端均为源极。
  14. 根据权利要求13所述的GOA扫描电路，其中所述第一薄膜晶体管至第十二薄膜晶体管的所述第二通道端均为漏极。
  15. 一种液晶显示装置，包括GOA扫描电路，所述GOA扫描电路，包括级联的多个GOA电路单元，每个GOA电路单元包括:
    双向输入模块，包括第一薄膜晶体管和第二薄膜晶体管，其中所述第一薄膜晶体管的控制端连接下四级GOA电路单元的级传信号，以及所述第二薄膜晶体管的控制端连接上四级GOA电路单元的级传信号，其中所述第一薄膜晶体管的第一通路端用于输入第一恒定电压，所述第一薄膜晶体管的第二通路端连接第一节点，所述第二薄膜晶体管的第一通路端用于输入第二恒定电压，以及所述第二薄膜晶体管的第二通路端连接所述第一节点;
    输出模块，与所述第一节点连接且用于根据所述第一节点的电位输出本级GOA电路单元的级传信号和输出所述本级GOA电路单元的扫描信号;以及
    下拉模块，与所述第一节点连接且用于根据所述第一节点的电位输出第一时钟信号。
  16.     如权利要求15所述的GOA扫描电路，其中所述输出模块包括第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管的控制端和所述第四薄膜晶体管的控制端均连接所述第一节点，所述第三薄膜晶体管的第一通路端用于输出第二时钟信号，所述第三薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述级传信号，所述第四薄膜晶体管的第一通路端用于输出所述第二时钟信号，所述第四薄膜晶体管的第二通路端用于输出所述本级GOA电路单元的所述扫描信号。
  17.     如权利要求16所述的GOA扫描电路，其中所述下拉模块包括第五薄膜晶体管和第六薄膜晶体管，所述第五薄膜晶体管的控制端和所述第六薄膜晶体管的控制端均用于输出所述第一时钟信号，所述第五薄膜晶体管的第一通路端连接所述第一节点，所述第五薄膜晶体管的第二通路端连接第一稳压电压，所述第六薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第六薄膜晶体管的第二通路端连接第二稳压电压。
  18.     如权利要求17所述的GOA扫描电路，其中每个GOA电路单元还包括第七薄膜晶体管和第八薄膜晶体管，所述第七薄膜晶体管的第一通路端连接所述第一节点，所述第七薄膜晶体管的第二通路端连接所述第一稳压电压，所述第八薄膜晶体管的第一通路端用于输出所述本级GOA电路单元的所述扫描信号，所述第八薄膜晶体管的第二通路端连接所述第二稳压电压。
  19.     如权利要求18所述的GOA扫描电路，其中每个GOA电路单元还包括第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第十二薄膜晶体管，所述第九薄膜晶体管的控制端和第一通路端均输出低频时钟信号，所述第九薄膜晶体管的第二通路端连接所述第十薄膜晶体管的第一通路端，所述第十薄膜晶体管的控制端连接所述第一节点，所述第十薄膜晶体管的第二通路端连接所述第二稳压电压，所述第十一薄膜晶体管的控制端连接所述第九薄膜晶体管的所述第二通道端和所述第十薄膜晶体管的所述第一通道端，所述第十一薄膜晶体管的第一通路端输出所述低频时钟信号，所述第十一薄膜晶体管的第二通道端连接所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的控制端连接所述第十薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第一通道端连接所述第十一薄膜晶体管的所述第二通道端和所述第七薄膜晶体管的所述控制端，所述第十二薄膜晶体管的第二通道端连接所述第二稳压电压。
  20.     如权利要求16所述的GOA扫描电路，其中所述第一时钟信号与所述第二时钟信号反相。
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