WO2020155453A1 - 显示驱动电路及显示装置 - Google Patents

显示驱动电路及显示装置 Download PDF

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Publication number
WO2020155453A1
WO2020155453A1 PCT/CN2019/085769 CN2019085769W WO2020155453A1 WO 2020155453 A1 WO2020155453 A1 WO 2020155453A1 CN 2019085769 W CN2019085769 W CN 2019085769W WO 2020155453 A1 WO2020155453 A1 WO 2020155453A1
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WO
WIPO (PCT)
Prior art keywords
frequency clock
clock signal
stage
drive unit
gate driving
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Application number
PCT/CN2019/085769
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English (en)
French (fr)
Inventor
田新斌
徐向阳
Original Assignee
深圳市华星光电技术有限公司
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Publication of WO2020155453A1 publication Critical patent/WO2020155453A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technology, in particular to a display drive circuit and a display device.
  • LCD Liquid Crystal Display
  • PDA personal digital assistant
  • LCD TV mobile phone
  • PDA personal digital assistant
  • digital camera computer screen or notebook computer screen, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is based on the thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and the color filter substrate (Color Filter (CF) is filled with liquid crystal molecules, and a driving voltage is applied on the two substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light from the backlight module to produce a picture.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • AMLCD Active Matrix Liquid Crystal Display
  • the active matrix liquid crystal display includes a plurality of pixels, and each pixel has a thin film transistor (Thin Film Transistor, TFT), the gate of the TFT is connected to the scan line extending in the horizontal direction, the drain is connected to the data line extending in the vertical direction, and the source of the TFT is connected to the corresponding pixel electrode.
  • TFT Thin Film Transistor
  • the horizontal scanning line drive (ie gate drive) of active liquid crystal display panels is mainly driven by an external integrated circuit (Integrated Circuit, IC) to complete, the external IC can control the step-by-step charging and discharging of the horizontal scan lines at all levels.
  • the GOA technology Gate Driver on Array
  • the GOA technology is the array substrate row drive technology, which can use the original manufacturing process of the liquid crystal display panel to fabricate the horizontal scanning line drive circuit on the substrate around the display area, so that it can replace the external IC to complete the horizontal scanning line drive.
  • GOA technology can reduce the bonding process of external ICs, which has the opportunity to increase production capacity and reduce product costs, and it can make LCD panels more suitable for manufacturing display products with narrow bezels or no bezels.
  • Existing gate driving circuits usually include cascaded multi-stage gate driving units.
  • the scanning method is that the first-level gate driving unit scans one row of scan lines. During each frame of scanning time, all gate driving units need to participate. Scanning, the power consumption of the gate drive circuit in this scanning mode is relatively large, the working time of each stage of the gate drive unit is long, the loss is large, and it cannot meet the green and energy-saving product standards.
  • the purpose of the present invention is to provide a display drive circuit that can reduce product power consumption, extend product life, and improve the green energy-saving level of the product.
  • the invention also provides a display device, which can reduce the power consumption of the product, extend the life of the product, and improve the green energy-saving level of the product.
  • the present invention provides a display driving circuit, which includes a gate driving circuit and a plurality of parallel and spaced scan lines electrically connected to the gate driving circuit.
  • the gate driving circuit includes multiple stages. Gate driving units, wherein the odd-numbered gate driving units are cascaded, and the even-numbered gate driving units are cascaded;
  • Each adjacent two-stage gate drive unit is a gate drive unit group, and each gate drive unit group corresponds to two rows of adjacent scan lines.
  • the two-stage gate drive units in the same gate drive unit group are Two rows of scan lines corresponding to the gate driving unit group are electrically connected;
  • the odd-numbered gate driving unit and the even-numbered gate driving unit alternately work according to the preset switching cycle; when the odd-numbered gate driving unit is working, the odd-numbered gate driving unit receives the first set of high frequency
  • the first set of high-frequency clock signals are used to generate scan signals to scan the scan lines of each row; when the even-numbered gate drive unit is working, the even-numbered gate drive unit receives the second set of high-frequency clock signals, and
  • the second group of high-frequency clock signals are used to generate scan signals, and scan lines of each row are scanned.
  • the first group of high-frequency clock signals includes a first high-frequency clock signal, a third high-frequency clock signal, and a fifth high-frequency clock signal;
  • the second group of high-frequency clock signals includes a second high-frequency clock signal, a fourth high-frequency clock signal, and a sixth high-frequency clock signal;
  • the generation times of the rising edges of the first high-frequency clock signal, the third high-frequency clock signal, and the fifth high-frequency clock signal are sequentially separated by a preset delay time; the second high-frequency clock signal, the fourth high-frequency clock signal The corresponding waveforms of the signal and the sixth high-frequency clock signal are the same as those of the first, third, and fifth high-frequency clock signals, respectively;
  • n be a positive integer
  • the first-stage gate drive unit and the 6nth-stage gate drive unit respectively receive a first high-frequency clock signal, a second high-frequency clock signal, a third high-frequency clock signal, a fourth high-frequency clock signal, a fifth high-frequency clock signal, and The sixth high-frequency clock signal.
  • the first group of high-frequency clock signals includes a first high-frequency clock signal, a third high-frequency clock signal, a fifth high-frequency clock signal, and a seventh high-frequency clock signal;
  • the second group of high-frequency clock signals includes a second high-frequency clock signal, a fourth high-frequency clock signal, a sixth high-frequency clock signal, and an eighth clock signal;
  • the generation times of the rising edges of the first high-frequency clock signal, the third high-frequency clock signal, the fifth high-frequency clock signal, and the seventh high-frequency clock signal are sequentially separated by a preset delay time; the second high-frequency clock
  • the waveforms of the signal, the fourth high-frequency clock signal, the sixth high-frequency clock signal, and the eighth high-frequency clock signal correspond to the first, third, fifth, and seventh high-frequency clock signals, respectively.
  • the waveform of the high frequency clock signal is the same;
  • n be a positive integer
  • the 8n-7th stage gate drive unit, the 8n-6th stage gate drive unit, the 8n-5th stage gate drive unit, the 8n-4th stage gate drive unit, the 8n-3th stage Stage gate drive unit, 8n-2 stage gate drive unit, 8n-1 stage gate drive unit and 8n stage gate drive unit respectively receive the first high-frequency clock signal, the second high-frequency clock signal, and the 3.
  • the first-stage gate driving unit When the odd-numbered-stage gate driving unit is working, the first-stage gate driving unit also receives a first start signal for driving the odd-numbered gate driving unit to start scanning;
  • the gate driving unit of the second stage When the gate driving unit of the even stage is working, the gate driving unit of the second stage also receives a second start signal for driving the gate driving unit of the even stage to start scanning.
  • Each stage of the gate drive unit also receives the first low-frequency clock signal and the second low-frequency clock signal, which are used to maintain the off state of the stage of the gate drive unit during the non-output period of the stage of the gate drive unit.
  • the operation of the odd-numbered gate driving unit and the even-numbered gate driving unit is switched every 80 to 120 frame scan time.
  • the operations of the odd-numbered gate driving units and the even-numbered gate driving units are switched every 100 frames of scanning time.
  • the display driving circuit further includes a plurality of pixel units arranged in an array, and each row of scan lines is electrically connected to a row of pixel units.
  • the gate drive circuit is a GOA circuit.
  • the present invention also provides a display device including the above-mentioned display drive circuit.
  • the present invention provides a display drive circuit, including a gate drive circuit and a plurality of parallel and spaced scan lines electrically connected to the gate drive circuit, and the gate drive circuit includes multiple Stage gate drive unit, in which each odd stage gate drive unit is cascaded, and even stage gate drive unit is cascaded; by setting each stage of GOA unit to scan two rows of scan lines, odd stage GOA unit and even stage The GOA unit alternately scans, which can halve the working time of each level of GOA unit, thereby reducing product power consumption, extending product life, and improving the product’s green energy-saving level.
  • the invention also provides a display device, which can reduce the power consumption of the product, extend the life of the product, and improve the green energy-saving level of the product.
  • FIG. 1 is a schematic diagram of the first embodiment of the display driving circuit of the present invention
  • FIG. 2 is a waveform diagram of the first embodiment of the display driving circuit of the present invention.
  • FIG. 3 is a circuit diagram of the gate driving unit of the display driving circuit of the present invention.
  • FIG. 4 is a schematic diagram of the second embodiment of the display driving circuit of the present invention.
  • the present invention provides a display driving circuit including a gate driving circuit 1 and a plurality of rows of scan lines 2 arranged in parallel and spaced apart electrically connected to the gate driving circuit 1.
  • the gate driving circuit 2 It includes a multi-stage gate driving unit 21, wherein each odd-numbered gate driving unit 21 is cascaded, and the even-numbered gate driving unit 21 is cascaded;
  • Each adjacent two-stage gate driving unit 21 is a gate driving unit group 210, and each gate driving unit group 210 corresponds to two rows of adjacent scan lines 2, and two stages in the same gate driving unit group 210
  • the gate driving units 21 are electrically connected to the two rows of scan lines 2 corresponding to the gate driving unit group 210.
  • the odd-numbered gate driving unit 21 and the even-numbered gate driving unit 21 alternately work according to a preset switching period; the odd-numbered gate driving unit 21 works When the gate driving unit 21 of the odd-numbered stage receives the first group of high-frequency clock signals, and uses the first group of high-frequency clock signals to generate the scanning signal, scan the scan lines 2 of each row; The gate driving unit 21 of the even-numbered stage receives the second group of high-frequency clock signals, and uses the second group of high-frequency clock signals to generate scan signals, and scans the scan lines 2 of each row.
  • the gate driving unit 21 of the first-stage also receives the first start signal STV1 for driving the odd-numbered gate driving unit 21 to start scanning;
  • the gate driving unit 21 of the second-stage When the gate driving unit 21 of the even-numbered stage is working, the gate driving unit 21 of the second-stage also receives a second start signal STV2 for driving the even-numbered gate driving unit 21 to start scanning.
  • each stage of the gate driving unit 21 also receives the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2, which are used to maintain the level of the gate driving unit 21 during the non-output period of the gate driving unit 21 of the stage. Disabled.
  • the operations of the gate driving unit 21 of the odd-numbered stages and the gate driving unit 21 of the even-numbered stages are switched every 80 to 120 frame scan time. More preferably, the operations of the gate driving unit 21 of the odd-numbered stages and the gate driving unit 21 of the even-numbered stages are switched every 100 frames of scanning time.
  • the display driving circuit further includes a plurality of pixel units 3 arranged in an array, and each row of scan lines 2 is correspondingly electrically connected to a row of pixel units 3.
  • the gate driving circuit 1 is a GOA circuit.
  • the first group of high-frequency clock signals includes a first high-frequency clock signal CK1, a third high-frequency clock signal CK3, and a fifth high-frequency clock signal.
  • the second group of high-frequency clock signals includes a second high-frequency clock signal CK2, a fourth high-frequency clock signal CK4, and a sixth high-frequency clock signal CK6;
  • the rising edge generation time of the high-frequency clock signal CK3 and the fifth high-frequency clock signal CK5 is sequentially separated by a preset delay time;
  • the waveform of the signal CK6 corresponds to the waveforms of the first high-frequency clock signal CK1, the third high-frequency clock signal CK3, and the fifth high-frequency clock signal CK5, respectively;
  • n be a positive integer
  • the first stage gate drive unit and the 6nth stage gate drive unit respectively receive the first high-frequency clock signal CK1, the second high-frequency clock signal CK2, the third high-frequency clock signal CK3, the fourth high-frequency clock signal CK4, and the fifth high-frequency clock signal.
  • the high-frequency clock signal CK5 and the sixth high-frequency clock signal CK6 respectively receive the first high-frequency clock signal CK1, the second high-frequency clock signal CK2, the third high-frequency clock signal CK3, the fourth high-frequency clock signal CK4, and the fifth high-frequency clock signal.
  • the high-frequency clock signal CK5 and the sixth high-frequency clock signal CK6 are examples of the sixth high-frequency clock signal CK6.
  • the working process of the above-mentioned first embodiment is as follows: firstly, the first start signal STV1 provides high-level pulses, and the second start signal STV2 does not provide high-level pulses of odd-numbered GOA
  • the unit 21 starts to work, the even-numbered GOA unit 21 does not work, and when the odd-numbered GOA unit 21 works, the first-stage GOA unit 21 first receives the first high-frequency clock signal CK1, generates the first scan signal, and converts the first A scan signal is output to the first scan line L1 and the second scan line L2 to scan the first scan line L1 and the second scan line L2, and the third-stage GOA unit 21 then receives the third high-frequency clock signal CK3, generate the second scan signal, and output the second scan signal to the third scan line L3 and the fourth scan line L4 to scan the third scan line L3 and the fourth scan line L4,
  • the five-level GOA unit 21 then receives the fifth high-frequency clock signal CK5, generates a third
  • the odd-numbered GOA unit 21 After the odd-numbered GOA unit 21 completes 100 frames of scanning, it starts from the 101st frame, and the second starts The signal STV2 provides a high-level pulse, the first start signal STV1 does not provide a high-level pulse, the even-numbered GOA unit 21 starts to work, the odd-numbered GOA unit 21 does not work, and the even-numbered GOA unit 21 works, the second stage
  • the GOA unit 21 first receives the second high frequency clock signal CK2, generates the first scan signal, and outputs the first scan signal to the first scan line L1 and the second scan line L2 for the first scan line L1 Scanning with the second scan line L2, the fourth-stage GOA unit 21 then receives the fourth high-frequency clock signal CK4, generates a second scan signal, and outputs the second scan signal to the third scan line L3 and The third scan line L3 and the fourth scan line L4 are scanned among the four scan lines L4.
  • the sixth-stage GOA unit 21 then receives the sixth high-frequency clock signal CK6, generates the third scan signal, and combines the third A scan signal is output to the fifth scan line L5 and the sixth scan line L6 to scan the fifth scan line L5 and the sixth scan line L6, and so on until the last odd-numbered GOA unit 21 is completed.
  • Frame scanning after the even-numbered GOA unit 21 completes the 100-frame scanning, starting from the 301st frame, the odd-numbered GOA unit 21 starts to work again, the even-numbered GOA unit 21 stops working, and then continues to work alternately.
  • the present invention By setting each level of GOA unit to scan two rows of scan lines, odd-numbered GOA units and even-numbered GOA units alternately scan, which can reduce the working time of each level of GOA unit by half, thereby reducing product power consumption and extending the product Life, improve the green energy-saving level of products
  • the first group of high-frequency clock signals includes a first high-frequency clock signal CK1, a third high-frequency clock signal CK3, and a fifth high-frequency clock signal.
  • the second group of high-frequency clock signals includes a second high-frequency clock signal CK2, a fourth high-frequency clock signal CK4, a sixth high-frequency clock signal CK6, and an eighth clock signal CK8;
  • the rising edge generation time of the first high-frequency clock signal CK1, the third high-frequency clock signal CK3, the fifth high-frequency clock signal CK5, and the seventh high-frequency clock signal CK7 are sequentially separated by a preset delay time;
  • the waveforms of the second high-frequency clock signal CK2, the fourth high-frequency clock signal CK4, the sixth high-frequency clock signal CK6, and the eighth high-frequency clock signal CK8 correspond to the first high-frequency clock signal CK1 and the third high-frequency clock signal CK3, respectively ,
  • the waveforms of the fifth high-frequency clock signal CK5 and the seventh high-frequency clock signal CK7 are the same;
  • n be a positive integer
  • the 8n-7th stage gate drive unit, the 8n-6th stage gate drive unit, the 8n-5th stage gate drive unit, the 8n-4th stage gate drive unit, the 8n-3th stage Stage gate driving unit, 8n-2th stage gate driving unit, 8n-1th stage gate driving unit, and 8nth stage gate driving unit respectively receive a first high-frequency clock signal CK1 and a second high-frequency clock signal CK2 ,
  • the third high frequency clock signal CK3, the fourth high frequency clock signal CK4 the fifth high frequency clock signal CK5, the sixth high frequency clock signal CK6, the seventh high frequency clock signal CK7, and the eighth high frequency clock signal CK8.
  • the working process of the second embodiment is the same as that of the first embodiment, except that the number of high-frequency clock signals is changed, which will not be repeated here.
  • the number of high-frequency clock signals included in the first group of high-frequency clock signals and the second group of high-frequency clock signals may also be other numbers, for example, both are 2 or both are 6. Therefore, it is only necessary to ensure that the number of high-frequency clock signals included in the first group of high-frequency clock signals and the second group of high-frequency clock signals are equal, and the waveforms are the same in one-to-one correspondence.
  • the M-th gate driving unit includes: a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a fourth thin film transistor T4 , Fifth thin film transistor T5, sixth thin film transistor T6, seventh thin film transistor T7, eighth thin film transistor T8, ninth thin film transistor T9, tenth thin film transistor T10, eleventh thin film transistor T11, and twelfth thin film transistor T12 , The thirteenth thin film transistor T13, the fourteenth thin film transistor T14, the fifteenth thin film transistor T15, the sixteenth thin film transistor T16 and the capacitor C1;
  • the gate and source of the first thin film transistor T1 both receive the scan signal G(M-2) of the M-2th stage gate driving unit, and the drain is electrically connected to the first node Q(M);
  • the gate of the second thin film transistor T2 is electrically connected to the first node Q(M), the source receives the high-frequency clock signal CK, and the drain outputs the scan signal G(M);
  • the gate of the third thin film transistor T3 receives the scan signal G(M+2) of the M+2th stage gate driving unit, the source is electrically connected to the first node Q(M), and the drain receives the low potential VSS;
  • the gate of the fourth thin film transistor T4 receives the scanning signal G(M+2) of the M+2th stage gate driving unit, the source is electrically connected to the drain of the second thin film transistor T2, and the drain receives the low potential VSS ;
  • the gate of the fifth thin film transistor T5 is electrically connected to the drain of the tenth thin film transistor T10, the source is electrically connected to the first node Q(M), and the drain receives the low potential VSS;
  • the gate of the sixth thin film transistor T6 is electrically connected to the drain of the tenth thin film transistor T10, the source is electrically connected to the drain of the second thin film transistor T2, and the drain receives the low potential VSS;
  • the gate and source of the seventh thin film transistor T7 both receive the first low-frequency clock signal LC1, and the drain is electrically connected to the gate of the tenth thin film transistor T10;
  • the gate of the eighth thin film transistor T8 is electrically connected to the first node Q(M), the source is electrically connected to the gate of the tenth thin film transistor T10, and the drain receives the low potential VSS;
  • the gate of the ninth thin film transistor T9 is electrically connected to the first node Q(M), the source is electrically connected to the drain of the tenth thin film transistor T10, and the drain receives the low potential VSS;
  • the source of the tenth thin film transistor T10 receives the first low-frequency clock signal LC1;
  • the gate of the eleventh thin film transistor T11 is electrically connected to the drain of the sixteenth thin film transistor T16, the source is electrically connected to the first node Q(M), and the drain receives the low potential VSS;
  • the gate of the twelfth thin film transistor T12 is electrically connected to the drain of the sixteenth thin film transistor T16, the source is electrically connected to the drain of the second thin film transistor T2, and the drain receives the low potential VSS;
  • the gate and source of the thirteenth thin film transistor T13 both receive the second low-frequency clock signal LC2, and the drain is electrically connected to the gate of the sixteenth thin film transistor T16;
  • the gate of the fourteenth thin film transistor T14 is electrically connected to the first node Q(M), the source is electrically connected to the gate of the sixteenth thin film transistor T16, and the drain receives the low potential VSS;
  • the gate of the fifteenth thin film transistor T15 is electrically connected to the first node Q(M), the source is electrically connected to the drain of the sixteenth thin film transistor T16, and the drain receives the low potential VSS;
  • the source of the sixteenth thin film transistor 16 receives the second low-frequency clock signal LC2;
  • the first terminal of the capacitor C1 is electrically connected to the first node Q(M), and the second terminal is electrically connected to the drain of the second thin film transistor T2.
  • the high-frequency clock signal CK in the gate driving unit 21 is the first high-frequency clock signal CK1 and the third One of the high-frequency clock signal CK3 and the fifth high-frequency clock signal CK.
  • the high-frequency clock signal CK in the gate driving unit 21 is the second high-frequency clock signal CK2 and the fourth high One of the high-frequency clock signal CK4 and the sixth high-frequency clock signal CK6.
  • the high-frequency clock signal CK in the gate driving unit 21 is the first high-frequency clock signal CK1 and the third One of the high-frequency clock signal CK3, the fifth high-frequency clock signal CK5, and the seventh high-frequency clock signal CK7.
  • the high-frequency clock signal CK in the gate driving unit 21 is the second highest One of the high-frequency clock signal CK2, the fourth high-frequency clock signal CK4, the sixth high-frequency clock signal CK6, and the eighth high-frequency clock signal CK8.
  • the source and drain of the first thin film transistor T1 in the first-stage gate driving unit 21 receive the first start signal STV1
  • the source and drain of the first thin film transistor T1 in the second-stage gate driving unit 21 receive the second start signal STV2
  • the third thin film transistor T3 and the fourth thin film transistor T4 of the last even-numbered GOA unit 21 The gate receives the second start signal STV2, and the gates of the third thin film transistor T3 and the fourth thin film transistor T4 of the last odd-numbered GOA unit 21 receive the first start signal STV1, so that the gate driving unit 21 can smoothly Startup and shutdown.
  • the working process of the gate driving unit 21 shown in FIG. 3 is as follows: first, the scan signal G(M-2) of the M-2th gate driving unit is at a high potential, and the first thin film transistor T1 is turned on. The first node Q(M) is charged so that the second thin film transistor T2 is turned on, the high-frequency clock signal CK outputs the scan signal G(M) through the drain of the second thin film transistor T2, and then the M+2th stage gate drive The unit scan signal G (M+2) is at a high potential, the third and fourth thin film transistors T3 and T4 are turned on, and the first node Q (M) and the scan signal G (M) are pulled down to a low potential VSS. Finally, the first low frequency The clock signal LC1 and the second high frequency clock signal LC2 work alternately, so that the first node Q (M) and the scan signal G (M) are maintained at a low potential VSS.
  • the present invention also provides a display device including the above-mentioned display driving circuit.
  • the present invention provides a display drive circuit, including a gate drive circuit and a plurality of parallel and spaced scan lines electrically connected to the gate drive circuit.
  • the gate drive circuit includes multiple stages. Gate driving unit, in which the odd-numbered gate driving units are cascaded, and the even-numbered gate driving units are cascaded; by setting each level of GOA unit to scan two rows of scan lines, the odd-numbered GOA unit and the even-numbered The alternate scanning of GOA units can halve the working time of each level of GOA unit, thereby reducing product power consumption, extending product life, and improving the product’s green and energy-saving level.
  • the invention also provides a display device, which can reduce the power consumption of the product, extend the life of the product, and improve the green energy-saving level of the product.

Abstract

提供了一种显示驱动电路及显示装置。显示驱动电路包括栅极驱动电路1及与栅极驱动电路1电性连接的多行平行间隔排列的扫描线2，栅极驱动电路1包括多级栅极驱动单元21，其中各个奇数级栅极驱动单元21进行级联，偶数级栅极驱动单元21进行级联；通过设置每一级GOA单元21对应扫描两行扫描线2，奇数级的GOA单元21和偶数级的GOA单元21交替进行扫描，能够使得每一级GOA单元21的工作时间减半，从而降低产品功耗，延长产品寿命，提升产品的绿色节能水平。

Description

显示驱动电路及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种显示驱动电路及显示装置。
 背景技术
液晶显示器（Liquid Crystal Display，LCD）具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理（PDA）、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组（backlight module）。液晶显示面板的工作原理是在薄膜晶体管阵列基板（Thin Film Transistor Array Substrate，TFT Array Substrate）与彩色滤光片基板（Color Filter，CF）之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动矩阵式液晶显示器（Active Matrix Liquid Crystal Display，AMLCD）是目前最常用的液晶显示装置，所述主动矩阵式液晶显示器包含多个像素，每个像素具有一个薄膜晶体管（Thin Film Transistor，TFT），该TFT的栅极连接至沿水平方向延伸的扫描线，漏极连接至沿垂直方向延伸的数据线，而该TFT的源极连接至对应的像素电极。如果在水平方向的某一扫描线上施加足够的正电压，则会使得连接在该条扫描线上的所有TFT打开，将数据线上所加载的数据信号电压写入像素电极中，控制不同液晶的透光度进而达到控制色彩的效果。
目前主动式液晶显示面板水平扫描线的驱动（即栅极驱动）主要由外接的集成电路（Integrated Circuit，IC）来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术（Gate Driver on Array）即阵列基板行驱动技术，可以运用液晶显示面板的原有制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接（bonding）工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
现有的栅极驱动电路通常包括级联的多级栅极驱动单元，扫描方式为一级栅极驱动单元扫描一行扫描线，在每一帧扫描时间内，所有的栅极驱动单元均需要参与扫描，这种扫描方式的栅极驱动电路的功耗较大，每一级栅极驱动单元的工作时间长，损耗大，无法满足绿色节能的产品标准。
 技术问题
本发明的目的在于提供一种显示驱动电路，能够降低产品功耗，延长产品寿命，提升产品的绿色节能水平。
本发明还提供一种显示装置，能够降低产品功耗，延长产品寿命，提升产品的绿色节能水平。
 技术解决方案
为实现上述目的，本发明提供了一种显示驱动电路，包括栅极驱动电路及与所述栅极驱动电路电性连接的多行平行间隔排列的扫描线，所述栅极驱动电路包括多级栅极驱动单元，其中各个奇数级栅极驱动单元进行级联，偶数级栅极驱动单元进行级联；
每相邻的两级栅极驱动单元为一个栅极驱动单元组，每一个栅极驱动单元组对应两行相邻的扫描线，同一个栅极驱动单元组中的两级栅极驱动单元均与该栅极驱动单元组对应的两行扫描线电性连接；
驱动时，奇数级的栅极驱动单元和偶数级的栅极驱动单元按照预设的切换周期交替工作；奇数级的栅极驱动单元工作时，奇数级的栅极驱动单元接收第一组高频时钟信号，并利用第一组高频时钟信号产生扫描信号，对各行扫描线进行扫描；偶数级的栅极驱动单元工作时，偶数级的栅极驱动单元接收第二组高频时钟信号，并利用第二组高频时钟信号产生扫描信号，对各行扫描线进行扫描。
所述第一组高频时钟信号包括第一高频时钟信号、第三高频时钟信号及第五高频时钟信号；
所述第二组高频时钟信号包括第二高频时钟信号、第四高频时钟信号及第六高频时钟信号；
所述第一高频时钟信号、第三高频时钟信号及第五高频时钟信号的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号、第四高频时钟信号及第六高频时钟信号的波形对应分别与第一高频时钟信号、第三高频时钟信号及第五高频时钟信号的波形相同；
设n为正整数，第6n-5级栅极驱动单元、第6n-4级栅极驱动单元、第6n-3级栅极驱动单元、第6n-2级栅极驱动单元、第6n-1级栅极驱动单元及第6n级栅极驱动单元分别接收第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号及第六高频时钟信号。
所述第一组高频时钟信号包括第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号；
所述第二组高频时钟信号包括第二高频时钟信号、第四高频时钟信号、第六高频时钟信号及第八时钟信号；
所述第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号、第四高频时钟信号、第六高频时钟信号及第八高频时钟信号的波形对应分别与第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号的波形相同；
设n为正整数，第8n-7级栅极驱动单元、第8n-6级栅极驱动单元、第8n-5级栅极驱动单元、第8n-4级栅极驱动单元、第8n-3级栅极驱动单元、第8n-2级栅极驱动单元、第8n-1级栅极驱动单元及第8n级栅极驱动单元分别接收第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号、第六高频时钟信号、第七高频时钟信号及第八高频时钟信号。
奇数级的栅极驱动单元工作时，第一级的栅极驱动单元还接收第一启动信号，用于驱动奇数级栅极驱动单元启动扫描；
偶数级的栅极驱动单元工作时，第二级的栅极驱动单元还接收第二启动信号，用于驱动偶数级栅极驱动单元启动扫描。
每一级栅极驱动单元均还接收第一低频时钟信号与第二低频时钟信号，用于在该级栅极驱动单元非输出期间维持该级栅极驱动单元的关闭状态。
奇数级的栅极驱动单元和偶数级的栅极驱动单元的工作每间隔80至120帧扫描时间切换一次。
奇数级的栅极驱动单元和偶数级的栅极驱动单元的工作每间隔100帧扫描时间切换一次。
所述显示驱动电路还包括阵列排布的多个像素单元，每一行扫描线均对应与一行像素单元电性连接。
所述栅极驱动电路为GOA电路。
本发明还提供一种显示装置，包括上述的显示驱动电路。
 有益效果
本发明的有益效果：本发明提供了一种显示驱动电路，包括栅极驱动电路及与所述栅极驱动电路电性连接的多行平行间隔排列的扫描线，所述栅极驱动电路包括多级栅极驱动单元，其中各个奇数级栅极驱动单元进行级联，偶数级栅极驱动单元进行级联；通过设置每一级GOA单元对应扫描两行扫描线，奇数级的GOA单元和偶数级的GOA单元交替进行扫描，能够使得每一级GOA单元的工作时间减半，从而降低产品功耗，延长产品寿命，提升产品的绿色节能水平。本发明还提供一种显示装置，能够降低产品功耗，延长产品寿命，提升产品的绿色节能水平。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的显示驱动电路的第一实施例的示意图；
图2为本发明的显示驱动电路的第一实施例的波形图；
图3为本发明的显示驱动电路的栅极驱动单元的电路图；
图4为本发明的显示驱动电路的第二实施例的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种显示驱动电路，包括栅极驱动电路1及与所述栅极驱动电路1电性连接的多行平行间隔排列的扫描线2，所述栅极驱动电路2包括多级栅极驱动单元21，其中各个奇数级栅极驱动单元21进行级联，偶数级栅极驱动单元21进行级联；
每相邻的两级栅极驱动单元21为一个栅极驱动单元组210，每一个栅极驱动单元组210对应两行相邻的扫描线2，同一个栅极驱动单元组210中的两级栅极驱动单元21均与该栅极驱动单元组210对应的两行扫描线2电性连接。
需要说明的是，本发明的显示驱动电路在驱动时，奇数级的栅极驱动单元21和偶数级的栅极驱动单元21按照预设的切换周期交替工作；奇数级的栅极驱动单元21工作时，奇数级的栅极驱动单元21接收第一组高频时钟信号，并利用第一组高频时钟信号产生扫描信号，对各行扫描线2进行扫描；偶数级的栅极驱动单元21工作时，偶数级的栅极驱动单元21接收第二组高频时钟信号，并利用第二组高频时钟信号产生扫描信号，对各行扫描线2进行扫描。
进一步地，奇数级的栅极驱动单元21工作时，第一级的栅极驱动单元21还接收第一启动信号STV1，用于驱动奇数级栅极驱动单元21启动扫描；
偶数级的栅极驱动单元21工作时，第二级的栅极驱动单元21还接收第二启动信号STV2，用于驱动偶数级栅极驱动单元21启动扫描。
进一步地，每一级栅极驱动单元21均还接收第一低频时钟信号LC1 与第二低频时钟信号LC2，用于在该级栅极驱动单元21非输出期间维持该级栅极驱动单元21的关闭状态。
优选地，奇数级的栅极驱动单元21和偶数级的栅极驱动单元21的工作每间隔80至120帧扫描时间切换一次。更优选地，奇数级的栅极驱动单元21和偶数级的栅极驱动单元21的工作每间隔100帧扫描时间切换一次。
进一步地，所述显示驱动电路还包括阵列排布的多个像素单元3，每一行扫描线2均对应与一行像素单元3电性连接。
优选地，所述栅极驱动电路1为GOA电路。
举例来说，如图1所示，在本发明的第一实施例中，所述第一组高频时钟信号包括第一高频时钟信号CK1、第三高频时钟信号CK3及第五高频时钟信号CK5；所述第二组高频时钟信号包括第二高频时钟信号CK2、第四高频时钟信号CK4及第六高频时钟信号CK6；所述第一高频时钟信号CK1、第三高频时钟信号CK3及第五高频时钟信号CK5的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号CK2、第四高频时钟信号CK4及第六高频时钟信号CK6的波形对应分别与第一高频时钟信号CK1、第三高频时钟信号CK3及第五高频时钟信号CK5的波形相同；
设n为正整数，第6n-5级栅极驱动单元、第6n-4级栅极驱动单元、第6n-3级栅极驱动单元、第6n-2级栅极驱动单元、第6n-1级栅极驱动单元及第6n级栅极驱动单元分别接收第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5及第六高频时钟信号CK6。
进一步地，如图2及图1所示，上述第一实施例的工作过程为：首先，第一启动信号STV1提供高电平脉冲，第二启动信号STV2不提供高电平脉冲奇数级的GOA单元21开始工作，偶数级的GOA单元21不工作，奇数级的GOA单元21工作时，第一级GOA单元21先接收第一高频时钟信号CK1，产生第一个扫描信号，并将第一个扫描信号输出到第一条扫描线L1和第二条扫描线L2中对第一条扫描线L1和第二条扫描线L2进行扫描，第三级GOA单元21接着接收第三高频时钟信号CK3，产生第二个扫描信号，并将第二个扫描信号输出到第三条扫描线L3和第四条扫描线L4中对第三条扫描线L3和第四条扫描线L4进行扫描，第五级GOA单元21再接收第五高频时钟信号CK5，产生第三个扫描信号，并将第三个扫描信号输出到第五条扫描线L5和第六条扫描线L6中对第五条扫描线L5和第六条扫描线L6进行扫描，依次类推直至最后一个奇数级的GOA单元21，完成一帧扫描，奇数级的GOA单元21完成100帧扫描之后，从第101帧开始，第二启动信号STV2提供高电平脉冲，第一启动信号STV1不提供高电平脉冲，偶数级的GOA单元21开始工作，奇数级的GOA单元21不工作，偶数级的GOA单元21工作时，第二级GOA单元21先接收第二高频时钟信号CK2，产生第一个扫描信号，并将第一个扫描信号输出到第一条扫描线L1和第二条扫描线L2中对第一条扫描线L1和第二条扫描线L2进行扫描，第四级GOA单元21接着接收第四高频时钟信号CK4，产生第二个扫描信号，并将第二个扫描信号输出到第三条扫描线L3和第四条扫描线L4中对第三条扫描线L3和第四条扫描线L4进行扫描，第六级GOA单元21再接收第六高频时钟信号CK6，产生第三个扫描信号，并将第三个扫描信号输出到第五条扫描线L5和第六条扫描线L6中对第五条扫描线L5和第六条扫描线L6进行扫描，依次类推直至最后一个奇数级的GOA单元21，完成一帧扫描，偶数级的GOA单元21又完成100帧扫描之后，从第301帧开始，奇数级的GOA单元21又开始工作，偶数级GOA单元21停止工作，后续不断循环交替工作，从而，本发明通过设置每一级GOA单元对应扫描两行扫描线，奇数级的GOA单元和偶数级的GOA单元交替进行扫描，能够使得每一级GOA单元的工作时间减半，从而降低产品功耗，延长产品寿命，提升产品的绿色节能水平
此外，如图4所示，在本发明的第二实施例中，所述第一组高频时钟信号包括第一高频时钟信号CK1、第三高频时钟信号CK3、第五高频时钟信号CK5及第七高频时钟信号CK7；所述第二组高频时钟信号包括第二高频时钟信号CK2、第四高频时钟信号CK4、第六高频时钟信号CK6及第八时钟信号CK8；
所述第一高频时钟信号CK1、第三高频时钟信号CK3、第五高频时钟信号CK5及第七高频时钟信号CK7的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号CK2、第四高频时钟信号CK4、第六高频时钟信号CK6及第八高频时钟信号CK8的波形对应分别与第一高频时钟信号CK1、第三高频时钟信号CK3、第五高频时钟信号CK5及第七高频时钟信号CK7的波形相同；
设n为正整数，第8n-7级栅极驱动单元、第8n-6级栅极驱动单元、第8n-5级栅极驱动单元、第8n-4级栅极驱动单元、第8n-3级栅极驱动单元、第8n-2级栅极驱动单元、第8n-1级栅极驱动单元及第8n级栅极驱动单元分别接收第一高频时钟信号CK1、第二高频时钟信号CK2、第三高频时钟信号CK3、第四高频时钟信号CK4、第五高频时钟信号CK5、第六高频时钟信号CK6、第七高频时钟信号CK7及第八高频时钟信号CK8。
具体地，该第二实施例的工作过程与第一实施例相同，仅仅是高频时钟信号的数量改变，此处不再赘述。
进一步地，在本发明的其他实施例中，第一组高频时钟信号和第二组高频时钟信号包括的高频时钟信号的数量还可以为其他数量，例如均为2个或均为6个，只需要保证第一组高频时钟信号和第二组高频时钟信号中包括的高频时钟信号的数量相等，且波形一一对应相同即可。
具体地，在本发明的一些实施例中，设M为正整数，第M级栅极驱动单元包括：第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管T16及电容C1；
所述第一薄膜晶体管T1的栅极和源极均接收第M-2级栅极驱动单元的扫描信号G(M-2)，漏极电性连接第一节点Q(M)；
所述第二薄膜晶体管T2的栅极电性连接第一节点Q(M)，源极接收高频时钟信号CK，漏极输出扫描信号G(M)；
所述第三薄膜晶体管T3的栅极接收第M+2级栅极驱动单元的扫描信号G(M+2)，源极电性连接第一节点Q(M)，漏极接收低电位VSS；
所述第四薄膜晶体管T4的栅极接收第M+2级栅极驱动单元的扫描信号G(M+2)，源极电性连接第二薄膜晶体管T2的漏极，漏极接收低电位VSS；
所述第五薄膜晶体管T5的栅极电性连接第十薄膜晶体管T10的漏极，源极电性连接第一节点Q(M)，漏极接收低电位VSS；
所述第六薄膜晶体管T6的栅极电性连接第十薄膜晶体管T10的漏极，源极电性连接第二薄膜晶体管T2的漏极，漏极接收低电位VSS；
所述第七薄膜晶体管T7的栅极和源极均接收第一低频时钟信号LC1，漏极电性连接第十薄膜晶体管T10的栅极；
所述第八薄膜晶体管T8的栅极电性连接第一节点Q(M)，源极电性连接第十薄膜晶体管T10的栅极，漏极接收低电位VSS；
所述第九薄膜晶体管T9的栅极电性连接第一节点Q(M)，源极电性连接第十薄膜晶体管T10的漏极，漏极接收低电位VSS；
所述第十薄膜晶体管T10的源极接收第一低频时钟信号LC1；
所述第十一薄膜晶体管T11的栅极电性连接第十六薄膜晶体管T16的漏极，源极电性连接第一节点Q(M)，漏极接收低电位VSS；
所述第十二薄膜晶体管T12的栅极电性连接第十六薄膜晶体管T16的漏极，源极电性连接第二薄膜晶体管T2的漏极，漏极接收低电位VSS；
所述第十三薄膜晶体管T13的栅极和源极均接收第二低频时钟信号LC2，漏极电性连接第十六薄膜晶体管T16的栅极；
所述第十四薄膜晶体管T14的栅极电性连接第一节点Q(M)，源极电性连接第十六薄膜晶体管T16的栅极，漏极接收低电位VSS；
所述第十五薄膜晶体管T15的栅极电性连接第一节点Q(M)，源极电性连接第十六薄膜晶体管T16的漏极，漏极接收低电位VSS；
所述第十六薄膜晶体管16的源极接收第二低频时钟信号LC2；
所述电容C1的第一端电性连接第一节点Q(M)，第二端电性连接第二薄膜晶体管T2的漏极。
具体地，对应到本发明的第一实施例中，如图3所示，当M为奇数时，该栅极驱动单元21中的高频时钟信号CK为第一高频时钟信号CK1、第三高频时钟信号CK3及第五高频时钟信号CK中的一个，当M为偶数时，该栅极驱动单元21中的高频时钟信号CK为所述第二高频时钟信号CK2、第四高频时钟信号CK4及第六高频时钟信号CK6中的一个。
具体地，对应到本发明的第二实施例中，如图3所示，当M为奇数时，该栅极驱动单元21中的高频时钟信号CK为第一高频时钟信号CK1、第三高频时钟信号CK3、第五高频时钟信号CK5及第七高频时钟信号CK7中的一个，当M为偶数时，该栅极驱动单元21中的高频时钟信号CK为所述第二高频时钟信号CK2、第四高频时钟信号CK4、第六高频时钟信号CK6及第八高频时钟信号CK8中的一个。
具体地，对应到图3所示的实施例中，为了保证栅极驱动电路的正常工作，第一级栅极驱动单元21中的第一薄膜晶体管T1的源极和漏极接收第一启动信号STV1，第二级栅极驱动单元21中的第一薄膜晶体管T1的源极和漏极接收第二启动信号STV2，最后一个偶数级GOA单元21的第三薄膜晶体管T3和第四薄膜晶体管T4的栅极接收第二启动信号STV2，最后一个奇数级GOA单元21的第三薄膜晶体管T3和第四薄膜晶体管T4的栅极接收第一启动信号STV1，以使得所述栅极驱动单元21能够顺利的启动和关闭。
进一步地，如图3所示的栅极驱动单元21的工作过程为：首先，第M-2级栅极驱动单元的扫描信号G(M-2)为高电位，第一薄膜晶体管T1打开，为第一节点Q(M)充电，使得第二薄膜晶体管T2打开，高频时钟信号CK经由第二薄膜晶体管T2的漏极输出扫描信号G(M)，接着，第M+2级栅极驱动单元扫描信号G(M+2)为高电位，第三和第四薄膜晶体管T3、T4打开，下拉第一节点Q(M)和扫描信号G(M)至低电位VSS，最后，第一低频时钟信号LC1和第二高频时钟信号LC2交替工作，使得第一节点Q(M)和扫描信号G(M)维持在低电位VSS。
此外，本发明还提供一种显示装置，包括上述的显示驱动电路。
综上所述，本发明提供了一种显示驱动电路，包括栅极驱动电路及与所述栅极驱动电路电性连接的多行平行间隔排列的扫描线，所述栅极驱动电路包括多级栅极驱动单元，其中各个奇数级栅极驱动单元进行级联，偶数级栅极驱动单元进行级联；通过设置每一级GOA单元对应扫描两行扫描线，奇数级的GOA单元和偶数级的GOA单元交替进行扫描，能够使得每一级GOA单元的工作时间减半，从而降低产品功耗，延长产品寿命，提升产品的绿色节能水平。本发明还提供一种显示装置，能够降低产品功耗，延长产品寿命，提升产品的绿色节能水平。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种显示驱动电路，包括栅极驱动电路及与所述栅极驱动电路电性连接的多行平行间隔排列的扫描线，所述栅极驱动电路包括多级栅极驱动单元，其中各个奇数级栅极驱动单元依次级联，各个偶数级栅极驱动单元依次级联；
    每相邻的两级栅极驱动单元为一个栅极驱动单元组，每一个栅极驱动单元组对应两行相邻的扫描线，同一个栅极驱动单元组中的两级栅极驱动单元均与该栅极驱动单元组对应的两行扫描线电性连接；
    驱动时，奇数级的栅极驱动单元和偶数级的栅极驱动单元按照预设的切换周期交替工作；奇数级的栅极驱动单元工作时，奇数级的栅极驱动单元接收第一组高频时钟信号，并利用第一组高频时钟信号产生扫描信号，对各行扫描线进行扫描；偶数级的栅极驱动单元工作时，偶数级的栅极驱动单元接收第二组高频时钟信号，并利用第二组高频时钟信号产生扫描信号，对各行扫描线进行扫描。
  2. 如权利要求1所述的显示驱动电路，其中，所述第一组高频时钟信号包括第一高频时钟信号、第三高频时钟信号及第五高频时钟信号；
    所述第二组高频时钟信号包括第二高频时钟信号、第四高频时钟信号及第六高频时钟信号；
    所述第一高频时钟信号、第三高频时钟信号及第五高频时钟信号的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号、第四高频时钟信号及第六高频时钟信号的波形对应分别与第一高频时钟信号、第三高频时钟信号及第五高频时钟信号的波形相同；
    设n为正整数，第6n-5级栅极驱动单元、第6n-4级栅极驱动单元、第6n-3级栅极驱动单元、第6n-2级栅极驱动单元、第6n-1级栅极驱动单元及第6n级栅极驱动单元分别接收第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号及第六高频时钟信号。
  3. 如权利要求1所述的显示驱动电路，其中，所述第一组高频时钟信号包括第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号；
    所述第二组高频时钟信号包括第二高频时钟信号、第四高频时钟信号、第六高频时钟信号及第八时钟信号；
    所述第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号、第四高频时钟信号、第六高频时钟信号及第八高频时钟信号的波形对应分别与第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号的波形相同；
    设n为正整数，第8n-7级栅极驱动单元、第8n-6级栅极驱动单元、第8n-5级栅极驱动单元、第8n-4级栅极驱动单元、第8n-3级栅极驱动单元、第8n-2级栅极驱动单元、第8n-1级栅极驱动单元及第8n级栅极驱动单元分别接收第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号、第六高频时钟信号、第七高频时钟信号及第八高频时钟信号。
  4. 如权利要求1所述的显示驱动电路，其中，奇数级的栅极驱动单元工作时，第一级的栅极驱动单元还接收第一启动信号，用于驱动奇数级栅极驱动单元启动扫描；
    偶数级的栅极驱动单元工作时，第二级的栅极驱动单元还接收第二启动信号，用于驱动偶数级栅极驱动单元启动扫描。
  5. 如权利要求1所述的显示驱动电路，其中，每一级栅极驱动单元均还接收第一低频时钟信号与第二低频时钟信号，用于在该级栅极驱动单元非输出期间维持该级栅极驱动单元的关闭状态。
  6. 如权利要求1所述的显示驱动电路，其中，奇数级的栅极驱动单元和偶数级的栅极驱动单元的工作每间隔80至120帧扫描时间切换一次。
  7. 如权利要求6所述的显示驱动电路，其中，奇数级的栅极驱动单元和偶数级的栅极驱动单元的工作每间隔100帧扫描时间切换一次。
  8. 如权利要求1所述的显示驱动电路，还包括阵列排布的多个像素单元，每一行扫描线均对应与一行像素单元电性连接。
  9. 如权利要求1所述的显示驱动电路，其中，所述栅极驱动电路为GOA电路。
  10. 一种显示装置，包括显示驱动电路；
    所述显示驱动电路，包括栅极驱动电路及与所述栅极驱动电路电性连接的多行平行间隔排列的扫描线，所述栅极驱动电路包括多级栅极驱动单元，其中各个奇数级栅极驱动单元依次级联，各个偶数级栅极驱动单元依次级联；
    每相邻的两级栅极驱动单元为一个栅极驱动单元组，每一个栅极驱动单元组对应两行相邻的扫描线，同一个栅极驱动单元组中的两级栅极驱动单元均与该栅极驱动单元组对应的两行扫描线电性连接；
    驱动时，奇数级的栅极驱动单元和偶数级的栅极驱动单元按照预设的切换周期交替工作；奇数级的栅极驱动单元工作时，奇数级的栅极驱动单元接收第一组高频时钟信号，并利用第一组高频时钟信号产生扫描信号，对各行扫描线进行扫描；偶数级的栅极驱动单元工作时，偶数级的栅极驱动单元接收第二组高频时钟信号，并利用第二组高频时钟信号产生扫描信号，对各行扫描线进行扫描。
  11. 如权利要求10所述的显示装置，其中，所述第一组高频时钟信号包括第一高频时钟信号、第三高频时钟信号及第五高频时钟信号；
    所述第二组高频时钟信号包括第二高频时钟信号、第四高频时钟信号及第六高频时钟信号；
    所述第一高频时钟信号、第三高频时钟信号及第五高频时钟信号的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号、第四高频时钟信号及第六高频时钟信号的波形对应分别与第一高频时钟信号、第三高频时钟信号及第五高频时钟信号的波形相同；
    设n为正整数，第6n-5级栅极驱动单元、第6n-4级栅极驱动单元、第6n-3级栅极驱动单元、第6n-2级栅极驱动单元、第6n-1级栅极驱动单元及第6n级栅极驱动单元分别接收第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号及第六高频时钟信号。
  12. 如权利要求10所述的显示装置，其中，所述第一组高频时钟信号包括第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号；
    所述第二组高频时钟信号包括第二高频时钟信号、第四高频时钟信号、第六高频时钟信号及第八时钟信号；
    所述第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号的上升沿产生时间依次间隔一个预设的延迟时间；所述第二高频时钟信号、第四高频时钟信号、第六高频时钟信号及第八高频时钟信号的波形对应分别与第一高频时钟信号、第三高频时钟信号、第五高频时钟信号及第七高频时钟信号的波形相同；
    设n为正整数，第8n-7级栅极驱动单元、第8n-6级栅极驱动单元、第8n-5级栅极驱动单元、第8n-4级栅极驱动单元、第8n-3级栅极驱动单元、第8n-2级栅极驱动单元、第8n-1级栅极驱动单元及第8n级栅极驱动单元分别接收第一高频时钟信号、第二高频时钟信号、第三高频时钟信号、第四高频时钟信号、第五高频时钟信号、第六高频时钟信号、第七高频时钟信号及第八高频时钟信号。
  13. 如权利要求10所述的显示装置，其中，奇数级的栅极驱动单元工作时，第一级的栅极驱动单元还接收第一启动信号，用于驱动奇数级栅极驱动单元启动扫描；
    偶数级的栅极驱动单元工作时，第二级的栅极驱动单元还接收第二启动信号，用于驱动偶数级栅极驱动单元启动扫描。
  14. 如权利要求10所述的显示装置，其中，每一级栅极驱动单元均还接收第一低频时钟信号与第二低频时钟信号，用于在该级栅极驱动单元非输出期间维持该级栅极驱动单元的关闭状态。
  15. 如权利要求10所述的显示装置，其中，奇数级的栅极驱动单元和偶数级的栅极驱动单元的工作每间隔80至120帧扫描时间切换一次。
  16. 如权利要求15所述的显示装置，其中，奇数级的栅极驱动单元和偶数级的栅极驱动单元的工作每间隔100帧扫描时间切换一次。
  17. 如权利要求10所述的显示装置，其中，所述显示驱动电路还包括阵列排布的多个像素单元，每一行扫描线均对应与一行像素单元电性连接。
  18. 如权利要求10所述的显示装置，其中，所述栅极驱动电路为GOA电路。
PCT/CN2019/085769 2019-01-29 2019-05-07 显示驱动电路及显示装置 WO2020155453A1 (zh)

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CN111445828A (zh) * 2020-04-20 2020-07-24 深圳市华星光电半导体显示技术有限公司 显示驱动电路及显示装置
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