WO2020244342A1 - 显示面板、其驱动方法及显示装置 - Google Patents

显示面板、其驱动方法及显示装置 Download PDF

Info

Publication number
WO2020244342A1
WO2020244342A1 PCT/CN2020/087292 CN2020087292W WO2020244342A1 WO 2020244342 A1 WO2020244342 A1 WO 2020244342A1 CN 2020087292 W CN2020087292 W CN 2020087292W WO 2020244342 A1 WO2020244342 A1 WO 2020244342A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
electrically connected
line
control circuit
display panel
Prior art date
Application number
PCT/CN2020/087292
Other languages
English (en)
French (fr)
Inventor
宗少雷
孙伟
孙继刚
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020244342A1 publication Critical patent/WO2020244342A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device.
  • the data driving chip in the display outputs the pixel voltage to the pixel unit through the data line. Due to the large number of data lines in the display, correspondingly, the data driving chip needs more pins, so there are correspondingly more data transmission lines for transmitting data signals to each data line, which is not conducive to realizing the narrow frame of the display.
  • a plurality of data lines are arranged in the display area of the base substrate;
  • a plurality of source input terminals arranged in the non-display area of the base substrate
  • a plurality of gate control circuits are arranged in the non-display area of the base substrate; one of the plurality of gate control circuits is electrically connected to one of the plurality of source input terminals, and the One of the plurality of gate control circuits is electrically connected to at least three of the plurality of data lines;
  • a plurality of precharge control circuits are arranged in the non-display area of the base substrate; one of the plurality of precharge control circuits is arranged corresponding to one of the plurality of gate control circuits, and One of the plurality of precharge control circuits is electrically connected to at least three of the plurality of data lines, and the data line electrically connected to the precharge control circuit is electrically connected to the corresponding data line of the gate control circuit the same;
  • the gate control circuit is configured to sequentially apply a data voltage to each electrically connected data line through a signal loaded from the source input terminal during the scanning period of each gate line; wherein The data line to which the data voltage is loaded for the first time in the scanning period is the first data line, and the other data lines are the second data lines;
  • the precharge control circuit is configured to load a precharge voltage to at least one of the second data lines while the corresponding gate control circuit loads the first data line with a data voltage.
  • the precharge control circuit is configured to apply a data voltage to all other second data lines while the gate control circuit loads the data voltage on the first data line. Load the precharge voltage.
  • the gate control circuit includes: a plurality of first switch transistors; The first switch transistor is arranged corresponding to one of the data lines;
  • each first switching transistor is electrically connected to a different first control signal line, and the first pole of each first switching transistor is connected to the corresponding data line Electrically connected, the second pole of each of the first switch transistors is electrically connected to the same source input terminal.
  • it further includes: a plurality of second control signal lines and precharge signal lines located in the display area;
  • the precharge control circuit includes: a plurality of second switch transistors; wherein, one switch transistor is arranged corresponding to one of the data lines;
  • each second switching transistor is electrically connected to a different second control signal line, and the first pole of each second switching transistor is connected to the corresponding data line Are electrically connected, and the second pole of each second switch transistor is electrically connected to the precharge signal line.
  • the number of the first control signal lines is the same as the number of the second control signal lines.
  • the precharge signal line includes two sub-precharge signal lines, and two adjacent data lines communicate with different sub-precharge signals through the corresponding second switching transistors.
  • the signal line is electrically connected.
  • a plurality of pixel units are further included, and the pixel units include a plurality of sub-pixels of different colors; wherein, the color of the sub-pixels in the same column is the same, and one data line and one column The sub-pixels are electrically connected;
  • Each of the gate control circuits is electrically connected to three data lines, and the colors of the sub-pixels electrically connected to the three data lines are all different.
  • the plurality of sub-pixels of different colors include first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels that are sequentially arranged along the row direction of the sub-pixels;
  • Two adjacent pixel units are used as a unit group, and the pixel units in different unit groups are different;
  • One unit group corresponds to the two gate control circuits, and the three data lines electrically connected to the two gate control circuits are alternately arranged along the row direction.
  • the display panel further includes:
  • the data driving circuit includes a plurality of signal output pins; wherein one of the source input terminals is electrically connected to one of the signal output pins;
  • the data driving circuit is configured to apply a data voltage to the electrically connected source input terminal through each of the signal output pins during the scanning period of each of the gate lines.
  • the embodiment of the present disclosure also provides a display device including the above-mentioned display panel.
  • the embodiment of the present disclosure also provides a driving method of the display panel, including:
  • the gate control circuit sequentially applies a data voltage to each of the electrically connected data lines through the signal loaded from the source input terminal; wherein, the first load is applied during the scanning period of the gate line
  • the data line of the data voltage is the first data line
  • the other data lines are the second data lines; and, while the gate control circuit loads the data voltage on the first data line, the precharge control circuit Load a precharge voltage to at least one of the second data lines; and, when the gate control circuit loads the second data line with a data voltage, disconnect the precharge control circuit from the data line Electrical connection.
  • the duration of applying the data voltage to the first data line is greater than the duration of applying the data voltage to the second data line.
  • the duration of applying the data voltage to the second data line is approximately the same.
  • the duration of applying the precharge voltage to the second data line is the same as the duration of applying the data voltage to the first data line.
  • Figure 1 is a schematic diagram of the structure of a display panel in the related art
  • Figure 2 is a timing diagram corresponding to Figure 1;
  • 3A-3C are schematic diagrams of the pixel charging effect of the display panel in the related art.
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of the timing structure of the display panel corresponding to FIG. 4;
  • 6A-6C are schematic diagrams of the pixel charging effect of the display panel provided by the embodiments of the disclosure.
  • a strobe control circuit (Multiplexer, MUX) is provided between the data drive chip and the data line in the related art.
  • the data driving chip can connect three RGB sub-pixels through MUX (may be called 1:3-MUX scheme), and the data driving chip may connect six RGB sub-pixels through MUX (may be called 1:6-MUX scheme) And so on, this can greatly reduce the number of data transmission lines, reduce the size of the data drive chip, and reduce the size of the display frame.
  • the pixel charging time under the 1:3-MUX design is reduced to 1/3 of the turn-on time of the sub-pixel under the control of the gate line, while 1:6-MUX
  • the pixel charging time is reduced to 1/6 of the turn-on time of the sub-pixel under the control of the gate line under the design.
  • the screen size and resolution increase, the RC Loading of the display panel itself increases.
  • the turn-on time of MUX is shortened, which greatly reduces the charging time of sub-pixels, resulting in insufficient charging of sub-pixels.
  • the larger n is, the more serious the insufficient charging problem is. For example, there is usually a serious insufficient charging problem, which affects the display quality of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art, and the display panel adopts a 1:3-MUX scheme to charge pixels.
  • the labels mux-r, mux-g, and mux-b are used to indicate the three control signal lines corresponding to the sub-pixel columns of different colors.
  • the display panel includes: multiple gate lines G1 ⁇ G1920, control signal lines mux-r, mux-g, and mux-b, first switching transistors T1 corresponding to the data lines (D1, D2, D3...) one-to-one, data
  • the driver IC (Integrated circuit, integrated circuit) 01 is electrically connected to the first pole of the corresponding first switching transistor T1 through a data transmission line (labeled S1, S2...in FIG.
  • the first switching transistor T1 The gate of the first switch transistor T1 is electrically connected to the corresponding control signal line, the second electrode of the first switch transistor T1 is electrically connected to the multiple columns of sub-pixels through the first end of the data line (D1, D2, D3...); the data transmission line (S1, S2 The ratio of the number of ...) to the number of data lines (D1, D2, D3...) is 1:3, and two adjacent data lines receive data voltages transmitted by different data transmission lines.
  • the data driver IC01 controls the control signal lines mux-r, mux-g and mux-b to switch to control the first switching transistor T1 to conduct, that is, the data driver IC01 and the data transmission line S1 , S2, the first switching transistor T1, the data line (D1, D2, D3...) and the sub-pixels form a data voltage transmission channel, and then the data driver IC01 outputs the data voltage to the data line of the corresponding column through the data transmission line, so that The data voltage is output to the corresponding sub-pixel.
  • the display panel shown in Figure 1 reduces the number of data transmission lines (S1, S2%) to 1/3 of the number of data lines (D1, D2, D3...), that is, one data transmission line is time-shared by the control signal line
  • the charging control sequence of R sub-pixels, G and B corresponding to the three data lines controlled by mux-r, mux-g and mux-b is shown in Figure 2.
  • the control signal lines mux-r, mux-g, and mux-b are turned on sequentially in turn, the turn-on times of the three are equal, and the sum of the turn-on times of the three is the turn-on time of a gate line, that is, the gate line G1 to the gate line G1920
  • the turn-on time of each gate line is divided equally by the turn-on time of the control signal lines mux-r, mux-g, and mux-b.
  • the data transmission line S1 only charges the first data line D1 and the R sub-pixel on the left side of the display panel.
  • the data transmission line S1 only charges the fifth data line D5 on the left side of the display panel and the G sub-pixel.
  • the data transmission line S1 only charges the third data line D3 on the left side of the display panel and the B sub-pixel.
  • This 1:3-MUX scheme design can reduce the number of data transmission lines (S1, S2%) to 1/3 of the number of data lines (D1, D2, D3...), greatly reducing data The number and size of the driver IC01 and the size of the fan-out area of the display panel.
  • the 1:3-MUX scheme design inevitably reduces the charging time of the sub-pixels to 1/3 of the gate opening time. Taking the liquid crystal display panel as an example, the charging time of the liquid crystal capacitor is greatly reduced, resulting in insufficient charging of the liquid crystal capacitor.
  • FIGS. 3A to 3C are respectively schematic diagrams of pixel charging effects from 0 gray scale voltage to 255 gray scale voltage corresponding to R, G, and B sub-pixels.
  • L1-MUX represents the turn-on time of the control signal line
  • L1-R represents the charging effect of the R sub-pixel
  • L2-MUX represents the turn-on time of the control signal line
  • L2-G represents the charging effect of the G sub-pixel
  • L3-MUX represents the turn-on time of the control signal line
  • L3-B represents the charging effect of the B sub-pixel.
  • a plurality of source input terminals Q-k are arranged in the non-display area of the base substrate.
  • a plurality of gate control circuits 100-k are arranged in the non-display area of the base substrate.
  • a plurality of precharge control circuits 200-k are arranged in the non-display area of the base substrate.
  • one of the plurality of gate control circuits 100-k is electrically connected to one of the plurality of source input terminals Qk, and one of the plurality of gate control circuits 100-k is respectively connected to the At least three of the multiple data lines are electrically connected.
  • One of the plurality of precharge control circuits 200-k is arranged corresponding to one of the plurality of gate control circuits 100-k, and one of the plurality of precharge control circuits 200-k is respectively connected to At least three of the plurality of data lines are electrically connected, and the data line electrically connected to the precharge control circuit 200-k is the same as the data line electrically connected to the corresponding gate control circuit 100-k.
  • the gate control circuit 100-k is configured to sequentially apply a data voltage to each electrically connected data line through the signal loaded from the source input terminal during the scanning period of each gate line;
  • the data line to which the data voltage is applied for the first time in the scanning period of the gate line is the first data line, and the other data lines are the second data lines;
  • the precharge control circuit 200-k is configured to load a precharge voltage to at least one of the second data lines while the corresponding gate control circuit loads the first data line with a data voltage.
  • the display panel provided by the embodiment of the present disclosure is provided with a precharge control circuit corresponding to the gate control circuit one by one, and each corresponding gate control circuit and precharge control circuit is electrically connected to the same data line.
  • the gate control circuit loads the first data line with the data voltage during the gate line scanning period
  • the precharge control circuit loads the second data line with the precharge voltage.
  • the gate control circuit sequentially performs When the second data line is loaded with the data voltage, since the second data line has been pre-loaded with the precharge voltage, the pixel charging time can be added to the pixel charging time.
  • the above-mentioned display panel provided by the embodiments of the present disclosure can not only solve the problem of insufficient pixel charging, but also can be used for ultra-high resolution, ultra-high frequency, large size, borderless, and other technologies that require extremely strict pixel charging time.
  • Direction to provide solutions can be used for ultra-high resolution, ultra-high frequency, large size, borderless, and other technologies that require extremely strict pixel charging time.
  • the gate control circuit 100-1 corresponds to the precharge control circuit 200-1 one to one
  • the gate control circuit 100-2 corresponds to the precharge control circuit 200-2 one to one
  • the gate control circuit 100-k is electrically connected to the three data lines
  • each precharge control circuit 200-k is electrically connected to the same data line with the corresponding gate control circuit 100-k.
  • the gate control circuit 100-1 is electrically connected to three data lines (D1, D3, and D5) and the source input terminal Q1, and the precharge control circuit 200-1 corresponding to the gate control circuit 100-1 is the same as the three The data lines (D1, D3, and D5) are electrically connected.
  • the gate control circuit 100-2 is electrically connected to the three data lines (D2, D4, and D6) and the source input terminal Q2, and the precharge control circuit 200-2 corresponding to the gate control circuit 100-2 is connected to the same three data lines (D2, D4 and D6) are electrically connected.
  • the gate control circuit 100-1 is configured to sequentially load data on the electrically connected data lines (D1, D3, and D5) during the scanning period of each gate line through the signal loaded through the source input terminal Q-1 Voltage.
  • the pass control circuit 100-2 is configured to sequentially apply a data voltage to each electrically connected data line (D2, D4, and D6) during the scanning period of each gate line through a signal loaded through the source input terminal Q-2.
  • the data line to which the data voltage is first applied during the scanning period of the gate line is the first data line.
  • the data lines D1 and D4 are the first data lines
  • the other data lines are the second data lines, such as the data lines D2, D3, and D3.
  • D5 and D6 are the second data lines;
  • the precharge control circuit 200-k is configured to apply a precharge voltage to at least one second data line while the gate control circuit 100-k loads the first data line (for example, the data line D1) with a data voltage, such as The line D3 is loaded with a precharge voltage, or the data line D5 is loaded with a precharge voltage, or the data lines D3 and D5 are loaded with a precharge voltage at the same time.
  • the first data line for example, the data line D1
  • the line D3 is loaded with a precharge voltage
  • the data line D5 is loaded with a precharge voltage
  • the data lines D3 and D5 are loaded with a precharge voltage at the same time.
  • the display panel provided by the embodiment of the present disclosure is provided with a precharge control circuit corresponding to the gate control circuit one-to-one, and each corresponding gate control circuit and precharge control circuit is electrically connected with the same preset number of data lines,
  • the gate control circuit loads the first data line with the data voltage during the scanning period of the gate line
  • the precharge control circuit loads the precharge voltage on at least one second data line.
  • the gate control circuit sequentially loads the data voltage during the scanning period of the gate line
  • the pixel charging time can be additionally increased on the basis of the original pixel charging time in the gate line scanning time.
  • the above-mentioned display panel provided by the embodiments of the present disclosure can not only solve the problem of insufficient pixel charging of existing display products, but also can require extremely strict pixel charging time for ultra-high resolution, ultra-high frequency, large size, and borderless. Provide solutions in demanding technical direction.
  • the pixel charging time is additionally increased.
  • the precharge control circuit 200-k is configured to load the first data line (for example, the data lines D1 and D4) with a data voltage while the gate control circuit 100-k applies the data voltage to all other second data lines (for example, the data line). D2, D3, D5 and D6) are all loaded with precharge voltage.
  • the above-mentioned display panel provided by the embodiment of the present disclosure further includes: a plurality of first control signal lines (for example, MUXR, MUXG, MUXB), multiple second control signal lines (for example, Pre_R, Pre_G, Pre_B), and precharge signal lines (for example, S_od(+), S_ev(-)); each gate control circuit 100-k includes: One first switching transistor T1; wherein, one of the first switching transistors is arranged corresponding to one of the data lines. For example, the first switching transistor T1 corresponds to each data line D1, D3, and D5 one-to-one.
  • first control signal lines for example, MUXR, MUXG, MUXB
  • multiple second control signal lines for example, Pre_R, Pre_G, Pre_B
  • precharge signal lines for example, S_od(+), S_ev(-)
  • each gate control circuit 100-k includes: One first switching transistor T1; wherein, one of the first switching transistors
  • each first switching transistor T1 is electrically connected to a different first control signal line, such as the gate of the first switching transistor T1 electrically connected to the data line D1 and the first control signal line.
  • the signal line MUXR is electrically connected.
  • the gate of the first switching transistor T1 electrically connected to the data line D3 is electrically connected to the first control signal line MUXB, such as the gate of the first switching transistor T1 electrically connected to the data line D5 and the first control signal line MUXB.
  • a control signal line MUXG is electrically connected.
  • each first switching transistor T1 is electrically connected to the corresponding data line (for example, data lines D1, D3, D5), and the second electrode of each first switching transistor T1 is connected to the same source input terminal (for example, the source The input terminals Q-1, Q-2) are electrically connected.
  • the precharge control circuit 200 includes: a plurality of second switching transistors T2; wherein, one switching transistor is arranged corresponding to one of the data lines.
  • the second switching transistor T2 corresponds to each data line D1, D3, and D5 one-to-one.
  • the gate of the second switching transistor T2 is electrically connected to a different second control signal line, for example, the gate of the second switching transistor T2 electrically connected to the data line D1 is electrically connected to the second control signal line Pre_R, such as to the data line D3
  • the gate of the electrically connected second switching transistor T2 is electrically connected to the second control signal line Pre_B, for example, the gate of the second switching transistor T2 electrically connected to the data line D5 is electrically connected to the second control signal line Pre_G.
  • the first pole of each second switching transistor T2 is electrically connected to the corresponding data line (for example, the data lines D1, D3, D5), and the second pole of each second switching transistor T2 is electrically connected to the precharge signal line.
  • the number of the first control signal lines is the same as the number of the second control signal lines.
  • three first control signal lines can be provided, namely, the first control signal lines MUXR, MUXG, and MUXB.
  • three second control signal lines are provided, namely the second control signal lines Pre_R, Pre_G, Pre_B.
  • the precharge signal line includes two sub-precharge signal lines S_od and S_ev, and two adjacent data lines pass through the corresponding first
  • the two switching transistors are electrically connected to different sub-precharge signal lines.
  • the second switching transistor T2 corresponding to the odd-numbered data lines (for example, data lines D1, D3, D5, D7...) is connected to the sub-precharge signal line S_od, and the even-numbered data lines (for example, the data lines D2, D4) , D6, D8...)
  • the corresponding second switch transistor T2 is connected to the sub-precharge signal line S_ev.
  • the display panel further includes: a data driving circuit including a plurality of signal output pins OP-k; among them, one The source input terminal Qk is electrically connected to the signal output pin OP-k.
  • the data driving circuit is configured to apply a data voltage to the electrically connected source input terminal through each of the signal output pins during the scanning period of each of the gate lines.
  • the source input terminal Q-k is electrically connected to the signal output pin OP-k in the data driving circuit 300 in a one-to-one correspondence.
  • the source input terminal Q-k and the signal output pin OP-k may be electrically connected using a bonding process.
  • the data driving circuit may be a data driving IC.
  • the voltage polarity of the sub-precharge signal line S_od needs to be outputted from the signal output pin OP-1 of the data driving circuit 300
  • the polarity of the voltage of S_ev must be consistent with the polarity of the voltage output by the signal output pin OP-2 of the data driving circuit 300, and the polarity is switched along with the frame switching, which is not fixed Positive and negative polarity.
  • the voltage polarities of the sub-precharge signal lines S_od and S_ev are opposite, and the odd-numbered data lines D1, D3, D5, D7...
  • the data lines D2, D4, D6, D8 of the even-numbered columns are connected to the sub-precharge signal line S_ev through the corresponding second switching transistor T2, that is, the sub-pixels in two adjacent columns are charged with voltages of opposite polarities.
  • the second control signal lines Pre_R, Pre_G, and Pre_B are sequentially The gate of the second switching transistor T2 is connected.
  • the second control signal line Pre_R controls the data lines electrically connected to the R sub-pixels (ie data lines D1, D4, D7, ...)
  • the second control signal line Pre_G controls the data lines electrically connected to the G sub-pixels (ie data lines). D2, D5, D8,...)
  • the second control signal line Pre_B controls the data lines (that is, data lines D3, D6, D9,...) electrically connected to the B sub-pixel.
  • the above-mentioned display panel provided by the embodiment of the present disclosure further includes a plurality of pixel units, and the pixel units include a plurality of sub-pixels of different colors;
  • the sub-pixels have the same color, and one data line is electrically connected to a column of the sub-pixels; each of the gate control circuits is electrically connected to three data lines, and the colors of the sub-pixels electrically connected to the three data lines are all Not the same.
  • the plurality of sub-pixels of different colors include first-color sub-pixels arranged in sequence along the row direction of the sub-pixels. Pixels (for example, R sub-pixels), second-color sub-pixels (for example, G sub-pixels), and third-color sub-pixels (for example, B sub-pixels). These multiple sub-pixels of different colors (such as R sub-pixels, G and B) are arranged in an array.
  • each column of sub-pixels is the same, starting from the left in Figure 4, the first column of sub-pixels are R sub-pixels, the second column of sub-pixels are G sub-pixels, the third column of sub-pixels are B sub-pixels, and the fourth column of sub-pixels
  • the pixels are all R sub-pixels, and so on.
  • the data line D1 is electrically connected to a corresponding column of R sub-pixels.
  • the gate control circuit 100-1 is electrically connected to the data lines D1, D3, and D5, and the precharge control circuit 200-1 corresponding to the gate control circuit 100-1 is electrically connected to the same data lines D1, D3, and D5.
  • the colors of the sub-pixel columns electrically connected to the data lines D1, D3, and D5 are all different.
  • the data line D1 is electrically connected to the R sub-pixel column
  • the data line D3 is electrically connected to the B sub-pixel column
  • the data line D5 is electrically connected to the G sub-pixel column.
  • two adjacent pixel units are used as a unit group, and the pixel units in different unit groups are different;
  • the group corresponds to the two gate control circuits, and the three data lines electrically connected to the two gate control circuits are alternately arranged along the row direction.
  • the sub-pixels in the first column to the third column are one pixel unit
  • the sub-pixels in the fourth column to the sixth column are another pixel unit.
  • the sub-pixels in the first column to the sixth column are a unit group
  • the unit group corresponds to the gate control circuits 100-1 and 100-2.
  • the data lines D1, D3, D5 electrically connected to the gate control circuit 100-1 and the data lines D2, D4, D6 electrically connected to the gate control circuit 100-2 are alternately arranged along the row direction.
  • the above-mentioned display panel provided by the embodiment of the present disclosure may be a liquid crystal display panel or an organic light emitting display panel, which is not limited herein.
  • the above-mentioned display panel provided by the embodiment of the present disclosure takes a liquid crystal display panel as an example, and the display panel also includes data lines (for example, data lines D1, D2, D3... ) Vertically crossing gate lines (for example, gate lines G1, G2, G3).
  • the gate lines G1, G2, G3... and the data lines D1, D2, D3... define a plurality of sub-pixels, and each sub-pixel includes a third switching transistor T3 and a storage capacitor Cst.
  • the structure of the sub-pixel may be basically the same as the structure in the related art.
  • the embodiments of the present disclosure are merely illustrative and will not be elaborated herein.
  • all the first switching transistors T1 and the second switching transistors T2 may be N-type transistors.
  • all the first switching transistors T1 and the second switching transistors T2 may also be P-type transistors.
  • the N-type transistor is turned on under the action of a high potential, and is turned off under the action of a low potential;
  • the P-type transistor is turned off under the action of a high potential, and is turned on under the action of a low potential.
  • the switching transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT, Thin Film Transistor), or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor), which is not limited here. .
  • TFT Thin Film Transistor
  • MOS Metal Oxide Scmiconductor
  • the functions of the first pole and the second pole of these switching transistors can be interchanged according to the transistor type and the input signal, and no specific distinction is made here.
  • the first electrode of the switching transistor mentioned in the above embodiments of the present disclosure may be a source and the second electrode may be a drain, or the first electrode may be a drain and the second electrode may be a source, and no specific distinction is made here. .
  • the pixel charging principle of the display panel shown in FIG. 4 of the embodiment of the present disclosure is described in detail below through specific embodiments.
  • the corresponding circuit control timing diagram is shown in FIG. 5, and all the first switch transistors T1 and the second switch in FIG.
  • the transistor T2 is an N-type transistor.
  • FIG. 5 is a circuit control timing diagram corresponding to FIG. 4.
  • the timing shown in FIG. 5 of the present disclosure is compared with the conventional scheme. (I.e., the duration of the signal transmitted on the gate line at high level) remains unchanged, and the turn-on time of each gate control circuit is changed.
  • the duration t2 of the signal transmitted on the first control signal line MUXG is at high level and the first The time period t3 during which the signal transmitted on the control signal line MUXB is at a high level is approximately the same, and the time period t2 during which the signal transmitted on the first control signal line MUXG is at a high level is less than that of the signal transmitted on the first control signal line MUXR.
  • the duration of the level t1, that is, t2 t3 ⁇ t1.
  • Fig. 4 is an example of a 1:3-MUX display panel product.
  • the present disclosure adds a precharge control circuit 200-k corresponding to the gate control circuit 100-k one-to-one.
  • the second control signal lines Pre_R, Pre_G, Pre_B, and the precharge signal lines S_od and S_ev, the other parts have not been changed. Therefore, this design can work in either a precharge mode (Precharge mode) or a normal mode without precharge (Normal mode).
  • Normal mode Consistent with the working state of the display panel shown in Figure 1, without additional pixel charging time. If you want to work in Normal mode, you only need to disconnect each second switch transistor T2 in the precharge control circuit 200-k from the corresponding electrically connected data line, that is, the second control signal lines Pre_R, Pre_G, and Pre_B are kept low.
  • the other parts of the circuit are the same as those in the display panel shown in Figure 1. That is, when the frame to be displayed is displayed, the data driving circuit 300 controls the first control signal line to switch and control the first switching transistor T1 to turn on, that is, the data driving circuit 300, the source input terminals Q-1, Q-2, and the first The switching transistor T, the data lines D1, D2, D3... and the sub-pixels form a data voltage transmission channel, and then the data driving circuit 300 outputs the data voltage to the data line of the corresponding column through the corresponding signal output pin OP-k, thereby The data voltage is output to the corresponding sub-pixel.
  • Figure 5 is the circuit control timing diagram corresponding to Figure 4. Taking the scanning of the gate line G1 of the first row, the gate control circuit 100-1 and the precharge control circuit 200-1 as an example, the corresponding data lines D1, D3, and D5, in the scanning period of the gate line G1 of the first row, When the data voltage is applied to the R sub-pixel electrically connected to the data line D1, the first control signal line MUXR is a high-level signal, the first switching transistor T1 electrically connected to the data line D1 is turned on, and the data driving circuit 300 passes through the first switching transistor T1 loads the data voltage on the data line D1.
  • the second control signal line Pre_R is always a low level signal
  • the second switching transistor T2 electrically connected to the data line D1 is turned off
  • the second control signal lines Pre_B and Pre_G are both high level Signal
  • the second switch transistor T2 electrically connected to the data line D3 and the data line D5 is both turned on
  • the precharge signal line S_od applies the precharge voltage to the data line D3 and the data line D5.
  • the data driving circuit 300 sequentially applies the data voltage to the data line D3 and the data line D5.
  • the second control signal lines Pre_B and Pre_G are both low-level signals.
  • the line D3 and the data line D5 are disconnected from the second switching transistor T2. The rest is the same, and so on, so I won't repeat it here.
  • the present disclosure adopts a special control sequence to increase the proportion of the turn-on time of the first control signal line MUXR that is turned on first in the scanning period of a row of gate lines (if the first control signal line MUXG or the first control signal line MUXB For the first turn-on, the turn-on time ratio of the first control signal line MUXG or the first control signal line MUXB can be increased).
  • the present disclosure takes the first control signal line MUXR as the first to turn on as an example, so as to increase the gate drive circuit 300 to control the data line controlled by the first control signal line MUXR and the corresponding R sub-pixels (from the left side of the display panel).
  • S_od provides an L127 gray-scale voltage signal that is consistent with the polarity of the odd-numbered column data line controlled by the data driving circuit 300
  • S_ev provides the L127 gray-scale voltage that is consistent with the polarity of the even-numbered column data line controlled by the data driving circuit 300 Signal (it can also be other gray-scale voltage, L127 is preferred).
  • S_od and S_ev are the G sub-pixel, the corresponding data line and the B sub-pixel, and the corresponding data line is precharged with the L127 voltage of the same polarity.
  • the data driving circuit 300 sequentially charges the data line electrically connected to the G sub-pixel and the data line electrically connected to the B sub-pixel. Since the G sub-pixel and B sub-pixel have been precharged with the voltage of L127, the data driver IC can charge the G sub-pixel and B sub-pixel to the highest potential L255 or discharge to the lowest potential L0 within a short MUXG and MUXB turn-on time, or It is any gray scale between L0 and L255.
  • Fig. 6A to Fig. 6C show that the R, G, and B sub-pixels are charged from 0 gray scale voltage to 255 gray scale voltage, Schematic diagram of the pixel charging effect of charging from 127 gray-scale voltage to 255 gray-scale voltage, and discharging from 127 gray-scale voltage to 0 gray-scale voltage.
  • L21-MUX represents the turn-on time of the first control signal line MUXR
  • L1-R represents the charging effect of the R sub-pixel.
  • FIG. 6A L21-MUX represents the turn-on time of the first control signal line MUXR
  • L1-R represents the charging effect of the R sub-pixel.
  • L22-MUX represents the turn-on time of the first control signal line MUXG
  • L22-G represents the charging effect of the G sub-pixel
  • L3-MUX represents the turn-on time of the first control signal line MUXB
  • L3-B represents the charging effect of the B sub-pixel.
  • the above-mentioned display panel provided by the embodiments of the present disclosure can increase the pixel charging time in addition to the pixel charging time provided by the conventional design. Therefore, the above-mentioned driving method of the display panel provided by the embodiments of the present disclosure can not only solve the problem of insufficient pixel charging, but also can require extremely strict pixel charging time for ultra-high resolution, ultra-high frequency, large size, borderless, etc.
  • the technical direction provides solutions.
  • the embodiments of the present disclosure also provide some driving methods of the display panel, including:
  • the gate control circuit sequentially applies a data voltage to each electrically connected data line through the signal loaded from the source input terminal;
  • the data line to which the data voltage is applied for the first time in the scanning period of the gate line is the first data line, and the other data lines are the second data lines;
  • the precharge control circuit loads a precharge voltage on at least one of the second data lines
  • the precharge control circuit loads the precharge voltage on at least one second data line
  • the gate control circuit sequentially loads the second data line with the data voltage during the scanning period of the gate line
  • the second data line has been pre-loaded with the precharge voltage, so it can be added to the pixel charging time provided by the prior art. Increase pixel charging time. Therefore, the above-mentioned driving method of the display panel provided by the embodiments of the present disclosure can not only solve the problem of insufficient charging of the pixels of the existing display products, but also can charge the pixels for ultra-high resolution, ultra-high frequency, large size, borderless, etc. Provide solutions for extremely demanding technical directions.
  • the time period during which the data driving circuit applies the data voltage to the first data line is longer than the time period during which the data voltage is applied to the second data line.
  • the first data line such as the data line D1
  • the second data line such as the data lines D3 and D5
  • the present disclosure sets the data driving circuit to apply the data voltage to the first data line (such as the data line D1) for a time longer than the first data line (such as the data line D1).
  • the duration of the data voltage applied to the second data lines (such as data lines D3 and D5), so that the three data lines controlled by each gate control circuit 100-k through the corresponding first switching transistor T1 are all based on the original pixel charging time On top, additional pixel charging time is added. Therefore, the problem of insufficient pixel charging can be better solved.
  • the duration of applying the data voltage to the second data line is approximately the same.
  • the second data line is loaded
  • the duration of the precharge voltage is the same as the duration of loading the data voltage to the first data line.
  • the working principle of the driving method of the above-mentioned display panel can be referred to the working principle described in the above-mentioned display panel, which will not be repeated here.
  • the above-mentioned features may not be completely the same, and there may be some deviations. Therefore, the same relationship between the above-mentioned features as long as the above-mentioned conditions are substantially satisfied. That is, all belong to the protection scope of the present disclosure.
  • the above-mentioned sameness may be the same as allowed within the allowable error range.
  • the embodiments of the present disclosure also provide some display devices, including the above-mentioned display panel.
  • the display device can be a display panel of any product with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the implementation of the display device can refer to the embodiment of the above-mentioned display panel, and the repetition is not repeated here.
  • Some display panels, driving methods and display devices provided by embodiments of the present disclosure are provided with a precharge control circuit corresponding to the gate control circuit one by one, and each corresponding gate control circuit and precharge control circuit It is electrically connected to the same preset number of data lines.
  • the gate control circuit loads the data voltage on the first data line during the scanning period of the gate line
  • the precharge control circuit loads the precharge voltage on at least one second data line
  • the election When the pass control circuit sequentially loads the second data line with the data voltage during the scanning period of the gate line, the second data line has been pre-loaded with the pre-charge voltage, so the pixel charging time can be added to the original pixel charging time.
  • the above-mentioned display panel provided by the embodiments of the present disclosure can not only solve the problem of insufficient pixel charging, but also can be a technical direction for ultra-high resolution, ultra-high frequency, large size, borderless, etc., which requires extremely strict pixel charging time. provide the solution.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板、其驱动方法及显示装置，包括：衬底基板；多条数据线（D），多个源极输入端，多个选通控制电路（100），多个预充电控制电路（200）；其中，选通控制电路（100）被配置为在各栅线的扫描时间段，通过源极输入端加载的信号依次对电连接的各条数据线加载数据电压；其中，在栅线的扫描时间段内首次加载数据电压的数据线为第一数据线，其他数据线为第二数据线；预充电控制电路（200）被配置为在对应的选通控制电路（100）对第一数据线加载数据电压的同时，向至少一条第二数据线加载预充电电压。

Description

显示面板、其驱动方法及显示装置
相关申请的交叉引用
本申请要求在2019年06月04日提交中国专利局、申请号为201910480911.1、申请名称为“一种显示面板、其驱动方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及显示面板、其驱动方法及显示装置。
背景技术
显示器中数据驱动芯片通过数据线向像素单元输出像素电压。由于显示器中数据线数量较多，相应地，数据驱动芯片需要较多的引脚，这样向每一数据线传输数据信号的数据传输线也相应较多，不利于实现显示器的窄边框。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板；
多条数据线，设置于所述衬底基板的显示区中；
多个源极输入端，设置于所述衬底基板的非显示区中；
多个选通控制电路，设置于所述衬底基板的非显示区中；所述多个选通控制电路中的一个与所述多个源极输入端中的一个对应电连接，且所述多个选通控制电路中的一个分别与所述多条数据线中的至少三条电连接；
多个预充电控制电路，设置于所述衬底基板的非显示区中；所述多个预充电控制电路中的一个与所述多个选通控制电路中的一个对应设置，以及，所述多个预充电控制电路中的一个分别与所述多条数据线中的至少三条电连接，且所述预充电控制电路电连接的数据线与对应的所述选通控制电路电连 接的数据线相同；
其中，所述选通控制电路被配置为在各栅线的扫描时间段，通过所述源极输入端加载的信号依次对电连接的各条数据线加载数据电压；其中，在所述栅线的扫描时间段内首次加载所述数据电压的数据线为第一数据线，其他数据线为第二数据线；
所述预充电控制电路被配置为在对应的所述选通控制电路对所述第一数据线加载数据电压的同时，向至少一条所述第二数据线加载预充电电压。
可选地，在本公开实施例中，所述预充电控制电路被配置为在所述选通控制电路对所述第一数据线加载数据电压的同时，向其他所有所述第二数据线均加载预充电电压。
可选地，在本公开实施例中，还包括：位于所述非显示区中的多条第一控制信号线；所述选通控制电路包括：多个第一开关晶体管；其中，一个所述第一开关晶体管与一条所述数据线对应设置；
同一所述选通控制电路中，各所述第一开关晶体管的栅极与不同的所述第一控制信号线电连接，各所述第一开关晶体管的第一极与对应的所述数据线电连接，各所述第一开关晶体管的第二极与同一所述源极输入端电连接。
可选地，在本公开实施例中，还包括：位于所述显示区中的多条第二控制信号线和预充电信号线；
所述预充电控制电路包括：多个第二开关晶体管；其中，一个开关晶体管与一条所述数据线对应设置；
同一所述预充电控制电路中，各所述第二开关晶体管的栅极与不同的所述第二控制信号线电连接，各所述第二开关晶体管的第一极与对应的所述数据线电连接，各所述第二开关晶体管的第二极与所述预充电信号线电连接。
可选地，在本公开实施例中，所述第一控制信号线的数量与所述第二控制信号线的数量相同。
可选地，在本公开实施例中，所述预充电信号线包括两条子预充电信号线，相邻两条所述数据线通过对应的所述第二开关晶体管与不同的所述子预 充电信号线电连接。
可选地，在本公开实施例中，还包括多个像素单元，所述像素单元包括多个不同颜色的子像素；其中，同一列所述子像素的颜色相同，一条所述数据线与一列所述子像素电连接；
每一所述选通控制电路与三条数据线电连接，且所述三条数据线电连接的子像素的颜色均不相同。
可选地，在本公开实施例中，所述多个不同颜色的子像素包括沿所述子像素的行方向依次排列的第一颜色子像素、第二颜色子像素以及第三颜色子像素；
以相邻的两个像素单元为一个单元组，且不同单元组中的像素单元不同；
一个单元组对应两个所述选通控制电路，且所述两个所述选通控制电路电连接的三条数据线沿所述行方向交替排列。
可选地，在本公开实施例中，所述显示面板还包括：
数据驱动电路，包括多个信号输出引脚；其中，一个所述源极输入端电连接一个所述信号输出引脚；
所述数据驱动电路被配置为在各所述栅线的扫描时间段，通过各所述信号输出引脚对电连接的源极输入端加载数据电压。
本公开实施例还提供了显示装置，包括上述显示面板。
本公开实施例还提供了显示面板的驱动方法，包括：
选通控制电路在各栅线的扫描时间段，通过所述源极输入端加载的信号依次对电连接的各条数据线加载数据电压；其中，在所述栅线的扫描时间段内首次加载所述数据电压的数据线为第一数据线，其他数据线为第二数据线；并且，在所述选通控制电路对所述第一数据线加载数据电压的同时，所述预充电控制电路向至少一条所述第二数据线加载预充电电压；以及，在所述选通控制电路对所述第二数据线加载数据电压时，断开所述预充电控制电路与所述数据线之间的电连接。
可选地，在本公开实施例中，向所述第一数据线加载数据电压的时长大 于向所述第二数据线加载数据电压的时长。
可选地，在本公开实施例中，向所述第二数据线加载数据电压的时长大致相同。
可选地，在本公开实施例中，向所述第二数据线加载预充电电压的时长与向所述第一数据线加载数据电压的时长相同。
附图说明
图1为相关技术中显示面板的结构示意图；
图2为图1对应的时序图；
图3A-图3C为相关技术中显示面板的像素充电效果示意图；
图4为本公开实施例提供的显示面板的结构示意图；
图5为图4对应的显示面板的时序结构示意图；
图6A-图6C为本公开实施例提供的显示面板的像素充电效果示意图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的显示面板、其驱动方法及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅被配置为说明和解释本公开，并不被配置为限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
为了实现全面屏，通过减少数据传输线的数量，相关技术中在数据驱动芯片和数据线之间设置选通控制电路(Multiplexer，MUX)。例如，数据驱动芯片可以通过MUX连接三个RGB子像素(可称为1:3-MUX方案)，以及数据驱动芯片可以通过MUX连接六个RGB子像素(可称为1:6-MUX方案)等，这样可以大大减少数据传输线的数量，降低数据驱动芯片的尺寸，减少显示器边框的尺寸。
但是在上述1:3-MUX和1:6-MUX方案中，1:3-MUX设计下像素充电时 间减少为子像素在栅线控制下的开启时间的1/3，而1:6-MUX设计下像素充电时间减少为子像素在栅线控制下的开启时间的1/6。由于屏幕尺寸以及分辨率的增加，使得显示面板本身的RC Loading增加。另外MUX的增多，MUX的开启时间缩短，极大减少了子像素的充电时间，导致子像素充电不足。并且，1:n-MUX方案设计中n越大，充电不足问题越严重，比如通常会存在严重的充电不足问题，影响显示面板的显示品质。
如图1所示，图1为相关技术中显示面板的结构示意图，该显示面板采用1:3-MUX方案对像素充电。图1中采用标号mux-r、mux-g和mux-b表示不同颜色子像素列对应的3条控制信号线。显示面板包括：多条栅线G1～G1920、控制信号线mux-r、mux-g和mux-b，与数据线(D1、D2、D3……)一一对应的第一开关晶体管T1，数据驱动IC(Integrated circuit，集成电路)01通过数据传输线(图1中采用标号S1、S2……表示不同的数据传输线)与对应的第一开关晶体管T1的第一极电连接，第一开关晶体管T1的栅极与对应的控制信号线电连接，第一开关晶体管T1的第二极通过数据线(D1、D2、D3……)的第一端与多列子像素电连接；数据传输线(S1、S2……)的数量与数据线(D1、D2、D3……)的数量之比为1:3，且相邻两条数据线接收不同数据传输线传输的数据电压。这样，在显示待显示帧画面时，数据驱动IC01控制这些控制信号线mux-r、mux-g和mux-b进行切换，以控制第一开关晶体管T1导通，即数据驱动IC01、数据传输线S1、S2、第一开关晶体管T1、数据线(D1、D2、D3……)与子像素之间形成数据电压传输通道，然后数据驱动IC01通过数据传输线向对应列的数据线输出数据电压，从而使数据电压输出到对应的子像素中。
图1所示的显示面板，将数据传输线(S1、S2……)的数量缩减为数据线(D1、D2、D3……)数量的1/3，即一个数据传输线分时给由控制信号线mux-r、mux-g和mux-b控制的3条数据线对应的R子像素、G、B充电，其充电控制时序如图2所示。控制信号线mux-r、mux-g和mux-b按顺序依次循环开启，三者开启时间相等，且三者开启时间之和为一个栅线的开启时间， 即栅线G1至栅线G1920中每一个栅线的开启时间被控制信号线mux-r、mux-g和mux-b的开启时间均分。当栅线与第一晶体管T1同时打开时，数据传输线上加载的信号才会对子像素充电。比如栅线G1与控制信号线mux-r同时打开时，数据传输线S1仅对显示面板左侧第1条数据线D1和R子像素充电。栅线G1与控制信号线mux-g同时打开时，数据传输线S1仅对显示面板左侧第5条数据线D5和G子像素充电。栅线G1与控制信号线mux-b同时打开时，数据传输线S1仅对显示面板左侧第3条数据线D3和B子像素充电。
这种1:3-MUX方案设计可以很好的将数据传输线(S1、S2……)的数量缩减为数据线(D1、D2、D3……)数量的1/3，极大的减小数据驱动IC01的数量、尺寸以及显示面板的扇出区的尺寸。但是1:3-MUX方案设计不可避免的将子像素的充电时间，降低为栅线开启时间的1/3。以液晶显示面板为例，极大减少了液晶电容的充电时间，导致液晶电容充电不足。如图3A至图3C所示，图3A至图3C分别为R、G和B子像素对应的从0灰阶电压充电至255灰阶电压的像素充电效果示意图。其中，图3A中，L1-MUX代表控制信号线的开启时间，L1-R代表R子像素的充电效果。图3B中，L2-MUX代表控制信号线的开启时间，L2-G代表G子像素的充电效果。图3C中，L3-MUX代表控制信号线的开启时间，L3-B代表B子像素的充电效果。从图3A至图3C中，可以看出在控制信号线的开启时间内，R子像素、G和B出现充电不足。而且1:n-MUX方案设计中n越大，充电不足问题越严重，比如1:6-MUX方案设计下，像素充电时间减少为栅线开启时间的1/6，通常会存在严重的充电不足问题。
有鉴于此，本公开实施例提供了一些显示面板，如图4所示，包括：衬底基板1000、多条数据线(D1、D2、D3……)，多个选通控制电路100-k(1≤k≤K，且k与K均为整数，K为选通控制电路的总数，图4以K＝2为例)，多个预充电控制电路200-k和多个源极输入端Q-k；其中，多条数据线(D1、D2、D3……)设置于所述衬底基板的显示区中。多个源极输入端Q-k设置于所述衬底基板的非显示区中。多个选通控制电路100-k设置于所述衬底基板的 非显示区中。多个预充电控制电路200-k设置于所述衬底基板的非显示区中。
并且，多个选通控制电路100-k中的一个与所述多个源极输入端Q-k中的一个对应电连接，且所述多个选通控制电路100-k中的一个分别与所述多条数据线中的至少三条电连接。所述多个预充电控制电路200-k中的一个与所述多个选通控制电路100-k中的一个对应设置，以及，所述多个预充电控制电路200-k中的一个分别与所述多条数据线中的至少三条电连接，且所述预充电控制电路200-k电连接的数据线与对应的所述选通控制电路100-k电连接的数据线相同。
其中，所述选通控制电路100-k被配置为在各栅线的扫描时间段，通过所述源极输入端加载的信号依次对电连接的各条数据线加载数据电压；其中，在所述栅线的扫描时间段内首次加载所述数据电压的数据线为第一数据线，其他数据线为第二数据线；
所述预充电控制电路200-k被配置为在对应的所述选通控制电路对所述第一数据线加载数据电压的同时，向至少一条所述第二数据线加载预充电电压。
本公开实施例提供的显示面板，通过设置与选通控制电路一一对应的预充电控制电路，且每一对应的选通控制电路和预充电控制电路与相同的数据线电连接。当选通控制电路在栅线的扫描时间段，对第一数据线加载数据电压的同时，预充电控制电路向第二数据线加载预充电电压，当选通控制电路在栅线的扫描时间段依次对第二数据线加载数据电压时，由于第二数据线已经预先加载了预充电电压，因此可以在像素充电时间的基础上，额外增加像素充电时间。因此，本公开实施例提供的上述显示面板，不仅可以解决像素充电不足的问题，而且还可以为超高分辨率、超高频、大尺寸、无边框等对像素充电时间要求极为严苛的技术方向提供解决方案。
示例性地，如图4所示，选通控制电路100-1与预充电控制电路200-1一一对应，选通控制电路100-2与预充电控制电路200-2一一对应，每一选通控制电路100-k分别与三条数据线电连接，每一预充电控制电路200-k与相对应 的选通控制电路100-k电连接相同的数据线。例如，选通控制电路100-1与三条数据线(D1、D3和D5)和源极输入端Q1电连接，与选通控制电路100-1对应的预充电控制电路200-1与相同的三条数据线(D1、D3和D5)电连接。选通控制电路100-2与三条数据线(D2、D4和D6)和源极输入端Q2电连接，与选通控制电路100-2对应的预充电控制电路200-2与相同的三条数据线(D2、D4和D6)电连接。
其中，选通控制电路100-1被配置为在各栅线的扫描时间段，通过源极输入端Q-1加载的信号依次对电连接的各条数据线(D1、D3和D5)加载数据电压。通控制电路100-2被配置为在各栅线的扫描时间段，通过源极输入端Q-2加载的信号依次对电连接的各条数据线(D2、D4和D6)加载数据电压。并且，在栅线的扫描时间段首次加载数据电压的数据线为第一数据线，如数据线D1和D4为第一数据线，其他数据线为第二数据线，如数据线D2、D3、D5和D6为第二数据线；
预充电控制电路200-k被配置为在选通控制电路100-k对第一数据线(例如数据线D1)加载数据电压的同时，向至少一条第二数据线加载预充电电压，如向数据线D3加载预充电电压，或向数据线D5加载预充电电压，或同时向数据线D3和D5加载预充电电压。
本公开实施例提供的显示面板，通过设置与选通控制电路一一对应的预充电控制电路，且每一对应的选通控制电路和预充电控制电路与相同预设数量的数据线电连接，当选通控制电路在栅线的扫描时间段对第一数据线加载数据电压的同时，预充电控制电路向至少一条第二数据线加载预充电电压，当选通控制电路在栅线的扫描时间段依次对第二数据线加载数据电压时，第二数据线由于已经预先加载了预充电电压，因此可以在栅线扫描时间中原像素充电时间基础上，额外增加像素充电时间。因此，本公开实施例提供的上述显示面板不仅可以解决现有显示产品像素充电不足的问题，而且还可以为超高分辨率、超高频、大尺寸、无边框等对像素充电时间要求极为严苛的技术方向提供解决方案。
进一步地，在具体实施时，为了能够使显示面板中所有第二数据线均在原像素充电时间基础上，额外增加像素充电时间，本公开实施例提供的上述显示面板中，如图4所示，预充电控制电路200-k被配置为在选通控制电路100-k对第一数据线(例如，数据线D1和D4)加载数据电压的同时，向其他所有第二数据线(例如，数据线D2、D3、D5和D6)均加载预充电电压。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，还包括：位于所述非显示区中的多条第一控制信号线(例如，MUXR、MUXG、MUXB)、多条第二控制信号线(例如，Pre_R、Pre_G、Pre_B)和预充电信号线(例如，S_od(+)，S_ev(-))；每一选通控制电路100-k包括：多个第一开关晶体管T1；其中，一个所述第一开关晶体管与一条所述数据线对应设置。例如，与各数据线D1、D3和D5一一对应的第一开关晶体管T1。同一选通控制电路100-k中，各第一开关晶体管T1的栅极与不同的第一控制信号线电连接，如与数据线D1电连接的第一开关晶体管T1的栅极与第一控制信号线MUXR电连接，如与数据线D3电连接的第一开关晶体管T1的栅极与第一控制信号线MUXB电连接，如与数据线D5电连接的第一开关晶体管T1的栅极与第一控制信号线MUXG电连接。各第一开关晶体管T1的第一极与对应的数据线(例如，数据线D1、D3、D5)电连接，各第一开关晶体管T1的第二极与同一源极输入端(例如，源极输入端Q-1、Q-2)电连接。
并且，预充电控制电路200包括：多个第二开关晶体管T2；其中，一个开关晶体管与一条所述数据线对应设置。例如，与各数据线D1、D3和D5一一对应的第二开关晶体管T2。第二开关晶体管T2的栅极与不同的第二控制信号线电连接，如与数据线D1电连接的第二开关晶体管T2的栅极与第二控制信号线Pre_R电连接，如与数据线D3电连接的第二开关晶体管T2的栅极与第二控制信号线Pre_B电连接，如与数据线D5电连接的第二开关晶体管T2的栅极与第二控制信号线Pre_G电连接。各第二开关晶体管T2的第一极与对应的数据线(例如，数据线D1、D3、D5)电连接，各第二开关晶体管T2的第二极与预充电信号线电连接。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，所述第一控制信号线的数量与所述第二控制信号线的数量相同。例如，可以设置3条第一控制信号线，即第一控制信号线MUXR、MUXG、MUXB。以及设置3条第二控制信号线，即第二控制信号线Pre_R、Pre_G、Pre_B。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，预充电信号线包括两条子预充电信号线S_od和S_ev，相邻两条数据线通过对应的第二开关晶体管与不同的子预充电信号线电连接。例如奇数列的数据线(例如，数据线D1、D3、D5、D7……)对应的第二开关晶体管T2连接到子预充电信号线S_od，偶数列的数据线(例如，数据线D2、D4、D6、D8……)对应的第二开关晶体管T2连接到子预充电信号线S_ev。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，所述显示面板还包括：数据驱动电路，包括多个信号输出引脚OP-k；其中，一个所述源极输入端Q-k电连接一个所述信号输出引脚OP-k。并且，所述数据驱动电路被配置为在各所述栅线的扫描时间段，通过各所述信号输出引脚对电连接的源极输入端加载数据电压。示例性地，源极输入端Q-k与数据驱动电路300中的信号输出引脚OP-k一一对应电连接。示例性地，源极输入端Q-k与信号输出引脚OP-k可以采用邦定工艺进行电连接。示例性地，数据驱动电路可以为数据驱动IC。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，子预充电信号线S_od的电压极性需与数据驱动电路300的信号输出引脚OP-1输出的电压的极性保持一致，S_ev的电压极性需与数据驱动电路300的信号输出引脚OP-2输出的电压的极性保持一致，且随着帧切换一起进行极性切换，并非固定的正负极性。如图4所示，子预充电信号线S_od和S_ev的电压极性相反，并且，奇数列的数据线D1、D3、D5、D7……通过对应的第二开关晶体管T2连接到子预充电信号线S_od，偶数列的数据线D2、D4、D6、D8……通过对应的第二开关晶体管T2连接到子预充电信号线S_ev，即相邻两列子像素充极性相反的电压。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，从左侧的第一个第二开关晶体管T2起，第二控制信号线Pre_R、Pre_G和Pre_B依次连接第二开关晶体管T2的栅极。第二控制信号线Pre_R控制与R子像素电连接的数据线(即数据线D1、D4、D7、……)，第二控制信号线Pre_G控制与G子像素电连接的数据线(即数据线D2、D5、D8、……)，第二控制信号线Pre_B控制与B子像素电连接的数据线(即数据线D3、D6、D9、……)。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，还包括多个像素单元，所述像素单元包括多个不同颜色的子像素；其中，同一列所述子像素的颜色相同，一条所述数据线与一列所述子像素电连接；每一所述选通控制电路与三条数据线电连接，且所述三条数据线电连接的子像素的颜色均不相同。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，所述多个不同颜色的子像素包括沿所述子像素的行方向依次排列的第一颜色子像素(例如R子像素)、第二颜色子像素(例如G子像素)以及第三颜色子像素(例如B子像素)。这些多个不同颜色的子像素(如R子像素、G和B)呈阵列排布。每一列子像素的颜色相同，如图4中从左侧开始，第一列子像素均为R子像素，第二列子像素均为G子像素，第三列子像素均为B子像素，第四列子像素均为R子像素，依次类推。示例性地，数据线D1与对应的一列R子像素电连接。并且，选通控制电路100-1与数据线D1、D3和D5电连接，与选通控制电路100-1对应的预充电控制电路200-1与相同的数据线D1、D3和D5电连接。数据线D1、D3和D5电连接的子像素列的颜色均不相同，如数据线D1电连接R子像素列，数据线D3电连接B子像素列，数据线D5电连接G子像素列。
进一步地，在具体实施时，本公开实施例提供的上述显示面板中，如图4所示，以相邻的两个像素单元为一个单元组，且不同单元组中的像素单元不同；一个单元组对应两个所述选通控制电路，且所述两个所述选通控制电路 电连接的三条数据线沿所述行方向交替排列。例如，第一列子像素至第三列子像素为一个像素单元，第四列子像素至第六列子像素为另一个像素单元。第一列子像素至第六列子像素为一个单元组，该单元组对应选通控制电路100-1和100-2。选通控制电路100-1电连接的数据线D1、D3、D5与选通控制电路100-2电连接的数据线D2、D4、D6沿所述行方向交替排列。
进一步地，在具体实施时，本公开实施例提供的上述显示面板可以为液晶显示面板，也可以为有机发光显示面板，在此不作限定。
进一步地，在具体实施时，如图4所示，本公开实施例提供的上述显示面板是以液晶显示面板为例，显示面板还包括与数据线(例如，数据线D1、D2、D3……)垂直交叉设置的栅线(例如，栅线G1、G2、G3……)。以显示面板具有1920条栅线为例，栅线G1、G2、G3……和数据线D1、D2、D3……限定出多个子像素，每一个子像素包括第三开关晶体管T3、存储电容Cst和液晶电容Clc，子像素的结构可以与相关技术中的结构基本相同，本公开实施例只是示意性说明，在此不做详细阐述。
进一步地，在具体实施时，在本公开实施例提供的显示面板中，如图4所示，所有第一开关晶体管T1和第二开关晶体管T2可以均为N型晶体管。
当然，在具体实施时，在本公开实施例提供的上述显示面板中，所有第一开关晶体管T1和第二开关晶体管T2也可以均为P型晶体管。
进一步地，在具体实施时，N型晶体管在高电位作用下导通，在低电位作用下截止；P型晶体管在高电位作用下截止，在低电位作用下导通。
需要说明的是本公开上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不做限定。在具体实施中，这些开关晶体管的第一极和第二极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。具体地，本公开上述实施例中提到的开关晶体管的第一极可以为源极，第二极为漏极，或者第一极可以为漏极，第二极为源极，在此不做具体区分。
下面通过具体的实施例对本公开实施例图4所示的显示面板的像素充电原理进行详细说明，对应的电路控制时序图如图5所示，图4中所有第一开关晶体管T1和第二开关晶体管T2均为N型晶体管。
本公开实施例提供的上述显示面板中，如图5所示，图5为图4对应的电路控制时序图，本公开图5所示的时序与传统方案比，栅线的扫描时间段的时长(即栅线上传输的信号为高电平的时长)保持不变，变更各选通控制电路开启时间，例如使第一控制信号线MUXG上传输的信号为高电平的时长t2与第一控制信号线MUXB上传输的信号为高电平的时长t3大致相同，且使第一控制信号线MUXG上传输的信号为高电平的时长t2小于第一控制信号线MUXR上传输的信号为高电平的时长t1，即t2＝t3<t1。以及，同一栅线的扫描时间段内，栅线的扫描时间段的时长t0为第一控制信号线MUXR、MUXG以及MUXB上传输的信号为高电平的时长之和，即t0＝t1+t2+t3。
图4是以1:3-MUX的显示面板产品为例，与图1所示的显示面板相比，本公开增加了与选通控制电路100-k一一对应的预充电控制电路200-k、第二控制信号线Pre_R、Pre_G、Pre_B、以及预充电信号线S_od和S_ev，其它部分未做变更。因此本设计既可以工作在有预充电的模式(Precharge mode)，也可以工作在不进行预充电的常规模式(Normal mode)。
Normal mode：和图1所示的显示面板的工作状态一致，不会额外增加像素的充电时间。若要工作在Normal mode，只需要将预充电控制电路200-k中的各第二开关晶体管T2与对应电连接的数据线断开接口，即第二控制信号线Pre_R、Pre_G、Pre_B保持低电平，其它部分电路与图1所示的显示面板中的保持一致。即在显示待显示帧画面时，数据驱动电路300控制第一控制信号线进行切换控制第一开关晶体管T1导通，即数据驱动电路300、源极输入端Q-1、Q-2、第一开关晶体管T、数据线D1、D2、D3……与子像素之间形成数据电压传输通道，然后数据驱动电路300通过对应的信号输出引脚OP-k向对应列的数据线输出数据电压，从而使数据电压输出到对应的子像素中。
Precharge mode：如图4和图5所示，图5为图4对应的电路控制时序图。 以扫描第一行栅线G1以及选通控制电路100-1以及预充电控制电路200-1为例，对应的数据线D1、D3和D5，在第一行栅线G1的扫描时间段，在对数据线D1电连接的R子像素加载数据电压时，第一控制信号线MUXR为高电平信号，数据线D1电连接的第一开关晶体管T1导通，数据驱动电路300通过第一开关晶体管T1对数据线D1加载数据电压.并且，第二控制信号线Pre_R一直为低电平信号，数据线D1电连接的第二开关晶体管T2截止，第二控制信号线Pre_B和Pre_G均为高电平信号，数据线D3和数据线D5电连接的第二开关晶体管T2均导通，预充电信号线S_od对数据线D3和数据线D5加载预充电电压，在数据线D1加载数据电压结束时，也即对数据线D3和数据线D5预充电完成时，在数据驱动电路300依次对数据线D3和数据线D5加载数据电压时间内，第二控制信号线Pre_B和Pre_G为均低电平信号，数据线D3和数据线D5与第二开关晶体管T2断开。其余同理，以此类推，在此不作赘述。
本公开采用特殊的控制时序，将一行栅线的扫描时间段中第一个开启的第一控制信号线MUXR的开启时间占比加大(若第一控制信号线MUXG或第一控制信号线MUXB为第一个开启，可将第一控制信号线MUXG或第一控制信号线MUXB的开启时间占比加大)。本公开以第一控制信号线MUXR为第一个开启为例进行说明，以便增加栅极驱动电路300对由第一控制信号线MUXR控制的数据线和对应的R子像素(显示面板左侧起第1、4、7、……列数据线和子像素)的充电时间，保证R子像素充电时间加长。R子像素充电的同时，Pre_G和Pre_B保持与MUXR同步开启、Pre_R一直保持低电平，Pre_G控制的数据线和对应的G子像素(显示面板左侧起第2、5、8、……列数据线和子像素)与Pre_B控制的数据线和对应的B子像素(显示面板左侧起第3、6、9、……列数据线和子像素)中的奇数列数据线连接到S_od、偶数列数据线连接到S_ev，S_od提供与数据驱动电路300控制的奇数列数据线极性一致的L127灰阶电压信号、S_ev提供与数据驱动电路300控制的偶数列数据线极性一致的L127灰阶电压信号(也可以为其它灰阶电压，优先采用 L127)。从而达到在数据驱动电路300为R子像素和对应的数据线充电的同时S_od、S_ev为G子像素、对应的数据线和B子像素、对应的数据线预充相同极性的L127电压。
当预充电完成后，在第一控制信号线MUXG和MUXB的开启阶段，第二控制信号线Pre_R、Pre_G和Pre_B均保持低电平，关闭各第二开关晶体管T2与数据线的电连接，由数据驱动电路300依次对G子像素电连接的数据线和B子像素电连接的数据线充电。由于G子像素和B子像素已经预充L127电压，所以数据驱动IC可以在较短的MUXG、MUXB开启时间内将G子像素和B子像素充电到最高电位L255或放电到最低电位L0，或者是L0～L255之间的任意灰阶，其充电效果示意图如图6A至图6C所示，图6A至图6C分别为R、G和B子像素从0灰阶电压充电至255灰阶电压、从127灰阶电压充电至255灰阶电压、从127灰阶电压放电至0灰阶电压的像素充电效果示意图。其中，图6A中，L21-MUX代表第一控制信号线MUXR的开启时间，L1-R代表R子像素的充电效果。图3B中，L22-MUX代表第一控制信号线MUXG的开启时间，L22-G代表G子像素的充电效果。图3C中，L3-MUX代表第一控制信号线MUXB的开启时间，L3-B代表B子像素的充电效果。从图6A至图6C中，可以看出相比于图3A至图3C所示的充电不足的情况具有明显改善，因此本公开实施例提供的显示面板可以解决像素充电不足的问题。
综上所述，本公开实施例提供的上述显示面板可以在常规设计提供的像素充电时间之上，额外增加像素充电时间。因此，本公开实施例提供的上述显示面板的驱动方法不仅可以解决像素充电不足的问题，而且还可以为超高分辨率、超高频、大尺寸、无边框等对像素充电时间要求极为严苛的技术方向提供解决方案。
基于同一发明构思，本公开实施例还提供了一些的显示面板的驱动方法，包括：
选通控制电路在各栅线的扫描时间段，通过所述源极输入端加载的信号 依次对电连接的各条数据线加载数据电压；
其中，在所述栅线的扫描时间段内首次加载所述数据电压的数据线为第一数据线，其他数据线为第二数据线；
并且，在所述选通控制电路对所述第一数据线加载数据电压的同时，所述预充电控制电路向至少一条所述第二数据线加载预充电电压；
以及，在所述选通控制电路对所述第二数据线加载数据电压时，断开所述预充电控制电路与所述数据线之间的电连接。
本公开实施例提供的显示面板的驱动方法，当选通控制电路在栅线的扫描时间段对第一数据线加载数据电压的同时，预充电控制电路向至少一条第二数据线加载预充电电压，当选通控制电路在栅线的扫描时间段依次对第二数据线加载数据电压时，第二数据线由于已经预先加载了预充电电压，因此可以在现有技术提供的像素充电时间基础上，额外增加像素充电时间。因此，本公开实施例提供的上述显示面板的驱动方法不仅可以解决现有显示产品像素充电不足的问题，而且还可以为超高分辨率、超高频、大尺寸、无边框等对像素充电时间要求极为严苛的技术方向提供解决方案。
进一步地，在具体实施时，在本公开实施例提供的上述显示面板的驱动方法中，数据驱动电路向第一数据线加载数据电压的时长大于向第二数据线加载数据电压的时长。以本公开实施例图4提供的显示面板为例，本公开实施例通过在一行栅线的扫描时间内，在向首次加载数据电压的第一数据线(如数据线D1)加载数据电压时，同时向第二数据线(如数据线D3和D5)加载预充电电压。即在第一数据线(如数据线D1)加载数据电压结束、依次对数据线D3和D5加载数据电压时，断开预充电电路200-1与数据线D3和D5的电连接。由于第二数据线(如数据线D3和D5)已经预先加载了预充电电压，因此本公开通过将数据驱动电路向第一数据线(如数据线D1)加载数据电压的时长设置为大于向第二数据线(如数据线D3和D5)加载数据电压的时长，这样可以实现每一选通控制电路100-k通过对应第一开关晶体管T1控制的三条数据线均在原有的像素充电时间的基础上，额外增加像素充电时间。因此， 能够更好的解决像素充电不足的问题。
进一步地，在具体实施时，在本公开实施例提供的上述显示面板的驱动方法中，向第二数据线加载数据电压的时长大致相同。
进一步地，在具体实施时，为了保证第二数据线对应的子像素能够更好的解决像素充电不足的问题，在本公开实施例提供的上述显示面板的驱动方法中，向第二数据线加载预充电电压的时长与向第一数据线加载数据电压的时长相同。
在具体实施时，上述显示面板的驱动方法的工作原理可以参见上述显示面板中描述的工作原理，在此不做赘述。
需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，上述各特征中的相同并不能完全相同，可能会有一些偏差，因此上述各特征之间的相同关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，上述相同可以是在误差允许范围之内所允许的相同。
基于同一发明构思，本公开实施例还提供了一些显示装置，包括上述的显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品的显示面板。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供的一些显示面板、其驱动方法及显示装置，该显示面板通过设置与选通控制电路一一对应的预充电控制电路，且每一对应的选通控制电路和预充电控制电路与相同预设数量的数据线电连接，当选通控制电路在栅线的扫描时间段对第一数据线加载数据电压的同时，预充电控制电路向至少一条第二数据线加载预充电电压，当选通控制电路在栅线的扫描时间段依次对第二数据线加载数据电压时，第二数据线由于已经预先加载了预充电电压，因此可以在原有的像素充电时间基础上，额外增加像素充电时间。因此，本公开实施例提供的上述显示面板不仅可以解决像素充电不足的问题，而且还可以为超高分辨率、超高频、大尺寸、无边框等对像素充电时间要求极为严苛的技术方向提供解决方案。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种显示面板，其中，包括：
    衬底基板；
    多条数据线，设置于所述衬底基板的显示区中；
    多个源极输入端，设置于所述衬底基板的非显示区中；
    多个选通控制电路，设置于所述衬底基板的非显示区中；所述多个选通控制电路中的一个与所述多个源极输入端中的一个对应电连接，且所述多个选通控制电路中的一个分别与所述多条数据线中的至少三条电连接；
    多个预充电控制电路，设置于所述衬底基板的非显示区中；所述多个预充电控制电路中的一个与所述多个选通控制电路中的一个对应设置，以及，所述多个预充电控制电路中的一个分别与所述多条数据线中的至少三条电连接，且所述预充电控制电路电连接的数据线与对应的所述选通控制电路电连接的数据线相同；
    其中，所述选通控制电路被配置为在各栅线的扫描时间段，通过所述源极输入端加载的信号依次对电连接的各条数据线加载数据电压；其中，在所述栅线的扫描时间段内首次加载所述数据电压的数据线为第一数据线，其他数据线为第二数据线；
    所述预充电控制电路被配置为在对应的所述选通控制电路对所述第一数据线加载数据电压的同时，向至少一条所述第二数据线加载预充电电压。
  2. 如权利要求1所述的显示面板，其中，所述预充电控制电路被配置为在所述选通控制电路对所述第一数据线加载数据电压的同时，向其他所有所述第二数据线均加载预充电电压。
  3. 如权利要求1或2所述的显示面板，其中，还包括：位于所述非显示区中的多条第一控制信号线；所述选通控制电路包括：多个第一开关晶体管；其中，一个所述第一开关晶体管与一条所述数据线对应设置；
    同一所述选通控制电路中，各所述第一开关晶体管的栅极与不同的所述 第一控制信号线电连接，各所述第一开关晶体管的第一极与对应的所述数据线电连接，各所述第一开关晶体管的第二极与同一所述源极输入端电连接。
  4. 如权利要求1-3任一项所述的显示面板，其中，还包括：位于所述显示区中的多条第二控制信号线和预充电信号线；
    所述预充电控制电路包括：多个第二开关晶体管；其中，一个开关晶体管与一条所述数据线对应设置；
    同一所述预充电控制电路中，各所述第二开关晶体管的栅极与不同的所述第二控制信号线电连接，各所述第二开关晶体管的第一极与对应的所述数据线电连接，各所述第二开关晶体管的第二极与所述预充电信号线电连接。
  5. 如权利要求4所述的显示面板，其中，所述第一控制信号线的数量与所述第二控制信号线的数量相同。
  6. 如权利要求4或5所述的显示面板，其中，所述预充电信号线包括两条子预充电信号线，相邻两条所述数据线通过对应的所述第二开关晶体管与不同的所述子预充电信号线电连接。
  7. 如权利要求1-6任一项所述的显示面板，其中，还包括多个像素单元，所述像素单元包括多个不同颜色的子像素；其中，同一列所述子像素的颜色相同，一条所述数据线与一列所述子像素电连接；
    每一所述选通控制电路与三条数据线电连接，且所述三条数据线电连接的子像素的颜色均不相同。
  8. 如权利要求7所述的显示面板，其中，所述多个不同颜色的子像素包括沿所述子像素的行方向依次排列的第一颜色子像素、第二颜色子像素以及第三颜色子像素；
    以相邻的两个像素单元为一个单元组，且不同单元组中的像素单元不同；
    一个单元组对应两个所述选通控制电路，且所述两个所述选通控制电路电连接的三条数据线沿所述行方向交替排列。
  9. 如权利要求1-8任一项所述的显示面板，其中，所述显示面板还包括：
    数据驱动电路，包括多个信号输出引脚；其中，一个所述源极输入端电 连接一个所述信号输出引脚；
    所述数据驱动电路被配置为在各所述栅线的扫描时间段，通过各所述信号输出引脚对电连接的源极输入端加载数据电压。
  10. 一种显示装置，其中，包括如权利要求1-9任一项所述的显示面板。
  11. 一种如权利要求1-9任一项所述的显示面板的驱动方法，其中，包括：
    选通控制电路在各栅线的扫描时间段，通过所述源极输入端加载的信号依次对电连接的各条数据线加载数据电压；其中，在所述栅线的扫描时间段内首次加载所述数据电压的数据线为第一数据线，其他数据线为第二数据线；并且，在所述选通控制电路对所述第一数据线加载数据电压的同时，所述预充电控制电路向至少一条所述第二数据线加载预充电电压；以及，在所述选通控制电路对所述第二数据线加载数据电压时，断开所述预充电控制电路与所述数据线之间的电连接。
  12. 如权利要求11所述的显示面板的驱动方法，其中，向所述第一数据线加载数据电压的时长大于向所述第二数据线加载数据电压的时长。
  13. 如权利要求12所述的显示面板的驱动方法，其中，向所述第二数据线加载数据电压的时长大致相同。
  14. 如权利要求11-13任一项所述的显示面板的驱动方法，其中，向所述第二数据线加载预充电电压的时长与向所述第一数据线加载数据电压的时长相同。
PCT/CN2020/087292 2019-06-04 2020-04-27 显示面板、其驱动方法及显示装置 WO2020244342A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910480911.1A CN110211547A (zh) 2019-06-04 2019-06-04 一种显示面板、其驱动方法及显示装置
CN201910480911.1 2019-06-04

Publications (1)

Publication Number Publication Date
WO2020244342A1 true WO2020244342A1 (zh) 2020-12-10

Family

ID=67790536

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/087292 WO2020244342A1 (zh) 2019-06-04 2020-04-27 显示面板、其驱动方法及显示装置

Country Status (2)

Country Link
CN (1) CN110211547A (zh)
WO (1) WO2020244342A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035891A (zh) * 2021-03-15 2021-06-25 厦门天马微电子有限公司 阵列基板和显示装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110211547A (zh) * 2019-06-04 2019-09-06 京东方科技集团股份有限公司 一种显示面板、其驱动方法及显示装置
CN112863414A (zh) * 2019-11-26 2021-05-28 上海和辉光电有限公司 显示面板及其驱动方法
CN110930889B (zh) * 2019-12-27 2022-07-22 厦门天马微电子有限公司 一种显示面板及其驱动方法、显示装置
TWI793844B (zh) * 2020-11-06 2023-02-21 聯詠科技股份有限公司 驅動顯示面板的方法及其驅動電路
CN112669749A (zh) * 2020-12-28 2021-04-16 合肥维信诺科技有限公司 显示面板及其驱动方法和显示装置
CN114019737B (zh) * 2021-11-15 2023-11-14 合肥京东方光电科技有限公司 一种阵列基板及其驱动方法、显示面板、显示装置
CN115691384B (zh) * 2022-10-21 2024-07-30 厦门天马微电子有限公司 一种显示面板及显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323025A (zh) * 2000-05-09 2001-11-21 夏普公司 数据信号线驱动电路、图象显示装置和电子设备
US20070001989A1 (en) * 2005-06-30 2007-01-04 Yoon Jin M Analog sampling apparatus for liquid crystal display
CN1892316A (zh) * 2005-07-05 2007-01-10 三星电子株式会社 液晶显示装置、驱动该装置的设备以及该装置的驱动方法
US20070279341A1 (en) * 2006-06-05 2007-12-06 Samsung Sdi Co., Ltd. Driving circuit and organic electroluminescence display thereof
JP2009025656A (ja) * 2007-07-20 2009-02-05 Tpo Displays Corp 液晶表示装置の駆動装置
CN103177685A (zh) * 2011-12-26 2013-06-26 乐金显示有限公司 Oled显示装置及感测像素驱动电路的特性参数的方法
CN104252852A (zh) * 2013-06-29 2014-12-31 乐金显示有限公司 用于液晶显示设备的数据驱动装置
CN110211547A (zh) * 2019-06-04 2019-09-06 京东方科技集团股份有限公司 一种显示面板、其驱动方法及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3110980B2 (ja) * 1995-07-18 2000-11-20 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 液晶表示装置の駆動装置及び方法
TWI297484B (en) * 2005-04-01 2008-06-01 Au Optronics Corp Time division driven display and method for driving same
CN1664910A (zh) * 2005-04-11 2005-09-07 友达光电股份有限公司 时间分割驱动的显示器及其驱动方法
KR100666643B1 (ko) * 2005-09-15 2007-01-09 삼성에스디아이 주식회사 유기전계발광표시장치 및 유기전계발광표시장치의 구동방법
JP2007279539A (ja) * 2006-04-11 2007-10-25 Nec Electronics Corp ドライバ回路、表示装置及びその駆動方法
CN101620841A (zh) * 2008-06-30 2010-01-06 恩益禧电子股份有限公司 显示面板驱动方法及显示装置
KR101888431B1 (ko) * 2011-11-15 2018-08-16 엘지디스플레이 주식회사 표시장치 및 그 구동방법
JP2015079138A (ja) * 2013-10-17 2015-04-23 セイコーエプソン株式会社 電気光学装置、電気光学装置の駆動方法及び電子機器
KR102318144B1 (ko) * 2015-05-08 2021-10-28 삼성디스플레이 주식회사 표시 장치 및 그것의 구동 방법
JP2017167426A (ja) * 2016-03-17 2017-09-21 セイコーエプソン株式会社 電気光学装置、及び電子機器
TWI645396B (zh) * 2018-03-07 2018-12-21 友達光電股份有限公司 顯示面板及預充電方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323025A (zh) * 2000-05-09 2001-11-21 夏普公司 数据信号线驱动电路、图象显示装置和电子设备
US20070001989A1 (en) * 2005-06-30 2007-01-04 Yoon Jin M Analog sampling apparatus for liquid crystal display
CN1892316A (zh) * 2005-07-05 2007-01-10 三星电子株式会社 液晶显示装置、驱动该装置的设备以及该装置的驱动方法
US20070279341A1 (en) * 2006-06-05 2007-12-06 Samsung Sdi Co., Ltd. Driving circuit and organic electroluminescence display thereof
JP2009025656A (ja) * 2007-07-20 2009-02-05 Tpo Displays Corp 液晶表示装置の駆動装置
CN103177685A (zh) * 2011-12-26 2013-06-26 乐金显示有限公司 Oled显示装置及感测像素驱动电路的特性参数的方法
CN104252852A (zh) * 2013-06-29 2014-12-31 乐金显示有限公司 用于液晶显示设备的数据驱动装置
CN110211547A (zh) * 2019-06-04 2019-09-06 京东方科技集团股份有限公司 一种显示面板、其驱动方法及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035891A (zh) * 2021-03-15 2021-06-25 厦门天马微电子有限公司 阵列基板和显示装置
CN113035891B (zh) * 2021-03-15 2024-03-15 厦门天马微电子有限公司 阵列基板和显示装置

Also Published As

Publication number Publication date
CN110211547A (zh) 2019-09-06

Similar Documents

Publication Publication Date Title
WO2020244342A1 (zh) 显示面板、其驱动方法及显示装置
US10255840B2 (en) Display panel, driving method for display panel, and display device
CN106019743B (zh) 一种阵列基板、其驱动方法及相关装置
CN107993629B (zh) 液晶显示装置的驱动方法
KR100967745B1 (ko) 표시장치용 구동회로 및 표시장치
US20160322008A1 (en) Display device
KR100561946B1 (ko) 액정표시장치 및 그 구동방법
KR100549983B1 (ko) 액정표시장치 및 그 구동방법
KR20080053600A (ko) 데이터 구동 장치 및 그것을 이용하는 액정 표시 장치
CN108133693B (zh) 显示面板、驱动方法及显示装置
US20170358268A1 (en) Data signal line drive circuit, display device provided with same, and method for driving same
JP3687344B2 (ja) 液晶装置及びその駆動方法、並びにそれを用いた投写型表示装置及び電子機器
JP2007279539A (ja) ドライバ回路、表示装置及びその駆動方法
CN100366048C (zh) 电光装置及其预充电方法、图像处理电路和电子设备
US10896650B2 (en) Video signal line drive circuit, display device including same, and drive method for video signal line
CN110010096B (zh) 显示面板、其驱动方法及显示装置
US9595233B2 (en) Display device and driving method thereof
JPH08137443A (ja) 画像表示装置
CN109658893B (zh) 显示面板的驱动方法、驱动装置及显示设备
CN112419992B (zh) 显示面板及其驱动方法、显示装置
WO2018171061A1 (zh) 驱动电路及液晶显示装置
CN111105761B (zh) 显示面板及其控制方法、显示装置
KR20180014338A (ko) 표시장치
KR20060061835A (ko) 액티브 매트릭스 디스플레이 장치
KR100412120B1 (ko) 액정표시장치의 구동회로 및 그 구동방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20818823

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20818823

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20818823

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 21.10.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20818823

Country of ref document: EP

Kind code of ref document: A1