WO2018171061A1 - 驱动电路及液晶显示装置 - Google Patents

驱动电路及液晶显示装置 Download PDF

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Publication number
WO2018171061A1
WO2018171061A1 PCT/CN2017/089606 CN2017089606W WO2018171061A1 WO 2018171061 A1 WO2018171061 A1 WO 2018171061A1 CN 2017089606 W CN2017089606 W CN 2017089606W WO 2018171061 A1 WO2018171061 A1 WO 2018171061A1
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Prior art keywords
chip
reference voltage
output
voltage
input
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PCT/CN2017/089606
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English (en)
French (fr)
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陈宥烨
何振伟
吴宇
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深圳市华星光电技术有限公司
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Publication of WO2018171061A1 publication Critical patent/WO2018171061A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a driving circuit and a liquid crystal display device.
  • the display modes of the existing display include two-dimensional and three-dimensional display modes, that is, two-dimensional display and three-dimensional display can be simultaneously realized.
  • the existing display has a problem that the charge and discharge capability is insufficient and the temperature of the drive chip is too high, which restricts the further development of the display.
  • FIG. 1 shows the pixel structure of the gate line parasitic capacitance of one pixel unit (RGB), Gn to Gn+2 represents the scan lines of the nth to n+2th rows, and Dn represents the nth data.
  • Cst is the storage capacitor
  • Cgs is the equivalent capacitance between the gate and source of the thin film transistor
  • Clc is the liquid crystal capacitor
  • Com is the common electrode.
  • FIG. 2 shows a schematic structural view of a conventional display.
  • the conventional display includes a plurality of pixel units 10.
  • Each of the pixel units 10 includes a first pixel 11 , a second pixel 12 , and a third pixel 13 , which are adjacent to each other.
  • the pixel 11, the second pixel 12, and the third pixel 13 are adjacent in the vertical direction; for example, the first pixel 11 is a blue pixel, the second pixel 12 is a green pixel, and the third pixel 13 is a red pixel. That is, the order of the pixels of the display in the vertical direction is blue pixels, green pixels, and red pixels.
  • Line1 to Line12 respectively indicate scanning lines of pixels of the 1st to 12th rows.
  • the 2nd line sequentially to the 2nd line, the 1st line, the 3rd line, the 5th line, the 4th line, the 6th line, the 8th line, the 7th line, the 9th line, the 11th line.
  • the scan lines corresponding to the pixels of the 10th row and the 12th row are input to the scan signal; that is, the scan order from top to bottom is changed to the interleave scan order.
  • the potentials of two adjacent pixels of the same color in the same column are high (H) and low (L). Therefore, by means of misalignment scanning, the potential HLHLHL can be effectively avoided to form HHHLLL ( The switching of L) of the first strip is excluded, thereby reducing the charging and discharging frequency, that is, the charging capability is improved. Secondly, when the charging and discharging frequency is lowered, the temperature of the driving chip is also lowered. Moreover, since the human eye is less sensitive to blue, only the blue to the switching point between the high potential and the low potential ensures color uniformity.
  • Gn+1 When the above scanning mode is enabled, Gn+1 is turned off before Gn. When Gn is turned off, the pixel voltage of Gn+1 is pulled down due to the coupling of the capacitance Cst shown in the dotted line. This phenomenon will appear in the second and fifth. 8, 8 lines. Since the positive and negative voltages are pulled low, the common voltage of the pixels of these rows is shifted down, and there may be a problem of flicker or display unevenness.
  • An object of the present invention is to provide a driving circuit and a liquid crystal display device which can improve display effects.
  • the present invention provides a driving circuit including:
  • timing control chip for providing a control signal to the programmable gamma correction buffer chip and providing a digital signal to the source driver chip
  • the programmable gamma correction buffer chip configured to drive the chip to the source when the timing control chip outputs the digital signals of the 3nth row of pixels and the 3n+1th row of pixels under the control of the control signal Outputting a first reference voltage; and outputting a second reference voltage to the source driving chip when the timing control chip outputs a digital signal of the 3n+2th row of pixels;
  • the source driving chip is configured to receive the first reference voltage and the second reference voltage and the digital signal, generate a first data voltage according to the first reference voltage and the digital signal, and according to the first Generating a second data voltage by the second reference voltage and the digital signal;
  • the timing control chip is electrically connected to the programmable gamma correction buffer chip and the source driving chip, and the programmable gamma correction buffer chip is electrically connected to the source driving chip.
  • the first data voltage is equal to a preset data voltage
  • a difference between the second data voltage and the preset data voltage is equal to a preset value
  • the difference ⁇ V between the second data voltage and the preset data voltage is as follows:
  • Vgh is the turn-on voltage of the thin film transistor
  • Vgl is the turn-off voltage of the thin film transistor
  • Cst is the storage capacitor
  • Cgs is the equivalent capacitance between the gate and the source of the thin film transistor
  • Clc is the liquid crystal capacitor
  • the timing control chip includes a control end and a first output end, the control end is configured to output the control signal, and the first output end is configured to output the digital signal;
  • the programmable gamma correction buffer chip includes a first input terminal, a second output terminal, and a third output terminal, wherein the first input terminal is configured to input the control signal; the second output terminal is configured to output the a first reference voltage; the third output terminal is configured to output the second reference voltage;
  • the source driving chip includes a second input terminal, a third input terminal, and a fourth input terminal; the second input terminal is configured to input the digital signal; and the third input terminal is configured to input the first reference voltage The fourth input terminal is configured to output the second reference voltage;
  • the control end is connected to the first input end, the first output end is connected to the second input end, the second output end is connected to the third input end, and the third output end is connected to The fourth input is connected.
  • the invention provides a driving circuit comprising:
  • Timing control chip for providing control signals to the programmable gamma correction buffer chip And providing a digital signal to the source driver chip;
  • the programmable gamma correction buffer chip configured to drive the chip to the source when the timing control chip outputs the digital signals of the 3nth row of pixels and the 3n+1th row of pixels under the control of the control signal Outputting a first reference voltage; and outputting a second reference voltage to the source driving chip when the timing control chip outputs a digital signal of the 3n+2th row of pixels;
  • the source driving chip is configured to receive the first reference voltage and the second reference voltage and the digital signal, and generate data according to the first reference voltage, the second reference voltage, and the digital signal Voltage.
  • the data voltage includes a first data voltage and a second data voltage
  • the source driving chip is further configured to generate a first data voltage according to the first reference voltage and the digital signal, and Generating a second data voltage based on the second reference voltage and the digital signal.
  • the first data voltage is equal to a preset data voltage
  • a difference between the second data voltage and the preset data voltage is equal to a preset value
  • the difference ⁇ V between the second data voltage and the preset data voltage is as follows:
  • Vgh is the turn-on voltage of the thin film transistor
  • Vgl is the thin film transistor Turn off the voltage
  • Cst is the storage capacitor
  • Cgs is the equivalent capacitance between the gate and source of the thin film transistor
  • Clc is the liquid crystal capacitor
  • the timing control chip is electrically connected to the programmable gamma correction buffer chip and the source driving chip, respectively, and the programmable gamma correction buffer chip and the source driving chip are electrically connected. Sexual connection.
  • the timing control chip includes a control end and a first output end, the control end is configured to output the control signal, and the first output end is configured to output the digital signal;
  • the programmable gamma correction buffer chip includes a first input terminal, a second output terminal, and a third output terminal, wherein the first input terminal is configured to input the control signal; the second output terminal is configured to output the a first reference voltage; the third output terminal is configured to output the second reference voltage;
  • the source driving chip includes a second input terminal, a third input terminal, and a fourth input terminal; the second input terminal is configured to input the digital signal; and the third input terminal is configured to input the first reference voltage The fourth input terminal is configured to output the second reference voltage;
  • the control end is connected to the first input end, the first output end is connected to the second input end, the second output end is connected to the third input end, and the third output end is connected to The fourth input is connected.
  • the present invention also provides a liquid crystal display device comprising: a liquid crystal display panel and a driving circuit, the driving circuit comprising:
  • timing control chip for providing a control signal to the programmable gamma correction buffer chip and providing a digital signal to the source driver chip
  • the programmable gamma correction buffer chip configured to drive the chip to the source when the timing control chip outputs the digital signals of the 3nth row of pixels and the 3n+1th row of pixels under the control of the control signal Outputting a first reference voltage; and outputting a second reference voltage to the source driving chip when the timing control chip outputs a digital signal of the 3n+2th row of pixels;
  • the source driving chip is configured to receive the first reference voltage and the second reference voltage and the digital signal, and generate data according to the first reference voltage, the second reference voltage, and the digital signal Voltage.
  • the data voltage includes a first data voltage and a second data voltage
  • the source driving chip is further configured to generate a first data voltage according to the first reference voltage and the digital signal. And generating a second data voltage according to the second reference voltage and the digital signal.
  • the first data voltage is equal to a preset data voltage
  • a difference between the second data voltage and the preset data voltage is equal to a preset value
  • the difference ⁇ V between the second data voltage and the preset data voltage is as follows:
  • Vgh is the turn-on voltage of the thin film transistor
  • Vgl is the thin film transistor Turn off the voltage
  • Cst is the storage capacitor
  • Cgs is the equivalent capacitance between the gate and source of the thin film transistor
  • Clc is the liquid crystal capacitor
  • the timing control chip is electrically connected to the programmable gamma correction buffer chip and the source driving chip, respectively, the programmable gamma correction buffer chip and the source driving chip. Electrical connection.
  • the timing control chip includes a control terminal and a first output terminal, the control terminal is configured to output the control signal, and the first output terminal is configured to output the digital signal;
  • the programmable gamma correction buffer chip includes a first input terminal, a second output terminal, and a third output terminal, wherein the first input terminal is configured to input the control signal; the second output terminal is configured to output the a first reference voltage; the third output terminal is configured to output the second reference voltage;
  • the source driving chip includes a second input terminal, a third input terminal, and a fourth input terminal; the second input terminal is configured to input the digital signal; and the third input terminal is configured to input the first reference voltage The fourth input terminal is configured to output the second reference voltage;
  • the control end is connected to the first input end, the first output end is connected to the second input end, the second output end is connected to the third input end, and the third output end is connected to The fourth input is connected.
  • the pixel voltage of all the pixels is in the driving process. It is kept constant to prevent flickering or uneven display, which improves the display.
  • FIG. 1 is a schematic structural view of a pixel of a conventional gate line parasitic capacitance method
  • FIG. 2 is a schematic structural view of a conventional display
  • FIG. 3 is a schematic diagram of driving waveforms of a conventional display
  • FIG. 4 is a schematic diagram showing potential changes of a conventional display
  • FIG. 5 is a schematic structural view of a driving circuit of the present invention.
  • FIG. 5 is a schematic structural diagram of a driving circuit of the present invention.
  • the driving circuit of the present invention includes: a timing control chip 21, a programmable gamma correction buffer chip 22, and a source driving chip 23; and the timing control chip 21 and the programmable gamma correction buffer chip 22, respectively.
  • the source driving chip 23 is electrically connected to the source driving chip 23, and the programmable gamma correction buffer chip 22 is electrically connected to the source driving chip 23.
  • the timing control chip 21 includes a control terminal 211 and a first output terminal 212.
  • the control terminal 211 is configured to output the control signal, where the control signal is used to switch between a first reference voltage and a second reference voltage.
  • An output 212 is operative to output the digital signal.
  • the programmable gamma correction buffer chip 22 includes a first input terminal 221, a second output terminal 222, and a third output terminal 223.
  • the first input terminal 221 is configured to input the control signal;
  • the second output terminal 222 is configured to output the first reference voltage Va;
  • the third output end 223 is configured to output the second reference voltage Vb.
  • the source driving chip 23 includes a second input end 233, a third input end 231, and a fourth input end 232; the second input end 233 is for inputting the digital signal; and the third input end 231 is for inputting The first reference voltage Va; the fourth input terminal 232 is configured to output the second reference voltage Vb.
  • the control terminal 211 is connected to the first input end 221, the first output end 212 is connected to the second input end 233, and the second output end 222 is connected to the third input end 231.
  • the third output terminal 223 is connected to the fourth input terminal 232.
  • the timing control chip 21 is for supplying a control signal to the programmable gamma correction buffer chip 22 and a digital signal to the source drive chip 23.
  • the programmable gamma correction buffer chip 22 is configured to output to the source driving chip 23 when the timing control chip 21 outputs the digital signals of the 3nth row of pixels and the 3n+1th row of pixels according to the control signal.
  • the first reference voltage Va; and the second reference voltage Vb is output to the source driving chip 23 when the timing control chip 21 outputs the digital signal of the 3n+2th row of pixels according to the control signal.
  • the source driving chip 23 is configured to receive the first reference voltage Va and the second reference voltage Vb and the digital signal, and generate a data voltage according to the first reference voltage Va, the second reference voltage Va, and the digital signal.
  • the data voltage includes a first data voltage V1 and a second data voltage V2, and the source driving chip 23 is configured to generate a first data voltage V1 according to the first reference voltage Va and the digital signal, and according to the second The reference voltage Vb and the digital signal generate a second data voltage V2.
  • the first data voltage V1 is equal to the preset data voltage V0, and the difference between the second data voltage V2 and the preset data voltage V0 is equal to a preset value.
  • a difference ⁇ V between the second data voltage V2 and the preset data voltage V0 is as follows:
  • Vgh is the turn-on voltage of the thin film transistor
  • Vgl is the turn-off voltage of the thin film transistor
  • Cst is the storage capacitor
  • Cgs is the equivalent capacitance between the gate and the source of the thin film transistor
  • Clc is the liquid crystal capacitor
  • the programmable gamma correction buffer chip 22 Since the programmable gamma correction buffer chip 22 stores two sets of reference voltages. When the timing control chip 21 outputs the data of the 3nth and 3n+1th rows of pixels, the programmable gamma correction buffer chip 22 outputs the first reference voltage; and when the timing control chip 21 outputs the data of the 3n+2th row of pixels, The programmable gamma correction buffer chip 22 is controlled to output a second reference voltage. Therefore, when Gn is turned off, although the coupling of the capacitor Cst pulls down the pixel voltage of the Gn+1 row pixel, due to the compensation effect of the second reference voltage, the pixel voltage after the pull-down is equal to the set value, that is, remains constant. And all The switching is done in H-blank time.
  • the driving circuit of the present invention since the data voltage of the pixels that are pulled down is compensated, the pixel voltage of all the pixels is kept constant during the driving process, and the problem of flicker or display unevenness is prevented, and the display effect is improved.
  • the present invention also provides a liquid crystal display device including a liquid crystal display panel and a driving circuit.
  • the driving circuit of the present invention includes a timing control chip 21, a programmable gamma correction buffer chip 22, and a source driving chip 23.
  • the timing control chip 21 is electrically connected to the programmable gamma correction buffer chip 22 and the source driving chip 23, respectively, and the programmable gamma correction buffer chip 22 is electrically connected to the source driving chip 23. .
  • the timing control chip 21 includes a control terminal 211 for outputting the control signal, and a first output terminal 212 for outputting the digital signal.
  • the programmable gamma correction buffer chip 22 includes a first input terminal 221, a second output terminal 222, and a third output terminal 223.
  • the first input terminal 221 is configured to input the control signal;
  • the second output terminal 222 is configured to output the first reference voltage Va;
  • the third output end 223 is configured to output the second reference voltage Vb.
  • the source driving chip 23 includes a second input end 233, a third input end 231, and a fourth input end 232; the second input end 233 is for inputting the digital signal; and the third input end 231 is for inputting The first reference voltage Va; the fourth input terminal 232 is configured to output the second reference voltage Vb.
  • the control terminal 211 is connected to the first input terminal 221, the first output terminal 212 is connected to the second input terminal 233, and the second output terminal 222 is connected to the second output terminal 222.
  • the third input terminal 231 is connected, and the third output terminal 223 is connected to the fourth input terminal 232.
  • the timing control chip 21 is for supplying a control signal to the programmable gamma correction buffer chip 22 and a digital signal to the source drive chip 23.
  • the programmable gamma correction buffer chip 22 is configured to output to the source driving chip 23 when the timing control chip 21 outputs the digital signals of the 3nth row of pixels and the 3n+1th row of pixels according to the control signal.
  • the first reference voltage Va; and the second reference voltage Vb is output to the source driving chip 23 when the timing control chip 21 outputs the digital signal of the 3n+2th row of pixels according to the control signal.
  • the source driving chip 23 is configured to receive the first reference voltage Va and the second reference voltage Vb and the digital signal, and generate a data voltage according to the first reference voltage Va, the second reference voltage Va, and the digital signal.
  • the source driving chip 23 is configured to generate a first data voltage V1 according to the first reference voltage Va and the digital signal, and generate a second data voltage V2 according to the second reference voltage Vb and the digital signal.
  • the first data voltage V1 is equal to the preset data voltage V0, and the difference between the second data voltage V2 and the preset data voltage V0 is equal to a preset value.
  • a difference ⁇ V between the second data voltage V2 and the preset data voltage V0 is as follows:
  • Vgh is the turn-on voltage of the thin film transistor
  • Vgl is the turn-off voltage of the thin film transistor
  • Cst is the storage capacitor
  • Cgs is between the gate and the source of the thin film transistor
  • Clc is the liquid crystal capacitor
  • the programmable gamma correction buffer chip 22 Since the programmable gamma correction buffer chip 22 stores two sets of reference voltages. When the timing control chip 21 outputs the data of the 3nth and 3n+1th rows of pixels, the programmable gamma correction buffer chip 22 outputs the first reference voltage; and when the timing control chip 21 outputs the data of the 3n+2th row of pixels, The programmable gamma correction buffer chip 22 is controlled to output a second reference voltage. Therefore, when Gn is turned off, although the coupling of the capacitor Cst pulls down the pixel voltage of the Gn+1 row pixel, due to the compensation effect of the second reference voltage, the pixel voltage after the pull-down is equal to the set value, that is, remains constant. And all switching is done in H-blank time.
  • the liquid crystal display device of the present invention since the data voltage of the pixels that are pulled down is compensated, the pixel voltages of all the pixels are kept constant during the driving process, and the problem of flicker or display unevenness is prevented, and the display effect is improved.

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  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种驱动电路及液晶显示装置，该驱动电路包括：可编程伽玛校正缓冲芯片（22），用于根据控制信号，在时序控制芯片（21）输出第3n行像素和第3n+1行像素的数字信号时，向源驱动芯片（23）输出第一参考电压（Va）；以及在时序控制芯片（21）输出第3n+2行像素的数字信号时，向源驱动芯片（23）输出第二参考电压（Vb）。

Description

驱动电路及液晶显示装置 【技术领域】
本发明涉及显示器技术领域，特别是涉及一种驱动电路及液晶显示装置。
【背景技术】
随着显示器的不断发展，显示器的显示模式越来越多。比如现有的显示器的显示模式包括二维和三维显示模式，也即可以同时实现二维显示和三维显示。但是，现有的显示器存在着充放电能力不足以及驱动芯片温度过高的问题，从而制约了显示器的进一步发展。
目前通过改变显示器的像素排布结构以及像素的驱动方式以解决现有技术的问题。但是对于栅线寄生电容(Cst on gate)的像素设计。如图1所示，图1给出一个像素单元(RGB)的栅线寄生电容的像素结构，Gn至Gn+2表示第n行至第n+2行的扫描线，Dn表示第n条数据线，其中Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容，Com为公共电极。
图2给出现有的显示器的结构示意图。如图2所示，现有的显示器包括：多个像素单元10。每个像素单元10包括依次相邻的一第一像素11、一第二像素12、一第三像素13，也即第一像 素11、第二像素12、第三像素13在竖直方向相邻；比如第一像素11为蓝色像素，第二像素12为绿色像素，第三像素13为红色像素。也即显示器的像素沿竖直方向的排列顺序为蓝色像素、绿色像素、红色像素。
如图3所示，Line1至Line12分别表示第1至12行像素的扫描线。在二维显示模式下，依次向第2行、第1行、第3行、第5行、第4行、第6行、第8行、第7行、第9行、第11行、第10行、第12行像素对应的扫描线输入扫描信号；也即将由上至下的扫描顺序变为交错扫描顺序。
结合图4，通常位于同一列中相邻两个同一颜色的像素的电位一高(H)一低(L)，因此通过错位扫描的方式，可以有效避开电位HLHLHL顺序切换，而形成HHHLLL(排除第一条的L)的切换，从而降低充放电频率，也即提高了充电能力。其次，当充放电频率降低时，也会使得驱动芯片的温度降低。且由于人眼对蓝色的敏感度较低，故仅将蓝色至于高电位与低电位的切换点，确保了颜色的均匀性。
在启用上述扫描方式时，Gn+1先于Gn关闭，在Gn关闭时，由于虚线框内所示的电容Cst的耦合将Gn+1的像素电压拉低，这个现象会出现在第2、5、8等行。而由于正负电压都被拉低，导致这些行的像素的公共电压下移，可能会出现闪烁或显示不均的问题。
因此，有必要提供一种驱动电路及液晶显示装置，以解决现有技术所存在的问题。
【发明内容】
本发明的目的在于提供一种驱动电路及液晶显示装置，能够提高显示效果。
为解决上述技术问题，本发明提供一种驱动电路，其包括：
时序控制芯片，用于向可编程伽玛校正缓冲芯片提供控制信号和向源驱动芯片提供数字信号；
所述可编程伽玛校正缓冲芯片，用于在所述控制信号的控制下，当所述时序控制芯片输出第3n行像素和第3n+1行像素的数字信号时，向所述源驱动芯片输出第一参考电压；以及当所述时序控制芯片输出第3n+2行像素的数字信号时，向所述源驱动芯片输出第二参考电压；
所述源驱动芯片，用于接收所述第一参考电压和所述第二参考电压以及所述数字信号，根据所述第一参考电压以及所述数字信号生成第一数据电压以及根据所述第二参考电压以及所述数字信号生成第二数据电压；
其中所述时序控制芯片分别与所述可编程伽玛校正缓冲芯片以及所述源驱动芯片电性连接，所述可编程伽玛校正缓冲芯片与所述源驱动芯片电性连接。
在本发明的驱动电路中，所述第一数据电压等于预设数据电压，所述第二数据电压与所述预设数据电压之间的差值等于预设值。
在本发明的驱动电路中，所述第二数据电压与所述预设数据电压之间的差值ΔV如下所示：
Figure PCTCN2017089606-appb-000001
其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容。
在本发明的驱动电路中，所述时序控制芯片包括控制端和第一输出端，所述控制端用于输出所述控制信号，所述第一输出端用于输出所述数字信号；
所述可编程伽玛校正缓冲芯片包括第一输入端、第二输出端以及第三输出端，所述第一输入端用于输入所述控制信号；所述第二输出端用于输出所述第一参考电压；所述第三输出端用于输出所述第二参考电压；
所述源驱动芯片包括第二输入端、第三输入端以及第四输入端；所述第二输入端用于输入所述数字信号；所述第三输入端用于输入所述第一参考电压；所述第四输入端用于输出所述第二参考电压；
所述控制端与所述第一输入端连接，所述第一输出端与所述第二输入端连接，所述第二输出端与所述第三输入端连接，所述第三输出端与所述第四输入端连接。
本发明提供一种驱动电路，其包括：
时序控制芯片，用于向可编程伽玛校正缓冲芯片提供控制信 号和向源驱动芯片提供数字信号；
所述可编程伽玛校正缓冲芯片，用于在所述控制信号的控制下，当所述时序控制芯片输出第3n行像素和第3n+1行像素的数字信号时，向所述源驱动芯片输出第一参考电压；以及当所述时序控制芯片输出第3n+2行像素的数字信号时，向所述源驱动芯片输出第二参考电压；
所述源驱动芯片，用于接收所述第一参考电压和所述第二参考电压以及所述数字信号，并根据所述第一参考电压、所述第二参考电压以及所述数字信号生成数据电压。
在本发明的驱动电路中，所述数据电压包括第一数据电压和第二数据电压，所述源驱动芯片，还用于根据所述第一参考电压以及所述数字信号生成第一数据电压以及根据所述第二参考电压以及所述数字信号生成第二数据电压。
在本发明的驱动电路中，所述第一数据电压等于预设数据电压，所述第二数据电压与所述预设数据电压之间的差值等于预设值。
在本发明的驱动电路中，所述第二数据电压与所述预设数据电压之间的差值ΔV如下所示：
Figure PCTCN2017089606-appb-000002
其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的 关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容。
在本发明的驱动电路中，所述时序控制芯片分别与所述可编程伽玛校正缓冲芯片以及所述源驱动芯片电性连接，所述可编程伽玛校正缓冲芯片与所述源驱动芯片电性连接。
在本发明的驱动电路中，所述时序控制芯片包括控制端和第一输出端，所述控制端用于输出所述控制信号，所述第一输出端用于输出所述数字信号；
所述可编程伽玛校正缓冲芯片包括第一输入端、第二输出端以及第三输出端，所述第一输入端用于输入所述控制信号；所述第二输出端用于输出所述第一参考电压；所述第三输出端用于输出所述第二参考电压；
所述源驱动芯片包括第二输入端、第三输入端以及第四输入端；所述第二输入端用于输入所述数字信号；所述第三输入端用于输入所述第一参考电压；所述第四输入端用于输出所述第二参考电压；
所述控制端与所述第一输入端连接，所述第一输出端与所述第二输入端连接，所述第二输出端与所述第三输入端连接，所述第三输出端与所述第四输入端连接。
本发明还提供一种液晶显示装置，其包括：液晶显示面板和驱动电路，所述驱动电路包括：
时序控制芯片，用于向可编程伽玛校正缓冲芯片提供控制信号和向源驱动芯片提供数字信号；
所述可编程伽玛校正缓冲芯片，用于在所述控制信号的控制下，当所述时序控制芯片输出第3n行像素和第3n+1行像素的数字信号时，向所述源驱动芯片输出第一参考电压；以及当所述时序控制芯片输出第3n+2行像素的数字信号时，向所述源驱动芯片输出第二参考电压；
所述源驱动芯片，用于接收所述第一参考电压和所述第二参考电压以及所述数字信号，并根据所述第一参考电压、所述第二参考电压以及所述数字信号生成数据电压。
在本发明的液晶显示装置中，所述数据电压包括第一数据电压和第二数据电压，所述源驱动芯片，还用于根据所述第一参考电压以及所述数字信号生成第一数据电压以及根据所述第二参考电压以及所述数字信号生成第二数据电压。
在本发明的液晶显示装置中，所述第一数据电压等于预设数据电压，所述第二数据电压与所述预设数据电压之间的差值等于预设值。
在本发明的液晶显示装置中，所述第二数据电压与所述预设数据电压之间的差值ΔV如下所示：
Figure PCTCN2017089606-appb-000003
其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的 关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容。
在本发明的液晶显示装置中，所述时序控制芯片分别与所述可编程伽玛校正缓冲芯片以及所述源驱动芯片电性连接，所述可编程伽玛校正缓冲芯片与所述源驱动芯片电性连接。
在本发明的液晶显示装置中，所述时序控制芯片包括控制端和第一输出端，所述控制端用于输出所述控制信号，所述第一输出端用于输出所述数字信号；
所述可编程伽玛校正缓冲芯片包括第一输入端、第二输出端以及第三输出端，所述第一输入端用于输入所述控制信号；所述第二输出端用于输出所述第一参考电压；所述第三输出端用于输出所述第二参考电压；
所述源驱动芯片包括第二输入端、第三输入端以及第四输入端；所述第二输入端用于输入所述数字信号；所述第三输入端用于输入所述第一参考电压；所述第四输入端用于输出所述第二参考电压；
所述控制端与所述第一输入端连接，所述第一输出端与所述第二输入端连接，所述第二输出端与所述第三输入端连接，所述第三输出端与所述第四输入端连接。
本发明的驱动电路及液晶显示装置，由于通过对被拉低行的像素的数据电压进行补偿，从而所有像素的像素电压在驱动过程 中维持恒定，防止出现闪烁或显示不均的问题，提高了显示效果。
【附图说明】
图1为现有栅线寄生电容方式的像素的结构示意图；
图2为现有的显示器的结构示意图；
图3为现有显示器的驱动波形示意图；
图4为现有显示器的电位变化示意图；
图5为本发明的驱动电路的结构示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图5，图5为本发明的驱动电路的结构示意图。
如图5所示，本发明的驱动电路包括：时序控制芯片21、可编程伽玛校正缓冲芯片22以及源驱动芯片23；所述时序控制芯片21分别与所述可编程伽玛校正缓冲芯片22以及所述源驱动芯片23电性连接，所述可编程伽玛校正缓冲芯片22与所述源驱动芯片23电性连接。
所述时序控制芯片21包括控制端211和第一输出端212，所述控制端211用于输出所述控制信号，所述控制信号用于切换第一参考电压和第二参考电压，所述第一输出端212用于输出所述数字信号。
所述可编程伽玛校正缓冲芯片22包括第一输入端221、第二输出端222以及第三输出端223，所述第一输入端221用于输入所述控制信号；所述第二输出端222用于输出所述第一参考电压Va；所述第三输出端223用于输出所述第二参考电压Vb。
所述源驱动芯片23包括第二输入端233、第三输入端231以及第四输入端232；所述第二输入端233用于输入所述数字信号；所述第三输入端231用于输入所述第一参考电压Va；所述第四输入端232用于输出所述第二参考电压Vb。
所述控制端211与所述第一输入端221连接，所述第一输出端212与所述第二输入端233连接，所述第二输出端222与所述第三输入端231连接，所述第三输出端223与所述第四输入端232连接。
时序控制芯片21用于向可编程伽玛校正缓冲芯片22提供控制信号和向源驱动芯片23提供数字信号。
所述可编程伽玛校正缓冲芯片22用于根据所述控制信号，在所述时序控制芯片21输出第3n行像素和第3n+1行像素的数字信号时，向所述源驱动芯片23输出第一参考电压Va；以及根据所述控制信号，在所述时序控制芯片21输出第3n+2行像素的数字信号时，向所述源驱动芯片23输出第二参考电压Vb。
所述源驱动芯片23用于接收第一参考电压Va和第二参考电压Vb以及数字信号，并根据所述第一参考电压Va、所述第二参考电压Va以及所述数字信号生成数据电压。
所述数据电压包括第一数据电压V1和第二数据电压V2，所述源驱动芯片23用于根据所述第一参考电压Va以及所述数字信号生成第一数据电压V1以及根据所述第二参考电压Vb以及所述数字信号生成第二数据电压V2。
所述第一数据电压V1等于预设数据电压V0，所述第二数据电压V2与所述预设数据电压V0之间的差值等于预设值。
具体地，所述第二数据电压V2与所述预设数据电压V0之间的差值ΔV如下式所示：
Figure PCTCN2017089606-appb-000004
其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容。
由于可编程伽玛校正缓冲芯片22存储两组参考电压。当时序控制芯片21输出第3n及3n+1行像素的数据时，控制可编程伽玛校正缓冲芯片22输出第一参考电压；而当时序控制芯片21输出第3n+2行像素的数据时，控制可编程伽玛校正缓冲芯片22输出第二参考电压。因此在Gn关闭时，虽然电容Cst的耦合将Gn+1行像素的像素电压拉低，但是由于第二参考电压的补偿作用，使得拉低后的像素电压等于设定值，也即保持恒定，且所有 的切换均在H-blank的时间内完成。
本发明的驱动电路，由于通过对被拉低行的像素的数据电压进行补偿，从而所有像素的像素电压在驱动过程中维持恒定，防止出现闪烁或显示不均的问题，提高了显示效果。
本发明还提供一种液晶显示装置，其包括液晶显示面板和驱动电路，如图5所示，本发明的驱动电路包括：时序控制芯片21、可编程伽玛校正缓冲芯片22以及源驱动芯片23；所述时序控制芯片21分别与所述可编程伽玛校正缓冲芯片22以及所述源驱动芯片23电性连接，所述可编程伽玛校正缓冲芯片22与所述源驱动芯片23电性连接。
所述时序控制芯片21包括控制端211和第一输出端212，所述控制端211用于输出所述控制信号，所述第一输出端212用于输出所述数字信号。
所述可编程伽玛校正缓冲芯片22包括第一输入端221、第二输出端222以及第三输出端223，所述第一输入端221用于输入所述控制信号；所述第二输出端222用于输出所述第一参考电压Va；所述第三输出端223用于输出所述第二参考电压Vb。
所述源驱动芯片23包括第二输入端233、第三输入端231以及第四输入端232；所述第二输入端233用于输入所述数字信号；所述第三输入端231用于输入所述第一参考电压Va；所述第四输入端232用于输出所述第二参考电压Vb。
所述控制端211与所述第一输入端221连接，所述第一输出端212与所述第二输入端233连接，所述第二输出端222与所述 第三输入端231连接，所述第三输出端223与所述第四输入端232连接。
时序控制芯片21用于向可编程伽玛校正缓冲芯片22提供控制信号和向源驱动芯片23提供数字信号。
所述可编程伽玛校正缓冲芯片22用于根据所述控制信号，在所述时序控制芯片21输出第3n行像素和第3n+1行像素的数字信号时，向所述源驱动芯片23输出第一参考电压Va；以及根据所述控制信号，在所述时序控制芯片21输出第3n+2行像素的数字信号时，向所述源驱动芯片23输出第二参考电压Vb。
所述源驱动芯片23用于接收第一参考电压Va和第二参考电压Vb以及数字信号，并根据所述第一参考电压Va、所述第二参考电压Va以及所述数字信号生成数据电压。
所述源驱动芯片23用于根据所述第一参考电压Va以及所述数字信号生成第一数据电压V1以及根据所述第二参考电压Vb以及所述数字信号生成第二数据电压V2。
所述第一数据电压V1等于预设数据电压V0，所述第二数据电压V2与所述预设数据电压V0之间的差值等于预设值。
具体地，所述第二数据电压V2与所述预设数据电压V0之间的差值ΔV如下式所示：
Figure PCTCN2017089606-appb-000005
其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间 的等效电容，Clc为液晶电容。
由于可编程伽玛校正缓冲芯片22存储两组参考电压。当时序控制芯片21输出第3n及3n+1行像素的数据时，控制可编程伽玛校正缓冲芯片22输出第一参考电压；而当时序控制芯片21输出第3n+2行像素的数据时，控制可编程伽玛校正缓冲芯片22输出第二参考电压。因此在Gn关闭时，虽然电容Cst的耦合将Gn+1行像素的像素电压拉低，但是由于第二参考电压的补偿作用，使得拉低后的像素电压等于设定值，也即保持恒定，且所有的切换均在H-blank的时间内完成。
本发明的液晶显示装置，由于通过对被拉低行的像素的数据电压进行补偿，从而所有像素的像素电压在驱动过程中维持恒定，防止出现闪烁或显示不均的问题，提高了显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种驱动电路，其包括：
    时序控制芯片，用于向可编程伽玛校正缓冲芯片提供控制信号和向源驱动芯片提供数字信号；
    所述可编程伽玛校正缓冲芯片，用于在所述控制信号的控制下，当所述时序控制芯片输出第3n行像素和第3n+1行像素的数字信号时，向所述源驱动芯片输出第一参考电压；以及当所述时序控制芯片输出第3n+2行像素的数字信号时，向所述源驱动芯片输出第二参考电压；
    所述源驱动芯片，用于接收所述第一参考电压和所述第二参考电压以及所述数字信号，根据所述第一参考电压以及所述数字信号生成第一数据电压以及根据所述第二参考电压以及所述数字信号生成第二数据电压；
    其中所述时序控制芯片分别与所述可编程伽玛校正缓冲芯片以及所述源驱动芯片电性连接，所述可编程伽玛校正缓冲芯片与所述源驱动芯片电性连接。
  2. 根据权利要求1所述的驱动电路，其中
    所述第一数据电压等于预设数据电压，所述第二数据电压与所述预设数据电压之间的差值等于预设值。
  3. 根据权利要求2所述的驱动电路，其中
    所述第二数据电压与所述预设数据电压之间的差值ΔV如下所示：
    Figure PCTCN2017089606-appb-100001
    其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容。
  4. 根据权利要求1所述的驱动电路，其中
    所述时序控制芯片包括控制端和第一输出端，所述控制端用于输出所述控制信号，所述第一输出端用于输出所述数字信号；
    所述可编程伽玛校正缓冲芯片包括第一输入端、第二输出端以及第三输出端，所述第一输入端用于输入所述控制信号；所述第二输出端用于输出所述第一参考电压；所述第三输出端用于输出所述第二参考电压；
    所述源驱动芯片包括第二输入端、第三输入端以及第四输入端；所述第二输入端用于输入所述数字信号；所述第三输入端用于输入所述第一参考电压；所述第四输入端用于输出所述第二参考电压；
    所述控制端与所述第一输入端连接，所述第一输出端与所述第二输入端连接，所述第二输出端与所述第三输入端连接，所述第三输出端与所述第四输入端连接。
  5. 一种驱动电路，其包括：
    时序控制芯片，用于向可编程伽玛校正缓冲芯片提供控制信号和向源驱动芯片提供数字信号；
    所述可编程伽玛校正缓冲芯片，用于在所述控制信号的控制 下，当所述时序控制芯片输出第3n行像素和第3n+1行像素的数字信号时，向所述源驱动芯片输出第一参考电压；以及当所述时序控制芯片输出第3n+2行像素的数字信号时，向所述源驱动芯片输出第二参考电压；
    所述源驱动芯片，用于接收所述第一参考电压和所述第二参考电压以及所述数字信号，并根据所述第一参考电压、所述第二参考电压以及所述数字信号生成数据电压。
  6. 根据权利要求5所述的驱动电路，其中所述数据电压包括第一数据电压和第二数据电压，所述源驱动芯片，还用于根据所述第一参考电压以及所述数字信号生成第一数据电压以及根据所述第二参考电压以及所述数字信号生成第二数据电压。
  7. 根据权利要求6所述的驱动电路，其中
    所述第一数据电压等于预设数据电压，所述第二数据电压与所述预设数据电压之间的差值等于预设值。
  8. 根据权利要求7所述的驱动电路，其中
    所述第二数据电压与所述预设数据电压之间的差值ΔV如下所示：
    Figure PCTCN2017089606-appb-100002
    其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容。
  9. 根据权利要求5所述的驱动电路，其中
    所述时序控制芯片分别与所述可编程伽玛校正缓冲芯片以及所述源驱动芯片电性连接，所述可编程伽玛校正缓冲芯片与所述源驱动芯片电性连接。
  10. 根据权利要求9所述的驱动电路，其中
    所述时序控制芯片包括控制端和第一输出端，所述控制端用于输出所述控制信号，所述第一输出端用于输出所述数字信号；
    所述可编程伽玛校正缓冲芯片包括第一输入端、第二输出端以及第三输出端，所述第一输入端用于输入所述控制信号；所述第二输出端用于输出所述第一参考电压；所述第三输出端用于输出所述第二参考电压；
    所述源驱动芯片包括第二输入端、第三输入端以及第四输入端；所述第二输入端用于输入所述数字信号；所述第三输入端用于输入所述第一参考电压；所述第四输入端用于输出所述第二参考电压；
    所述控制端与所述第一输入端连接，所述第一输出端与所述第二输入端连接，所述第二输出端与所述第三输入端连接，所述第三输出端与所述第四输入端连接。
  11. 一种液晶显示装置，其包括：液晶显示面板和驱动电路，所述驱动电路包括：
    时序控制芯片，用于向可编程伽玛校正缓冲芯片提供控制信号和向源驱动芯片提供数字信号；
    所述可编程伽玛校正缓冲芯片，用于在所述控制信号的控制下，当所述时序控制芯片输出第3n行像素和第3n+1行像素的数 字信号时，向所述源驱动芯片输出第一参考电压；以及当所述时序控制芯片输出第3n+2行像素的数字信号时，向所述源驱动芯片输出第二参考电压；
    所述源驱动芯片，用于接收第一参考电压和第二参考电压以及数字信号，并根据所述第一参考电压、所述第二参考电压以及所述数字信号生成数据电压。
  12. 根据权利要求11所述的液晶显示装置，其中
    所述数据电压包括第一数据电压和第二数据电压，所述源驱动芯片，还用于根据所述第一参考电压以及所述数字信号生成第一数据电压以及根据所述第二参考电压以及所述数字信号生成第二数据电压。
  13. 根据权利要求12所述的液晶显示装置，其中
    所述第一数据电压等于预设数据电压，所述第二数据电压与所述预设数据电压之间的差值等于预设值。
  14. 根据权利要求13所述的液晶显示装置，其中
    所述第二数据电压与所述预设数据电压之间的差值ΔV如下所示：
    Figure PCTCN2017089606-appb-100003
    其中Vgh为薄膜晶体管的开启电压，Vgl为薄膜晶体管的关闭电压，Cst为存储电容，Cgs为薄膜晶体管的栅极与源极之间的等效电容，Clc为液晶电容。
  15. 根据权利要求11所述的液晶显示装置，其中所述时序 控制芯片分别与所述可编程伽玛校正缓冲芯片以及所述源驱动芯片电性连接，所述可编程伽玛校正缓冲芯片与所述源驱动芯片电性连接。
  16. 根据权利要求15所述的液晶显示装置，其中
    所述时序控制芯片包括控制端和第一输出端，所述控制端用于输出所述控制信号，所述第一输出端用于输出所述数字信号；
    所述可编程伽玛校正缓冲芯片包括第一输入端、第二输出端以及第三输出端，所述第一输入端用于输入所述控制信号；所述第二输出端用于输出所述第一参考电压；所述第三输出端用于输出所述第二参考电压；
    所述源驱动芯片包括第二输入端、第三输入端以及第四输入端；所述第二输入端用于输入所述数字信号；所述第三输入端用于输入所述第一参考电压；所述第四输入端用于输出所述第二参考电压；
    所述控制端与所述第一输入端连接，所述第一输出端与所述第二输入端连接，所述第二输出端与所述第三输入端连接，所述第三输出端与所述第四输入端连接。
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