WO2021168952A1 - Goa电路和显示面板 - Google Patents

Goa电路和显示面板 Download PDF

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Publication number
WO2021168952A1
WO2021168952A1 PCT/CN2020/080776 CN2020080776W WO2021168952A1 WO 2021168952 A1 WO2021168952 A1 WO 2021168952A1 CN 2020080776 W CN2020080776 W CN 2020080776W WO 2021168952 A1 WO2021168952 A1 WO 2021168952A1
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Prior art keywords
transistor
electrode
node
twenty
gate
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PCT/CN2020/080776
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English (en)
French (fr)
Inventor
薛炎
王宪
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/757,840 priority Critical patent/US11257411B2/en
Publication of WO2021168952A1 publication Critical patent/WO2021168952A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display technology, and in particular to a GOA circuit and a display panel.
  • the existing real-time compensation GOA circuit structure is shown in Figure 1.
  • the GOA circuit includes transistors Ta, Tb, Tc, T1, T1A, T1B, T1C, T3, T3A, T3nA, T3nB, T3nC, T3n, T3q, T4, T4l , T4q, T5, T5A, T5B, T5q, T6, T6cr, T7, T7cr, T8, T9 and storage capacitors Cm1, Cm2, Cm3, the connection of each transistor is shown in Figure 1.
  • the GOA circuit also includes a first node Q, the second node M, the third node Qb, the fifth node Mh, and the sixth node Qh, where C(n-3), C(n+3), and COUT(n) are all graded transmission signals, CRCLK, SCCLK and SECLK are timing signals, LSP, VST are the input signals of the GOA circuit, SCOUT(n) and SEOUT(n) are the output signals of the GOA circuit, GVDD is the power high signal, GVSS0, GVSS1 and GVSS2 are all Power low signal, G-RESET is the reset signal.
  • COUT(n), SCOUT(n) and SEOUT(n) are the driving signals provided to the scan lines in the display panel. To ensure that the scan lines in the display panel can receive the driving signals to turn on the transistors controlled by them, COUT must be guaranteed (n), SCOUT(n) and SEOUT(n) output is normal. Since the gates of T6, T6cr, and T8 are connected to the first node Q, the output of each output signal is controlled by the first node Q, and whether the charging rate at point Q is sufficient is controlled by the potential of the second node M. In the display period, when LSP and C(n-3) are at high potential, Ta and Tb are turned on, and the potential of the second node M is at high potential.
  • T1B and T1C Turn on, the first node Q is pulled high by the potential of the second node M, so that when CRCLK, SCCLK, and SECLK are high, T6, T6cr, and T8 are turned on, and COUT(n), SCOUT(n) and COUT(n) with high potentials are output.
  • SEOUT(n) provided to the scan line. It can be seen that the level of the potential of the first node Q is very important to the normal output of the output signal. Normally, the first node Q can control the normal output of the output signal.
  • the threshold voltage margin in the GOA circuit moves forward, the Q point needs a higher potential to ensure COUT(n), SCOUT(n) To ensure the normal output of the GOA circuit and SEOUT(n), the threshold voltage margin allowed by the GOA circuit needs to be reduced.
  • the prior art GOA circuit is a real-time compensation circuit with a relatively complicated structure. Therefore, when the threshold voltage margin (Vth margin) allowed by the GOA circuit itself is small, the process of the transistor needs to be extremely stable, so the development of the transistor process is more difficult. high.
  • Vth margin threshold voltage margin
  • the existing GOA circuit has a technical problem that the development of the transistor manufacturing process is relatively difficult and needs to be improved.
  • the present application provides a GOA circuit and a display panel to alleviate the technical problem of high difficulty in the development of the transistor manufacturing process in the existing GOA circuit.
  • the present application provides a GOA circuit, including m cascaded GOA units, wherein the nth level GOA unit includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node during the display time period;
  • the logical addressing module includes a second node, the logical addressing module is connected to the first node, and is configured to raise the potential of the second node twice during the display time period, and in the blank time period , Pulling up the potential of the first node through the second node;
  • a pull-up module connected to the first node, for pulling up the potentials of the n-th stage transmission signal, the first output signal, and the second output signal;
  • a first pull-down module connected to the first node, and used to pull down the potential of the first node during the blank time period
  • the second pull-down module is connected to the first node and the third node, and is used to pull down the potentials of the first node and the third node respectively during the display time period;
  • a third pull-down module connected to the third node and the second pull-down module, and is used to pull down the potential of the third node during a blank time period;
  • a first pull-down maintenance module including the third node, the first pull-down maintenance module is connected to the first node and the first pull-down module, and is configured to maintain a low potential of the first node;
  • the second pull-down maintaining module is connected to the third node and the pull-up module, and is used to maintain the low potentials of the n-th stage transmission signal, the first output signal, and the second output signal.
  • the pull-up control module includes a first transistor and a second transistor, and the gate and the first electrode of the first transistor, and the gate of the second transistor are both connected to the n-th transistor. Two-level signal transmission, the second electrode of the first transistor is connected to the first electrode of the second transistor, and the second electrode of the second transistor is connected to the first node.
  • the logic addressing module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a first storage capacitor.
  • the gate of the third transistor is connected to the n-2th level transmitting signal
  • the first electrode of the third transistor is connected to the first low potential signal
  • the second electrode of the third transistor is connected to the first electrode of the fourth transistor
  • the gate and second electrode of the fourth transistor are both connected to a high-potential signal
  • the gate of the fifth transistor is connected to the first input signal
  • the first electrode of the fifth transistor is connected to the n-2th stage signal
  • the second electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the first electrode of the seventh transistor
  • the gate of the sixth transistor is connected to the first input signal
  • the second electrode of the sixth transistor Both electrodes and the gate of the seventh transistor are connected to the second node, the second electrode of the seventh transistor is connected to the high potential signal, and the gate of the eighth transistor is
  • the pull-up module includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a second storage capacitor, and a third storage capacitor.
  • the gate of the tenth transistor The electrode, the gate of the eleventh transistor, and the gate of the twelfth transistor are all connected to the first node, the first electrode of the tenth transistor is connected to the first clock signal, and the gate of the tenth transistor is The second electrode is connected to the n-th stage signal, the first electrode of the eleventh transistor is connected to a second clock signal, the second electrode of the eleventh transistor is connected to the first output signal, and the first electrode of the eleventh transistor is connected to the first output signal.
  • the first electrode of the twelfth transistor is connected to the third clock signal, the second electrode of the twelfth transistor is connected to the second output signal, the gate of the thirteenth transistor is connected to the first node, and the first node is connected to the gate of the thirteenth transistor.
  • the first electrode of the thirteenth transistor is connected to the fourth node, the second electrode of the thirteenth transistor is connected to the first output signal, the first plate of the second storage capacitor is connected to the first node, and the second electrode is connected to the first node.
  • the electrode plate is connected to the first output signal, the first electrode plate of the third storage capacitor is connected to the first node, and the second electrode plate is connected to the second output signal.
  • the first pull-down module includes a fourteenth transistor and a fifteenth transistor, and the gate of the fourteenth transistor and the gate of the fifteenth transistor are both connected to the second input Signal, the first electrode of the fourteenth transistor is connected to the first node, the second electrode of the fourteenth transistor is connected to the first electrode of the fifteenth transistor and the fourth node, and the The second electrode of the fifteen transistor is connected to the first low potential signal.
  • the second pull-down module includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor, and the gate of the sixteenth transistor is connected to the gate of the seventeenth transistor
  • the n+2 stage transmits signals, the first electrode of the sixteenth transistor is connected to the first node, and the second electrode of the sixteenth transistor is connected to the first electrode of the seventeenth transistor and the At the fourth node, the second electrode of the seventeenth transistor is connected to the first low potential signal, the gate of the eighteenth transistor is connected to the n-2th stage signal, the eighteenth transistor The first electrode of the transistor is connected to the second low potential signal, and the first electrode of the eighteenth transistor is connected to the third node.
  • the third pull-down module includes a nineteenth transistor and a twentieth transistor, the gate of the nineteenth transistor is connected to the second node, and the first of the nineteenth transistor The electrode is connected to the second low potential signal, the second electrode of the nineteenth transistor is connected to the first electrode of the twentieth transistor, the gate of the twentieth transistor is connected to the reset signal, and the second The second electrode of the ten transistor is connected to the third node.
  • the first pull-down sustain module includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a twenty-first transistor.
  • the gate of the twenty-first transistor and the gate of the twenty-second transistor are connected to the third node, and the first electrode of the twenty-first transistor is connected to the first node, so The second electrode of the twenty-first transistor is connected to the first electrode of the twenty-second transistor and the fourth node, and the second electrode of the twenty-second transistor is connected to the first low potential signal, so The gate and first electrode of the twenty-third transistor are connected to the high potential signal, the second electrode of the twenty-third transistor is connected to the first electrode of the twenty-fourth transistor, and the twenty-fourth transistor is connected to the first electrode of the twenty-fourth transistor.
  • the gate of the transistor is connected to the first node, the second electrode of the twenty-fourth transistor is connected to a second low-potential signal, and the gate of the twenty-fifth transistor is connected to the second of the twenty-third transistor.
  • An electrode, the first electrode of the twenty-fifth transistor is connected to the high potential signal, and the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor and the third node,
  • the gate of the twenty-sixth transistor is connected to the first node, and the second electrode of the twenty-sixth transistor is connected to the second low potential signal.
  • the second pull-down sustain module includes a twenty-seventh transistor, a twenty-eighth transistor, and a twenty-ninth transistor.
  • the gate of the twenty-seventh transistor and the twenty-eighth transistor The gate of the twenty-seventh transistor and the gate of the twenty-ninth transistor are both connected to the third node, the first electrode of the twenty-seventh transistor is connected to the first low potential signal, and the second The electrode is connected to the n-th stage signal, the first electrode of the twenty-eighth transistor is connected to the third low-potential signal, the second electrode of the twenty-eighth transistor is connected to the first output signal, the The first electrode of the twenty-ninth transistor is connected to the third low potential signal, and the second electrode of the twenty-ninth transistor is connected to the second output signal.
  • the first input signal, the second input signal, and the reset signal are all provided by an external sequencer.
  • the present application also provides a display panel, including a GOA circuit, the GOA circuit includes m cascaded GOA units, wherein the nth level GOA unit includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node during the display time period;
  • the logical addressing module includes a second node, the logical addressing module is connected to the first node, and is configured to raise the potential of the second node twice during the display time period, and in the blank time period , Pulling up the potential of the first node through the second node;
  • a pull-up module connected to the first node, for pulling up the potentials of the n-th stage transmission signal, the first output signal, and the second output signal;
  • a first pull-down module connected to the first node, and used to pull down the potential of the first node during the blank time period
  • the second pull-down module is connected to the first node and the third node, and is used to pull down the potentials of the first node and the third node respectively during the display time period;
  • a third pull-down module connected to the third node and the second pull-down module, and is used to pull down the potential of the third node during a blank time period;
  • a first pull-down maintenance module including the third node, the first pull-down maintenance module is connected to the first node and the first pull-down module, and is configured to maintain a low potential of the first node;
  • the second pull-down maintaining module is connected to the third node and the pull-up module, and is used to maintain the low level of the n-th stage transmission signal, the first output signal, and the second output signal.
  • the pull-up control module includes a first transistor and a second transistor, and the gate and the first electrode of the first transistor and the gate of the second transistor are both connected to the n-th transistor. Two-level signal transmission, the second electrode of the first transistor is connected to the first electrode and the fourth node of the second transistor, and the second electrode of the second transistor is connected to the first node.
  • the logical addressing module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a first storage capacitor.
  • the gate of the third transistor is connected to the n-2th stage signal, the first electrode of the third transistor is connected to the first low potential signal, and the second electrode of the third transistor is connected to the first signal of the fourth transistor.
  • the gate and the second electrode of the fourth transistor are both connected to a high potential signal, the gate of the fifth transistor is connected to the first input signal, and the first electrode of the fifth transistor is connected to the n-2th stage Signal, the second electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the first electrode of the seventh transistor, the gate of the sixth transistor is connected to the first input signal, so The second electrode of the sixth transistor and the gate of the seventh transistor are both connected to the second node, the second electrode of the seventh transistor is connected to the high potential signal, and the gate of the eighth transistor is connected to In the second node, the first electrode of the eighth transistor is connected to the high potential signal, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor, and the gate of the ninth transistor is Connect the reset signal, the second electrode of the ninth transistor is connected to the first node, the first plate of the first storage capacitor is connected to the second electrode of the third transistor, and the second plate is connected to the first node. Two nodes.
  • the pull-up module includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a second storage capacitor, and a third storage capacitor.
  • the gate of the tenth transistor The electrode, the gate of the eleventh transistor, and the gate of the twelfth transistor are all connected to the first node, the first electrode of the tenth transistor is connected to the first clock signal, and the gate of the tenth transistor is The second electrode is connected to the n-th stage signal, the first electrode of the eleventh transistor is connected to a second clock signal, the second electrode of the eleventh transistor is connected to the first output signal, and the first electrode of the eleventh transistor is connected to the first output signal.
  • the first electrode of the twelfth transistor is connected to the third clock signal, the second electrode of the twelfth transistor is connected to the second output signal, the gate of the thirteenth transistor is connected to the first node, and the first node is connected to the gate of the thirteenth transistor.
  • the first electrode of the thirteenth transistor is connected to the fourth node, the second electrode of the thirteenth transistor is connected to the first output signal, and the first plate of the second storage capacitor is connected to the first node,
  • the second plate is connected to the first output signal, the first plate of the third storage capacitor is connected to the first node, and the second plate is connected to the second output signal.
  • the first pull-down module includes a fourteenth transistor and a fifteenth transistor, and the gate of the fourteenth transistor and the gate of the fifteenth transistor are both connected to the second input Signal, the first electrode of the fourteenth transistor is connected to the first node, the second electrode of the fourteenth transistor is connected to the first electrode of the fifteenth transistor and the fourth node, and the The second electrode of the fifteen transistor is connected to the first low potential signal.
  • the second pull-down module includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor, and the gate of the sixteenth transistor is connected to the gate of the seventeenth transistor
  • the n+2 stage transmits signals, the first electrode of the sixteenth transistor is connected to the first node, and the second electrode of the sixteenth transistor is connected to the first electrode of the seventeenth transistor and the At the fourth node, the second electrode of the seventeenth transistor is connected to the first low potential signal, the gate of the eighteenth transistor is connected to the n-2th stage signal, the eighteenth transistor The first electrode of the transistor is connected to the second low potential signal, and the first electrode of the eighteenth transistor is connected to the third node.
  • the third pull-down module includes a nineteenth transistor and a twentieth transistor, the gate of the nineteenth transistor is connected to the second node, and the first transistor of the nineteenth transistor The electrode is connected to the second low potential signal, the second electrode of the nineteenth transistor is connected to the first electrode of the twentieth transistor, the gate of the twentieth transistor is connected to the reset signal, and the second electrode of the nineteenth transistor is connected to the reset signal.
  • the second electrode of the twenty transistor is connected to the third node.
  • the first pull-down sustain module includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a twenty-first transistor.
  • Six transistors, the gate of the twenty-first transistor and the gate of the twenty-second transistor are connected to the third node, and the first electrode of the twenty-first transistor is connected to the first node, so The second electrode of the twenty-first transistor is connected to the first electrode of the twenty-second transistor and the fourth node, and the second electrode of the twenty-second transistor is connected to the first low potential signal, so
  • the gate and first electrode of the twenty-third transistor are connected to the high potential signal, the second electrode of the twenty-third transistor is connected to the first electrode of the twenty-fourth transistor, and the twenty-fourth transistor is connected to the first electrode of the twenty-fourth transistor.
  • the gate of the transistor is connected to the first node, the second electrode of the twenty-fourth transistor is connected to a second low-potential signal, and the gate of the twenty-fifth transistor is connected to the second of the twenty-third transistor.
  • An electrode, the first electrode of the twenty-fifth transistor is connected to the high potential signal, and the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor and the third node,
  • the gate of the twenty-sixth transistor is connected to the first node, and the second electrode of the twenty-sixth transistor is connected to the second low potential signal.
  • the second pull-down sustain module includes a twenty-seventh transistor, a twenty-eighth transistor, and a twenty-ninth transistor.
  • the gate of the twenty-seventh transistor, the twenty-ninth transistor The gates of the eight transistors and the gates of the twenty-ninth transistor are both connected to the third node, the first electrode of the twenty-seventh transistor is connected to the first low-potential signal, and the twenty-seventh transistor is connected to the first low potential signal.
  • the second electrode of the transistor is connected to the n-th stage transmitting signal, the first electrode of the twenty-eighth transistor is connected to a third low potential signal, and the second electrode of the twenty-eighth transistor is connected to the first output Signal, the first electrode of the twenty-ninth transistor is connected to the third low potential signal, and the second electrode of the twenty-ninth transistor is connected to the second output signal.
  • the first input signal, the second input signal, and the reset signal are all provided by an external timing device.
  • the beneficial effects of the present application provides a GOA circuit and a display panel.
  • the GOA circuit includes m cascaded GOA units, where the nth level GOA unit includes a pull-up control module, a logic addressing module, a pull-up module, and a first A pull-down module, a second pull-down module, a third pull-down module, a first pull-down maintenance module, and a second pull-down maintenance module.
  • the pull-up control module is connected to the first node for displaying the first node
  • the logic addressing module includes a second node, the logic addressing module is connected to the first node, and is used to raise the potential of the second node twice during the display time period, In the blank time period, the potential of the first node is pulled up through the second node; the pull-up module is connected to the first node for transmitting the nth stage signal, the first output signal and the second The potential of the output signal is pulled high; the first pull-down module is connected to the first node, and is used to pull the potential of the first node low during the blank period; the second pull-down module is connected to the first node and the third node.
  • the node connection is used to pull down the potentials of the first node and the third node respectively during the display time period;
  • the third pull-down module is connected to the third node and the second pull-down module and is used to The potential of the third node is pulled down during the time period;
  • the first pull-down maintenance module includes the third node, and the first pull-down maintenance module is connected to the first node and the first pull-down module, Is used to maintain the low potential of the first node;
  • a second pull-down maintaining module is connected to the third node and the pull-up module, and is used to maintain the n-th stage transmission signal, the first output signal, and The low level of the second output signal.
  • the potential of the second node twice during the display period By raising the potential of the second node twice during the display period, the potential of the first node is also higher during the blank period, and the charging rate is ensured, thereby increasing the threshold voltage margin allowed by the GOA circuit.
  • the stability of the GOA circuit is improved, and the development difficulty of the transistor manufacturing process is reduced.
  • FIG. 1 is a schematic diagram of the structure of a GOA circuit in the prior art.
  • FIG. 2 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • FIG. 3 is a timing diagram of each signal of the GOA circuit in the embodiment of the application during the display period and the blank period.
  • FIG. 4 is a timing diagram of various signals of the GOA circuit provided in an embodiment of the application during the display time period.
  • FIG. 5 is a timing diagram of various signals in the blank period of the GOA circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of the comparison of the influence of the overall threshold voltage deviation on the potential of the second node in the GOA circuit of this application and the GOA circuit of the prior art.
  • FIG. 7 is a schematic diagram of the comparison of the influence of the overall deviation of the threshold voltage on the first output signal in the GOA circuit of this application and the GOA circuit of the prior art.
  • the present application provides a GOA circuit and a display panel to alleviate the technical problem of high difficulty in the development of the transistor manufacturing process in the existing GOA circuit.
  • the GOA circuit includes m cascaded GOA units.
  • the n-th GOA unit includes a pull-up control module 100, a logical addressing module 200, a pull-up module 300, a first pull-down module 400, a second pull-down module 500, and a first pull-down module.
  • the pull-up control module 100 is connected to the first node Q, and is used to pull up the potential of the first node Q during the display period.
  • the logical addressing module 200 includes a second node M.
  • the logical addressing module is connected to the first node and is used to raise the potential of the second node twice during the display time period. The potential of a node is pulled high.
  • the pull-up module 300 is connected to the first node Q, and is used to pull up the potentials of the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n).
  • the first pull-down module 400 is connected to the first node Q, and is used to pull down the potential of the first node Q during the blank period.
  • the second pull-down module 500 is connected to the first node Q and the third node QB, and is used to pull down the potentials of the first node Q and the third node QB respectively during the display time period.
  • the third pull-down module 600 is connected to the third node QB and the second pull-down module 500, and is used to pull down the potential of the third node QB during the blank period.
  • the first pull-down maintenance module 700 includes a third node QB, and the first pull-down maintenance module 700 is connected to the first node Q and the first pull-down module 400 for maintaining the low potential of the first node Q.
  • the second pull-down maintaining module 800 is connected to the third node QB and the pull-up module 300, and is used to maintain the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n). Low potential.
  • the display panel needs to pass through the display time period Promgraming and the blank time period Blank when displaying the picture.
  • the display time period is the actual display time period of each frame
  • the blank time period is the time period between the actual display times of adjacent frames.
  • the charging rate of the first node Q is guaranteed during the blank time period, thereby increasing the threshold voltage margin allowed by the GOA circuit.
  • the stability of the GOA circuit is improved, and the development difficulty of the transistor manufacturing process is reduced.
  • the pull-up control module 100 includes a first transistor T11 and a second transistor T12.
  • the gate and the first electrode of the first transistor T11 and the gate of the second transistor T12 are both connected to the n-2th stage.
  • the second electrode of the first transistor T11 is connected to the first electrode of the second transistor T12, and the second electrode of the second transistor T12 is connected to the first node Q.
  • the logical addressing module 200 includes a third transistor T91, a fourth transistor T92, a fifth transistor T71, a sixth transistor T72, a seventh transistor T73, an eighth transistor T81, a ninth transistor T91, a first storage capacitor Cbt3, and a third transistor
  • the gate of T91 is connected to the n-2th level transmission signal Cout(n-2)
  • the first electrode of the third transistor T91 is connected to the first low-potential signal VGL1
  • the second electrode of the third transistor T91 is connected to the fourth transistor T92.
  • the first electrode, the gate and the second electrode of the fourth transistor T92 are all connected to the high potential signal VGH, the gate of the fifth transistor T71 is connected to the first input signal LSP, and the first electrode of the fifth transistor T71 is connected to the n-2th stage
  • the second electrode of the fifth transistor T71 is connected to the first electrode of the sixth transistor T72 and the first electrode of the seventh transistor T73, and the gate of the sixth transistor T72 is connected to the first input signal.
  • the second electrode of the sixth transistor T72 and the gate of the seventh transistor T73 are both connected to the second node M, the second electrode of the seventh transistor T73 is connected to the high potential signal VGH, and the gate of the eighth transistor T81 is connected to the second node M,
  • the first electrode of the eighth transistor T81 is connected to the high potential signal VGH, the second electrode of the eighth transistor T81 is connected to the first electrode of the ninth transistor T91, the gate of the ninth transistor T91 is connected to the reset signal Total-Reset, and the ninth transistor T91
  • the second electrode of Cbt3 is connected to the first node Q, the first plate of the first storage capacitor Cbt3 is connected to the second electrode of the third transistor T91, and the second plate is connected to the second node M.
  • the pull-up module 300 includes a tenth transistor T23, an eleventh transistor T22, a twelfth transistor T21, a thirteenth transistor T6, a second storage capacitor Cbt1, and a third storage capacitor Cbt2.
  • the gate of a transistor T22 and the gate of the twelfth transistor T21 are both connected to the first node Q, the first electrode of the tenth transistor T23 is connected to the first clock signal CKa, and the second electrode of the tenth transistor T23 is connected to the nth stage.
  • the first electrode of the eleventh transistor T22 is connected to the second clock signal CKb, the second electrode of the eleventh transistor T22 is connected to the first output signal WR(n), and the first electrode of the twelfth transistor T21 is connected to the first output signal WR(n).
  • the electrode is connected to the third clock signal CKc, the second electrode of the twelfth transistor T21 is connected to the second output signal RD(n), the gate of the thirteenth transistor T6 is connected to the first node Q, and the first electrode of the thirteenth transistor T6 Connected to the fourth node N, the second electrode of the thirteenth transistor T6 is connected to the first output signal WR(n), the first plate of the second storage capacitor Cbt1 is connected to the first node Q, and the second plate is connected to the first output signal WR(n), the first plate of the third storage capacitor Cbt2 is connected to the first node Q, and the second plate is connected to the second output signal RD(n).
  • the first pull-down module 400 includes a fourteenth transistor T33 and a fifteenth transistor T34.
  • the gate of the fourteenth transistor T33 and the gate of the fifteenth transistor T34 are both connected to the second input signal VST.
  • the first electrode is connected to the first node Q
  • the second electrode of the fourteenth transistor T33 is connected to the first electrode of the fifteenth transistor T34 and the fourth node N
  • the second electrode of the fifteenth transistor T34 is connected to the first low potential signal VGL1 .
  • the second pull-down module 500 includes a sixteenth transistor T31, a seventeenth transistor T32, and an eighteenth transistor T55.
  • the gate of the sixteenth transistor T31 and the gate of the seventeenth transistor T32 are connected to the n+2 stage signal Cout(n+2), the first electrode of the sixteenth transistor T31 is connected to the first node Q, the second electrode of the sixteenth transistor T31 is connected to the first electrode of the seventeenth transistor T32 and the fourth node N, the seventeenth
  • the second electrode of the transistor T32 is connected to the first low-potential signal VGL1, the gate of the eighteenth transistor T55 is connected to the n-2th level transmission signal Cout(n-2), and the first electrode of the eighteenth transistor T55 is connected to the first With two low-level signals VGL2, the first electrode of the eighteenth transistor T55 is connected to the third node QB.
  • the third pull-down module 600 includes a nineteenth transistor T102 and a twentieth transistor T101.
  • the gate of the nineteenth transistor T102 is connected to the second node, and the first electrode of the nineteenth transistor T102 is connected to the second low potential signal VGL2,
  • the second electrode of the nineteenth transistor T102 is connected to the first electrode of the twentieth transistor T101, the gate of the twentieth transistor T101 is connected to the reset signal Total-Reset, and the second electrode of the twentieth transistor T101 is connected to the third node QB.
  • the first pull-down sustaining module 700 includes a twenty-first transistor T44, a twenty-second transistor T45, a twenty-third transistor T51, a twenty-fourth transistor T52, a twenty-fifth transistor T53, and a twenty-sixth transistor T54,
  • the gate of the twenty-first transistor T44 and the gate of the twenty-second transistor T45 are connected to the third node QB, the first electrode of the twenty-first transistor T44 is connected to the first node Q, and the second electrode of the twenty-first transistor T44 is connected to the first node Q.
  • the electrode is connected to the first electrode of the twenty-second transistor T45 and the fourth node N
  • the second electrode of the twenty-second transistor T45 is connected to the first low-potential signal VGL1
  • the gate of the twenty-third transistor T51 is connected to the first electrode
  • the high potential signal VGH the second electrode of the twenty-third transistor T51 is connected to the first electrode of the twenty-fourth transistor T52
  • the gate of the twenty-fourth transistor T52 is connected to the first node Q
  • the second electrode of the twenty-fourth transistor T52 is connected to the first node Q.
  • the two electrodes are connected to the second low-potential signal VGL2, the gate of the twenty-fifth transistor T53 is connected to the second electrode of the twenty-third transistor T51, the first electrode of the twenty-fifth transistor T53 is connected to the high-potential signal VGH, and the twenty-fifth transistor T53 is connected to the high-potential signal VGH.
  • the second electrode of the five transistor T53 is connected to the first electrode of the twenty-sixth transistor T54 and the third node QB, the gate of the twenty-sixth transistor T54 is connected to the first node Q, and the second electrode of the twenty-sixth transistor T54 is connected The second low level signal VGL2.
  • the second pull-down sustain module 800 includes a twenty-seventh transistor T43, a twenty-eighth transistor T42, and a twenty-ninth transistor T41, the gate of the twenty-seventh transistor T43, the gate of the twenty-eighth transistor T42, and the second The gates of the nineteenth transistor T41 are all connected to the third node QB, the first electrode of the twenty-seventh transistor T43 is connected to the first low-potential signal VGL1, and the second electrode of the twenty-seventh transistor T43 is connected to the n-th stage transmission signal Cout.
  • the first electrode of the twenty-eighth transistor T42 is connected to the third low potential signal VGL3, the second electrode of the twenty-eighth transistor T42 is connected to the first output signal WR(n), and the second electrode of the twenty-ninth transistor T41 is connected to the first output signal WR(n).
  • One electrode is connected to the third low potential signal VGL3, and the second electrode of the twenty-ninth transistor T41 is connected to the second output signal RD(n).
  • the GOA circuit of the present application includes m cascaded GOA units, wherein the stage transmission signal output by the nth stage GOA unit is the nth stage transmission signal Cout(n), 2 ⁇ n ⁇ m, and n is an integer .
  • the n-2th level transmission signal Cout(n-2) is the level transmission signal before and one level apart from the nth level transmission signal Cout(n), and the n+2 level transmission signal Cout(n+2) It is the level transmission signal before and one level apart from the nth level transmission signal Cout(n).
  • the first input signal LSP, the second input signal VST, and the reset signal Total-Reset are all provided by an external timing device.
  • the GOA circuit provided by the embodiment of the application is a real-time compensation circuit, which requires GOA to output a normal drive timing display screen in the display time period corresponding to each frame, and output a wide pulse timing for threshold voltage during the blank time period between each frame For Vth detection.
  • FIG. 3 shows the timing of each signal in the display period Promgraming and blank period Blank of the GOA circuit of the embodiment of the present application, wherein the voltage setting values of each signal at a high potential and a low potential are shown in Table 1.
  • the display time period includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4, and a fifth display stage S5.
  • the n-2th level transmission signal Cout(n-2) rises to a high potential
  • the first transistor T11 and the second transistor T12 are turned on
  • the first node Q is pulled to a high potential
  • the second The fourteenth transistor T52, the twenty-sixth transistor T54, the tenth transistor T23, the eleventh transistor T22, and the twelfth transistor T21 are turned on. Since the first node Q and the third node QB are connected to form an inverter structure, The potentials between them are opposite. Therefore, the third node QB is at a low potential.
  • the twenty-seventh transistor T43, the twenty-eighth transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44, and the twenty-second transistor T45 are all turned off, at the same time, the n+2 level transmission signal Cout(n+2) is at a low level, the sixteenth transistor T31 and the seventeenth transistor T32 are turned off, the second input signal VST is at a low level, and the fourteenth transistor T33 and the fifteenth transistor T34 are turned off.
  • the first timing signal CKa, the second timing signal CKb, and the third timing signal CKc are at a low level, and the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n) The output is low. Since the n-2th stage transmission signal Cout(n-2) is at a high level, the third transistor T91 is turned on, and the point P connected to the first plate of the first storage capacitor Cbt3 is reset to a low level, and the second plate is connected At the same time, the second node M is low.
  • the first input signal LSP rises to a high potential.
  • the n-2th stage transmission signal Cout(n-2) maintains a high potential
  • the second node M is raised to a high potential
  • the fourth transistor T92 When it is turned on, point P maintains a low level. Since signals such as the reset signal Totaol-Rest and the second input signal VST are at a low level, the first node Q maintains a high level, and the third node QB maintains a low level.
  • the first input signal LSP drops from a high level to a low level
  • the fifth transistor T71 and the sixth transistor T72 are turned off
  • the n-2th stage transfer signal Cout(n-2) changes from a high level to a low level.
  • Low potential so the third transistor T91 is turned off, and the potential at point P is switched from a low potential to a high potential.
  • the second node M is coupled to a higher potential.
  • the first timing signal Cka, the second timing signal CKb, and the third timing signal CKc change from a low level to a high level, so the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal
  • the potential of RD(n) is also raised to a high potential, and at the same time, due to the existence of the second storage capacitor Cbt1 and the third storage capacitor Cbt2, the first node Q is coupled to a higher potential.
  • the first timing signal Cka, the second timing signal CKb, and the third timing signal CKc are switched from a high level to a low level, and the n-th stage transmission signal Cout(n), the first output signal WR(n ) And the potential of the second output signal RD(n) is pulled to a low potential, and the signal coupling of the first node Q is reduced, which is consistent with the potential in the second display stage S2.
  • the n+2 level transmission signal Cout(n+2) rises from a low level to a high level
  • the sixteenth transistor T31 and the seventeenth transistor T32 are turned on, and the potential of the first node Q is pulled down
  • the twenty-fourth transistor T52, the twenty-sixth transistor T54, the tenth transistor T23, the eleventh transistor T22, and the twelfth transistor T21 are turned off, and the potential of the third node QB is raised to a high potential.
  • the seven transistors T43, the twenty-eighth transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44, and the twenty-second transistor T45 are all turned on, the first node Q, the n-th stage transmission signal Cout(n), The first output signal WR(n) and the second output signal RD(n) maintain a low level.
  • the blank period includes a first blank period B1, a second blank period B2, a third blank period B3, and a fourth blank period B4.
  • the reset signal Total reset rises to a high potential
  • the ninth transistor T82 is turned on, and the potential of the first node Q is pulled to a high potential.
  • the twenty-fourth transistor T52, the twenty-sixth transistor T54, and the tenth transistor T23, the eleventh transistor T22 and the twelfth transistor T21 are turned on. Since the first node Q and the third node QB are connected to form an inverter structure, the potential between them is opposite, so the third node QB is at a low level.
  • the twenty-seventh transistor T43, the twenty-eighth transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44, and the twenty-second transistor T45 are all turned off, and at the same time, the n+2 stage transmits the signal Cout (n+2) is at a low potential, the sixteenth transistor T31 and the seventeenth transistor T32 are turned off, the second input signal VST is at a low potential, and the fourteenth transistor T33 and the fifteenth transistor T34 are turned off.
  • the first timing signal CKa, the second timing signal CKb, and the third timing signal CKc are at a low level, and the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n) The output is low.
  • the reset signal Toatal reset drops to a low level
  • the ninth transistor T82 is turned off
  • the first timing signal Cka maintains a low level
  • the second timing signal CKb and the third timing signal CKc rise to a high level
  • the nth stage The level transmission signal Cout(n) maintains a low level
  • the first output signal WR(n) and the second output signal RD(n) output a high level.
  • the first node Q is coupled to a higher potential.
  • the second input signal VST rises from a low potential to a high potential
  • the fourteenth transistor T33 and the fifteenth transistor T34 are turned on, the potential of the first node Q is pulled down to a low potential
  • the twenty-fourth The transistor T52, the twenty-sixth transistor T54, the tenth transistor T23, the eleventh transistor T22, and the twelfth transistor T21 are turned off, and the potential of the third node QB is raised to a high potential.
  • the twenty-seventh transistor T43, the twenty-eighth transistor The transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44, and the twenty-second transistor T45 are all turned on, and the first node Q, the first output signal WR(n) and the second output signal RD(n) are pulled down To a low level, the n-th stage transmission signal Cout(n) maintains a low level.
  • the first input signal LSP rises to a high level
  • the fifth transistor T71 and the sixth transistor T72 are turned on, and because the n-2th stage transmission signal Cout(n-2) is at a low level, the second node M is reset to a low level, and the eighth transistor T81 is turned off.
  • the first node Q, the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n) maintain a low level.
  • the GOA circuit provided by the embodiment of the present application is a real-time compensation GOA circuit, and through the above process, a driving signal is provided for the scan line, so that the display panel can display a picture.
  • the third transistor T91 and the fourth transistor T92 are both turned on, so that P The potential of point and the second node M are low.
  • the third transistor T91 and the fourth transistor T92 are both turned on, the potential of point P remains low, and the potential of the second node M is pulled up for the first time.
  • the third transistor T91 is turned off, and the fourth transistor T92 is turned on, which pulls the potential of point P high. Due to the coupling effect, the potential of the second node M is pulled high for the second time.
  • the potential of the first node Q is pulled higher compared to the prior art, and the charging rate is ensured, thereby increasing the allowable threshold voltage margin of the GOA circuit and improving the stability of the GOA circuit , which reduces the difficulty of the development of the transistor manufacturing process.
  • FIG. 6 a comparison diagram of the influence of the overall deviation of the threshold voltage in the GOA circuit of the present application and the prior art GOA circuit on the potential of the second node M, where the first curve A1 is the threshold voltage of 0 in the prior art.
  • the second curve A2 is the potential waveform of the second node M when the threshold voltage is 0 in this application
  • the third curve B1 is the potential of the second node M when the threshold voltage is 5V in the prior art.
  • Waveform, the fourth curve B2 is the potential waveform of the second node M when the threshold voltage is 5V in this application.
  • FIG. 7 a comparison diagram of the influence of the overall deviation of the threshold voltage in the GOA circuit of this application and the GOA circuit of the prior art on the first output signal WR(n), wherein the fifth curve C1 is the threshold in the prior art The potential waveform of the first output signal WR(n) when the voltage is 0, the sixth curve C2 is the potential waveform of the first output signal WR(n) in the application when the threshold voltage is 0, and the seventh curve D1 is in the prior art The potential waveform of the first output signal WR(n) when the threshold voltage is 5V, and the eighth curve D2 is the potential waveform of the first output signal WR(n) when the threshold voltage is 5V in this application.
  • the GOA circuit of the present application raises the potential of the second node M twice during the display period, so that during the blank period, the potential of the first node Q is also higher, and the charging rate is obtained.
  • the guarantee increases the allowable threshold voltage margin of the GOA circuit, improves the stability of the GOA circuit, and reduces the development difficulty of the transistor manufacturing process.
  • the present application also provides a display panel including the GOA circuit described in any of the above embodiments.
  • the present application provides a GOA circuit and a display panel.
  • the GOA circuit includes m cascaded GOA units, where the nth level GOA unit includes a pull-up control module, a logic addressing module, a pull-up module, a first pull-down module, and a first pull-down module.
  • the second pull-down module, the third pull-down module, the first pull-down maintenance module, and the second pull-down maintenance module is included in the GOA circuit.
  • the pull-up control module is connected to the first node and is used to pull the potential of the first node high during the display time period; logical addressing The module includes a second node, the logical addressing module is connected to the first node, and is used to pull up the potential of the second node twice during the display time period, and pull the potential of the first node through the second node during the blank time period.
  • the pull-up module is connected to the first node and used to pull up the potentials of the n-th stage transmission signal, the first output signal and the second output signal;
  • the first pull-down module is connected to the first node and is used to The time period pulls down the potential of the first node;
  • the second pull-down module is connected to the first node and the third node, and is used to pull down the potentials of the first node and the third node respectively during the display time period;
  • the third pull-down module is connected with The third node is connected to the second pull-down module, and is used to pull down the potential of the third node during the blank period;
  • the first pull-down maintenance module includes the third node, and the first pull-down maintenance module is connected to the first node It is connected to the first pull-down module to maintain the low potential of the first node;
  • the second pull-down maintenance module is connected to the third node and the pull-up module to maintain the n-th stage transmission signal, the first output signal, and the
  • the potential of the second node twice during the display period By raising the potential of the second node twice during the display period, the potential of the first node is also higher during the blank period, and the charging rate is ensured, thereby increasing the threshold voltage margin allowed by the GOA circuit.
  • the stability of the GOA circuit is improved, and the development difficulty of the transistor manufacturing process is reduced.

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Abstract

本申请提供一种GOA电路和显示面板，GOA电路中第n级GOA单元包括与第一节点连接的上拉控制模块、逻辑寻址模块、上拉模块、第一下拉模块、第二下拉模块、第一下拉维持模块，与第三节点连接的第二下拉模块、第三下拉模块、第二下拉维持模块，以及逻辑寻址模块。逻辑寻址模块对第二节点电位进行两次拉高，有利于阈值电压余量提升。

Description

GOA电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种GOA电路和显示面板。
背景技术
现有的实时补偿型GOA电路结构如图1所示，GOA电路包括晶体管Ta、Tb、Tc、T1、T1A、T1B、T1C、T3、T3A、T3nA、T3nB、T3nC、T3n、T3q、T4、T4l、T4q、T5、T5A、T5B、T5q、T6、T6cr、T7、T7cr、T8、T9和存储电容Cm1、Cm2、Cm3，各晶体管的连接方式如图1中所示，GOA电路还包括第一节点Q、第二节点M、第三节点Qb、第五节点Mh和第六节点Qh，其中，C(n-3)、C(n+3)、COUT(n)均为级传信号，CRCLK、SCCLK和SECLK均为时序信号，LSP、VST均为GOA电路的输入信号，SCOUT(n)和SEOUT(n)均为GOA电路的输出信号，GVDD为电源高电位信号，GVSS0、GVSS1和GVSS2均为电源低电位信号，G-RESET为复位信号。
COUT(n)、SCOUT(n)和SEOUT(n)为提供给显示面板中扫描线的驱动信号，为保证显示面板中扫描线能接受到驱动信号，以打开其控制的各晶体管，必须保证COUT(n)、SCOUT(n)和SEOUT(n)输出正常。由于T6、T6cr和T8的栅极与第一节点Q连接，各输出信号的输出由第一节点Q来控制，而Q点充电率是否充足由第二节点M的电位来控制。在显示时间段，在LSP和C(n-3)为高电位时，Ta和Tb打开，第二节点M的电位为高电位，在空白时间段，G-RESET为高电位时，T1B和T1C打开，第一节点Q被第二节点M的电位拉高，从而在CRCLK、SCCLK和SECLK为高电位时，将T6、T6cr和T8打开，输出高电位的COUT(n)、SCOUT(n)和SEOUT(n)，提供给扫描线。由此可见，第一节点Q的电位高低，对输出信号的正常输出至关重要。通常情况下，第一节点Q可以控制输出信号的正常输出，然而，在GOA电路中阈值电压余量发生正向移动时，Q点需要更高的电位才能保证COUT(n)、SCOUT(n)和SEOUT(n)的正常输出，为保证GOA电路能够正常输出，需要减小GOA电路允许的阈值电压余量。
然而，现有技术的GOA电路为实时补偿型电路，结构较为复杂，因此在GOA电路自身允许的阈值电压余量(Vth margin)较小时，需要晶体管的制程极为稳定，因而晶体管制程的开发难度较高。
因此，现有的GOA电路存在晶体管制程的开发难度较高的技术问题，需要改进。
技术问题
本申请提供一种GOA电路和显示面板，以缓解现有GOA电路中晶体管制程的开发难度较高的技术问题。
技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种GOA电路，包括m个级联的GOA单元，其中第n级GOA单元包括：
上拉控制模块，与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；
逻辑寻址模块，包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；
上拉模块，与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；
第一下拉模块，与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；
第二下拉模块，与所述第一节点和第三节点连接，用于在显示时间段分别将所述第一节点和所述第三节点的电位拉低；
第三下拉模块，与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节点的电位拉低；
第一下拉维持模块，包括所述第三节点，所述第一下拉维持模块与所述第一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；
第二下拉维持模块，与所述第三节点和所述上拉模块连接，用于维持所述 第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。
在本申请的GOA电路中，所述上拉控制模块包括第一晶体管和第二晶体管，所述第一晶体管的栅极和第一电极、以及所述第二晶体管的栅极均连接第n-2级级传信号，所述第一晶体管的第二电极连接所述第二晶体管的第一电极，所述第二晶体管的第二电极连接所述第一节点。
在本申请的GOA电路中，所述逻辑寻址模块包括第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第一存储电容，所述第三晶体管的栅极连接第n-2级级传信号，所述第三晶体管的第一电极连接第一低电位信号，所述第三晶体管的第二电极连接第四晶体管的第一电极，所述第四晶体管的栅极和第二电极均连接高电位信号，所述第五晶体管的栅极连接第一输入信号，所述第五晶体管的第一电极连接第n-2级级传信号，所述第五晶体管的第二电极连接第六晶体管的第一电极和第七晶体管的第一电极，所述第六晶体管的栅极连接所述第一输入信号，所述第六晶体管的第二电极和所述第七晶体管的栅极均连接所述第二节点，所述第七晶体管的第二电极连接所述高电位信号，所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一电极连接所述高电位信号，所述第八晶体管的第二电极连接所述第九晶体管的第一电极，所述第九晶体管的栅极连接复位信号，所述第九晶体管的第二电极连接所述第一节点，所述第一存储电容的第一极板连接所述第三晶体管的第二电极，第二极板连接所述第二节点。
在本申请的GOA电路中，所述上拉模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第二存储电容和第三存储电容，所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均连接所述第一节点，所述第十晶体管的第一电极连接第一时钟信号，所述第十晶体管的第二电极连接所述第n级级传信号，所述第十一晶体管的第一电极连接第二时钟信号，所述第十一晶体管的第二电极连接所述第一输出信号，所述第十二晶体管的第一电极连接第三时钟信号，所述第十二晶体管的第二电极连接所述第二输出信号，所述第十三晶体管的栅极连接所述第一节点，所述第十三晶体管的第一电极连接第四节点，所述第十三晶体管的第二电极连接所述第一输出信号，所述第二存储电容的第一极板连接所述第一节点，第二极板连接所述第一 输出信号，所述第三存储电容的第一极板连接所述第一节点，第二极板连接所述第二输出信号。
在本申请的GOA电路中，所述第一下拉模块包括第十四晶体管和第十五晶体管，所述第十四晶体管的栅极和所述第十五晶体管的栅极均连接第二输入信号，所述第十四晶体管的第一电极连接所述第一节点，所述第十四晶体管的第二电极连接所述第十五晶体管的第一电极和所述第四节点，所述第十五晶体管的第二电极连接所述第一低电位信号。
在本申请的GOA电路中，所述第二下拉模块包括第十六晶体管、第十七晶体管和第十八晶体管，所述第十六晶体管的栅极和所述第十七晶体管的栅极连接第n+2级级传信号，所述第十六晶体管的第一电极连接所述第一节点，所述第十六晶体管的第二电极连接所述第十七晶体管的第一电极和所述第四节点，所述第十七晶体管的第二电极连接所述第一低电位信号，所述第十八晶体管的栅极连接所述第n-2级级传信号，所述第十八晶体管的第一电极连接所述第二低电位信号，所述第十八晶体管的第一电极连接所述第三节点。
在本申请的GOA电路中，所述第三下拉模块包括第十九晶体管和第二十晶体管，所述第十九晶体管的栅极连接所述第二节点，所述第十九晶体管的第一电极连接所述第二低电位信号，所述第十九晶体管的第二电极连接所述二十晶体管的第一电极，所述第二十晶体管的栅极连接所述复位信号，所述第二十晶体管的第二电极连接所述第三节点。
在本申请的GOA电路中，所述第一下拉维持模块包括第二十一晶体管、第二十二晶体管、第二十三晶体管、第二十四晶体管、第二十五晶体管和第二十六晶体管，所述第二十一晶体管的栅极和所述第二十二晶体管的栅极连接所述第三节点，所述第二十一晶体管的第一电极连接所述第一节点，所述第二十一晶体管的第二电极连接所述第二十二晶体管的第一电极和所述第四节点，所述第二十二晶体管的第二电极连接所述第一低电位信号，所述第二十三晶体管的栅极和第一电极连接所述高电位信号，所述第二十三晶体管的第二电极连接所述第二十四晶体管的第一电极，所述第二十四晶体管的栅极连接所述第一节点，所述第二十四晶体管的第二电极连接第二低电位信号，所述第二十五晶体管的栅极连接所述第二十三晶体管的第二电极，所述第二十五晶体管的第一电 极连接所述高电位信号，所述第二十五晶体管的第二电极连接所述第二十六晶体管的第一电极和所述第三节点，所述第二十六晶体管的栅极连接所述第一节点，所述第二十六晶体管的第二电极连接所述第二低电位信号。
在本申请的GOA电路中，所述第二下拉维持模块包括第二十七晶体管、第二十八晶体管和第二十九晶体管，所述第二十七晶体管的栅极、第二十八晶体管的栅极以及第二十九晶体管的栅极均连接所述第三节点，所述第二十七晶体管的第一电极连接所述第一低电位信号，所述第二十七晶体管的第二电极连接所述第n级级传信号，所述第二十八晶体管的第一电极连接第三低电位信号，所述第二十八晶体管的第二电极连接所述第一输出信号，所述第二十九晶体管的第一电极连接所述第三低电位信号，所述第二十九晶体管的第二电极连接所述第二输出信号。
在本申请的GOA电路中，所述第一输入信号、所述第二输入信号和所述复位信号均由外部时序器提供。
本申请还提供一种显示面板，包括GOA电路，所述GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括：
上拉控制模块，与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；
逻辑寻址模块，包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；
上拉模块，与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；
第一下拉模块，与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；
第二下拉模块，与所述第一节点和第三节点连接，用于在显示时间段分别将所述第一节点和所述第三节点的电位拉低；
第三下拉模块，与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节点的电位拉低；
第一下拉维持模块，包括所述第三节点，所述第一下拉维持模块与所述第 一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；
第二下拉维持模块，与所述第三节点和所述上拉模块连接，用于维持所述第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。
在本申请的显示面板中，所述上拉控制模块包括第一晶体管和第二晶体管，所述第一晶体管的栅极和第一电极、以及所述第二晶体管的栅极均连接第n-2级级传信号，所述第一晶体管的第二电极连接所述第二晶体管的第一电极和第四节点，所述第二晶体管的第二电极连接所述第一节点。
在本申请的显示面板中，所述逻辑寻址模块包括第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第一存储电容，所述第三晶体管的栅极连接第n-2级级传信号，所述第三晶体管的第一电极连接第一低电位信号，所述第三晶体管的第二电极连接所述第四晶体管的第一电极，所述第四晶体管的栅极和第二电极均连接高电位信号，所述第五晶体管的栅极连接第一输入信号，所述第五晶体管的第一电极连接第n-2级级传信号，所述第五晶体管的第二电极连接所述第六晶体管的第一电极和所述第七晶体管的第一电极，所述第六晶体管的栅极连接所述第一输入信号，所述第六晶体管的第二电极和所述第七晶体管的栅极均连接所述第二节点，所述第七晶体管的第二电极连接所述高电位信号，所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一电极连接所述高电位信号，所述第八晶体管的第二电极连接所述第九晶体管的第一电极，所述第九晶体管的栅极连接复位信号，所述第九晶体管的第二电极连接所述第一节点，所述第一存储电容的第一极板连接所述第三晶体管的第二电极，第二极板连接所述第二节点。
在本申请的显示面板中，所述上拉模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第二存储电容和第三存储电容，所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均连接所述第一节点，所述第十晶体管的第一电极连接第一时钟信号，所述第十晶体管的第二电极连接所述第n级级传信号，所述第十一晶体管的第一电极连接第二时钟信号，所述第十一晶体管的第二电极连接所述第一输出信号，所述第十二晶体管的第一电极连接第三时钟信号，所述第十二晶体管的第二电极连接所述第二输出信号，所述第十三晶体管的栅极连接所述第一节点，所述第十三晶体管 的第一电极连接所述第四节点，所述第十三晶体管的第二电极连接所述第一输出信号，所述第二存储电容的第一极板连接所述第一节点，第二极板连接所述第一输出信号，所述第三存储电容的第一极板连接所述第一节点，第二极板连接所述第二输出信号。
在本申请的显示面板中，所述第一下拉模块包括第十四晶体管和第十五晶体管，所述第十四晶体管的栅极和所述第十五晶体管的栅极均连接第二输入信号，所述第十四晶体管的第一电极连接所述第一节点，所述第十四晶体管的第二电极连接所述第十五晶体管的第一电极和所述第四节点，所述第十五晶体管的第二电极连接所述第一低电位信号。
在本申请的显示面板中，所述第二下拉模块包括第十六晶体管、第十七晶体管和第十八晶体管，所述第十六晶体管的栅极和所述第十七晶体管的栅极连接第n+2级级传信号，所述第十六晶体管的第一电极连接所述第一节点，所述第十六晶体管的第二电极连接所述第十七晶体管的第一电极和所述第四节点，所述第十七晶体管的第二电极连接所述第一低电位信号，所述第十八晶体管的栅极连接所述第n-2级级传信号，所述第十八晶体管的第一电极连接所述第二低电位信号，所述第十八晶体管的第一电极连接所述第三节点。
在本申请的显示面板中，所述第三下拉模块包括第十九晶体管和第二十晶体管，所述第十九晶体管的栅极连接所述第二节点，所述第十九晶体管的第一电极连接所述第二低电位信号，所述第十九晶体管的第二电极连接所述第二十晶体管的第一电极，所述第二十晶体管的栅极连接所述复位信号，所述第二十晶体管的第二电极连接所述第三节点。
在本申请的显示面板中，所述第一下拉维持模块包括第二十一晶体管、第二十二晶体管、第二十三晶体管、第二十四晶体管、第二十五晶体管和第二十六晶体管，所述第二十一晶体管的栅极和所述第二十二晶体管的栅极连接所述第三节点，所述第二十一晶体管的第一电极连接所述第一节点，所述第二十一晶体管的第二电极连接所述第二十二晶体管的第一电极和所述第四节点，所述第二十二晶体管的第二电极连接所述第一低电位信号，所述第二十三晶体管的栅极和第一电极连接所述高电位信号，所述第二十三晶体管的第二电极连接所述第二十四晶体管的第一电极，所述第二十四晶体管的栅极连接所述第一节 点，所述第二十四晶体管的第二电极连接第二低电位信号，所述第二十五晶体管的栅极连接所述第二十三晶体管的第二电极，所述第二十五晶体管的第一电极连接所述高电位信号，所述第二十五晶体管的第二电极连接所述第二十六晶体管的第一电极和所述第三节点，所述第二十六晶体管的栅极连接所述第一节点，所述第二十六晶体管的第二电极连接所述第二低电位信号。
在本申请的显示面板中，所述第二下拉维持模块包括第二十七晶体管、第二十八晶体管和第二十九晶体管，所述第二十七晶体管的栅极、所述第二十八晶体管的栅极以及所述第二十九晶体管的栅极均连接所述第三节点，所述第二十七晶体管的第一电极连接所述第一低电位信号，所述第二十七晶体管的第二电极连接所述第n级级传信号，所述第二十八晶体管的第一电极连接第三低电位信号，所述第二十八晶体管的第二电极连接所述第一输出信号，所述第二十九晶体管的第一电极连接所述第三低电位信号，所述第二十九晶体管的第二电极连接所述第二输出信号。
在本申请的显示面板中，所述第一输入信号、所述第二输入信号和所述复位信号均由外部时序器提供。
有益效果
本申请的有益效果：本申请提供一种GOA电路和显示面板，GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括上拉控制模块、逻辑寻址模块、上拉模块、第一下拉模块、第二下拉模块、第三下拉模块、第一下拉维持模块和第二下拉维持模块，上拉控制模块与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；逻辑寻址模块包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；上拉模块与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；第一下拉模块与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；第二下拉模块与所述第一节点和第三节点连接，用于在显示时间段分别将所述第一节点和所述第三节点的电位拉低；第三下拉模块与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节 点的电位拉低；第一下拉维持模块包括所述第三节点，所述第一下拉维持模块与所述第一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；第二下拉维持模块与所述第三节点和所述上拉模块连接，用于维持所述第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。通过在显示时间段对第二节点的电位进行两次拉高，使得在空白时间段，第一节点的电位也更高，充电率得到保证，进而使得GOA电路允许的阈值电压余量提升，提高了GOA电路的稳定性，降低了晶体管制程的开发难度。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的GOA电路的结构示意图。
图2为本申请实施例提供的GOA电路的结构示意图。
图3为本申请实施例的GOA电路在显示时间段和空白时间段内各信号的时序图。
图4为本申请实施例提供的GOA电路在显示时间段内各信号的时序图。
图5为本申请实施例提供的GOA电路在空白时间段内各信号的时序图。
图6为本申请的GOA电路和现有技术的GOA电路中阈值电压整体偏移对第二节点电位的影响对比示意图。
图7为本申请的GOA电路和现有技术的GOA电路中阈值电压整体偏移对第一输出信号的影响对比示意图。
本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相近的单元是用以相同标号表示。
本申请提供一种GOA电路和显示面板，以缓解现有GOA电路中晶体管制程的开发难度较高的技术问题。
如图2所示，为本申请实施例提供的GOA电路的结构示意图。GOA电路，包括m个级联的GOA单元，其中第n级GOA单元包括上拉控制模块100、逻辑寻址模块200、上拉模块300、第一下拉模块400、第二下拉模块500、第三下拉模块600、第一下拉维持模块700和第二下拉维持模块800。
上拉控制模块100与第一节点Q连接，用于在显示时间段将第一节点Q的电位拉高。
逻辑寻址模块200包括第二节点M，逻辑寻址模块与第一节点连接，用于在显示时间段，对第二节点电位进行两次拉高，在空白时间段，通过第二节点将第一节点的电位拉高。
上拉模块300与第一节点Q连接，用于将第n级级传信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)的电位拉高。
第一下拉模块400与第一节点Q连接，用于在空白时间段将第一节点Q的电位拉低。
第二下拉模块500与第一节点Q和第三节点QB连接，用于在显示时间段分别将第一节点Q和第三节点QB的电位拉低。
第三下拉模块600与第三节点QB和第二下拉模块500连接，用于在空白时间段将第三节点QB的电位拉低。
第一下拉维持模块700包括第三节点QB，第一下拉维持模块700与第一节点Q和第一下拉模块400连接，用于维持第一节点Q的低电位。
第二下拉维持模块800与第三节点QB和上拉模块300连接，用于维持第n级级传信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)的低电位。
显示面板在显示画面时需要经过显示时间段Promgraming和空白时间段Blank，其中显示时间段为每帧画面的实际显示时间段，空白时间段为相邻帧画面的实际显示时间之间的时间段。
本申请中，通过在显示时间段对第二节点M的电位进行两次拉高，使得在空白时间段，第一节点Q的充电率得到保证，进而使得GOA电路允许的阈值电压余量提升，提高了GOA电路的稳定性，降低了晶体管制程的开发难度。
如图2所示，上拉控制模块100包括第一晶体管T11和第二晶体管T12，第一晶体管T11的栅极和第一电极、以及第二晶体管T12的栅极均连接第n-2级级传信号Cout(n-2)，第一晶体管T11的第二电极连接第二晶体管T12的第一电极，第二晶体管T12的第二电极连接第一节点Q。
逻辑寻址模块200包括第三晶体管T91、第四晶体管T92、第五晶体管T71、第六晶体管T72、第七晶体管T73、第八晶体管T81、第九晶体管T91和第一存储电容Cbt3，第三晶体管T91的栅极连接第n-2级级传信号Cout(n-2)，第三晶体管T91的第一电极连接第一低电位信号VGL1，第三晶体管T91的第二电极连接第四晶体管T92的第一电极，第四晶体管T92的栅极和第二电极均连接高电位信号VGH，第五晶体管T71的栅极连接第一输入信号LSP，第五晶体管T71的第一电极连接第n-2级级传信号Cout(n-2)，第五晶体管T71的第二电极连接第六晶体管T72的第一电极和第七晶体管T73的第一电极，第六晶体管T72的栅极连接第一输入信号，第六晶体管T72的第二电极和第七晶体管T73的栅极均连接第二节点M，第七晶体管T73的第二电极连接高电位信号VGH，第八晶体管T81的栅极连接第二节点M，第八晶体管T81的第一电极连接高电位信号VGH，第八晶体管T81的第二电极连接第九晶体管T91的第一电极，第九晶体管T91的栅极连接复位信号Total-Reset，第九晶体管T91的第二电极连接第一节点Q，第一存储电容Cbt3的第一极板连接第三晶体管T91的第二电极，第二极板连接第二节点M。
上拉模块300包括第十晶体管T23、第十一晶体管T22、第十二晶体管T21、第十三晶体管T6、第二存储电容Cbt1和第三存储电容Cbt2，第十晶体管T23的栅极、第十一晶体管T22的栅极以及第十二晶体管T21的栅极均连接第一节点Q，第十晶体管T23的第一电极连接第一时钟信号CKa，第十晶体管T23的第二电极连接第n级级传信号Cout(n)，第十一晶体管T22的第一电极连接第二时钟信号CKb，第十一晶体管T22的第二电极连接第一输出信号WR(n)，第十二晶体管T21的第一电极连接第三时钟信号CKc，第十二晶体管T21的第二电极连接第二输出信号RD(n)，第十三晶体管T6的栅极连接第一节点Q，第十三晶体管T6的第一电极连接第四节点N，第十三晶体管T6的第二电极连接第一输出信号WR(n)，第二存储电容Cbt1的第一极板连接第一节点Q， 第二极板连接第一输出信号WR(n)，第三存储电容Cbt2的第一极板连接第一节点Q，第二极板连接第二输出信号RD(n)。
第一下拉模块400包括第十四晶体管T33和第十五晶体管T34，第十四晶体管T33的栅极和第十五晶体管T34的栅极均连接第二输入信号VST，第十四晶体管T33的第一电极连接第一节点Q，第十四晶体管T33的第二电极连接第十五晶体管T34的第一电极和第四节点N，第十五晶体管T34的第二电极连接第一低电位信号VGL1。
第二下拉模块500包括第十六晶体管T31、第十七晶体管T32和第十八晶体管T55，第十六晶体管T31的栅极和第十七晶体管T32的栅极连接第n+2级级传信号Cout(n+2)，第十六晶体管T31的第一电极连接第一节点Q，第十六晶体管T31的第二电极连接第十七晶体管T32的第一电极和第四节点N，第十七晶体T32管的第二电极连接第一低电位信号VGL1，第十八晶体管T55的栅极连接第n-2级级传信号Cout(n-2)，第十八晶体管T55的第一电极连接第二低电位信号VGL2，第十八晶体管T55的第一电极连接第三节点QB。
第三下拉模块600包括第十九晶体管T102和第二十晶体管T101，第十九晶体管T102的栅极连接所述第二节点，第十九晶体管T102的第一电极连接第二低电位信号VGL2，第十九晶体管T102的第二电极连接第二十晶体管T101的第一电极，第二十晶体管T101的栅极连接复位信号Total-Reset，第二十晶体管T101的第二电极连接第三节点QB。
第一下拉维持模块700包括第二十一晶体管T44、第二十二晶体管T45、第二十三晶体管T51、第二十四晶体管T52、第二十五晶体管T53和第二十六晶体管T54，第二十一晶体管T44的栅极和第二十二晶体管T45的栅极连接第三节点QB，第二十一晶体管T44的第一电极连接第一节点Q，第二十一晶体管T44的第二电极连接第二十二晶体管T45的第一电极和第四节点N，第二十二晶体管T45的第二电极连接第一低电位信号VGL1，第二十三晶体管T51的栅极和第一电极连接高电位信号VGH，第二十三晶体管T51的第二电极连接第二十四晶体管T52的第一电极，第二十四晶体管T52的栅极连接第一节点Q，第二十四晶体管T52的第二电极连接第二低电位信号VGL2，第二十五晶体管T53的栅极连接第二十三晶体管T51的第二电极，第二十五晶体管T53 的第一电极连接高电位信号VGH，第二十五晶体管T53的第二电极连接第二十六晶体管T54的第一电极和第三节点QB，第二十六晶体管T54的栅极连接第一节点Q，第二十六晶体管T54的第二电极连接第二低电位信号VGL2。
第二下拉维持模块800包括第二十七晶体管T43、第二十八晶体管T42和第二十九晶体管T41，第二十七晶体管T43的栅极、第二十八晶体管T42的栅极以及第二十九晶体管T41的栅极均连接第三节点QB，第二十七晶体管T43的第一电极连接第一低电位信号VGL1，第二十七晶体管T43的第二电极连接第n级级传信号Cout(n)，第二十八晶体管T42的第一电极连接第三低电位信号VGL3，第二十八晶体管T42的第二电极连接第一输出信号WR(n)，第二十九晶体管T41的第一电极连接第三低电位信号VGL3，第二十九晶体管T41的第二电极连接第二输出信号RD(n)。
在本申请的GOA电路中，包括m个级联的GOA单元，其中第n级GOA单元输出的级传信号为第n级级传信号Cout(n)，2≤n≤m，且n为整数。第n-2级级传信号Cout(n-2)为第n级级传信号Cout(n)之前且与其相隔一级的级传信号，第n+2级级传信号Cout(n+2)为第n级级传信号Cout(n)之前且与其相隔一级的级传信号。
在本申请的GOA电路中，第一输入信号LSP、第二输入信号VST、复位信号Total-Reset均由外部时序器提供。
本申请实施例提供的GOA电路为实时补偿电路，要求GOA在每一帧对应的显示时间段输出正常的驱动时序显示画面，而在每一帧之间的空白时间段输出宽脉冲时序进行阈值电压Vth探测用。图3示出了本申请实施例的GOA电路在显示时间段Promgraming和空白时间段Blank内各信号的时序，其中各信号在高电位和低电位时的电压设置数值如表1中所示。
Figure PCTCN2020080776-appb-000001
Figure PCTCN2020080776-appb-000002
表1
下面结合图4和图5对显示时间段和空白时间段内GOA电路的工作进行具体说明。
如图4所示，显示时间段包括第一显示阶段S1、第二显示阶段S2、第三显示阶段S3、第四显示阶段S4和第五显示阶段S5。
在第一显示阶段S1，第n-2级级传信号Cout(n-2)升为高电位，第一晶体管T11与第二晶体管T12打开，第一节点Q被拉升为高电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21打开，由于第一节点Q与第三节点QB之间连接构成了反相器结构，它们之间的电位相反，因此，第三节点QB处于低电位，第二十七晶体管T43、第二十八晶体管T42、第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均关闭，同时，第n+2级级传信号Cout(n+2)处于低电位，第十六晶体管T31和第十七晶体管T32关闭，第二输入信号VST为低电位，第十四晶体管T33与第十五晶体管T34关闭。第一时序信号CKa、第二时序信号CKb和第三时序信号CKc处于低电位，第n级级传信号信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)输出低电位。由于第n-2级级传信号Cout(n-2)为高电位，第三晶体管T91打开，第一存储电容Cbt3的第一极板连接的P点被复位成低电位，第二极板连接的第二节点M同时为低电位。
在第二显示阶段S2，第一输入信号LSP升为高电位，此时第n-2级级传 信号Cout(n-2)维持高电位，第二节点M被抬升至高电位，第四晶体管T92打开，P点维持低电位，由于复位信号Totaol-Rest和第二输入信号VST等信号为低电位，第一节点Q维持高电位，第三节点QB维持低电位。
在第三显示阶段S3，第一输入信号LSP由高电位降为低电位，第五晶体管T71及第六晶体管T72关闭，第n-2级级传信号Cout(n-2)由高电位变为低电位，因此第三晶体管T91关闭，P点电位由低电位切换为高电位，由于第一存储电容Cbt3的存在，第二节点M受到耦合作用，被抬升至更高电位。第一时序信号Cka、第二时序信号CKb和第三时序信号CKc由低电位变为高电位，因此第n级级传信号Cout(n)、第一输出信号WR(n)以及第二输出信号RD(n)的电位也被抬升至高电位，同时由于第二存储电容Cbt1及第三存储电容Cbt2的存在，第一节点Q被耦合至更高电位。
在第四显示阶段S4，第一时序信号Cka、第二时序信号CKb和第三时序信号CKc由高电位切换为低电位，第n级级传信号Cout(n)、第一输出信号WR(n)以及第二输出信号RD(n)的电位被拉至低电位，第一节点Q的信号耦合降低，与第二显示阶段S2时的电位一致。
在第五显示阶段S5，第n+2级级传信号Cout(n+2)由低电位升至高电位，第十六晶体管T31及第十七晶体管T32打开，第一节点Q的电位被拉低至低电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21关闭，第三节点QB的电位被抬升至高电位，第二十七晶体管T43、第二十八晶体管T42、第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均打开，第一节点Q、第n级级传信号Cout(n)、第一输出信号WR(n)以及第二输出信号RD(n)维持低电位。
如图5所示，空白时间段包括第一空白阶段B1、第二空白阶段B2、第三空白阶段B3和第四空白阶段B4。
在第一空白阶段B1，复位信号Total reset升为高电位，第九晶体管T82打开，第一节点Q的电位被拉至高电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21打开，由于第一节点Q与第三节点QB之间连接构成了反相器结构，它们之间的电位相反，因此，第三节点QB处于低电位，第二十七晶体管T43、第二十八晶体管T42、 第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均关闭，同时，第n+2级级传信号Cout(n+2)处于低电位，第十六晶体管T31和第十七晶体管T32关闭，第二输入信号VST为低电位，第十四晶体管T33与第十五晶体管T34关闭。第一时序信号CKa、第二时序信号CKb和第三时序信号CKc处于低电位，第n级级传信号信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)输出低电位。
在第二空白阶段B2，复位信号Toatal reset降为低电位，第九晶体管T82关闭，第一时序信号Cka维持低电位，第二时序信号CKb及第三时序信号CKc升为高电位，第n级级传信号信号Cout(n)维持低电位，第一输出信号WR(n)和第二输出信号RD(n)输出高电位。第一节点Q被耦合至更高电位。
在第三空白阶段B3，第二输入信号VST由低电位升为高电位，第十四晶体管T33与第十五晶体管T34打开，第一节点Q的电位被拉低至低电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21关闭，第三节点QB的电位被抬升至高电位，第二十七晶体管T43、第二十八晶体管T42、第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均打开，第一节点Q、第一输出信号WR(n)和第二输出信RD(n)拉低至低电位，第n级级传信号Cout(n)维持低电位。
在第四空白阶段B4，第一输入信号LSP升为高电位，第五晶体管T71及第六晶体管T72打开，由于第n-2级级传信号Cout(n-2)为低电位，第二节点M被复位为低电位，第八晶体管T81关闭。第一节点Q、第n级级传信号Cout(n)、第一输出信号WR(n)和第二输出信RD(n)维持低电位。
本申请实施例提供的GOA电路为实时补偿型GOA电路，通过上述过程，为扫描线提供驱动信号，以使显示面板显示画面。
在上述过程中，通过在第一存储电容Cbt3的第一极板侧设置第三晶体管T91和第四晶体管T92，在第一显示阶段S1，第三晶体管T91和第四晶体管T92均打开，使得P点和第二节点M电位为低电位，在第二显示阶段S2，第三晶体管T91和第四晶体管T92均打开，P点的电位维持低电位，第二节点M电位进行第一次拉高，在第三显示阶段S3，第三晶体管T91关闭，第四晶体管T92打开，将P点电位拉高，由于耦合作用，第二节点M的电位进行了第 二次拉高。因此，在第一空白阶段B1，第一节点Q的电位相对于现有技术被拉至更高，充电率得到保证，进而使得GOA电路允许的阈值电压余量提升，提高了GOA电路的稳定性，降低了晶体管制程的开发难度。
如图6所示，为本申请的GOA电路和现有技术的GOA电路中阈值电压整体偏移对第二节点M电位的影响对比示意图，其中第一曲线A1为现有技术中阈值电压为0时第二节点M的电位波形，第二曲线A2为本申请中阈值电压为0时第二节点M的电位波形，第三曲线B1为现有技术中阈值电压为5V时第二节点M的电位波形，第四曲线B2为本申请中阈值电压为5V时第二节点M的电位波形。
如图7所示，为本申请的GOA电路和现有技术的GOA电路中阈值电压整体偏移对第一输出信号WR(n)的影响对比示意图，其中第五曲线C1为现有技术中阈值电压为0时第一输出信号WR(n)的电位波形，第六曲线C2为本申请中阈值电压为0时第一输出信号WR(n)的电位波形，第七曲线D1为现有技术中阈值电压为5V时第一输出信号WR(n)的电位波形，第八曲线D2为本申请中阈值电压为5V时第一输出信号WR(n)的电位波形。
结合图6和图7可以看出，当阈值电压Vth为5V时，在显示时间段，现有技术中GOA电路的第二节点M的电位较低，而本申请的第二节点M的电位仍然较高，在空白时间段，现有技术中GOA电路已无波形输出，电路已完全失效，而本申请的第一输出信号WR(n)仍然存在输出，GOA电路正常工作。因此，本申请的GOA电路相对于现有技术，通过在显示时间段对第二节点M的电位进行两次拉高，使得在空白时间段，第一节点Q的电位也更高，充电率得到保证，进而使得GOA电路允许的阈值电压余量提升，提高了GOA电路的稳定性，降低了晶体管制程的开发难度。
本申请还提供一种显示面板，包括上述任一实施例所述的GOA电路。
根据上述实施例可知：
本申请提供一种GOA电路和显示面板，GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括上拉控制模块、逻辑寻址模块、上拉模块、第一下拉模块、第二下拉模块、第三下拉模块、第一下拉维持模块和第二下拉 维持模块，上拉控制模块与第一节点连接，用于在显示时间段将第一节点的电位拉高；逻辑寻址模块包括第二节点，逻辑寻址模块与第一节点连接，用于在显示时间段，对第二节点电位进行两次拉高，在空白时间段，通过第二节点将第一节点的电位拉高；上拉模块与第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；第一下拉模块与第一节点连接，用于在空白时间段将第一节点的电位拉低；第二下拉模块与第一节点和第三节点连接，用于在显示时间段分别将第一节点和第三节点的电位拉低；第三下拉模块与第三节点和第二下拉模块连接，用于在空白时间段将第三节点的电位拉低；第一下拉维持模块包括所述第三节点，所述第一下拉维持模块与第一节点和第一下拉模块连接，用于维持第一节点的低电位；第二下拉维持模块与第三节点和上拉模块连接，用于维持第n级级传信号、第一输出信号和第二输出信号的低电位。通过在显示时间段对第二节点的电位进行两次拉高，使得在空白时间段，第一节点的电位也更高，充电率得到保证，进而使得GOA电路允许的阈值电压余量提升，提高了GOA电路的稳定性，降低了晶体管制程的开发难度。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种GOA电路，其包括m个级联的GOA单元，其中第n级GOA单元包括：
    上拉控制模块，与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；
    逻辑寻址模块，包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；
    上拉模块，与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；
    第一下拉模块，与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；
    第二下拉模块，与所述第一节点和第三节点连接，用于在显示时间段分别将所述第一节点和所述第三节点的电位拉低；
    第三下拉模块，与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节点的电位拉低；
    第一下拉维持模块，包括所述第三节点，所述第一下拉维持模块与所述第一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；
    第二下拉维持模块，与所述第三节点和所述上拉模块连接，用于维持所述第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。
  2. 如权利要求1所述的GOA电路，其中，所述上拉控制模块包括第一晶体管和第二晶体管，所述第一晶体管的栅极和第一电极、以及所述第二晶体管的栅极均连接第n-2级级传信号，所述第一晶体管的第二电极连接所述第二晶体管的第一电极和第四节点，所述第二晶体管的第二电极连接所述第一节点。
  3. 如权利要求2所述的GOA电路，其中，所述逻辑寻址模块包括第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第一存储电容，所述第三晶体管的栅极连接第n-2级级传信号，所述第三晶体管的第一电极连接第一低电位信号，所述第三晶体管的第二电极 连接所述第四晶体管的第一电极，所述第四晶体管的栅极和第二电极均连接高电位信号，所述第五晶体管的栅极连接第一输入信号，所述第五晶体管的第一电极连接第n-2级级传信号，所述第五晶体管的第二电极连接所述第六晶体管的第一电极和所述第七晶体管的第一电极，所述第六晶体管的栅极连接所述第一输入信号，所述第六晶体管的第二电极和所述第七晶体管的栅极均连接所述第二节点，所述第七晶体管的第二电极连接所述高电位信号，所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一电极连接所述高电位信号，所述第八晶体管的第二电极连接所述第九晶体管的第一电极，所述第九晶体管的栅极连接复位信号，所述第九晶体管的第二电极连接所述第一节点，所述第一存储电容的第一极板连接所述第三晶体管的第二电极，第二极板连接所述第二节点。
  4. 如权利要求3所述的GOA电路，其中，所述上拉模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第二存储电容和第三存储电容，所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均连接所述第一节点，所述第十晶体管的第一电极连接第一时钟信号，所述第十晶体管的第二电极连接所述第n级级传信号，所述第十一晶体管的第一电极连接第二时钟信号，所述第十一晶体管的第二电极连接所述第一输出信号，所述第十二晶体管的第一电极连接第三时钟信号，所述第十二晶体管的第二电极连接所述第二输出信号，所述第十三晶体管的栅极连接所述第一节点，所述第十三晶体管的第一电极连接所述第四节点，所述第十三晶体管的第二电极连接所述第一输出信号，所述第二存储电容的第一极板连接所述第一节点，第二极板连接所述第一输出信号，所述第三存储电容的第一极板连接所述第一节点，第二极板连接所述第二输出信号。
  5. 如权利要求4所述的GOA电路，其中，所述第一下拉模块包括第十四晶体管和第十五晶体管，所述第十四晶体管的栅极和所述第十五晶体管的栅极均连接第二输入信号，所述第十四晶体管的第一电极连接所述第一节点，所述第十四晶体管的第二电极连接所述第十五晶体管的第一电极和所述第四节点，所述第十五晶体管的第二电极连接所述第一低电位信号。
  6. 如权利要求5所述的GOA电路，其中，所述第二下拉模块包括第十 六晶体管、第十七晶体管和第十八晶体管，所述第十六晶体管的栅极和所述第十七晶体管的栅极连接第n+2级级传信号，所述第十六晶体管的第一电极连接所述第一节点，所述第十六晶体管的第二电极连接所述第十七晶体管的第一电极和所述第四节点，所述第十七晶体管的第二电极连接所述第一低电位信号，所述第十八晶体管的栅极连接所述第n-2级级传信号，所述第十八晶体管的第一电极连接所述第二低电位信号，所述第十八晶体管的第一电极连接所述第三节点。
  7. 如权利要求6所述的GOA电路，其中，所述第三下拉模块包括第十九晶体管和第二十晶体管，所述第十九晶体管的栅极连接所述第二节点，所述第十九晶体管的第一电极连接所述第二低电位信号，所述第十九晶体管的第二电极连接所述第二十晶体管的第一电极，所述第二十晶体管的栅极连接所述复位信号，所述第二十晶体管的第二电极连接所述第三节点。
  8. 如权利要求7所述的GOA电路，其中，所述第一下拉维持模块包括第二十一晶体管、第二十二晶体管、第二十三晶体管、第二十四晶体管、第二十五晶体管和第二十六晶体管，所述第二十一晶体管的栅极和所述第二十二晶体管的栅极连接所述第三节点，所述第二十一晶体管的第一电极连接所述第一节点，所述第二十一晶体管的第二电极连接所述第二十二晶体管的第一电极和所述第四节点，所述第二十二晶体管的第二电极连接所述第一低电位信号，所述第二十三晶体管的栅极和第一电极连接所述高电位信号，所述第二十三晶体管的第二电极连接所述第二十四晶体管的第一电极，所述第二十四晶体管的栅极连接所述第一节点，所述第二十四晶体管的第二电极连接第二低电位信号，所述第二十五晶体管的栅极连接所述第二十三晶体管的第二电极，所述第二十五晶体管的第一电极连接所述高电位信号，所述第二十五晶体管的第二电极连接所述第二十六晶体管的第一电极和所述第三节点，所述第二十六晶体管的栅极连接所述第一节点，所述第二十六晶体管的第二电极连接所述第二低电位信号。
  9. 如权利要求8所述的GOA电路，其中，所述第二下拉维持模块包括第二十七晶体管、第二十八晶体管和第二十九晶体管，所述第二十七晶体管的栅极、所述第二十八晶体管的栅极以及所述第二十九晶体管的栅极均连接所述 第三节点，所述第二十七晶体管的第一电极连接所述第一低电位信号，所述第二十七晶体管的第二电极连接所述第n级级传信号，所述第二十八晶体管的第一电极连接第三低电位信号，所述第二十八晶体管的第二电极连接所述第一输出信号，所述第二十九晶体管的第一电极连接所述第三低电位信号，所述第二十九晶体管的第二电极连接所述第二输出信号。
  10. 如权利要求9所述的GOA电路，其中，所述第一输入信号、所述第二输入信号和所述复位信号均由外部时序器提供。
  11. 一种显示面板，其包括GOA电路，所述GOA电路包括m个级联的GOA单元，其中第n级GOA单元包括：
    上拉控制模块，与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；
    逻辑寻址模块，包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；
    上拉模块，与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；
    第一下拉模块，与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；
    第二下拉模块，与所述第一节点和第三节点连接，用于在显示时间段分别将所述第一节点和所述第三节点的电位拉低；
    第三下拉模块，与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节点的电位拉低；
    第一下拉维持模块，包括所述第三节点，所述第一下拉维持模块与所述第一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；
    第二下拉维持模块，与所述第三节点和所述上拉模块连接，用于维持所述第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。
  12. 如权利要求11所述的显示面板，其中，所述上拉控制模块包括第一晶体管和第二晶体管，所述第一晶体管的栅极和第一电极、以及所述第二晶体管的栅极均连接第n-2级级传信号，所述第一晶体管的第二电极连接所述第二 晶体管的第一电极和第四节点，所述第二晶体管的第二电极连接所述第一节点。
  13. 如权利要求12所述的显示面板，其中，所述逻辑寻址模块包括第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第一存储电容，所述第三晶体管的栅极连接第n-2级级传信号，所述第三晶体管的第一电极连接第一低电位信号，所述第三晶体管的第二电极连接所述第四晶体管的第一电极，所述第四晶体管的栅极和第二电极均连接高电位信号，所述第五晶体管的栅极连接第一输入信号，所述第五晶体管的第一电极连接第n-2级级传信号，所述第五晶体管的第二电极连接所述第六晶体管的第一电极和所述第七晶体管的第一电极，所述第六晶体管的栅极连接所述第一输入信号，所述第六晶体管的第二电极和所述第七晶体管的栅极均连接所述第二节点，所述第七晶体管的第二电极连接所述高电位信号，所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一电极连接所述高电位信号，所述第八晶体管的第二电极连接所述第九晶体管的第一电极，所述第九晶体管的栅极连接复位信号，所述第九晶体管的第二电极连接所述第一节点，所述第一存储电容的第一极板连接所述第三晶体管的第二电极，第二极板连接所述第二节点。
  14. 如权利要求13所述的显示面板，其中，所述上拉模块包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第二存储电容和第三存储电容，所述第十晶体管的栅极、所述第十一晶体管的栅极以及所述第十二晶体管的栅极均连接所述第一节点，所述第十晶体管的第一电极连接第一时钟信号，所述第十晶体管的第二电极连接所述第n级级传信号，所述第十一晶体管的第一电极连接第二时钟信号，所述第十一晶体管的第二电极连接所述第一输出信号，所述第十二晶体管的第一电极连接第三时钟信号，所述第十二晶体管的第二电极连接所述第二输出信号，所述第十三晶体管的栅极连接所述第一节点，所述第十三晶体管的第一电极连接所述第四节点，所述第十三晶体管的第二电极连接所述第一输出信号，所述第二存储电容的第一极板连接所述第一节点，第二极板连接所述第一输出信号，所述第三存储电容的第一极板连接所述第一节点，第二极板连接所述第二输出信号。
  15. 如权利要求14所述的显示面板，其中，所述第一下拉模块包括第十四晶体管和第十五晶体管，所述第十四晶体管的栅极和所述第十五晶体管的栅极均连接第二输入信号，所述第十四晶体管的第一电极连接所述第一节点，所述第十四晶体管的第二电极连接所述第十五晶体管的第一电极和所述第四节点，所述第十五晶体管的第二电极连接所述第一低电位信号。
  16. 如权利要求15所述的显示面板，其中，所述第二下拉模块包括第十六晶体管、第十七晶体管和第十八晶体管，所述第十六晶体管的栅极和所述第十七晶体管的栅极连接第n+2级级传信号，所述第十六晶体管的第一电极连接所述第一节点，所述第十六晶体管的第二电极连接所述第十七晶体管的第一电极和所述第四节点，所述第十七晶体管的第二电极连接所述第一低电位信号，所述第十八晶体管的栅极连接所述第n-2级级传信号，所述第十八晶体管的第一电极连接所述第二低电位信号，所述第十八晶体管的第一电极连接所述第三节点。
  17. 如权利要求16所述的显示面板，其中，所述第三下拉模块包括第十九晶体管和第二十晶体管，所述第十九晶体管的栅极连接所述第二节点，所述第十九晶体管的第一电极连接所述第二低电位信号，所述第十九晶体管的第二电极连接所述第二十晶体管的第一电极，所述第二十晶体管的栅极连接所述复位信号，所述第二十晶体管的第二电极连接所述第三节点。
  18. 如权利要求17所述的显示面板，其中，所述第一下拉维持模块包括第二十一晶体管、第二十二晶体管、第二十三晶体管、第二十四晶体管、第二十五晶体管和第二十六晶体管，所述第二十一晶体管的栅极和所述第二十二晶体管的栅极连接所述第三节点，所述第二十一晶体管的第一电极连接所述第一节点，所述第二十一晶体管的第二电极连接所述第二十二晶体管的第一电极和所述第四节点，所述第二十二晶体管的第二电极连接所述第一低电位信号，所述第二十三晶体管的栅极和第一电极连接所述高电位信号，所述第二十三晶体管的第二电极连接所述第二十四晶体管的第一电极，所述第二十四晶体管的栅极连接所述第一节点，所述第二十四晶体管的第二电极连接第二低电位信号，所述第二十五晶体管的栅极连接所述第二十三晶体管的第二电极，所述第二十五晶体管的第一电极连接所述高电位信号，所述第二十五晶体管的第二电极连 接所述第二十六晶体管的第一电极和所述第三节点，所述第二十六晶体管的栅极连接所述第一节点，所述第二十六晶体管的第二电极连接所述第二低电位信号。
  19. 如权利要求18所述的显示面板，其中，所述第二下拉维持模块包括第二十七晶体管、第二十八晶体管和第二十九晶体管，所述第二十七晶体管的栅极、所述第二十八晶体管的栅极以及所述第二十九晶体管的栅极均连接所述第三节点，所述第二十七晶体管的第一电极连接所述第一低电位信号，所述第二十七晶体管的第二电极连接所述第n级级传信号，所述第二十八晶体管的第一电极连接第三低电位信号，所述第二十八晶体管的第二电极连接所述第一输出信号，所述第二十九晶体管的第一电极连接所述第三低电位信号，所述第二十九晶体管的第二电极连接所述第二输出信号。
  20. 如权利要求19所述的显示面板，其中，所述第一输入信号、所述第二输入信号和所述复位信号均由外部时序器提供。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115862514A (zh) * 2022-12-16 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109935208B (zh) * 2018-02-14 2021-03-02 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
CN112365855B (zh) * 2020-11-04 2022-11-08 深圳市华星光电半导体显示技术有限公司 Goa电路及液晶显示器
CN112509511B (zh) * 2020-12-08 2022-07-12 深圳市华星光电半导体显示技术有限公司 显示装置
CN112634974B (zh) * 2020-12-24 2024-08-13 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板以及控制方法
CN112908259A (zh) * 2021-03-24 2021-06-04 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN113140187B (zh) * 2021-04-06 2022-07-12 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN113506543A (zh) * 2021-06-09 2021-10-15 深圳职业技术学院 一种利于窄边框的goa电路
CN113628587B (zh) * 2021-08-17 2022-07-12 深圳市华星光电半导体显示技术有限公司 外部补偿侦测电路、驱动电路、显示装置及驱动方法
CN113808533B (zh) * 2021-09-15 2023-06-02 深圳市华星光电半导体显示技术有限公司 显示面板及显示终端
KR20230095552A (ko) 2021-12-22 2023-06-29 엘지디스플레이 주식회사 디스플레이 장치 및 구동 회로
CN114203112B (zh) * 2021-12-29 2023-07-25 深圳市华星光电半导体显示技术有限公司 Goa电路、显示面板以及显示设备
CN114495793B (zh) * 2022-02-14 2023-08-22 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048382A (ja) * 2005-08-10 2007-02-22 Mitsubishi Electric Corp シフトレジスタ
US20110228893A1 (en) * 2010-03-18 2011-09-22 Mitsubishi Electric Corporation Shift register circuit
CN105528985A (zh) * 2016-02-03 2016-04-27 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN108806611A (zh) * 2018-06-28 2018-11-13 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109710113A (zh) * 2019-03-07 2019-05-03 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路及其驱动方法、显示装置
CN109935209A (zh) * 2018-07-18 2019-06-25 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN110223648A (zh) * 2019-05-09 2019-09-10 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101924860B1 (ko) * 2012-06-29 2018-12-05 에스케이하이닉스 주식회사 신호송신회로
CN104008741A (zh) * 2014-05-20 2014-08-27 深圳市华星光电技术有限公司 一种扫描驱动电路及液晶显示装置
CN106205538A (zh) * 2016-08-31 2016-12-07 深圳市华星光电技术有限公司 一种goa驱动单元及驱动电路
CN106157916A (zh) * 2016-08-31 2016-11-23 深圳市华星光电技术有限公司 一种栅极驱动单元及驱动电路
KR102562947B1 (ko) * 2016-10-07 2023-08-04 엘지디스플레이 주식회사 게이트 구동 회로와 이를 이용한 표시장치
KR102542874B1 (ko) * 2016-10-18 2023-06-14 엘지디스플레이 주식회사 표시장치
CN108831398B (zh) * 2018-07-25 2020-05-05 深圳市华星光电半导体显示技术有限公司 Goa电路及显示装置
CN109166600B (zh) * 2018-10-26 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN109448656B (zh) * 2018-12-26 2021-01-26 惠科股份有限公司 移位暂存器和栅极驱动电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048382A (ja) * 2005-08-10 2007-02-22 Mitsubishi Electric Corp シフトレジスタ
US20110228893A1 (en) * 2010-03-18 2011-09-22 Mitsubishi Electric Corporation Shift register circuit
CN105528985A (zh) * 2016-02-03 2016-04-27 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN108806611A (zh) * 2018-06-28 2018-11-13 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109935209A (zh) * 2018-07-18 2019-06-25 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109710113A (zh) * 2019-03-07 2019-05-03 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路及其驱动方法、显示装置
CN110223648A (zh) * 2019-05-09 2019-09-10 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115862514A (zh) * 2022-12-16 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862514B (zh) * 2022-12-16 2024-03-15 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

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