WO2021042512A1 - 显示驱动电路 - Google Patents

显示驱动电路 Download PDF

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Publication number
WO2021042512A1
WO2021042512A1 PCT/CN2019/116689 CN2019116689W WO2021042512A1 WO 2021042512 A1 WO2021042512 A1 WO 2021042512A1 CN 2019116689 W CN2019116689 W CN 2019116689W WO 2021042512 A1 WO2021042512 A1 WO 2021042512A1
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WO
WIPO (PCT)
Prior art keywords
transistor
signal input
input terminal
electrically connected
node
Prior art date
Application number
PCT/CN2019/116689
Other languages
English (en)
French (fr)
Inventor
郑旭煌
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/620,930 priority Critical patent/US11373569B2/en
Publication of WO2021042512A1 publication Critical patent/WO2021042512A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technology, and in particular to a display drive circuit.
  • GOA Gate Driver on Array
  • the array substrate row drive technology is to directly fabricate the scan drive circuit on the array substrate, thereby saving the space for separately setting the scanning drive circuit through the integrated chip, which is conducive to the realization of the narrow frame design of the display, and reduces The welding process of the integrated chip. Therefore, GOA technology is more and more widely used in the field of display panels.
  • the display drive circuit based on GOA technology needs to provide scanning signals for the entire row of display units of the display panel, and the scanning signals provided by the display drive circuit will cause signal loss during the transmission process. Therefore, in order to reduce the signal loss on the display of the display panel The influence of the function needs to increase the intensity of the scanning signal provided by the display driving circuit as much as possible.
  • FIG. 1 is a schematic diagram of the structure of a display driving circuit used in the prior art.
  • the display driving circuit includes a first clock signal input terminal CLK1, a second clock signal input terminal CLK2, a high voltage signal input terminal VGH, a low voltage signal input terminal VGL, a cascade signal input terminal OUT (n-1) and a signal output terminal OUT ( n), further comprising: a first transistor T1' electrically connected to the first clock signal input terminal CLK1, the cascade signal input terminal OUT (n-1) and the first node Q, and the high voltage signal input terminal VGH and the second transistor T1'
  • the second transistor T2' electrically connected to the node QB is connected to the second clock signal input terminal, the first node Q and the signal output terminal OUT (n)
  • the third transistor T3' electrically connected to the second node QB, the low voltage signal input unit VGL, and the signal output terminal OUT (n)
  • the fourth transistor T4' electrically connected to the first node Q, low voltage
  • a capacitor C' is connected between the first node Q and the signal output terminal OUT (n), and the capacitor C'is used to maintain and further increase the potential of the first node Q to ensure that the second clock signal input terminal CLK2 is input
  • the voltage signal of is transmitted to the signal output terminal OUT (n) through the third transistor T3'. Since the signal output terminal OUT (n) is directly electrically connected to the capacitor C', the voltage signal input from the second clock signal input terminal CLK2 will charge the capacitor C'before being transmitted to the signal output terminal OUT (n), thereby causing loss
  • the storage capacitor electrically connected to the cascade signal output terminal consumes the signal strength flowing to the cascade signal output terminal, resulting in the display unit being unable to obtain a driving signal of sufficient strength and displaying abnormality.
  • the present invention provides a display drive circuit, which includes a multi-level drive unit, and the drive unit includes:
  • the pull-up control unit is electrically connected to the first clock signal input terminal, the first cascade signal input terminal, and the first node, and is used for controlling the first clock signal input terminal under the control of the signal input from the first clock signal input terminal.
  • the signal input from the cascade signal input terminal is transmitted to the first node;
  • the pull-up unit is electrically connected to the first node, the second clock signal input terminal, and the second node, and is used for transmitting the signal input from the second clock signal input terminal under the signal control of the first node To the second node;
  • the second node is electrically connected to the cascade signal output terminal
  • the pull-up unit includes a capacitor and a first transistor, a first end of the capacitor is electrically connected to the second clock signal input end, and a second end of the capacitor is electrically connected to the first node;
  • the gate of the first transistor is electrically connected to the first node, the source of the first transistor is electrically connected to the second clock signal input terminal, and the drain of the first transistor is electrically connected to the first node.
  • the pull-up control unit includes a second transistor, the gate of the second transistor is electrically connected to the first clock signal input terminal, and the source of the second transistor is electrically connected Connected to the cascade signal input terminal, and the drain of the second transistor is electrically connected to the first node.
  • the first transistor and the second transistor are n-type transistors or p-type transistors.
  • the driving unit includes a first low-voltage signal input terminal and a second low-voltage signal input terminal, and the voltage input from the first low-voltage signal input terminal is less than the voltage input from the second low-voltage signal input terminal. Voltage.
  • the driving unit further includes a pull-down unit
  • the pull-down unit is electrically connected to the second node, the third node, and the second low-voltage signal input terminal, and is used to input the second low-voltage signal input terminal under the signal control of the third node The signal is transmitted to the second node.
  • the pull-down unit includes a third transistor, the gate of the third transistor is electrically connected to the third node, and the source of the third transistor is electrically connected to the second node.
  • a low-voltage signal input terminal, and the drain of the third transistor is electrically connected to the second node.
  • the third transistor is an n-type transistor or a p-type transistor.
  • the driving unit further includes a pull-down control unit
  • the pull-down control unit is electrically connected to the first node, the second cascade signal input terminal, and the first low voltage signal input terminal, and is configured to control the signal input from the second cascade signal input terminal.
  • the signal input from the first low-voltage signal input terminal is transmitted to the first node.
  • the pull-down control unit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the second cascade signal input terminal, and the source of the fourth transistor is electrically connected Connected to the first low-voltage signal input terminal, and the drain of the fourth transistor is electrically connected to the first node.
  • the fourth transistor is an n-type transistor or a p-type transistor.
  • the driving unit further includes a pull-down sustaining unit
  • the pull-down sustaining unit is electrically connected to the first node, the third node, the high-voltage signal input terminal, and the first low-voltage signal input terminal, and is used to control the signal from the first node.
  • the signal input from the first low-voltage signal input terminal or the signal input from the high-voltage signal input terminal is transmitted to the third node.
  • the pull-down sustain unit includes a fifth transistor, a sixth transistor, and a seventh transistor, and the source of the fifth transistor and the source of the sixth transistor are electrically connected to the first transistor.
  • a low-voltage signal input terminal, the drain of the fifth transistor and the gate of the sixth transistor are electrically connected to the first node, and the gate of the fifth transistor and the drain of the sixth transistor are electrically connected Is electrically connected to the third node, the gate and source of the seventh transistor are electrically connected to the high-voltage signal input terminal, and the drain of the seventh transistor is electrically connected to the third node.
  • the fifth transistor, the sixth transistor, and the seventh transistor are n-type transistors or p-type transistors.
  • the first cascade signal input terminal of the nth level driving unit is electrically connected to the cascade signal output terminal of the n-1th level driving unit; all of the nth level driving unit The second cascade signal input terminal is electrically connected to the cascade signal output terminal of the n+1th stage drive unit;
  • n is an integer greater than or equal to 2.
  • the first cascade signal input terminal of the first-level driving unit is electrically connected to a start signal line.
  • the first clock signal input terminal is electrically connected to a first clock signal line
  • the second clock signal input terminal is electrically connected to a second clock signal line
  • the first low voltage signal input The terminal is electrically connected to a first low-voltage signal line
  • the second low-voltage signal input terminal is electrically connected to a second low-voltage signal line
  • the high-voltage signal input terminal is electrically connected to a high-voltage signal line.
  • the clock signal transmitted by the first clock signal line is opposite to the clock signal transmitted by the second clock signal line.
  • the display driving circuit provided by the present invention eliminates the loss of the output signal of the cascade signal output terminal by the capacitor and improves the output signal of the cascade signal output terminal by arranging the capacitor and the cascade signal output terminal in parallel with each other.
  • the cascaded signal output terminal is connected to the low-voltage signal input terminal through a switch transistor to ensure that the cascaded signal output terminal maintains a low-voltage state when there is no high-voltage signal output, and prevents the cascaded signal output terminal from appearing The output signal fluctuates.
  • FIG. 1 is a schematic diagram of the structure of a driving unit of a display driving circuit in the prior art
  • FIG. 2 is a schematic structural diagram of a single driving unit of a display driving circuit provided by an embodiment of the present invention
  • FIG. 3 is a cascade relationship diagram of the display driving circuit provided by the embodiment of the present invention.
  • FIG. 4 is an input/output timing diagram of the display driving circuit provided by the embodiment of the present invention.
  • the embodiment of the present invention provides a display driving circuit.
  • a capacitor and a cascaded signal output terminal are connected in parallel with each other, the loss of the capacitor to the output signal of the cascaded signal output terminal is eliminated, and the cascading is improved.
  • the strength and stability of the output signal at the signal output terminal; in addition, the cascade signal output terminal is connected to the low voltage signal input terminal through a switching transistor to ensure that the cascade signal output terminal maintains a low voltage state when there is no high voltage signal output, and prevents the The output signal fluctuates at the signal output terminal.
  • FIG. 2 it is a schematic structural diagram of a single-stage driving unit in a display driving circuit provided by an embodiment of the present invention. It should be noted that the display driving circuit includes multiple stages of driving units as shown in FIG. 2, and there is a connection relationship between adjacent driving units.
  • the driving unit includes a pull-up control unit 101 and a pull-up unit 102.
  • the pull-up control unit 101 is electrically connected to the first clock signal input terminal 21, the first cascade signal input terminal 31, and the first node A, respectively.
  • the pull-up control unit 101 is configured to transmit the signal input from the first cascade signal input terminal 31 to the first node A under the control of the signal input from the first clock signal input terminal 21.
  • the pull-up control unit 101 includes a second transistor T2, the gate of the second transistor T2 is electrically connected to the first clock signal input terminal 21, and the source of the second transistor T2 is electrically connected to The cascade signal input terminal 31 and the drain of the second transistor T2 are electrically connected to the first node A.
  • the transistor used in the display driving circuit provided by the embodiment of the present invention may be an n-type transistor or a p-type transistor.
  • an n-type transistor is used as an example for description in the following embodiments. It should be understood that for an n-type transistor, when the gate of the transistor is at a high level, the source and drain of the transistor are turned on, the transistor is turned on, and vice versa; for a p-type transistor, when the gate of the transistor is at a low level, The source and drain of the transistor are turned on, the transistor is turned on, otherwise the transistor is turned off.
  • the pull-up unit 102 is electrically connected to the first node A, the second clock signal input terminal 22, and the second node B, respectively.
  • the pull-up unit 102 is configured to transmit the signal input from the second clock signal input terminal 22 to the second node B under the control of the signal of the first node A.
  • the pull-up unit 102 includes a capacitor Cp and a first transistor T1.
  • the first terminal of the capacitor Cp is electrically connected to the second clock signal input terminal 22, and the second terminal of the capacitor Cp is electrically connected to the first node A.
  • the capacitor Cp is used to couple the potential of the first node A and the second clock signal input terminal 22.
  • the gate of the first transistor T1 is electrically connected to the first node A, the source of the first transistor T1 is electrically connected to the second clock signal input terminal 22, and the drain of the first transistor T1
  • the second node B is electrically connected.
  • the first transistor T1 is used to transmit the signal input from the second clock signal input terminal 22 to the second node B under the control of the voltage signal of the first node A.
  • the second node B is electrically connected to the cascade signal output terminal 61.
  • the cascade signal output terminal 61 is used to provide scan signals for the display unit of the display panel.
  • the two ends of the capacitor Cp are respectively connected to the second clock signal input terminal 22 and the first node A, and the cascade signal output terminal 61 is connected to the capacitor through the first transistor T1.
  • Cp are arranged in parallel, therefore, the signal transmitted from the second clock signal input terminal 22 to the cascade signal output terminal 61 via the first transistor T1 will not be lost by the capacitor Cp, thereby ensuring the cascade signal
  • the signal output by the output terminal 61 has sufficient strength and stability.
  • the driving unit further includes a pull-down unit 103, a pull-down control unit 104 and a pull-down maintenance unit 105.
  • the pull-down unit 103 is electrically connected to the second node B, the third node C, and the second low-voltage signal input terminal 52, respectively.
  • the pull-down unit 103 is configured to transmit the signal input from the second low-voltage signal input terminal 52 to the second node B under the signal control of the third node C, so as to pull down the potential of the second node B , So that the cascade signal output terminal 61 outputs a low level.
  • the pull-down unit 103 includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the third node C, and the source of the third transistor T3 is electrically connected to the second low voltage For the signal input terminal 52, the drain of the third transistor T3 is electrically connected to the second node B.
  • the pull-down control unit 104 is electrically connected to the first node A, the second cascade signal input terminal 32, and the first low voltage signal input terminal 51, respectively.
  • the pull-down control unit 104 is configured to transmit the signal input from the first low-voltage signal input terminal 51 to the first node A under the control of the signal input from the second cascade signal input terminal 32, so as to pull down the The potential of the first node A.
  • the pull-down control unit 104 includes a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the second cascade signal input terminal 32, and the source of the fourth transistor T4 is electrically connected to The first low-voltage signal input terminal 51 and the drain of the fourth transistor T4 are electrically connected to the first node A.
  • the pull-down maintaining unit 105 is electrically connected to the first node A, the third node C, the high-voltage signal input terminal 41, and the first low-voltage signal input terminal 51, respectively, and is used to connect to the first node A
  • the signal input from the first low-voltage signal input terminal 51 or the signal input from the high-voltage signal input terminal 41 is transmitted to the third node C under the control of the signal, thereby pulling down or raising the potential of the third node C.
  • the pull-down sustain unit 105 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • the source of the fifth transistor T5 and the source of the sixth transistor T6 are electrically connected to the first low-voltage signal input terminal 51, and the drain of the fifth transistor T5 and the sixth transistor T6
  • the gate of the fifth transistor T5 and the drain of the sixth transistor T6 are electrically connected to the first node A
  • the gate of the fifth transistor T5 and the drain of the sixth transistor T6 are electrically connected to the third node C
  • the gate of the seventh transistor T7 The electrode and the source are electrically connected to the high-voltage signal input terminal 41
  • the drain of the seventh transistor T7 is electrically connected to the third node C.
  • the third node C is electrically connected to the first low-voltage signal input terminal 51 through the sixth transistor T6, so that when the sixth transistor T6 is turned on, the third node C is pulled down To a low potential; in addition, the third node C is electrically connected to the high-voltage signal input terminal 41 through the seventh transistor T7.
  • the seventh transistor T7 is a normally-on transistor, so that when the sixth transistor T6 is turned off At this time, the third node C is raised to a high potential.
  • the display driving circuit pulls down the potential of the first node A through the first low voltage signal input terminal 51, and at the same time pulls down the second node B through the second low voltage signal input terminal 52
  • the potential of the cascade signal output terminal 61 can ensure that the cascade signal output terminal 61 maintains a low voltage state when there is no high voltage signal output, and prevent the signal output from the cascade signal output terminal 61 from being abnormal due to the potential fluctuation of the second node B.
  • the voltage input from the first low-voltage signal input terminal 51 is less than the voltage input from the second low-voltage signal input terminal 52.
  • the third node C is connected to the high-voltage signal input terminal 41 and the first low-voltage signal input terminal 51 through the seventh transistor T7 and the sixth transistor T6, respectively.
  • both the seventh transistor T7 and the sixth transistor T6 are turned on, in order to pull down the third node C to a sufficiently low potential, the voltage input to the first low-voltage signal input terminal 51 needs to be set sufficiently low.
  • the display driving circuit provided by the present invention includes multi-level cascaded driving units, and the following describes the cascading relationship between the various levels of driving units in the display driving circuit.
  • FIG. 3 it is a cascade relationship diagram of the display driving circuit provided by the embodiment of the present invention.
  • the first cascade signal input terminal 31 of the n-th drive unit U (n) is electrically connected to the cascade signal output terminal 61 of the n-1th drive unit U (n-1); the n-th drive
  • the second cascade signal input terminal 32 of the unit U (n) is electrically connected to the cascade signal output terminal 61 of the n+1th level driving unit U (n+1); where n is greater than or equal to 2 Integer.
  • the first cascade signal input terminal 31 of the first-level driving unit is electrically connected to the start signal line STV.
  • the first clock signal input terminal 21 is electrically connected to the first clock signal line CK1, and the first clock signal line CK1 is used to transmit the signal to the first clock signal line CK1.
  • a clock signal input terminal 21 transmits the first clock signal;
  • the second clock signal input terminal 22 is electrically connected to a second clock signal line CK2, and the second clock signal line CK2 is used to transmit the second clock signal input terminal 22 transmits the second clock signal;
  • the first low-voltage signal input terminal 51 is electrically connected to the first low-voltage signal line VL1, and the first low-voltage signal line VL1 is used to transmit the first low-voltage signal to the first low-voltage signal input terminal 51.
  • the second low-voltage signal input terminal 52 is electrically connected to a second low-voltage signal line VL2, and the second low-voltage signal line VL2 is used to transmit a second low-voltage signal to the second low-voltage signal input terminal 52;
  • the high-voltage The signal input terminal 41 is electrically connected to a high-voltage signal line VH, and the high-voltage signal line VH is used to transmit a high-voltage signal to the high-voltage signal input terminal 41.
  • the cascade signal output terminal 61 outputs a cascade signal G, and the cascade signal G can be used to drive the display unit of the display panel.
  • FIG. 4 is an input/output timing diagram of the display driving circuit provided by the embodiment of the present invention.
  • the first clock signal line CK1 is at a high level
  • the second clock signal line CK2 is at a low level
  • the cascade signal G (n-1) of the n-1th stage is at a high level. level.
  • the cascade signal G (n-1) of the n-1th stage corresponds to the start signal STV.
  • the second transistor T2 is turned on, and the first node A receives the cascade signal G (n-1) of the n-1th stage and exhibits a high level.
  • the first transistor T1 and the sixth transistor T6 are turned on, the third node C is pulled low by the first low-voltage signal line VL1, the third transistor T3 is turned off, and the second node
  • the signal received by B from the second clock signal line CK2 is represented as a low level
  • the n-th cascade signal G (n) is represented as a low level signal.
  • the first clock signal line CK1 is at a low level
  • the second clock signal line CK2 is at a high level
  • the n-1th stage cascade signal G (n-1) or start signal STV is low.
  • the second transistor T2 is turned off, and under the effect of the voltage coupling of the capacitor Cp, the level of the first node A is further pulled up, showing a higher level.
  • the first transistor T1 is further turned on, the third transistor T3 remains turned off, the high level of the second clock signal line CK2 is transmitted to the second node B, and the n-th stage cascade signal G(n) Appears as a high-level signal.
  • the first clock signal line CK1 is at a high level
  • the second clock signal line CK2 is at a low level.
  • the cascade signal G (n+1) of the n+1th stage is at a high level.
  • the fourth transistor T4 is turned on, and the first node A is pulled down to a low level by the first low voltage signal line VL1.
  • the first transistor T1 and the sixth transistor T6 are turned off, the third node C is raised to a high level by the high voltage signal line VH, the third transistor T3 is turned on, and the second node B is turned off by the The second low-voltage signal line VL2 is pulled down to a low level, and the n-th stage cascade signal G (n) appears as a low-level signal.
  • the signal of the second clock signal line CK2 is directly transmitted to the cascaded signal output terminal 61 through the first transistor T1, and the capacitor Cp will not be transmitted to all signals.
  • the signal at the cascade signal output terminal 61 causes loss, thereby ensuring that the cascade signal output terminal 61 outputs a stable cascade signal.
  • the cascade signal output by the cascade signal output terminal 61 is always maintained at a low level by the second low voltage signal line VL2, thereby preventing the The signal fluctuation of the second clock signal line CK2 causes the cascade signal output by the cascade signal output terminal 61 to abnormally jump.

Abstract

一种显示驱动电路，包括上拉控制单元(101)和上拉单元(102)，上拉单元(101)通过第一节点与上拉控制单元(102)电性连接；上拉单元(101)包括电容和第一晶体管，电容的第一端电性连接时钟信号输入端，电容的第二端电性连接第一节点；第一晶体管的栅极电性连接第一节点，第一晶体管的源极电性连接时钟信号输入端，第一晶体管的漏极电性连接信号输出端。

Description

显示驱动电路 技术领域
本发明涉及显示技术领域，尤其涉及一种显示驱动电路。
 背景技术
GOA (Gate Driver on Array)技术，即阵列基板行驱动技术，是将扫描驱动电路直接制作在阵列基板上，从而节省了通过集成芯片单独设置扫描驱动电路的空间，有利于实现显示器的窄边框设计，且减少了集成芯片的焊接工序。因此，GOA技术在显示面板领域的应用越来越广泛。
基于GOA技术的显示驱动电路需要为显示面板的整行显示单元提供扫描信号，而显示驱动电路提供的扫描信号在传递的过程中会产生信号损耗，因此，为了减小信号损耗对显示面板的显示功能的影响，需要尽量提高显示驱动电路提供的扫描信号的强度。
图1是现有技术中使用的显示驱动电路的结构示意图。该显示驱动电路包括第一时钟信号输入端CLK1、第二时钟信号输入端CLK2、高压信号输入端VGH、低压信号输入端VGL、级联信号输入端OUT (n-1)和信号输出端OUT (n)，还包括：与第一时钟信号输入端CLK1、级联信号输入端OUT (n-1)及第一节点Q电性连接的第一晶体管T1’，与高压信号输入端VGH及第二节点QB电性连接的第二晶体管T2’，与第二时钟信号输入端、第一节点Q及信号输出端OUT (n)电性连接的第三晶体管T3’，与第二节点QB、低压信号输入单VGL及信号输出端OUT (n)电性连接的第四晶体管T4’，与第一节点Q、低压信号输入端VGL及第二节点QB电性连接的第五晶体管T5’，以及与第二节点QB、低压信号输入端VGL及第一节点Q电性连接的第六晶体管T6’。其中，在第一节点Q和信号输出端OUT (n)之间连接电容C’，所述电容C’用于维持并进一步提升第一节点Q的电位，以保证第二时钟信号输入端CLK2输入的电压信号通过第三晶体管T3’传递至信号输出端OUT (n)。由于信号输出端OUT (n)直接与电容C’电性相连，第二时钟信号输入端CLK2输入的电压信号在传递至信号输出端OUT (n)之前会先对电容C’进行充电，从而损耗传递至信号输出端OUT (n)的信号强度。对于距离显示驱动电路较远的显示单元，会因无法接收到足够强度的信号而出现显示异常的现象。
 技术问题
现有技术的显示驱动电路中，与级联信号输出端电性连接的存储电容会消耗流向所述级联信号输出端的信号强度，导致显示单元无法获得足够强度的驱动信号而出现显示异常。
 技术解决方案
基于上述技术问题，本申请的解决方案如下：
本发明提供一种显示驱动电路，包括多级驱动单元，所述驱动单元包括：
上拉控制单元，与第一时钟信号输入端、第一级联信号输入端及第一节点电性连接，用于在所述第一时钟信号输入端输入的信号的控制下将所述第一级联信号输入端输入的信号传输至所述第一节点；
上拉单元，与所述第一节点、第二时钟信号输入端及第二节点电性连接，用于在所述第一节点的信号控制下将所述第二时钟信号输入端输入的信号传输至所述第二节点；
所述第二节点电性连接级联信号输出端；
其中，所述上拉单元包括电容和第一晶体管，所述电容的第一端电性连接所述第二时钟信号输入端，所述电容的第二端电性连接所述第一节点；所述第一晶体管的栅极电性连接所述第一节点，所述第一晶体管的源极电性连接所述第二时钟信号输入端，所述第一晶体管的漏极电性连接所述第二节点。
在本申请的显示驱动电路中，所述上拉控制单元包括第二晶体管，所述第二晶体管的栅极电性连接所述第一时钟信号输入端，所述第二晶体管的源极电性连接所述级联信号输入端，所述第二晶体管的漏极电性连接所述第一节点。
在本申请的显示驱动电路中，所述第一晶体管和所述第二晶体管为n型晶体管或p型晶体管。
在本申请的显示驱动电路中，所述驱动单元包括第一低压信号输入端和第二低压信号输入端，所述第一低压信号输入端输入的电压小于所述第二低压信号输入端输入的电压。
在本申请的显示驱动电路中，所述驱动单元还包括下拉单元；
所述下拉单元与所述第二节点、第三节点及所述第二低压信号输入端电性连接，用于在所述第三节点的信号控制下将所述第二低压信号输入端输入的信号传输至所述第二节点。
在本申请的显示驱动电路中，所述下拉单元包括第三晶体管，所述第三晶体管的栅极电性连接所述第三节点，所述第三晶体管的源极电性连接所述第二低压信号输入端，所述第三晶体管的漏极电性连接所述第二节点。
在本申请的显示驱动电路中，所述第三晶体管为n型晶体管或p型晶体管。
在本申请的显示驱动电路中，所述驱动单元还包括下拉控制单元；
所述下拉控制单元与所述第一节点、第二级联信号输入端及所述第一低压信号输入端电性连接，用于在所述第二级联信号输入端输入的信号控制下将所述第一低压信号输入端输入的信号传输至所述第一节点。
在本申请的显示驱动电路中，所述下拉控制单元包括第四晶体管，所述第四晶体管的栅极电性连接所述第二级联信号输入端，所述第四晶体管的源极电性连接所述第一低压信号输入端，所述第四晶体管的漏极电性连接所述第一节点。
在本申请的显示驱动电路中，所述第四晶体管为n型晶体管或p型晶体管。
在本申请的显示驱动电路中，所述驱动单元还包括下拉维持单元；
所述下拉维持单元与所述第一节点、所述第三节点、高压信号输入端及所述第一低压信号输入端电性连接，用于在所述第一节点的信号控制下将所述第一低压信号输入端输入的信号或所述高压信号输入端输入的信号传输至所述第三节点。
在本申请的显示驱动电路中，所述下拉维持单元包括第五晶体管、第六晶体管和第七晶体管，所述第五晶体管的源极和所述第六晶体管的源极电性连接所述第一低压信号输入端，所述第五晶体管的漏极和所述第六晶体管的栅极电性连接所述第一节点，所述第五晶体管的栅极和所述第六晶体管的漏极电性连接所述第三节点，所述第七晶体管的栅极和源极电性连接所述高压信号输入端，所述第七晶体管的漏极电性连接所述第三节点。
在本申请的显示驱动电路中，所述第五晶体管、所述第六晶体管和所述第七晶体管为n型晶体管或p型晶体管。
在本申请的显示驱动电路中，第n级驱动单元的所述第一级联信号输入端电性连接第n-1级驱动单元的所述级联信号输出端；第n级驱动单元的所述第二级联信号输入端电性连接第n+1级驱动单元的所述级联信号输出端；
其中，n为大于或等于2的整数。
在本申请的显示驱动电路中，第1级驱动单元的所述第一级联信号输入端电性连接启动信号线。
在本申请的显示驱动电路中，所述第一时钟信号输入端电性连接第一时钟信号线，所述第二时钟信号输入端电性连接第二时钟信号线，所述第一低压信号输入端电性连接第一低压信号线，所述第二低压信号输入端电性连接第二低压信号线，所述高压信号输入端电性连接高压信号线。
在本申请的显示驱动电路中，所述第一时钟信号线传输的时钟信号与所述第二时钟信号线传输的时钟信号相反。
 有益效果
本发明提供的显示驱动电路通过将电容和级联信号输出端设置在相互并联的两条支路上，从而消除所述电容对级联信号输出端输出信号的损耗，提升级联信号输出端输出信号的强度和稳定性；另外，又将级联信号输出端通过一开关晶体管连接低压信号输入端，以保证级联信号输出端在无高压信号输出时维持在低压状态，防止级联信号输出端出现输出信号波动。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术的显示驱动电路的驱动单元结构示意图；
图2是本发明实施例提供的显示驱动电路的单一驱动单元的结构示意图；
图3时本发明实施例提供的显示驱动电路的级联关系图；
图4时本发明实施例提供的显示驱动电路的输入/输出时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明实施例提供了一种显示驱动电路，通过将电容和级联信号输出端设置在相互并联的两条支路上，从而消除所述电容对级联信号输出端输出信号的损耗，提升级联信号输出端输出信号的强度和稳定性；另外，将级联信号输出端通过一开关晶体管连接低压信号输入端，以保证级联信号输出端在无高压信号输出时维持在低压状态，防止所述信号输出端出现输出信号波动。
如图2所示，是本发明实施例提供的显示驱动电路中的单级驱动单元的结构示意图。需要说明的是，所述显示驱动电路包括多级如图2所示的驱动单元，并且相邻所述驱动单元之间存在连接关系。
所述驱动单元包括上拉控制单元101和上拉单元102。
所述上拉控制单元101分别与第一时钟信号输入端21、第一级联信号输入端31及第一节点A电性连接。所述上拉控制单元101用于在所述第一时钟信号输入端21输入的信号的控制下将所述第一级联信号输入端31输入的信号传输至所述第一节点A。
具体地，所述上拉控制单元101包括第二晶体管T2，所述第二晶体管T2的栅极电性连接所述第一时钟信号输入端21，所述第二晶体管T2的源极电性连接所述级联信号输入端31，所述第二晶体管T2的漏极电性连接所述第一节点A。
需要说明的是，本发明实施例提供的显示驱动电路中使用的晶体管可以是n型晶体管，也可以是p型晶体管。为了便于理解本发明，在以下实施例中均以n型晶体管为例进行说明。应当理解的是，对于n型晶体管，当晶体管的栅极为高电平时，晶体管的源极与漏极导通，晶体管打开，反之晶体管关闭；对于p型晶体管，当晶体管的栅极为低电平时，晶体管的源极与漏极导通，晶体管打开，反之晶体管关闭。
所述上拉单元102分别与所述第一节点A、第二时钟信号输入端22及第二节点B电性连接。所述上拉单元102用于在所述第一节点A的信号控制下将所述第二时钟信号输入端22输入的信号传输至所述第二节点B。
具体地，所述上拉单元102包括电容Cp和第一晶体管T1。所述电容Cp的第一端电性连接所述第二时钟信号输入端22，所述电容Cp的第二端电性连接所述第一节点A。所述电容Cp用于耦合所述第一节点A和所述第二时钟信号输入端22的电位。所述第一晶体管T1的栅极电性连接所述第一节点A，所述第一晶体管T1的源极电性连接所述第二时钟信号输入端22，所述第一晶体管T1的漏极电性连接所述第二节点B。所述第一晶体管T1用于在所述第一节点A的电压信号控制下，将所述第二时钟信号输入端22输入的信号传输至所述第二节点B。
具体地，所述第二节点B电性连接级联信号输出端61。所述级联信号输出端61用于为显示面板的显示单元提供扫描信号。
需要说明的是，所述电容Cp的两端分别连接所述第二时钟信号输入端22和所述第一节点A，所述级联信号输出端61通过所述第一晶体管T1与所述电容Cp并联设置，因此，所述第二时钟信号输入端22经所述第一晶体管T1传输至所述级联信号输出端61的信号不会被所述电容Cp损耗，从而保证所述级联信号输出端61输出的信号具有足够的强度和稳定性。
根据本发明一实施例，如图2所示，所述驱动单元还包括下拉单元103、下拉控制单元104以及下拉维持单元105。
所述下拉单元103分别与所述第二节点B、第三节点C及第二低压信号输入端52电性连接。所述下拉单元103用于在所述第三节点C的信号控制下将所述第二低压信号输入端52输入的信号传输至所述第二节点B，从而下拉所述第二节点B的电位，使所述级联信号输出端61输出低电平。
具体地，所述下拉单元103包括第三晶体管T3，所述第三晶体管T3的栅极电性连接所述第三节点C，所述第三晶体管T3的源极电性连接所述第二低压信号输入端52，所述第三晶体管T3的漏极电性连接所述第二节点B。
所述下拉控制单元104分别与所述第一节点A、第二级联信号输入端32及第一低压信号输入端51电性连接。所述下拉控制单元104用于在所述第二级联信号输入端32输入的信号控制下将所述第一低压信号输入端51输入的信号传输至所述第一节点A，从而下拉所述第一节点A的电位。
具体地，所述下拉控制单元104包括第四晶体管T4，所述第四晶体管T4的栅极电性连接所述第二级联信号输入端32，所述第四晶体管T4的源极电性连接所述第一低压信号输入端51，所述第四晶体管T4的漏极电性连接所述第一节点A。
所述下拉维持单元105分别与所述第一节点A、所述第三节点C、高压信号输入端41及所述第一低压信号输入端51电性连接，用于在所述第一节点A的信号控制下将所述第一低压信号输入端51输入的信号或所述高压信号输入端41输入的信号传输至所述第三节点C，从而下拉或抬升所述第三节点C的电位。
具体地，所述下拉维持单元105包括第五晶体管T5、第六晶体管T6和第七晶体管T7。其中，所述第五晶体管T5的源极和所述第六晶体管T6的源极电性连接所述第一低压信号输入端51，所述第五晶体管T5的漏极和所述第六晶体管T6的栅极电性连接所述第一节点A，所述第五晶体管T5的栅极和所述第六晶体管T6的漏极电性连接所述第三节点C，所述第七晶体管T7的栅极和源极电性连接所述高压信号输入端41，所述第七晶体管T7的漏极电性连接所述第三节点C。
应当理解的是，所述第三节点C通过所述第六晶体管T6电性连接所述第一低压信号输入端51，从而当所述第六晶体管T6打开时，所述第三节点C被下拉至低电位；另外，所述第三节点C通过所述第七晶体管T7电性连接所述高压信号输入端41，所述第七晶体管T7为常开晶体管，从而当所述第六晶体管T6关闭时，所述第三节点C被抬升至高电位。
需要说明的是，本发明实施例提供的显示驱动电路通过所述第一低压信号输入端51下拉所述第一节点A的电位，同时通过第二低压信号输入端52下拉所述第二节点B的电位，可保证所述级联信号输出端61在无高压信号输出时维持在低压状态，防止因所述第二节点B的电位波动导致的所述级联信号输出端61输出的信号异常。
可选地，所述第一低压信号输入端51输入的电压小于所述第二低压信号输入端52输入的电压。应当理解的是，所述第三节点C分别通过所述第七晶体管T7和所述第六晶体管T6与所述高压信号输入端41和所述第一低压信号输入端51连接，在所述第七晶体管T7和所述第六晶体管T6均打开的情况下，为了使所述第三节点C下拉至足够低的电位，需将所述第一低压信号输入端51输入的电压设置的足够小。
在上述实施例中已经对所述显示驱动电路中的单个驱动单元的结构进行了说明。应当理解的是，本发明提供的显示驱动电路包括多级级联的驱动单元，下面针对所述显示驱动电路中的各级驱动单元之间的级联关系进行说明。
如图3所示，是本发明实施例提供的显示驱动电路的级联关系图。第n级驱动单元U (n)的所述第一级联信号输入端31电性连接第n-1级驱动单元U (n-1)的所述级联信号输出端61；第n级驱动单元U (n)的所述第二级联信号输入端32电性连接第n+1级驱动单元U (n+1)的所述级联信号输出端61；其中，n为大于或等于2的整数。
特别地，参考图3所示，当n=2时，第1级驱动单元的所述第一级联信号输入端31电性连接启动信号线STV。
如图3所示，对于任意一级驱动单元存在以下连接关系：所述第一时钟信号输入端21电性连接第一时钟信号线CK1，所述第一时钟信号线CK1用于向所述第一时钟信号输入端21传输第一时钟信号；所述第二时钟信号输入端22电性连接第二时钟信号线CK2，所述第二时钟信号线CK2用于向所述第二时钟信号输入端22传输第二时钟信号；所述第一低压信号输入端51电性连接第一低压信号线VL1，所述第一低压信号线VL1用于向所述第一低压信号输入端51传输第一低压信号；所述第二低压信号输入端52电性连接第二低压信号线VL2，所述第二低压信号线VL2用于向所述第二低压信号输入端52传输第二低压信号；所述高压信号输入端41电性连接高压信号线VH，所述高压信号线VH用于向所述高压信号输入端41传输高压信号。
需要说明的是，所述级联信号输出端61输出级联信号G，所述级联信号G可用于驱动显示面板的显示单元。
下面结合图2至图4对本发明实施例提供的显示驱动电路的输入/输出时序进行分析，其中图4是本发明实施例提供的显示驱动电路的输入/输出时序图。
在t1时间段内，所述第一时钟信号线CK1为高电平，所述第二时钟信号线CK2为低电平，第n-1级的级联信号G (n-1)为高电平。需要说明的是，当n=2时，所述第n-1级的级联信号G (n-1)对应为启动信号STV。所述第二晶体管T2打开，所述第一节点A接收所述第n-1级的级联信号G (n-1)表现为高电平。所述第一晶体管T1和所述第六晶体管T6打开，所述第三节点C被所述第一低压信号线VL1拉低为低电平，所述第三晶体管T3关闭，所述第二节点B接收所述第二时钟信号线CK2的信号表现为低电平，第n级的级联信号G (n)表现为低电平信号。
在t2时间段内，所述第一时钟信号线CK1为低电平，所述第二时钟信号线CK2为高电平，第n-1级的级联信号G (n-1)或启动信号STV为低电平。所述第二晶体管T2关闭，在所述电容Cp的电压耦合作用下，所述第一节点A的电平被进一步拉升，表现为更高电平。所述第一晶体管T1进一步打开，所述第三晶体管T3保持关闭，所述第二时钟信号线CK2的高电平传输至所述第二节点B，第n级的级联信号G (n)表现为高电平信号。
在t3时间段内，所述第一时钟信号线CK1为高电平，所述第二时钟信号线CK2为低电平。此时随着级联信号G的传递，第n+1级的级联信号G (n+1)为高电平。所述第四晶体管T4打开，所述第一节点A被所述第一低压信号线VL1下拉至低电平。所述第一晶体管T1和所述第六晶体管T6关闭，所述第三节点C被所述高压信号线VH抬升至高电平，所述第三晶体管T3打开，所述第二节点B被所述第二低压信号线VL2下拉至低电平，第n级的级联信号G (n)表现为低电平信号。
需要说明的是，在t2时间段内，所述第二时钟信号线CK2的信号直接通过所述第一晶体管T1传输至所述级联信号输出端61，所述电容Cp不会对传输至所述级联信号输出端61的信号造成损耗，从而保证所述级联信号输出端61输出稳定的级联信号。另外，在t3时间段及t3时间段之后的时间内，所述级联信号输出端61输出的级联信号始终被所述第二低压信号线VL2维持在低电平，从而防止因所述第二时钟信号线CK2的信号波动造成所述级联信号输出端61输出的级联信号异常跳动。
综上所述，虽然本发明以具体实施例揭露如上，但上述实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定发范围为准。

Claims (17)

  1. 一种显示驱动电路，其包括多级驱动单元，每级所述驱动单元包括：
    上拉控制单元，与第一时钟信号输入端、第一级联信号输入端及第一节点电性连接，用于在所述第一时钟信号输入端输入的信号的控制下将所述第一级联信号输入端输入的信号传输至所述第一节点；
    上拉单元，与所述第一节点、第二时钟信号输入端及第二节点电性连接，用于在所述第一节点的信号控制下将所述第二时钟信号输入端输入的信号传输至所述第二节点；
    所述第二节点电性连接级联信号输出端；
    其中，所述上拉单元包括电容和第一晶体管，所述电容的第一端电性连接所述第二时钟信号输入端，所述电容的第二端电性连接所述第一节点；所述第一晶体管的栅极电性连接所述第一节点，所述第一晶体管的源极电性连接所述第二时钟信号输入端，所述第一晶体管的漏极电性连接所述第二节点。
  2. 根据权利要求1所述的显示驱动电路，其中，所述上拉控制单元包括第二晶体管，所述第二晶体管的栅极电性连接所述第一时钟信号输入端，所述第二晶体管的源极电性连接所述级联信号输入端，所述第二晶体管的漏极电性连接所述第一节点。
  3. 根据权利要求2所述的显示驱动电路，其中，所述第一晶体管和所述第二晶体管为n型晶体管或p型晶体管。
  4. 根据权利要求1所述的显示驱动电路，其中，所述驱动单元包括第一低压信号输入端和第二低压信号输入端，所述第一低压信号输入端输入的电压小于所述第二低压信号输入端输入的电压。
  5. 根据权利要求4所述的显示驱动电路，其中，所述驱动单元还包括下拉单元；
    所述下拉单元与所述第二节点、第三节点及所述第二低压信号输入端电性连接，用于在所述第三节点的信号控制下将所述第二低压信号输入端输入的信号传输至所述第二节点。
  6. 根据权利要求5所述的显示驱动电路，其中，所述下拉单元包括第三晶体管，所述第三晶体管的栅极电性连接所述第三节点，所述第三晶体管的源极电性连接所述第二低压信号输入端，所述第三晶体管的漏极电性连接所述第二节点。
  7. 根据权利要求6所述的显示驱动电路，其中，所述第三晶体管为n型晶体管或p型晶体管。
  8. 根据权利要求5所述的显示驱动电路，其中，所述驱动单元还包括下拉控制单元；
    所述下拉控制单元与所述第一节点、第二级联信号输入端及所述第一低压信号输入端电性连接，用于在所述第二级联信号输入端输入的信号控制下将所述第一低压信号输入端输入的信号传输至所述第一节点。
  9. 根据权利要求8所述的显示驱动电路，其中，所述下拉控制单元包括第四晶体管，所述第四晶体管的栅极电性连接所述第二级联信号输入端，所述第四晶体管的源极电性连接所述第一低压信号输入端，所述第四晶体管的漏极电性连接所述第一节点。
  10. 根据权利要求9所述的显示驱动电路，其中，所述第四晶体管为n型晶体管或p型晶体管。
  11. 根据权利要求8所述的显示驱动电路，其中，所述驱动单元还包括下拉维持单元；
    所述下拉维持单元与所述第一节点、所述第三节点、高压信号输入端及所述第一低压信号输入端电性连接，用于在所述第一节点的信号控制下将所述第一低压信号输入端输入的信号或所述高压信号输入端输入的信号传输至所述第三节点。
  12. 根据权利要求11所述的显示驱动电路，其中，所述下拉维持单元包括第五晶体管、第六晶体管和第七晶体管，所述第五晶体管的源极和所述第六晶体管的源极电性连接所述第一低压信号输入端，所述第五晶体管的漏极和所述第六晶体管的栅极电性连接所述第一节点，所述第五晶体管的栅极和所述第六晶体管的漏极电性连接所述第三节点，所述第七晶体管的栅极和源极电性连接所述高压信号输入端，所述第七晶体管的漏极电性连接所述第三节点。
  13. 根据权利要求12所述的显示驱动电路，其中，所述第五晶体管、所述第六晶体管和所述第七晶体管为n型晶体管或p型晶体管。
  14. 根据权利要求11所述的显示驱动电路，其中，第n级驱动单元的所述第一级联信号输入端电性连接第n-1级驱动单元的所述级联信号输出端；第n级驱动单元的所述第二级联信号输入端电性连接第n+1级驱动单元的所述级联信号输出端；
    其中，n为大于或等于2的整数。
  15. 根据权利要求11所述的显示驱动电路，其中，第1级驱动单元的所述第一级联信号输入端电性连接启动信号线。
  16. 根据权利要求11所述的显示驱动电路，其中，所述第一时钟信号输入端电性连接第一时钟信号线，所述第二时钟信号输入端电性连接第二时钟信号线，所述第一低压信号输入端电性连接第一低压信号线，所述第二低压信号输入端电性连接第二低压信号线，所述高压信号输入端电性连接高压信号线。
  17. 根据权利要求16所述的显示驱动电路，其中，所述第一时钟信号线传输的时钟信号与所述第二时钟信号线传输的时钟信号相反。
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