WO2020133823A1 - Goa电路 - Google Patents
Goa电路 Download PDFInfo
- Publication number
- WO2020133823A1 WO2020133823A1 PCT/CN2019/083258 CN2019083258W WO2020133823A1 WO 2020133823 A1 WO2020133823 A1 WO 2020133823A1 CN 2019083258 W CN2019083258 W CN 2019083258W WO 2020133823 A1 WO2020133823 A1 WO 2020133823A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pull
- transistor
- goa
- terminal
- bootstrap capacitor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Definitions
- the invention relates to the field of liquid crystal display, in particular to a circuit for gate driver on array (GOA).
- GOA gate driver on array
- Array substrate row (Gate Driver on Array, GOA) circuits are currently widely used in liquid crystal display devices.
- GOA Gate Driver on Array
- the existing GOA circuit is shown in FIG. 1.
- the GOA unit circuit of each stage outputs a gate scan signal, STV is the start signal, and STV sends a high-level signal at the beginning of each frame. Then receive the clock signals CK and XCK, where CK and XCK are two high-frequency alternating current signals of opposite levels.
- the voltage VSS is a low-level direct current and is used to provide a reference level when the gate signal is pulled down.
- FIG. 2 is a timing diagram of a start signal STV, a clock signal CK/XCK, a low-voltage direct current VSS, and a gate scan signal G(N) in a GOA circuit in the prior art.
- the start signal STV sends a high level
- the clock The signal CK is at a high level
- the GOA unit of the first stage outputs the gate scan signal G1.
- the GOA unit of the second stage receives the gate scan signal G1, and when the clock signal XCK received by the GOA unit of the second stage is at a high level, the gate scan signal G2 is output.
- Each level of GOA unit will receive the gate scan signal generated by the previous level and alternately receive the clock signal CK or XCK, that is, the adjacent two levels of clock signals have opposite levels.
- the start signal STV is output.
- the GOA unit of each stage has a pull-down sustain unit and a pull-down unit.
- the pull-down unit of the Nth stage will have the gate scan signal G(N+1) of the next stage ) Connection, so when the next-level GOA unit acts to output the next-level gate scan signal G(N+1), the N-th level pull-down unit will pull down the current-level gate scan signal G(N) to low Level, the pull-down sustaining unit of the Nth stage maintains the gate scanning signal G(N) at a low level until the end of this frame.
- the charging time is H, which is the time interval for scanning each data line.
- H the time interval for scanning each data line.
- the present invention provides a GOA circuit with an HG2D structure, that is, when the number of data is twice the original, the number of gate drive circuits is reduced to half, so that the charging time is twice the original, so GOA
- the charging capacity of the unit solves the problem of poor display quality caused by insufficient charging time in the prior art solutions.
- the purpose of the embodiment is to provide a GOA circuit including several stages of GOA units, wherein the Nth stage GOA unit is used to output the nth stage gate scanning signal and the n+1th stage gate scanning signal, where n is equal to (2N -1), n and N are positive integers, and the GOA unit of the Nth stage includes a pull-up transistor, a pull-down circuit, a pull-down sustain unit, a first output unit, and a second output unit.
- the pull-down circuit includes a first pull-down transistor and a second pull-down transistor, wherein the control terminals of the first pull-down transistor and the second pull-down transistor are connected to the n+2th stage gate line.
- the pull-down sustain unit is connected to the output terminal of the pull-up transistor, and outputs the n-th gate scanning signal and the n+1-th gate scanning signal.
- the first output unit includes a first switching transistor and a first bootstrap capacitor, the control terminal of the first switching transistor is connected to the first terminal of the first bootstrap capacitor, and the input terminal of the first switching transistor Receive the first clock signal.
- the second output unit includes a second switching transistor and a second bootstrap capacitor, the control terminal of the second switching transistor is connected to the first terminal of the second bootstrap capacitor, and the input of the second switching transistor The terminal receives the second clock signal. Wherein the output end of the pull-up transistor, the control end of the first switching transistor, the control end of the second switching transistor, the first end of the first bootstrap capacitor and the second end of the bootstrap capacitor The first end is connected to node Q.
- the control terminal and the input terminal of the pull-up transistor receive the start signal.
- the control terminal of the pull-up transistor receives the n-2 stage start signal, and the input terminal of the pull-up transistor receives the n-2 stage gate scan signal.
- the first clock signal and the second clock signal are the same clock signal source.
- the input terminal of the first pull-down transistor is connected to the node Q, and the input terminal of the second pull-down transistor is connected to the n+1th gate scanning signal.
- the input terminal of the first pull-down transistor is connected to the node Q, and the input terminal of the second pull-down transistor is connected to the n+1th gate scanning signal.
- the pull-down sustain unit is connected to the first voltage source and the second voltage source.
- the second terminal of the first bootstrap capacitor and the output terminal of the first switching transistor are connected to the n-th gate scanning signal.
- the second terminal of the second bootstrap capacitor and the output terminal of the second switching transistor are connected to the n+1th gate scanning signal.
- the pulses of the nth stage gate scan signal and the n+1th stage gate scan signal are the same.
- the present invention also provides a liquid crystal display device including the above-mentioned GOA circuit.
- the GOA circuit provided by the present invention and the liquid crystal display device having the GOA circuit of the present invention can reduce the production cost and simplify the manufacturing process, and can effectively save the wiring space of the GOA circuit, thereby further narrowing the liquid crystal display device frame.
- Fig. 1 is a circuit diagram of a prior art GOA.
- Figure 2 is a timing diagram of a GOA circuit in the prior art.
- Fig. 3 is a circuit diagram of the GOA of the present invention.
- FIG. 4 is a circuit diagram of the GOA unit of the present invention.
- FIG. 5 is a timing diagram of the GOA circuit of the present invention.
- first and second are used to distinguish the constituent elements from other constituent elements, and not to limit the nature, order, or order of the corresponding constituent elements by the terms. .
- a certain part is “included” or “has” a certain constituent element, it means that when there is no exclusive record, it does not exclude other constituent elements, but also includes other constituent elements.
- the terms “... part” and “unit” described in the specification refer to a unit that processes at least one function or action, and it is realized by hardware or software or a combination of hardware and software.
- Fig. 3 is a circuit diagram of the GOA of the present invention.
- the GOA unit of each stage uses two signal lines to connect the clock signal CK, and the GOA unit 20 of each stage receives the DC low-level voltage sources VSSG and VSSQ.
- the gate scan signal Gn generated by the GOA unit 20 of the Nth stage is transmitted to the GOA unit 20 of the N+1th stage, and the GOA unit 20 of the Nth stage receives the generated by the GOA unit 20 of the N+1th stage Gate scanning signal Gn+2.
- the GOA unit 20 of each stage includes a pull-down sustain circuit 30, a pull-down unit 40, a pull-up transistor T31, a first switching transistor T32, a second switching transistor T33, and a first bootstrapping The capacitor Cb1 and the second bootstrap capacitor Cb2.
- the pull-up transistor T31 outputs a gate signal according to the start signal STn-2 of the previous stage and the gate scan signal Gn-2 of the previous stage, and the pull-down sustain unit 30 receives the gate signal and generates gate scan signals Gn and Gn+ 1.
- the first switching transistor T32 is turned on after the charging of the first bootstrap capacitor Cb1 is completed, and outputs the gate scan signal Gn.
- the second switching transistor T33 is turned on after the charging of the second bootstrap capacitor Cb2 is completed, and outputs the gate scan signal Gn+1.
- the pull-up transistor T31 receives the start signal STn-2 of the previous stage and the gate scan signal Gn-2 of the previous stage. Specifically, in addition to the GOA unit of the first stage, in the GOA unit 20 of the Nth stage, the input terminal of the pull-up transistor T31 is connected to the gate scanning line Gn-2 of the previous stage, and the control terminal of the pull-up transistor T31 The start signal STn-2 of the previous stage is connected, and the output terminal of the pull-up transistor T31 outputs the gate signal to the node Q(N). In the GOA unit of the first stage, both the input terminal and the control terminal of the pull-up transistor T31 receive the start signal ST, and the output terminal of the pull-up transistor T31 also outputs the gate signal to the node Q(N).
- the input terminal of the first switching transistor T32 receives the first clock signal CK1, the control terminal is connected to the node Q(N), and the output terminal is connected to the n-th gate signal line.
- the input terminal of the second switching transistor T33 receives the second clock signal CK2, the control terminal is connected to the node Q(N), and the output terminal is connected to the n+1th gate signal line.
- One end of the first bootstrap capacitor Cb1 is connected to the control end of the first switching transistor T32, and the other end is connected to the n-th gate signal line.
- One end of the second bootstrap capacitor Cb2 is connected to the control end of the second switching transistor T33, and the other end is connected to the n+1th gate signal line.
- the pull-up transistor T31 when the pull-up transistor T31 receives ST/ST or Gn-2/STn-2, it will output a high level to the node Q(N), and the first bootstrap capacitor Cb1 and the second bootstrap capacitor Cb2 will start to charge. After the charging of the first bootstrap capacitor Cb1 and the second bootstrap capacitor Cb2 is completed, the first switching transistor T32 and the second switching transistor T33 are turned on, so that the gate scan signals Gn and Gn+1 are at a high level.
- the first pull-down transistor T34 and the second pull-down transistor T35 constitute a pull-down unit 40.
- the input terminal of the first pull-down transistor T34 is connected to the nth and n+1th gate lines, and the output terminal is connected to the low voltage direct current VSSG.
- the input terminal of the second pull-down transistor T35 is connected to the node Q(N), and the output terminal is connected to the low-voltage direct current VSSQ.
- the control terminal of the first pull-down transistor T34 and the control terminal of the second pull-down transistor T35 are connected to each other and to the n+2th gate signal line in the GOA unit of the next stage.
- the first pull-down transistor T34 and the second pull-down transistor T35 connect the node Q(N), the gate scan signal Gn and the gate The level of the scan signal Gn+1 is pulled down.
- the levels of the node Q(N), the gate scan signal Gn, and the gate scan signal Gn+1 will all be Maintain at low level.
- the start signal ST begins to output a high-level signal, representing the start of the first frame.
- the control terminal and the input terminal of the pull-up transistor T31 in the GOA unit of the first stage both receive the start signal ST.
- the pull-up transistor T31 will turn on the high-level start signal ST to the node Q(1).
- the first bootstrap capacitor Cb1 and the second bootstrap capacitor Cb2 in the first-stage GOA unit start to charge.
- the first bootstrap capacitor Cb1 and the second bootstrap capacitor Cb2 complete charging, turning on the first switching transistor T32 and the second switching transistor T33, and at the same time the clock signals CK1 and CK2 output high levels to scan the gate
- the signals G1 and G2 are output to the gate line.
- the input terminal of the pull-up transistor of the second-stage GOA unit simultaneously receives the gate scan signal G1, and then at time t2, the first bootstrap capacitor and the second bootstrap in the second-stage GOA unit
- the capacitor charging is completed, where the distance between t0 and t2 is 2H, that is, the charging time of the first and second bootstrap capacitors is 2H, which is twice the charging time of the prior art.
- the control terminals of the first pull-down transistor and the second pull-down transistor in the pull-down unit of the first-stage GOA unit will receive high power and low power.
- the first pull-down transistor pulls the gate scan signals G1 and G2 to the same level as VSSG, and the second pull-down transistor causes the telecommunication of the node Q(1) to be pulled down to the same level as VSSQ, thereby making the first stage
- the first switching transistor and the second switching transistor in the GOA unit are turned off, so that the clock signals CK1 and CK2 stop outputting.
- t1 and t2 are separated by 4.8H. Then, under the action of the pull-down sustaining unit in the first stage GOA, the gate scanning signals G1 and G2 are both kept at a low level until the end of this frame.
- the pull-up transistor T31 outputs a high level to the node Q(N), at this time node Q(N) charges the first bootstrap capacitor Cb1 and the second bootstrap capacitor Cb2, at this time the first clock signal CK1, the second clock signal CK2, the gate scan signal Gn and the gate
- the scanning signals Gn+1 are all low level. Since the node Q(N) simultaneously charges the first bootstrap capacitor Cb1 and the second bootstrap capacitor Cb2, the time required for charging is 2H.
- the first clock signal CK1, the second clock signal CK2, the gate scan signal Gn and the gate scan signal Gn+1 are all high level.
- the potential of the node Q(N) will reach a level close to twice the gate scanning signals Gn and Gn+1.
- the GOA unit of the Nth stage will transmit the gate scanning signal to the GOA unit of the next stage as the input signal of the input terminal of the pull-up transistor of the next stage.
- the control terminals of the first pull-down transistor T34 and the second pull-down transistor T35 are both connected to the gate scan signal Gn+2, when the gate scan signal Gn+2 output by the GOA unit of the next stage (N+1 stage) At the same time, the pull-down unit 40 of the N-th stage GOA unit will start to function.
- Turning on the first pull-down transistor T34 pulls the gate scan signals Gn and Gn+1 to the same level as SSG
- turning on the second pull-down transistor T35 pulls the node Q(N) to the same level as VSSQ, so that the first The on transistor T32 and the second switching transistor T33 are turned off, and the outputs of the gate scan signals Gn and Gn+1 are stopped.
- the first clock signal CK1 and the second clock signal CK2 may be the same clock signal source, but they are respectively transmitted through two unused signal lines, so as to realize the adjacent gate scan signal Gn in the GOA unit of the Nth stage And Gn+1 is the same pulse.
- a two-stage GOA unit was originally required to output two gate scan signals.
- the adjacent gate scan signals Gn and Gn+1 share the same in the N-th stage GOA unit
- the clock signal source, pull-down sustain unit and pull-down unit so only the components and signal source required by the first-level GOA unit are needed, so that two gate scan signals can be output. Therefore, since the number of required down-hold sustaining circuits is halved, the production cost can be greatly reduced, the manufacturing process can be simplified, and the wiring space of the GOA circuit can be effectively saved, thereby further narrowing the frame of the liquid crystal display device.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
一种GOA电路(10)及液晶显示装置。GOA电路(10)包括数级的GOA单元(20),其中第N级GOA单元(20)用来输出第n级栅极扫描信号(Gn)以及第n+1级栅极扫描信号(Gn+1),其中n等于(2N-1),n与N为正整数,第N级的GOA单元(20)包括上拉晶体管(T31)、下拉电路(40)、下拉维持单元(30)、第一输出单元及第二输出单元。每级GOA单元(20)输出两个栅极扫描信号,因此能减少GOA单元(20)的数量,节省布线空间而窄化显示器的边框。
Description
本发明涉及液晶显示领域,特别是涉及一种用于阵列基板行(Gate Driver on Array, GOA)电路。
阵列基板行(Gate Driver on Array, GOA)电路目前广泛利用于液晶显示装置,通过将栅极驱动电路集成于阵列基板上,藉此节省液晶显示装置所需的栅极驱动芯片数,从而节省生产成本,同时随著栅极驱动芯片数量的减少,也减少了栅极驱动电路所需的面积,使窄化液晶显示装置边框得以实现。
现有的GOA电路如图1所示,每一级的GOA单元电路输出一个栅极扫描信号,STV是起始信号,STV在每一帧(frame)开始时会送出一个高电平的信号,接著接收时钟信号CK及XCK,其中CK与XCK是电平相反的两个高频交流电信号。电压VSS是低电平直流电,用来提供栅信号下拉时参考电平。
图2为现有技术的GOA电路中起始信号STV、时钟信号CK/XCK、低压直流电VSS与栅极扫描信号G(N)的时序图,当起始信号STV送出高电平后、接著时钟信号CK为高电平,第一级的GOA单元输出栅极扫描信号G1。第二级的GOA单元会接收栅极扫描信号G1,当第二级GOA单元接收到的时钟信号XCK为高电平后,输出栅极扫描信号G2。每一级GOA单元会接收上一级产生的栅极扫信号,并交替接收时钟信号CK或XCK,即相邻的两级时钟信号电平相反。在每一帧开始时,输出起始信号STV,同时每一级的GOA单元皆有下拉维持单元及下拉单元,第N级的下拉单元会与下一级的栅极扫描信号G(N+1)连接,因此当下一级GOA单元作用而输出下一级的栅极扫描信号G(N+1)时,第N级的下拉单元会将本级的栅极扫描信号G(N)下拉为低电平,第N级的下拉维持单元则将栅极扫描信号G(N)维持在低电平,直到此帧结束。
然而,现有的GOA单元,其充电时间为H,即每一数据线Data line扫描的时间间隔。然而当现有的GOA电路应用于大尺寸高解析液晶显示装置时,由于驱动电路的走线较长,导致寄生阻抗较大,使得充电时间不足而导致液晶显示装置出现色彩的偏差。
因此,本发明提供一种GOA电路,具有HG2D的结构,即当Data的数量为原本的两倍时,栅极驱动电路的数量减为一半,使得充电时间为原来的两倍,因此可以提GOA单元的充电能力,解决现有技术方案中因充电时间不足而造成显示品质不佳的问题。
实施例的目的在于提供一种GOA电路,包括数级的GOA单元,其中第N级GOA单元用来输出第n级栅极扫描信号以及第n+1级栅极扫描信号,其中n等于(2N-1),n与N为正整数,所述第N级的GOA单元包括上拉晶体管、下拉电路、下拉维持单元、第一输出单元、及第二输出单元。所述下拉电路包括第一下拉晶体管及第二下拉晶体管,其中第一下拉晶体管及第二下拉晶体管的控制端与第n+2级栅极线相连接。所述下拉维持单元连接所述上拉晶体管的输出端,并输出所述第n级栅极扫描信号以及第n+1级栅极扫描信号。所述第一输出单元包括第一开关晶体管及第一自举电容,所述第一开关晶体管的控制端与所述第一自举电容的第一端相连,所述第一开关晶体管的输入端接收第一时钟信号。所述第二输出单元,包括第二开关晶体管及第二自举电容,所述第二开关晶体管的控制端与所述第二自举电容的第一端相连,所述第二开关晶体管的输入端接收第二时钟信号。其中所述上拉晶体管的输出端、所述第一开关晶体管的控制端、所述第二开关晶体管的控制端、所述第一自举电容的第一端及所述第二自举电容的第一端与节点Q相连。
较佳地,当N等于1时,所述上拉晶体管的控制端与输入端接收起始信号。
较佳地,当N大于1时,所述上拉晶体管的控制端接收第n-2级起始信号,所述上拉晶体管的输入端接收第n-2级栅极扫描信号。
较佳地,所述第一时钟信号以及所述第二时钟信号为相同的时钟信号源。
较佳地,所述第一下拉晶体管的输入端与所述节点Q相连,所述第二下拉晶体管的输入端与所述第n+1级栅极扫描信号相连。
较佳地,所述第一下拉晶体管的输入端与所述节点Q相连,所述第二下拉晶体管的输入端与所述第n+1级栅极扫描信号相连。
较佳地,所述下拉维持单元与所述第一电压源及所述第二电压源相连。
较佳地,所述第一自举电容的第二端以及所述第一开关晶体管的输出端与所述第n级栅极扫描信号相连。
较佳地,所述第二自举电容的第二端以及所述第二开关晶体管的输出端与所述第n+1级栅极扫描信号相连。
较佳地,所述第n级栅极扫描信号以及所述第n+1级栅极扫描信号的脉冲相同。
本发明还提供一种液晶显示装置,其包括上述的GOA电路。
通过本发明所提供的GOA电路及具有本发明GOA电路的液晶显示装置,可减少生产成本及简化制作的程序,同时可以有效节省GOA电路的布线空间,进而得以更进一步地窄化液晶显示装置的边框。
图1为现有技术的GOA电路图。
图2为现有技术的GOA电路时序图。
图3为本发明的GOA电路图。
图4为本发明GOA单元的电路图。
图5为本发明GOA电路的时序图。
下面,通过例示的附图对本发明的一部分实施例进行具体说明。在各个附图的构成要素附加参照符号时,应当注意,对于相同的构成要素,即使标注在不同的附图上,尽可能的具有相同的符号。并且,在对本发明进行说明时,在判断相关的公知的构成或功能的具体说明混淆本发明的要旨的情况下,省略其具体说明。
并且,在对本发明的构成要素进行说明时,使用第一、第二等用语是用语仅用于将该构成要素与其它构成要素区分,并非通过该用语限定相应构成要素的本质或次序或顺序等。在整个说明中,称某一部分“包括”、“具有”某一构成要素时,其是指在不存在排它性记载的情况下,并非排除其它构成要素,也包括其它构成要素。并且,记载于说明书中的“…部”、“单元”等用语是指处理至少一个功能或动作的单位,并且,其通过硬件或软件或者硬件及软件的结合实现。
图3为本发明的GOA电路图。本发明的GOA电路包括多级的GOA单元20,每一级GOA单元20输出两个栅极扫描信号,在第N级的GOA单元20会输出两个栅极扫描信号Gn及Gn+1,其中n=(2N-1),n与N为正整数。每一级的GOA单元利用两条信号线连接时钟信号CK,并且每一级的GOA单元20都会接收直流低电平的电压源VSSG与VSSQ。其中第N级的GOA单元20所产生的栅极扫描信号Gn会传送到第N+1级的GOA单元20,且第N级的GOA单元20会接收第N+1级GOA单元20所产生的栅极扫描信号Gn+2。
图4为本发明GOA单元20的电路图,每一级的GOA单元20中包括下拉维持电路30、下拉单元40、上拉晶体管T31、第一开关晶体管T32、第二开关晶体管T33、第一自举电容Cb1以及第二自举电容Cb2。上拉晶体管T31根据上一级的起始信号STn-2及上一级的栅极扫描信号Gn-2输出栅极信号,下拉维持单元30接收栅极信号并产生栅极扫描信号Gn以及Gn+1。第一开关晶体管T32在第一自举电容Cb1充电完成后导通,并输出栅极扫描信号Gn。第二开关晶体管T33在第二自举电容Cb2充电完成后导通,并输出栅极扫描信号Gn+1。本发明的GOA单元20详细说明如下。
上拉晶体管T31接收上一级的起始信号STn-2及上一级的栅极扫描信号Gn-2。具体而言,除了第一级的GOA单元外,在第N级的GOA单元20中,上拉晶体管T31的输入端连接上一级的栅极扫描线Gn-2,上拉晶体管T31的控制端连接上一级的起始信号STn-2,上拉晶体管T31的输出端输出栅极信号至节点Q(N)。而在第一级的GOA单元中,上拉晶体管T31的输入端与控制端皆接收起始信号ST,上拉晶体管T31的输出端同样输出栅极信号至节点Q(N)。
第一开关晶体管T32的输入端接收第一时钟信号CK1,控制端与节点Q(N)相连,输出端与第n条栅极信号线相连。第二开关晶体管T33的输入端接收第二时钟信号CK2,控制端与节点Q(N)相连,输出端与第n+1修栅极信号线相连。第一自举电容Cb1的一端与第一开关晶体管T32的控制端相连,另一端与第n条栅极信号线相连。第二自举电容Cb2的一端与第二开关晶体管T33的控制端相连,另一端与第n+1条栅极信号线相连。因此当上拉晶体管T31接收了ST/ST或Gn-2/STn-2后,会输出高电平至节点Q(N),第一自举电容Cb1及第二自举电容Cb2会开始充电。在第一自举电容Cb1及第二自举电容Cb2充电完成后,第一开关晶体管T32与第二开关晶体管T33导通,使栅极扫描信号Gn及Gn+1为高电平。
第一下拉晶体管T34与第二下接晶体管T35组成一下拉单元40。第一下拉晶体管T34的输人端与第n条及第n+1条栅极线相连,输出端连接至低压直流电VSSG。第二下拉晶体管T35的输入端与节点Q(N)相连,输出端连接至低压直流电VSSQ。第一下拉晶体管T34的控制端与第二下拉晶体管T35的控制端相互连接,并连接至下一级的GOA单元中第n+2条栅极信号线。因此当下一级的GOA单元开始运作后,在栅极扫描信号Gn+2的作用下,第一下拉晶体管T34与第二下拉晶体管T35将节点Q(N)、栅极扫描信号Gn及栅极扫描信号Gn+1的电平下拉,接下来在下拉维持单元30的作用下,在此帧结束前,节点Q(N)、栅极扫描信号Gn及栅极扫描信号Gn+1的电平都会维持在低电平。
图5为本发明GOA电路的时序图。在时点t0时,起始信号ST开始输出高电平信号,代表第一帧开始。此时第一级的GOA单元中上拉晶体管T31的控制端与输入端均接收到起始信号ST。上拉晶体管T31会导通高电平的起始信号ST至节点Q(1),此时第一级GOA单元中的第一自举电容Cb1及第二自举电容Cb2开始充电。在t1时,第一自举电容Cb1及第二自举电容Cb2完成充电,使第一开关晶体管T32及第二开关晶体管T33导通,同时时钟信号CK1与CK2输出高电平,使栅极扫描信号G1与G2输出至栅极线。
在时点t1时,第二级GOA单元的上拉晶体管的输入端同时接收栅极扫描信号G1,接著在时点t2时,第二级GOA单元中的第一自举电容及第二自举电容充电完成,其中t0与t2的间距为2H,即第一与第二自举电容的充电时间为2H,为现有技术的充电时间的两倍。
在时点t3时,因为第二级GOA单元输出栅极扫描信号G3时,第一级GOA单元中的下拉单元中第一下拉晶体管与第二下拉晶体管的控制端会接收到高电低进而导通,第一下拉晶体管使栅极扫描信号G1及G2下拉至与VSSG等电平,第二下拉晶体管使节点Q(1)的电信被下拉至与VSSQ等电平,进而使第一级GOA单元中的第一开关晶体管与第二开关晶体管截止,使时钟信号CK1与CK2停止输出。在本发明的实施例中,t1与t2相隔4.8H。接著在第一级GOA中的下拉维持单元的作用下,栅极扫描信号G1与G2在这一帧结束前皆保持在低电平。
因此在第N级GOA单元中,上拉晶体管T31上一级(第N-1级)的栅极扫描信号Gn-2与起始信号STn-2后,上拉晶体管T31输出高电平至节点Q(N),此时节点Q(N)对第一自举电容Cb1及第二自举电容Cb2充电,此时第一时钟信号CK1、第二时钟信号CK2、栅极扫描信号Gn及栅极扫描信号Gn+1皆为低电平。因为节点Q(N)同时对第一自举电容Cb1及第二自举电容Cb2充电,因此充电所需的时间为2H。当第一自举电容Cb1及第二自举电容Cb2充电完成后,第一时钟信号CK1、第二时钟信号CK2、栅极扫描信号Gn及栅极扫描信号Gn+1皆为高电平,此时节点Q(N)的电位会来到接近两倍栅极扫描信号Gn及Gn+1的电平。同时第N级的GOA单元会将栅极扫描信号传送至下一级的GOA单元,作为下一级上拉晶体管输入端的输入信号。
由于第一下拉晶体管T34与第二下拉晶体管T35的控制端皆与栅极扫描信号Gn+2相连,因此当下一级(第N+1级)的GOA单元输出的栅极扫描信号Gn+2时,同时第N级GOA单元的下拉单元40会开始作用。第一下拉晶体管T34导通使栅极扫描信号Gn与Gn+1下拉至与SSG相同电平,第二下拉晶体管T35导通使节点Q(N)下拉至与VSSQ相同电平,使得第一开开晶体管T32与第二开关晶体管T33截止,而停出栅极扫描信号Gn与Gn+1的输出。
接著在下拉维持单元30的作用下,栅极扫描信号Gn、栅极扫描信号Gn+1及节点Q(N)的电平在此帧结束前皆保持在低电平。其中第一时钟信号CK1与第二时钟信号CK2可以是同一时钟信号源,但分别通过两条不用的信号线信输,以实现在第N级的GOA单元中,相邻的栅极扫描信号Gn及Gn+1为相同的脉冲。
现有技术中原本需要两级的GOA单元才能输出两个栅极扫信号,通过本发明的GOA电路,使第N级的GOA单元中,相邻的栅极扫描信号Gn及Gn+1共用相同的时钟信号源、下拉维持单元及下拉单元,因此只需一级的GOA单元所需的元件及信号源,使可实现输出两个栅极扫描信号。因此由于所需的下接维持电路数量减半,可大大地减少生产成本,简化制作的程序,同时可以有效节省GOA电路的布线空间,进而得以更进一步地窄化液晶显示装置的边框。
综上说明,仅为例示说明本发明的技术思想,本实施例所属技术领域的普通技术人员在不脱离本发明的本质特征的范围内能够进行各种修正及变形。因此,本实施例用于说明本发明的技术思想而非限定本发明的技术思想,并非通过该实施例限定本发明的技术思想的范围。本发明的保护范围应通过权利要求范围解释,对于与其同等范围内的所有技术思想,以包括于本发明的权利要求进行解释。
Claims (11)
- 一种GOA (Gate Driver on Array)电路,其包括数级的GOA单元,其中第N级GOA单元用来输出第n级栅极扫描信号以及第n+1级栅极扫描信号,其中n等于(2N-1),n与N为正整数,所述第N级的GOA单元包括:上拉晶体管;下拉电路,包括第一下拉晶体管及第二下拉晶体管,其中所述第一下拉晶体管及所述第二下拉晶体管的控制端与第n+2级栅极线相连接;下拉维持单元,连接所述上拉晶体管的输出端,并输出所述第n级栅极扫描信号以及所述第n+1级栅极扫描信号;第一输出单元,包括第一开关晶体管及第一自举电容,所述第一开关晶体管的控制端与所述第一自举电容的第一端相连,所述第一开关晶体管的输入端接收第一时钟信号;第二输出单元,包括第二开关晶体管及第二自举电容,所述第二开关晶体管的控制端与所述第二自举电容的第一端相连,所述第二开关晶体管的输入端接收第二时钟信号;其中所述上拉晶体管的输出端、所述第一开关晶体管的控制端、所述第二开关晶体管的控制端、所述第一自举电容的第一端及所述第二自举电容的第一端与节点Q相连;所述第一下拉晶体管的输入端与所述节点Q相连,所述第二下拉晶体管的输入端与所述第n+1级栅极扫描信号相连,所述第一下拉晶体管的输出端与第一电压源相连,所述第二下拉晶体管的输出端与第二电压源相连,所述第一下拉晶体管的输出端与第一电压源相连,所述第二下拉晶体管的输出端与第二电压源相连,所述下拉维持单元与所述第一电压源及所述第二电压源相连。
- 一种GOA (Gate Driver on Array)电路,其包括数级的GOA单元,其中第N级GOA单元用来输出第n级栅极扫描信号以及第n+1级栅极扫描信号,其中n等于(2N-1),n与N为正整数,所述第N级的GOA单元包括:上拉晶体管;下拉电路,包括第一下拉晶体管及第二下拉晶体管,其中所述第一下拉晶体管及所述第二下拉晶体管的控制端与第n+2级栅极线相连接;下拉维持单元,连接所述上拉晶体管的输出端,并输出所述第n级栅极扫描信号以及所述第n+1级栅极扫描信号;第一输出单元,包括第一开关晶体管及第一自举电容,所述第一开关晶体管的控制端与所述第一自举电容的第一端相连,所述第一开关晶体管的输入端接收第一时钟信号;第二输出单元,包括第二开关晶体管及第二自举电容,所述第二开关晶体管的控制端与所述第二自举电容的第一端相连,所述第二开关晶体管的输入端接收第二时钟信号;其中所述上拉晶体管的输出端、所述第一开关晶体管的控制端、所述第二开关晶体管的控制端、所述第一自举电容的第一端及所述第二自举电容的第一端与节点Q相连。
- 根据权利要求2所述的GOA电路,其中当N等于1时,所述上拉晶体管的控制端与输入端接收起始信号。
- 根据权利要求2所述的GOA电路,其中当N大于1时,所述上拉晶体管的控制端接收第n-2级起始信号,所述上拉晶体管的输入端接收第n-2级栅极扫描信号。
- 根据权利要求2所述的GOA电路,其中所述第一时钟信号以及所述第二时钟信号为相同的时钟信号源。
- 根据权利要求2所述的GOA电路,其中所述第一下拉晶体管的输入端与所述节点Q相连,所述第二下拉晶体管的输入端与所述第n+1级栅极扫描信号相连。
- 根据权利要求2所述的GOA电路,其中所述第一下拉晶体管的输出端与第一电压源相连,所述第二下拉晶体管的输出端与第二电压源相连。
- 根据权利要求7所述的GOA电路,其中所述下拉维持单元与所述第一电压源及所述第二电压源相连。
- 根据权利要求2所述的GOA电路,其中所述第一自举电容的第二端以及所述第一开关晶体管的输出端与所述第n级栅极扫描信号相连。
- 根据权利要求2所述的GOA电路,其中所述第二自举电容的第二端以及所述第二开关晶体管的输出端与所述第n+1级栅极扫描信号相连。
- 根据权利要求2所述的GOA电路,其中所述第n级栅极扫描信号以及所述第n+1级栅极扫描信号的脉冲相同。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811615683.6 | 2018-12-27 | ||
CN201811615683.6A CN109410886A (zh) | 2018-12-27 | 2018-12-27 | Goa电路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2020133823A1 true WO2020133823A1 (zh) | 2020-07-02 |
Family
ID=65462268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2019/083258 WO2020133823A1 (zh) | 2018-12-27 | 2019-04-18 | Goa电路 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN109410886A (zh) |
WO (1) | WO2020133823A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109410886A (zh) * | 2018-12-27 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | Goa电路 |
CN111028755B (zh) * | 2019-12-06 | 2022-07-12 | 武汉华星光电半导体显示技术有限公司 | 一种单级goa电路及显示装置 |
CN110910853B (zh) * | 2019-12-19 | 2021-10-29 | 京东方科技集团股份有限公司 | 一种移位寄存器及其驱动方法、栅极驱动电路 |
CN111477190A (zh) * | 2020-05-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Goa器件及栅极驱动电路 |
CN111884637B (zh) * | 2020-07-10 | 2024-05-31 | 苏州赛芯电子科技股份有限公司 | 自举电路和功率芯片 |
KR102678721B1 (ko) * | 2020-12-01 | 2024-06-26 | 엘지디스플레이 주식회사 | 게이트 회로 및 디스플레이 장치 |
CN114664245B (zh) * | 2022-05-25 | 2022-11-15 | 惠科股份有限公司 | 驱动基板及其显示面板 |
CN115938324A (zh) * | 2022-11-22 | 2023-04-07 | 武汉华星光电半导体显示技术有限公司 | Goa电路及显示面板 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130107528A (ko) * | 2012-03-22 | 2013-10-02 | 삼성디스플레이 주식회사 | 게이트 구동 회로 및 이를 이용한 표시 장치 |
CN103680451A (zh) * | 2013-12-18 | 2014-03-26 | 深圳市华星光电技术有限公司 | 用于液晶显示的goa电路及显示装置 |
CN104050941A (zh) * | 2014-05-27 | 2014-09-17 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路 |
CN105096865A (zh) * | 2015-08-06 | 2015-11-25 | 京东方科技集团股份有限公司 | 移位寄存器的输出控制单元、移位寄存器及其驱动方法以及栅极驱动装置 |
CN106531053A (zh) * | 2017-01-06 | 2017-03-22 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极驱动电路及显示面板 |
CN106601175A (zh) * | 2017-01-09 | 2017-04-26 | 京东方科技集团股份有限公司 | 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 |
CN109036310A (zh) * | 2018-08-03 | 2018-12-18 | 深圳市华星光电半导体显示技术有限公司 | Goa单元及其驱动方法 |
CN109410886A (zh) * | 2018-12-27 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | Goa电路 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009084331A1 (ja) * | 2007-12-27 | 2009-07-09 | Sharp Kabushiki Kaisha | 液晶表示装置、液晶表示装置の駆動方法、テレビジョン受像機 |
WO2009084332A1 (ja) * | 2007-12-27 | 2009-07-09 | Sharp Kabushiki Kaisha | 液晶表示装置、液晶表示装置の駆動方法、テレビジョン受像機 |
JP5669453B2 (ja) * | 2010-06-22 | 2015-02-12 | 株式会社ジャパンディスプレイ | 双方向シフトレジスタ、及びこれを用いた画像表示装置 |
TWI411232B (zh) * | 2010-12-10 | 2013-10-01 | Au Optronics Corp | 移位暫存器電路 |
TW201301289A (zh) * | 2011-06-29 | 2013-01-01 | Au Optronics Corp | 移位暫存器電路 |
CN202332230U (zh) * | 2011-11-25 | 2012-07-11 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路及其液晶显示装置 |
CN103197481B (zh) * | 2013-03-27 | 2015-07-15 | 深圳市华星光电技术有限公司 | 阵列基板及液晶显示装置 |
CN105895046B (zh) * | 2016-06-22 | 2018-12-28 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路以及显示设备 |
CN106128380B (zh) * | 2016-08-16 | 2019-01-01 | 深圳市华星光电技术有限公司 | Goa电路 |
CN106910453A (zh) * | 2017-05-09 | 2017-06-30 | 京东方科技集团股份有限公司 | 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置 |
-
2018
- 2018-12-27 CN CN201811615683.6A patent/CN109410886A/zh active Pending
-
2019
- 2019-04-18 WO PCT/CN2019/083258 patent/WO2020133823A1/zh active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130107528A (ko) * | 2012-03-22 | 2013-10-02 | 삼성디스플레이 주식회사 | 게이트 구동 회로 및 이를 이용한 표시 장치 |
CN103680451A (zh) * | 2013-12-18 | 2014-03-26 | 深圳市华星光电技术有限公司 | 用于液晶显示的goa电路及显示装置 |
CN104050941A (zh) * | 2014-05-27 | 2014-09-17 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路 |
CN105096865A (zh) * | 2015-08-06 | 2015-11-25 | 京东方科技集团股份有限公司 | 移位寄存器的输出控制单元、移位寄存器及其驱动方法以及栅极驱动装置 |
CN106531053A (zh) * | 2017-01-06 | 2017-03-22 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极驱动电路及显示面板 |
CN106601175A (zh) * | 2017-01-09 | 2017-04-26 | 京东方科技集团股份有限公司 | 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 |
CN109036310A (zh) * | 2018-08-03 | 2018-12-18 | 深圳市华星光电半导体显示技术有限公司 | Goa单元及其驱动方法 |
CN109410886A (zh) * | 2018-12-27 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | Goa电路 |
Also Published As
Publication number | Publication date |
---|---|
CN109410886A (zh) | 2019-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2020133823A1 (zh) | Goa电路 | |
US9928797B2 (en) | Shift register unit and driving method thereof, gate driving apparatus and display apparatus | |
JP4912186B2 (ja) | シフトレジスタ回路およびそれを備える画像表示装置 | |
JP5079350B2 (ja) | シフトレジスタ回路 | |
JP5128102B2 (ja) | シフトレジスタ回路およびそれを備える画像表示装置 | |
KR101552408B1 (ko) | 주사 신호선 구동 회로 및 주사 신호선 구동 방법 | |
WO2015089954A1 (zh) | 移位寄存器单元、栅极驱动电路及显示器件 | |
US11263988B2 (en) | Gate driving circuit and display device using the same | |
JP2009049985A (ja) | 電子回路のブートストラップポイント電圧を低下する方法、及びその方法を用いた装置 | |
WO2017107294A1 (zh) | Goa电路及液晶显示装置 | |
WO2020259574A1 (zh) | 阵列基板行驱动电路单元与其驱动电路及液晶显示面板 | |
JP2008287753A (ja) | シフトレジスタ回路およびそれを備える画像表示装置 | |
CN112927644B (zh) | 栅极驱动电路和显示面板 | |
WO2019205962A1 (zh) | 一种移位寄存器单元、栅极驱动电路、驱动方法及显示装置 | |
JP2008140522A (ja) | シフトレジスタ回路およびそれを備える画像表示装置、並びに電圧信号生成回路 | |
WO2020082956A1 (zh) | 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 | |
US10825412B2 (en) | Liquid crystal panel including GOA circuit and driving method thereof | |
CN112102768A (zh) | Goa电路及显示面板 | |
WO2019140943A1 (zh) | 移位寄存器及其驱动方法、栅极驱动电路 | |
WO2021103164A1 (zh) | 一种 goa 电路及液晶显示面板 | |
CN109102782B (zh) | 栅极驱动电路以及使用该栅极驱动电路的液晶显示器 | |
WO2019010736A1 (zh) | Goa电路及液晶显示装置 | |
CN113314067B (zh) | 栅极驱动电路及显示面板 | |
WO2022007059A1 (zh) | Goa电路、显示面板和显示装置 | |
CN109671382A (zh) | 栅极驱动电路以及使用该栅极驱动电路的显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 19906577 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 19906577 Country of ref document: EP Kind code of ref document: A1 |