WO2009084331A1 - 液晶表示装置、液晶表示装置の駆動方法、テレビジョン受像機 - Google Patents
液晶表示装置、液晶表示装置の駆動方法、テレビジョン受像機 Download PDFInfo
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Definitions
- the present invention relates to a liquid crystal display device that performs simultaneous writing to a plurality of pixels included in the same pixel column.
- Patent Document 1 discloses a configuration in which two data signal lines are provided for one pixel column, and scanning signal lines connected to two adjacent pixels are simultaneously selected. Note that the polarity of the signal potential supplied to each data signal line is inverted for each frame. According to this configuration, the signal potential can be simultaneously written into two adjacent pixels, and the charging time of each pixel can be increased. Japanese Patent Publication “Japanese Patent Laid-Open No. 10-253987 (published on September 25, 1998)”
- the present invention has been made in view of the above problems, and an object thereof is to provide a liquid crystal display device capable of increasing the pixel charging time while suppressing flicker.
- the liquid crystal display device of the present invention is a liquid crystal display device having pixels arranged in the row and column directions, assuming that the extending direction of the scanning signal lines is the row direction, and the first and first corresponding to one pixel column. 2 data signal lines are provided, and one pixel included in the pixel column is connected to one scanning signal line and connected to one of the first and second data signal lines. Signal potentials having opposite polarities are supplied to the two data signal lines, and the predetermined pixel in the pixel column is set as the first pixel to be counted, and the odd-numbered one pixel and the even-numbered one pixel counted in the scanning direction And n pairs (n is a natural number) are considered as one group, and each group is connected to different data signal lines in the same group.
- n 2 or more, the odd number Each pixel is connected to the same data signal line, and between two consecutive groups, an odd number pixel included in one group and a data signal line connected to an odd number pixel included in one group Is different from the data signal line to be connected.
- a period in which a potential corresponding to one pixel is output to the data signal line is defined as one horizontal scanning period (1H).
- the polarity of the signal potential supplied to each data signal line is inverted every n horizontal scanning periods, and a group is selected according to the above order, and two pairs forming a pair in the selected group are selected.
- the scanning signal lines connected to each pixel are simultaneously selected, and when n is 2 or more, the simultaneous selection is sequentially performed for each pair, thereby simultaneously selecting two scanning signal lines and Each pixel can be dot-inverted.
- n is 2 or more
- the present liquid crystal display device is suitable for double speed driving in which the number of frames per unit time (for example, the number of frames, the number of subframes, and the number of fields) is doubled (for example, 120 frames / second).
- the pixel charging time is inevitably reduced in the double speed driving, the necessary pixel charging time can be ensured by using this configuration.
- the present liquid crystal display device is also suitable for a digital cinema standard display device having 2160 scanning signal lines and a super high vision standard display device having 4320 scanning signal lines.
- a pair of two pixels may be adjacent to each other.
- the pixel is connected to a data signal line different from the previous pixel, while the 2 ⁇ n ⁇ i + 1th pixel is connected to the same data signal line as the previous pixel. It is also possible to adopt a configuration in which two adjacent scanning signal lines are selected simultaneously in order from the scanning signal line connected to a predetermined pixel.
- the liquid crystal display device of the present invention is a liquid crystal display device having pixels arranged in the row and column directions, assuming that the extending direction of the scanning signal lines is the row direction, and the first and first corresponding to one pixel column. 2 data signal lines are provided, and one pixel included in the pixel column is connected to one scanning signal line and connected to one of the first and second data signal lines.
- Signal potentials having opposite polarities are supplied to the two data signal lines, and the predetermined pixel in the pixel column is set as the first pixel to be counted, and the odd-numbered one pixel and the even-numbered one pixel counted in the scanning direction
- the two pixels in each pair are connected to different data signal lines, and two pairs in which the above order is continuous are included in one pair.
- the data signal line connected to the odd-numbered pixels and the other And data signal lines odd-numbered pixels are connections in the is wherein the at least.
- the polarity of the signal potential supplied to each data signal line is inverted every one vertical scanning period, and the scanning signal line connected to each of two pairs of pixels is selected simultaneously.
- each pixel in the pixel column can be dot-inverted while simultaneously selecting two scanning signal lines.
- the present liquid crystal display device is suitable for double speed driving in which the number of frames per unit time is doubled (for example, 120 frames / second). Although the pixel charging time is inevitably reduced in the double speed driving, the necessary pixel charging time can be ensured by using this configuration. Similarly, the present liquid crystal display device is also suitable for a digital cinema standard display device having 2160 scanning signal lines and a super high vision standard display device having 4320 scanning signal lines.
- a pair of two pixels may be adjacent to each other.
- each pixel located on the scanning direction side with respect to the predetermined pixel is connected to a data signal line different from the preceding pixel, and the scanning signal lines are adjacent to each other in order from the scanning signal line connected to the predetermined pixel. It can also be configured to be selected simultaneously.
- each pixel included in one pixel row is connected to the same scanning signal line, a first data signal line corresponding to one of two adjacent pixel columns, and the two pixel columns.
- the signal potential having the same polarity is supplied to the first data signal line corresponding to the other, and the connection relationship with the first and second data signal lines is reversed between the pixels adjacent in the row direction. It can also be configured. In this way, it is possible to invert each pixel in the pixel row.
- the first and second data signal lines corresponding to the pixel column are arranged on both sides of one pixel column, and the first data signal line corresponding to one of the two adjacent pixel columns and the two The first data signal line corresponding to the other of the pixel columns is adjacent to the pixel column without sandwiching the pixel column, or the second data signal line corresponding to one of the two pixel columns and the other of the two pixel columns The second data signal line corresponding to can be adjacent to each other without sandwiching the pixel column.
- the signal potentials supplied to two adjacent (closest) data signal lines without interposing the pixel column always have the same polarity, and this is caused by the parasitic capacitance between the two data signal lines. Power consumption can be suppressed and the load on the source driver can be reduced.
- the first and second data signal lines corresponding to the pixel column are arranged on both sides of one pixel column, and the first data signal line corresponding to one of the two adjacent pixel columns and the two pixels
- the second data signal line corresponding to the other of the columns is adjacent to the pixel column without sandwiching the pixel column, or the second data signal line corresponding to one of the two pixel columns is connected to the other of the two pixel columns.
- the corresponding first data signal line may be adjacent to each other without sandwiching the pixel column.
- the liquid crystal display device of the present invention is a liquid crystal display device having pixels arranged in the row and column directions, assuming that the extending direction of the scanning signal lines is the row direction, and the first and first corresponding to one pixel column. 2 data signal lines are provided, and one pixel included in the pixel column is connected to one scanning signal line and connected to one of the first and second data signal lines. Signal potentials having the same polarity are supplied to the two data signal lines.
- the predetermined pixel in the pixel column is set as the first pixel to be counted, and the odd numbered two pixels counted in the scanning direction are paired and the even numbered number.
- each pair of two pixels corresponding to The two pixels in the pair are different Is connected to the data signal line, the polarity is n horizontal scanning period of a signal potential supplied to each data signal line (n is a natural number), characterized in that inverted every.
- a group is selected according to the above order, and scanning signal lines connected to each of two pairs of pixels in the selected group are simultaneously selected.
- the two scanning signal lines are simultaneously selected, and in this way, each pixel of the pixel row can be dot-reversed.
- the present liquid crystal display device is suitable for double speed driving in which the number of frames per unit time is doubled (for example, 120 frames / second). Although the pixel charging time is inevitably reduced in the double speed driving, the necessary pixel charging time can be ensured by using this configuration. Similarly, the present liquid crystal display device is also suitable for a digital cinema standard display device having 2160 scanning signal lines and a super high vision standard display device having 4320 scanning signal lines.
- the polarity of the signal potential supplied to the data signal line may be different. In this way, it is possible to invert each pixel in the pixel row.
- the two pixels in each pair may correspond to two consecutive odd-numbered pixels or two consecutive even-numbered pixels.
- the present liquid crystal display device includes a plurality of storage capacitor lines (for example, storage capacitor lines to which a storage capacitor line signal is supplied) that can be controlled in potential.
- the one pixel includes a first transistor, a second transistor, and a first transistor.
- the second pixel electrode, and the first and second pixel electrodes are connected to the same data signal line through the first and second transistors, respectively, and the first and second transistors Is connected to the one scanning signal line, and the first and second pixel electrodes form different storage capacitor lines and storage capacitors, respectively, and form the storage capacitors with the first and second pixel electrodes.
- each of the two storage capacitor lines (for example, the potential of the storage capacitor line signal supplied to each of the two storage capacitor lines) is synchronized with the end of scanning of the scanning signal line connected to the first and second transistors.
- the Te or after may be configured to level shift in opposite directions. In this way, a bright subpixel and a dark subpixel can be formed in one pixel to display halftone, and viewing angle characteristics during halftone display can be enhanced.
- one storage capacitor wiring is provided corresponding to two pixels adjacent in the column direction, and the first or second pixel electrode provided on one of the two pixels and the two pixel regions are provided. The first or second pixel electrode provided on the other side may form the storage capacitor wiring and the storage capacitor.
- each pixel can be dot-inverted, even when one storage capacitor line is shared by two pixels as in the present configuration, a bright subpixel and a dark subpixel are provided. It can be arranged in a checkered pattern so that bright subpixels or dark subpixels are not adjacent to each other in one pixel column. This makes it possible to improve the viewing angle characteristics while suppressing the feeling of roughness (jaggy).
- the signal potential may be supplied to the first and second data signal lines after a preliminary potential (for example, a refresh potential) is supplied in each horizontal scanning period. it can.
- a preliminary potential for example, a refresh potential
- the potential level supplied to the same data signal line before one horizontal scanning period is increased. It is possible to suppress the variation in the reached potential (charge rate) in the current horizontal scanning period due to the difference.
- a halfway selection period is provided between the scanning period of the scanning signal lines and the scanning period, and the pixels connected to the scanning signal lines are provided during the halfway selection period.
- the preliminary potential can be written.
- specific display for example, black display
- specific display can be performed in each pixel in part of one frame period, tailing or the like during moving image display can be reduced, and moving image display quality can be improved.
- the preliminary potential may be a constant value.
- the constant value may be a median value of the signal potential range.
- the preliminary potential can be set to the black display potential.
- the preliminary potential may be a value determined based on the signal potential supplied to the same data signal line before one horizontal scanning period and the signal potential in the current horizontal scanning period. By so doing, it is possible to more effectively suppress variations in the potential reached (charging rate) in the current horizontal scanning period due to the difference in potential level supplied to the same data signal line before one horizontal scanning period.
- one of the first and second data signal lines may be arranged on one side of the pixel column, and the other may be arranged so as to overlap the pixel column. it can.
- the distance between the data signal lines can be kept wider than the configuration in which the data signal lines corresponding to the pixel columns are arranged on both sides of the pixel column. Thereby, the short circuit rate between the data signal lines can be reduced, and the manufacturing yield can be increased.
- the scanning signal lines that are simultaneously selected may be connected within the liquid crystal panel, or may be connected to the same output terminal of the gate driver that drives the scanning signal lines.
- a plurality of regions are provided in the display unit, and the data signal lines, the scanning signal lines, and the pixels are provided in each region, and these can be individually driven for each region.
- this configuration is applied to a liquid crystal display device (for example, a 120 frame / second liquid crystal display device) in which the number of frames (for example, the number of frames, the number of subframes, and the number of fields) displayed per second is greater than 60. Is preferred.
- the liquid crystal display device includes a plurality of storage capacitor lines capable of controlling a potential, and each pixel includes first and second transistors and first and second pixel electrodes, and the first and second pixels
- the electrodes are connected to the same data signal line through first and second transistors, respectively, the first and second transistors are connected to the same scanning signal line, and the first and second pixel electrodes are held differently.
- a capacitor wiring and a storage capacitor are formed, and one storage capacitor wiring is provided corresponding to two adjacent pixels in the pixel column, and one of the two pixels is provided with one of the pixel electrodes and the other One of the provided pixel electrodes forms one storage capacitor line and a storage capacitor corresponding to the two pixels, and a storage capacitor line that forms a storage capacitor with each pixel electrode of the first pixel Is first and second
- the second storage capacitor line forms a storage capacitor with any one of the pixel electrodes of the second pixel, and at or after the end of writing of the first and second pixels,
- the potentials of the first and second storage capacitor lines are synchronously level-shifted in the opposite direction, and the first storage capacitor line is counted in the scanning direction starting from counting, and between the two consecutive odd-numbered storage capacitor lines, After one horizontal scanning period from the level shift of the potential of the previous storage capacitor line, the potential of the subsequent storage capacitor line is level-shifted in the same direction as that between two consecutive even-numbered storage capacitor lines.
- the potential of the subsequent storage capacitor line may be shifted in the same direction after one horizontal scanning period from the level shift of the potential of the previous storage capacitor line.
- the potentials of the storage capacitor wiring signals supplied to the first and second storage capacitor wirings are level-shifted in the opposite direction synchronously, and consecutive odd numbers
- the phase of the storage capacitor line signal supplied to each of the first storage capacitor lines is delayed by one horizontal scanning period in order from the first, and the phase of the storage capacitor line signal supplied to each successive even-numbered storage capacitor line is In order from the second, it is delayed by one horizontal scanning period.
- liquid crystal display device having a multi-pixel structure in which the polarities of signal potentials supplied to the first and second data signal lines are different can be easily configured.
- the liquid crystal display device includes a plurality of storage capacitor lines capable of controlling a potential, and each pixel includes first and second transistors and first and second pixel electrodes, and the first and second pixels
- the electrodes are connected to the same data signal line through first and second transistors, respectively, the first and second transistors are connected to the same scanning signal line, and the first and second pixel electrodes are held differently.
- a capacitor wiring and a storage capacitor are formed, and one storage capacitor wiring is provided corresponding to two adjacent pixels in the pixel column, and one of the two pixels is provided with one of the pixel electrodes and the other One of the provided pixel electrodes forms one storage capacitor line and a storage capacitor corresponding to the two pixels, and a storage capacitor line that forms a storage capacitor with each pixel electrode of the first pixel Is first and second
- the second storage capacitor line forms a storage capacitor with any pixel electrode of the second pixel, and forms a storage capacitor with each pixel electrode of the first pixel.
- the wiring is the first and second storage capacitor wiring, and the second storage capacitor wiring forms a storage capacitor with any one of the pixel electrodes of the second pixel, and writing of the first and second pixels is completed.
- the potentials of the first and second storage capacitor lines are synchronously level-shifted in the opposite direction, and the first storage capacitor line is counted in the scanning direction.
- the potentials of the two storage capacitor lines are synchronously level shifted in the same direction, and between two adjacent bundles, the bundle located upstream in the scanning direction Potential of each storage capacitor wiring
- Two horizontal scans in which the potentials of the two storage capacitor lines are synchronously level shifted in the same direction, and the potentials of the storage capacitor wires in the bundle located upstream in the scanning direction are level shifted between two adjacent bundles.
- the potential of each storage capacitor wiring of the bundle located downstream in the scanning direction is level-shifted.
- the potentials of the storage capacitor wiring signals supplied to the first and second storage capacitor wirings are level-shifted in the opposite direction synchronously, and consecutive odd numbers
- the phase of the storage capacitor line signal supplied to each of the first storage capacitor lines is delayed by two horizontal scanning periods in order from the first, and the phase of the storage capacitor line signal supplied to each successive even-numbered storage capacitor line is The second horizontal scanning period is delayed in order from the second.
- a liquid crystal display device having a multi-pixel structure with the same polarity of the signal potential supplied to the first and second data signal lines can be easily configured.
- the potential of the subsequent storage capacitor line is level-shifted in the same direction in synchronization with the level shift of the potential of the storage capacitor wire of the previous number. That is, the two storage capacitor lines in each bundle may be controlled with the same potential, and a signal (Cs signal) supplied to these storage capacitor lines can be shared. Thereby, the control circuit of the storage capacitor wiring can be simplified.
- the driving method of the present liquid crystal display device includes pixels arranged in the row and column directions when the extending direction of the scanning signal lines is the row direction, and the first and second data signal lines correspond to one pixel column.
- One pixel included in the pixel column is connected to one scanning signal line and one of the first and second data signal lines, and starts counting predetermined pixels in the pixel column.
- the first pixel is a pair of odd-numbered pixels and even-numbered pixels counted in the scanning direction, and n (n is a natural number) pairs are grouped together, and each group is ordered.
- two pixels forming a pair are connected to different data signal lines, and all odd-numbered pixels are connected to one data signal line, and two consecutive pixels are in sequence.
- First and second data signal lines for a liquid crystal display device in which a data signal line connected to an odd-numbered pixel is different from a data signal line connected to an odd-numbered pixel included in the other group Are supplied with signal potentials having opposite polarities to each other, the polarity of the signal potential supplied to each data signal line is inverted every n horizontal scanning periods, and a group is selected according to the above order.
- the scanning signal lines connected to each of the two pixels forming the above are simultaneously selected, and when n is 2 or more, the simultaneous selection is sequentially performed for each pair.
- the driving method of the present liquid crystal display device includes pixels arranged in the row and column directions when the extending direction of the scanning signal lines is the row direction, and the first and second data signal lines correspond to one pixel column.
- One pixel included in the pixel column is connected to one scanning signal line and one of the first and second data signal lines, and starts counting predetermined pixels in the pixel column.
- the first pixel is considered as a pair of an odd numbered pixel and an even numbered pixel counted in the scanning direction, and each pair is considered as an order, two pairs of pixels have different data signal lines.
- a data signal line connected to an odd-numbered pixel included in one pair and a data signal connected to an odd-numbered pixel included in the other pair For liquid crystal display devices with the same line Two pixels forming a pair by supplying signal potentials having opposite polarities to the first and second data signal lines, inverting the polarity of the signal potential supplied to each data signal line every vertical scanning period The simultaneous selection of the scanning signal lines connected to each is performed for each pair according to the above order.
- the driving method of the present liquid crystal display device includes pixels arranged in the row and column directions when the extending direction of the scanning signal lines is the row direction, and the first and second data signal lines correspond to one pixel column.
- One pixel included in the pixel column is connected to one scanning signal line and one of the first and second data signal lines, and starts counting predetermined pixels in the pixel column.
- the first and second data signal lines are connected to each other.
- the polarity of the signal potential supplied to each data signal line is inverted every n horizontal scanning periods (n is a natural number), and a group is selected according to the above order, and within the selected group,
- the scanning signal lines connected to each of two pixels forming a pair are simultaneously selected.
- n is 2 or more, the simultaneous selection is sequentially performed for each pair.
- a television receiver includes the above-described liquid crystal display device and a tuner unit that receives a television broadcast.
- each pixel of the pixel column is inverted in dots to suppress flicker, and by simultaneously selecting two scanning signal lines, one horizontal scanning period is extended and pixel charging is performed. You can increase your time.
- FIG. (A) is a schematic diagram which shows the display part of the liquid crystal display device concerning Embodiment 1
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- 2 is a timing chart showing a method for driving the display section shown in FIG. (A) is a schematic diagram which shows the display part of the other liquid crystal display device concerning Embodiment 1
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- FIG.5 It is a timing chart which shows the drive method of the display part shown to Fig.5 (a).
- A) is a schematic diagram which shows the display part of the further another liquid crystal display device concerning Embodiment 1
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- 6 is a timing chart showing another driving method of the display section shown in FIG. 10 is a timing chart showing still another driving method of the display section shown in FIG. 6 is a timing chart showing still another driving method of the display section shown in FIG.
- FIG. (A) is a schematic diagram which shows the display part of the liquid crystal display device concerning Embodiment 2
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- 14 is a timing chart showing a method for driving the display section shown in FIG. (A) is a schematic diagram which shows the display part of the other liquid crystal display device concerning Embodiment 2
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- 16 is a timing chart illustrating a method for driving the display section illustrated in FIG. (A) is a schematic diagram which shows the display part of the further another liquid crystal display device concerning Embodiment 2
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- FIG.17 It is a timing chart which shows the drive method of the display part shown to Fig.17 (a).
- A) is a schematic diagram which shows the display part of the further another liquid crystal display device concerning Embodiment 2
- (b)-(d) is a schematic diagram which shows the drive method of this display part.
- 14 is a timing chart showing another driving method of the display section shown in FIG. 18 is a timing chart showing another driving method of the display section shown in FIG. 14 is a timing chart showing still another driving method of the display section shown in FIG. 18 is a timing chart showing still another driving method of the display section shown in FIG.
- (A) is a schematic diagram which shows the display part of the liquid crystal display device concerning Embodiment 3
- (b)-(d) is a schematic diagram which shows the drive method of this display part. It is a timing chart which shows the drive method of the display part shown to Fig.25 (a).
- (A) is a schematic diagram which shows the display part of the other liquid crystal display device concerning Embodiment 3
- (b)-(d) is a schematic diagram which shows the drive method of this display part. It is a timing chart which shows the drive method of the display part shown to Fig.27 (a).
- FIG. 26 is a timing chart showing another driving method of the display section shown in FIG. It is a timing chart which shows the other drive method of the display part shown to Fig.27 (a).
- FIG. 26 is a timing chart showing still another driving method of the display section shown in FIG.
- FIG. 28 is a timing chart showing still another driving method of the display section shown in FIG.
- (A) is a schematic diagram which shows the display part of the liquid crystal display device concerning Embodiment 4
- (b)-(e) is a schematic diagram which shows the drive method of this display part. It is a timing chart which shows the drive method of the display part shown to Fig.33 (a).
- (A) is a schematic diagram which shows the display part of the other liquid crystal display device concerning Embodiment 4
- (b) * (c) is a schematic diagram which shows the drive method of this display part.
- 36 is a timing chart showing how to drive the display section shown in (a) of FIG.
- FIG. 10 is a waveform diagram showing variations in potentials reached in a current horizontal scanning period depending on a potential level supplied before one horizontal scanning period when the polarity of a signal potential supplied to a data signal line is inverted every vertical scanning period.
- FIG. 6 is a waveform chart showing variations in potential reached during the current horizontal scanning period.
- the refresh potential is supplied to the data signal line at the beginning of one horizontal scanning period while inverting the polarity of the signal potential supplied to the data signal line every horizontal scanning period
- the potential level supplied before one horizontal scanning period is a waveform chart showing variations in potential reached during the current horizontal scanning period.
- FIG. 6 is a waveform diagram showing variations in potentials reached in a current horizontal scanning period depending on a potential level supplied before one horizontal scanning period when the polarity of a signal potential supplied to a data signal line is inverted every horizontal scanning period. It is a block diagram which shows the structure of this liquid crystal display device (non-pixel division
- (A) is a block diagram showing a configuration of a gate driver of the present liquid crystal display device
- (b) is a block diagram showing a configuration of a gate driver when refresh driving is performed in the present liquid crystal display device. It is a block diagram which shows the structure of the data rearrangement circuit of this liquid crystal display device.
- (A) and (b) are block diagrams showing a source driver when refresh driving is performed in the present liquid crystal display device. It is a block diagram which shows the other source driver in the case of performing refresh drive in this liquid crystal display device. It is a schematic diagram which shows the other example of arrangement
- FIG. 26 is a block diagram illustrating functions of the present television receiver. It is a disassembled perspective view which shows the structure of this television receiver.
- refresh period 100% of the time constant of the data signal line
- wave form diagram which shows the dispersion
- FIGS. 1 to 53 An example of an embodiment according to the present invention will be described with reference to FIGS. 1 to 53 as follows.
- the liquid crystal display device for example, normally black mode
- pixels are arranged in the row and column directions.
- the i-th pixel row in the figure is denoted as PGi, j-th column.
- the pixel column is denoted as PSj
- the pixel in the i-th row and the j-th column is denoted as P (i, j).
- the extending direction of the scanning signal lines is hereinafter referred to as the row direction.
- the scanning signal line may extend in the horizontal direction or in the vertical direction in the use (viewing) state of the liquid crystal display device.
- One horizontal scanning period (1H) is a period during which a potential (signal potential or signal potential and refresh potential) corresponding to one pixel is output to the data signal line.
- FIG. 1A is a schematic diagram showing a configuration example of a display unit of the present liquid crystal display device
- FIGS. 1B to 1D are schematic diagrams showing a driving method of the display unit. These are timing charts showing the driving method.
- the display unit 10a is provided with first and second data signal lines (for example, S1x / S1y) corresponding to one pixel column (for example, PS1), and the pixels One pixel (for example, P (1,1)) included in the column is connected to one scanning signal line (for example, G1) and the first and second data signal lines (for example, S1x / S1y) Connected to either.
- first and second data signal lines for example, S1x / S1y
- the two pixels in each pair are different.
- the odd numbered pixels included in the other pair are connected to the data signal line connected to the odd numbered pixels included in the one pair.
- the data signal line is the same. That is, in one pixel column, each pixel in the second and subsequent rows is connected to a data signal line different from that of the previous pixel.
- the pixel electrode PE is connected to one data signal line through a transistor (TFT), and the gate terminal of the transistor is connected to one scanning signal line.
- signal potentials having opposite polarities are supplied to the first and second data signal lines, and the polarity of the signal potential supplied to each data signal line is inverted every one vertical scanning period (one frame). Furthermore, each pixel included in one pixel row is connected to the same scanning signal line, and a first data signal line corresponding to one of two adjacent pixel columns and a second data line corresponding to the other of the two pixel columns. A signal potential having the same polarity is supplied to one data signal line, and the connection relationship with the first and second data signal lines is reversed between pixels adjacent in the row direction.
- the first and second data signal lines corresponding to the pixel column are arranged on both sides of the pixel column, and the first data signal line and the two pixels corresponding to one of the two adjacent pixel columns.
- the first data signal line corresponding to the other of the columns is adjacent without interposing the pixel column, or the second data signal line corresponding to one of the two pixel columns and the other of the two pixel columns
- the second data signal line to be adjacent to each other without sandwiching the pixel column.
- the process of simultaneously selecting the scanning signal lines connected to each of the two pixels forming a pair is sequentially performed according to the scanning direction (the above order). That is, two adjacent scanning signal lines are simultaneously selected in order from the scanning signal line connected to the pixels in the first row.
- the first and second data signal lines S1x and S1y are arranged on both sides of the pixel column PS1, and the first pixel P (1, 1) and the second pixel P (2, 1) and the pixel P (1,1) are connected to the scanning signal line G1 and the first data signal line S1x, and the pixel P (2,1) is connected to the scanning signal line G2. And connected to the second data signal line S1y.
- the third pixel P (3,1) and the fourth pixel P (4,1) are paired, and the pixel P (3,1) Connected to the scanning signal line G3 and connected to the first data signal line S1x, the pixel P (4, 1) is connected to the scanning signal line G4 and connected to the second data signal line S1y.
- the pixel P (5,1) in the sixth row and the pixel P (6,1) in the sixth row are paired, and the image P (5, 1) is connected to the scanning signal line G5 and connected to the first data signal line S1x, and the pixel P (6, 1) is connected to the scanning signal line G6 and to the second data signal line S1y. It is connected.
- the first and second data signal lines S2x and S2y are arranged on both sides of the pixel column PS2, and the first pixel P (1,2) and the second pixel P (2 , 2) are paired, the pixel P (1,2) is connected to the scanning signal line G1 and is connected to the second data signal line S2y, and the pixel P (2,2) is connected to the scanning signal line G2. And connected to the first data signal line S2x.
- the third pixel P (3,2) and the fourth pixel P (4,2) are paired, and the pixel P (3,2) Is connected to the scanning signal line G3 and connected to the second data signal line S2y, and the pixel P (4, 2) is connected to the scanning signal line G4 and connected to the first data signal line S2x.
- the fifth pixel P (5,2) and the sixth pixel P (6,2) are paired, and the image P (5, 2) is connected to the scanning signal line G5 and connected to the second data signal line S2y, and the pixel P (6, 2) is connected to the scanning signal line G6 and to the first data signal line S2x. It is connected.
- a positive polarity potential is always supplied to the first data signal line S1x in a predetermined frame (the state shown in FIGS. 1B to 1D).
- a negative polarity potential is supplied to the second data signal line S1y, and in the next frame, a negative polarity potential is supplied to the first data signal line S1x, while a positive polarity potential is supplied to the second data signal line S1y. Is done.
- a positive polarity potential is always supplied to the first data signal line S2x in the predetermined frame (the state shown in FIGS. 1B to 1D).
- a negative polarity potential is supplied to the second data signal line S2y.
- a negative polarity potential is supplied to the first data signal line S2x, while a positive polarity is supplied to the second data signal line S2y.
- a potential is supplied.
- the second data signal line S1y corresponding to the pixel column PS1 and the second data signal line S2y corresponding to the pixel column PS2 are adjacent to each other without sandwiching the pixel column.
- the scanning signal line G1 connected to the pixels P (1,1) ⁇ P (1,2) and the pixels P (2,1) ⁇ P The scanning signal line G2 connected to (2, 2) is first selected simultaneously, and then the scanning signal line G3 connected to the pixels P (3, 1) and P (3, 2) and the pixel P (4, 1).
- the scanning signal line G4 connected to P (4,2) is simultaneously selected, and then the scanning signal line G5 connected to the pixel P (5,1) P (5,2) and the pixel P (6,1) ).
- the scanning signal line G6 connected to P (6, 2) is simultaneously selected.
- the second data signal is synchronized with the writing of the positive polarity potential from the first data signal line S1x to the pixel electrode of the pixel P (1,1) in the first horizontal scanning period.
- a negative polarity potential is written from the line S1y to the pixel electrode of the pixel P (2,1), and a negative polarity potential is written from the second data signal line S2y to the pixel electrode of the pixel P (1,2).
- a positive polarity potential is written from the first data signal line S2x to the pixel electrode of the pixel P (2, 2) (see FIG. 1B).
- the second data signal line S1y to the pixel P are synchronized with the writing of the positive polarity potential from the first data signal line S1x to the pixel electrode of the pixel P (3, 1).
- the negative polarity potential is written to the pixel electrode of (4, 1) and the negative polarity potential is written to the pixel electrode of the pixel P (3, 2) from the second data signal line S2y.
- a positive polarity potential is written from one data signal line S2x to the pixel electrode of the pixel P (4, 2) (see FIG. 1C).
- each pixel can be dot-inverted while extending one horizontal scanning period by simultaneously selecting two scanning signal lines. That is, it is possible to increase the pixel charging time while suppressing flicker.
- the signal potential supplied to two adjacent (adjacent) data signal lines (for example, S1y and S2y) without interposing the pixel column always has the same polarity. Power consumption due to parasitic capacitance can be suppressed, and the load on the source driver can be reduced.
- the present liquid crystal display device is suitable for double speed driving in which the number of frames per unit time is doubled (for example, 120 frames / second). Although the pixel charging time is inevitably reduced in the double speed driving, the necessary pixel charging time can be ensured by using this configuration.
- the present liquid crystal display device is suitable for a digital cinema standard liquid crystal display device having 2160 scanning signal lines and a super high vision standard liquid crystal display device having 4320 scanning signal lines.
- the display unit of the present liquid crystal display device can also be configured as shown in FIG.
- the display unit 10b in FIG. 3A differs from the display unit 10a in FIG. 1A in that it corresponds to the second data signal line corresponding to one of the two adjacent pixel columns and the other of the two pixel columns.
- a first data signal line corresponding to one of the two pixel columns and a second data signal line corresponding to the other of the two pixel columns. are adjacent to each other without interposing a pixel column.
- first and second data signal lines S1x and S1y are arranged on both sides of the pixel column PS1, and the first and second data signal lines S2x and S2y are arranged on both sides of the pixel column PS2, and correspond to the pixel column PS1.
- the second data signal line S1y is adjacent to the first data signal line S2x corresponding to the pixel column PS2.
- a driving method of the display portion 10b is shown in FIG. 4, and a writing state to each pixel is shown in FIGS. 3 (b) to 3 (d). As shown in these drawings, each pixel can be dot-inverted while extending one horizontal scanning period also by the display unit 10b.
- the display unit 10a in FIG. 1A may be a pixel division method (multi-pixel structure) as shown in FIG. 5A, for example.
- one scanning signal line corresponding to a pixel is provided so as to cross one pixel, and a plurality of storage capacitor lines are provided in parallel with the scanning signal line.
- Each pixel includes a first transistor and a first pixel electrode PE1 on one side of the scanning signal line, and a second transistor and a second pixel electrode PE2 on the other side of the scanning signal line.
- the second pixel electrodes PE1 and PE2 are connected to the same data signal line through first and second transistors, respectively, and the first and second transistors are connected to the same scanning signal line, and the first and second transistors
- the two pixel electrodes PE1 and PE2 form different storage capacitor lines and storage capacitors, respectively.
- one storage capacitor wiring is provided corresponding to two pixels (two pixel columns) adjacent in the column direction, and the first or second pixel electrode provided on one of the two pixels and the above-mentioned
- the first or second pixel electrode provided in the other of the two pixel regions forms the storage capacitor line and the storage capacitor.
- the connection relationship between each pixel (the first and second pixel electrodes PE1 and PE2 and the first and second transistors included therein), the data signal line, and the scanning signal line is shown in FIG. It is the same as 10a.
- a scanning signal line G1 is provided so as to cross the pixel P (1,1), and a plurality of storage capacitor wirings (Cs1 to Cs7) are provided in parallel with the scanning signal lines (G1 to G6).
- the first transistor and the first pixel electrode PE1 are provided on one side of the scanning signal line G1, and the second transistor and the second pixel electrode PE2 are provided on the other side.
- the first pixel electrode PE1 is connected to the first data signal line S1x via the first transistor
- the second pixel electrode PE2 is connected to the first data signal line S1x via the second transistor.
- the transistor is connected to the scanning signal line G1, the first pixel electrode PE1 forms a storage capacitor line Cs1 and a storage capacitor, and the second pixel electrode PE2 forms a storage capacitor line Cs2 and a storage capacitor.
- the first pixel electrode PE1 of the pixel P (2,1) is connected to the second data signal line S1y via the first transistor, and the second pixel electrode PE2 is connected to the second data signal line via the second transistor.
- the first and second transistors are connected to the scanning signal line G2, and the first pixel electrode PE1 of the pixel P (2,1) forms a storage capacitor line Cs2 and a storage capacitor, and is connected to the second pixel.
- the electrode PE2 forms a storage capacitor with the storage capacitor line Cs3.
- the first pixel electrode PE1 of the pixel P (1,2) is connected to the second data signal line S2y via the first transistor, and the second pixel electrode PE2 is connected to the second data signal line via the second transistor.
- the first and second transistors are connected to the scanning signal line G1, and the first pixel electrode PE1 of the pixel P (1,2) forms a storage capacitor line Cs2 and a storage capacitor, and is connected to the second pixel.
- the electrode PE2 forms a storage capacitor with the storage capacitor line Cs1.
- the first pixel electrode PE1 of the pixel P (2, 2) is connected to the first data signal line S2x via the first transistor, and the second pixel electrode PE2 is connected to the first data signal line via the second transistor.
- the first and second transistors are connected to the scanning signal line G2, and the first pixel electrode PE1 of the pixel P (2, 2) forms the storage capacitor line Cs3 and the storage capacitor, and is connected to the second pixel.
- the electrode PE2 forms a storage capacitor with the storage capacitor line Cs2.
- the storage capacitor wiring Cs2 is composed of two pixels (P (1,1) and P (2,1) or P (1,2) and P (2,2)) adjacent in the column direction. Share.
- FIG. 6 is a timing chart showing a method for driving each data signal line, each scanning signal line, and each storage capacitor line of the display unit 10c.
- the driving method of each data signal line and each scanning signal line is the same as that in FIG. 2, and in synchronization with turning off the scanning signal line connected to one pixel or after turning off,
- the potentials of the first and second pixel electrodes PE1 and PE2 of the pixel and the two storage capacitor lines forming the storage capacitor are level-shifted in the opposite directions (the push-up and push-down directions).
- the level of the storage capacitor line Cs1 is shifted in the direction of pushing up and the potential of the holding capacitor line Cs2 is pushed down to shift the level of the scanning signal line G3.
- the level is shifted in the direction of pushing up the potential of the storage capacitor line Cs3, and the level is shifted in the direction of pushing down the potential of the storage capacitor line Cs4.
- each storage capacitor wiring of the display unit 10c is formed as follows, and the potential is controlled. That is, the storage capacitor lines that form the storage capacitors with the pixel electrodes PE1 and PE2 of the pixels in the first row (for example, P (1,1)) are the first and second storage capacitor lines Cs1 and Cs2.
- the second storage capacitor line Cs2 also forms a storage capacitor with the pixel electrode PE2 of the pixel in the second row (for example, P (2,1)), or when the simultaneous writing of the pixels in the first row and the second row ends or After that, the potentials of the first and second storage capacitor lines Cs1 and Cs2 are level-shifted in the opposite directions synchronously, and between the two consecutive storage capacitor lines (for example, Cs1 and Cs3), After one horizontal scanning period from the level shift of the potential of the storage capacitor line (for example, Cs1), the potential of the subsequent storage capacitor line (for example, Cs3) is level-shifted in the same direction as this, Between the storage capacitor lines corresponding to the even number (for example, Cs2 and Cs4), the storage capacitor line that becomes the latter (for example, Cs2 and Cs4) after the one horizontal scanning period after the level shift of the potential of the former hold capacitor line (for example, Cs2). , Cs4) is level-shifted in the same direction. Note that the period of potential level shift of each storage capacitor
- the scanning signal lines G1 and G2 are simultaneously turned on (selected) in the first horizontal scanning period, and the pixel P (1,1) is switched from the first data signal line S1x.
- the first and second pixel electrodes PE1 and PE2 of the pixel P (2,1) from the second data signal line S1y are synchronized with the writing of the same positive potential to the first and second pixel electrodes PE1 and PE2.
- the same negative potential is written to the first and second pixel electrodes PE1 and PE2 of the pixel P (1,2) from the second data signal line S2y.
- the same positive polarity potential is written from the first data signal line S2x to the first and second pixel electrodes PE1 and PE2 of the pixel P (2, 2).
- the storage capacitor line Cs1 is pushed up and the storage capacitor line Cs2 is pushed down.
- the portion including the first pixel electrode PE1 of the pixel P (1,1) is the bright subpixel
- the portion including the second pixel electrode PE2 of the pixel P (1,1) is the dark subpixel
- the pixel P (2, 1) a portion including the first pixel electrode PE1 is a bright subpixel
- a portion including the first pixel electrode PE1 of the pixel P (1,2) is a bright subpixel
- the part including the second pixel electrode PE2 of the pixel P (2, 2) is a dark subpixel.
- the next horizontal scanning period is as shown in FIG. 5C, and the next horizontal scanning period is as shown in FIG. 5D.
- the sub-pixels are arranged in the order of light, dark, bright, dark, bright,..., While in the pixel column PS2, the sub-pixels are dark, bright, dark, bright, dark,.
- the bright subpixels and the dark subpixels are arranged in a checkered pattern.
- the pixel charging time is increased while the flicker is suppressed, and the viewing angle characteristic is also improved (that is, a bright sub-pixel and a dark sub-pixel are formed in one pixel to achieve a halftone. Display, and suppression of whitening or the like during halftone display).
- the signal potential supplied to two adjacent (adjacent) data signal lines for example, S1y and S2y
- the signal potential supplied to two adjacent (adjacent) data signal lines for example, S1y and S2y
- the bright subpixels and the dark subpixels can be arranged in a checkered pattern so that the bright subpixels or the dark subpixels are not adjacent to each other. This makes it possible to improve the viewing angle characteristics while suppressing the feeling of roughness (jaggy).
- the present liquid crystal display device is suitable for a liquid crystal display device that performs double speed driving, and a liquid crystal display device that conforms to the digital cinema standard or the super high vision standard.
- the display section of the present liquid crystal display device can also be configured as shown in FIG.
- the display unit 10d in FIG. 7A differs from the display unit 10c in FIG. 5A in that it corresponds to the second data signal line corresponding to one of the two adjacent pixel columns and the other of the two pixel columns.
- a first data signal line corresponding to one of the two pixel columns and a second data signal line corresponding to the other of the two pixel columns. are adjacent to each other without interposing a pixel column.
- the first and second data signal lines S1x and S1y are arranged on both sides of the pixel column PS1, and the first and second data signal lines S2x and S2y are arranged on both sides of the pixel column PS2, and correspond to the pixel column PS1.
- the second data signal line S1y is adjacent to the first data signal line S2x corresponding to the pixel column PS2.
- a driving method of the display unit 10d is shown in FIG. 8, and a writing state to each pixel is shown in FIGS. 7B to 7D.
- the display unit 10d can also invert each pixel with a dot while extending one horizontal scanning period and improve the viewing angle characteristics.
- the bright subpixels and the dark subpixels can be arranged in a checkered pattern so that the bright subpixels or the dark subpixels are not adjacent to each other. This makes it possible to improve the viewing angle characteristics while suppressing the feeling of roughness (jaggy).
- a refresh period R is provided at the beginning of each horizontal scanning period, and a refresh potential (preliminary potential, for example, Vcom) is supplied to each data signal line during the refresh period R.
- the refresh period R is synchronized with, for example, a period when the latch strobe signal LS is “High” (described later).
- the inventors of the present application for example, at a double speed drive of 120 frames / second, the gray level in the current horizontal scanning period is a halftone (for example, 101 gray levels in a 256 gray scale display of 0 to 255 gray levels,
- the gradation potential V101 2.1 V (potential when the common potential is set to potential 0))
- the potential level supplied before one horizontal scanning period is a value corresponding to the white gradation; It was found that the pixel potential reached level (hereinafter, reached potential) differs depending on the value corresponding to the black gradation.
- a refresh period R is provided at the beginning of each horizontal scanning period, a refresh potential (for example, Vcom) is supplied to each data signal line in the refresh period R, and each scanning signal line is set to 2/3 from the previous scanning.
- the selection is performed a plurality of times (for example, three times) so as to be synchronized with the refresh period R, and the refresh potential (for example, Vcom) is applied to the pixels connected to each scanning signal line in this midway selection period.
- the halfway selection period is shorter than one horizontal scanning period, black is written to each pixel (black insertion is performed by providing the halfway selection period a plurality of times at intervals of one horizontal scanning period and performing impulse driving. )be able to.
- each pixel displays the input video data during the 2/3 frame period of one frame period, while performing the black display during the remaining 1/3 frame period. Etc. can be reduced, and the moving image display quality can be improved.
- FIG. 13A is a schematic diagram showing a configuration example of the display unit of the present liquid crystal display device
- FIGS. 13B to 13D are schematic diagrams showing a driving method of the display unit. These are timing charts showing the driving method.
- the display unit 10e is provided with first and second data signal lines (for example, S1x / S1y) corresponding to one pixel column (for example, PS1), and the pixels One pixel (for example, P (1,1)) included in the column is connected to one scanning signal line (for example, G1) and the first and second data signal lines (for example, S1x / S1y) Connected to either.
- first and second data signal lines for example, S1x / S1y
- the two pixels in each pair are different.
- the odd numbered pixels included in the other pair are connected to the data signal line connected to the odd numbered pixels included in the one pair.
- the data signal line is different. That is, the pixel in the first row is the first pixel to be counted, and the pixels other than the 2 ⁇ 1 ⁇ i + 1th pixel (i is a natural number) counted in the scanning direction are connected to a data signal line different from the previous pixel.
- the 2 ⁇ 1 ⁇ i + 1-th pixel is connected to the same data signal line as the previous pixel.
- the pixel electrode PE is connected to one data signal line through a transistor (TFT), and the gate terminal of the transistor is connected to one scanning signal line.
- signal potentials having opposite polarities are supplied to the first and second data signal lines, and the polarity of the signal potential supplied to each data signal line is inverted every horizontal scanning period (1H).
- each pixel included in one pixel row is connected to the same scanning signal line, and a first data signal line corresponding to one of two adjacent pixel columns and a second data line corresponding to the other of the two pixel columns.
- a signal potential having the same polarity is supplied to one data signal line, and the connection relationship with the first and second data signal lines is reversed between pixels adjacent in the row direction.
- the first and second data signal lines corresponding to the pixel column are arranged on both sides of the pixel column, and the first data signal line and the two pixels corresponding to one of the two adjacent pixel columns.
- the first data signal line corresponding to the other of the columns is adjacent without interposing the pixel column, or the second data signal line corresponding to one of the two pixel columns and the other of the two pixel columns The second data signal line to be adjacent to each other without sandwiching the pixel column.
- the simultaneous selection of the scanning signal lines connected to each of the two pixels forming a pair is sequentially performed according to the scanning direction (the above order). That is, two adjacent scanning signal lines are simultaneously selected in order from the scanning signal line connected to the pixels in the first row.
- the first and second data signal lines S1x and S1y are arranged on both sides of the pixel column PS1, and the first pixel P (1, 1) and the second pixel P (2, 1) and the pixel P (1,1) are connected to the scanning signal line G1 and the first data signal line S1x, and the pixel P (2,1) is connected to the scanning signal line G2. And connected to the second data signal line S1y.
- the third pixel P (3,1) and the fourth pixel P (4,1) are paired, and the pixel P (3,1) Connected to the scanning signal line G3 and connected to the second data signal line S1y, the pixel P (4, 1) is connected to the scanning signal line G4 and connected to the first data signal line S1x.
- the pixel P (5,1) in the sixth row and the pixel P (6,1) in the sixth row are paired, and the image P (5, 1) is connected to the scanning signal line G5 and connected to the first data signal line S1x, and the pixel P (6, 1) is connected to the scanning signal line G6 and to the second data signal line S1y. It is connected.
- the first and second data signal lines S2x and S2y are arranged on both sides of the pixel column PS2, and the first pixel P (1,2) and the second pixel P (2 , 2) are paired, the pixel P (1,2) is connected to the scanning signal line G1 and is connected to the second data signal line S2y, and the pixel P (2,2) is connected to the scanning signal line G2. And connected to the first data signal line S2x.
- the third pixel P (3,2) and the fourth pixel P (4,2) are paired, and the pixel P (3,2) Is connected to the scanning signal line G3 and connected to the first data signal line S2x, and the pixel P (4, 2) is connected to the scanning signal line G4 and connected to the second data signal line S2y.
- the fifth pixel P (5,2) and the sixth pixel P (6,2) are paired, and the image P (5, 2) is connected to the scanning signal line G5 and connected to the second data signal line S2y, and the pixel P (6, 2) is connected to the scanning signal line G6 and to the first data signal line S2x. It is connected.
- a positive polarity potential is supplied to the first data signal line S1x in the predetermined horizontal scanning period (the state shown in FIG. 13B), while the second A negative polarity potential is supplied to the data signal line S1y, and in the next horizontal scanning period (the state shown in FIG. 13C), a negative polarity potential is supplied to the first data signal line S1x.
- a positive polarity potential is supplied to the data signal line S1y.
- a positive polarity potential is supplied to the first data signal line S2x in a predetermined horizontal scanning period (the state shown in FIG. 13B).
- a negative polarity potential is supplied to the second data signal line S2y.
- a negative polarity potential is supplied to the first data signal line S2x.
- a positive polarity potential is supplied to the second data signal line S2y.
- the second data signal line S1y corresponding to the pixel column PS1 and the second data signal line S2y corresponding to the pixel column PS2 are adjacent to each other without sandwiching the pixel column.
- the scanning signal line G1 connected to the pixels P (1,1) ⁇ P (1,2) and the pixels P (2,1) ⁇ P The scanning signal line G2 connected to (2, 2) is first selected simultaneously, and then the scanning signal line G3 connected to the pixels P (3, 1) and P (3, 2) and the pixel P (4, 1).
- the scanning signal line G4 connected to P (4,2) is simultaneously selected, and then the scanning signal line G5 connected to the pixel P (5,1) P (5,2) and the pixel P (6,1) ).
- the scanning signal line G6 connected to P (6, 2) is simultaneously selected.
- the second data signal is synchronized with the writing of the positive polarity potential from the first data signal line S1x to the pixel electrode of the pixel P (1,1) in the first horizontal scanning period.
- a negative polarity potential is written from the line S1y to the pixel electrode of the pixel P (2,1), and a negative polarity potential is written from the second data signal line S2y to the pixel electrode of the pixel P (1,2).
- a positive polarity potential is written from the first data signal line S2x to the pixel electrode of the pixel P (2, 2) (see FIG. 13B).
- the first data signal line S1x to the pixel P are synchronized with the writing of the positive polarity potential from the second data signal line S1y to the pixel electrode of the pixel P (3, 1).
- the negative polarity potential is written to the pixel electrode of (4, 1) and the negative polarity potential is written from the first data signal line S2x to the pixel electrode of the pixel P (3, 2).
- the positive potential is written from the two data signal lines S2y to the pixel electrode of the pixel P (4, 2) (see FIG. 13C).
- each pixel can be dot-inverted while extending one horizontal scanning period by simultaneously selecting two scanning signal lines. That is, it is possible to increase the pixel charging time while suppressing flicker.
- the signal potential supplied to two adjacent (adjacent) data signal lines (for example, S1y and S2y) without interposing the pixel column always has the same polarity. Power consumption due to parasitic capacitance can be suppressed, and the load on the source driver can be reduced.
- the present liquid crystal display device is suitable for double speed driving in which the number of frames per unit time is doubled (for example, 120 frames / second). Although the pixel charging time is inevitably reduced in the double speed driving, the necessary pixel charging time can be ensured by using this configuration.
- the present liquid crystal display device is suitable for a digital cinema standard liquid crystal display device having 2160 scanning signal lines and a super high vision standard liquid crystal display device having 4320 scanning signal lines.
- the polarity of the signal potential supplied to the data signal line is inverted every horizontal scanning period as shown in FIG.
- the pixel potential waveform when the potential level corresponds to a black gradation (gradation potential V0 0V)
- the potential level corresponding to a halftone Align with pixel potential waveform Can, the ultimate potential in each case can be substantially matched.
- FIG. 44 shows the case of double speed driving as described above, and 1H (one horizontal scanning period) is 14.82 [ ⁇ s]. Also in FIG. 14, the specific time of 1H is as described above during double speed driving.
- the display unit of the present liquid crystal display device can also be configured as shown in FIG.
- the display unit 10f in FIG. 15A differs from the display unit 10e in FIG. 13A in that it corresponds to the second data signal line corresponding to one of the two adjacent pixel columns and the other of the two pixel columns.
- a first data signal line corresponding to one of the two pixel columns and a second data signal line corresponding to the other of the two pixel columns. are adjacent to each other without interposing a pixel column.
- the first and second data signal lines S1x and S1y are arranged on both sides of the pixel column PS1, and the first and second data signal lines S2x and S2y are arranged on both sides of the pixel column PS2, and correspond to the pixel column PS1.
- the second data signal line S1y is adjacent to the first data signal line S2x corresponding to the pixel column PS2.
- the driving method of the display unit 10f is shown in FIG. 16, and the writing state to each pixel is shown in FIGS.
- the display unit 10f also increases the pixel charging time while suppressing flicker, and attains the potential reached in the current horizontal scanning period due to the difference in the potential level supplied before one horizontal scanning period. The problem that the (charge rate) varies can be generally solved.
- the display unit 10e shown in FIG. 13A may have a pixel division method (multi-pixel structure) as shown in FIG. 17A, for example.
- one scanning signal line corresponding to one pixel is provided so as to cross one pixel, and a plurality of storage capacitor lines are provided in parallel with the scanning signal line.
- Each pixel includes a first transistor and a first pixel electrode PE1 on one side of the scanning signal line, and a second transistor and a second pixel electrode PE2 on the other side of the scanning signal line.
- the second pixel electrodes PE1 and PE2 are connected to the same data signal line through first and second transistors, respectively, and the first and second transistors are connected to the same scanning signal line, and the first and second transistors
- the two pixel electrodes PE1 and PE2 form different storage capacitor lines and storage capacitors, respectively.
- one storage capacitor wiring is provided corresponding to two pixels (two pixel columns) adjacent in the column direction, and the first or second pixel electrode provided on one of the two pixels and the above-mentioned
- the first or second pixel electrode provided in the other of the two pixel regions forms the storage capacitor line and the storage capacitor.
- a scanning signal line G1 is provided so as to cross the pixel P (1,1), and a plurality of storage capacitor wirings (Cs1 to Cs7) are provided in parallel with the scanning signal lines (G1 to G6).
- the connection relationship of the pixels P (1,1), P (2,1), P (1,2), and P (2,2) is the same as that of the display unit 10c in FIG.
- the first pixel electrode PE1 of the pixel P (3, 1) is connected to the second data signal line S1y via the first transistor, and the second pixel electrode PE2 is connected to the second data signal line via the second transistor.
- the first and second transistors are connected to the scanning signal line G3, and the first pixel electrode PE1 of the pixel P (3, 1) forms a storage capacitor line Cs3 and a storage capacitor, and is connected to the second pixel.
- the electrode PE2 forms a storage capacitor with the storage capacitor line Cs4.
- the first pixel electrode PE1 of the pixel P (4, 1) is connected to the first data signal line S1x via the first transistor, and the second pixel electrode PE2 is connected to the first data signal line via the second transistor.
- the first and second transistors are connected to the scanning signal line G4, the first pixel electrode PE1 of the pixel P (4, 1) forms a storage capacitor line Cs4 and a storage capacitor, and is connected to the second pixel.
- the electrode PE2 forms a storage capacitor with the storage capacitor line Cs5.
- the first pixel electrode PE1 of the pixel P (3, 2) is connected to the first data signal line S2x via the first transistor, and the second pixel electrode PE2 is connected to the first data signal line via the second transistor.
- the first and second transistors are connected to the scanning signal line G3, and the first pixel electrode PE1 of the pixel P (3, 2) forms a storage capacitor line Cs4 and a storage capacitor, and is connected to the second pixel.
- the electrode PE2 forms a storage capacitor with the storage capacitor line Cs3.
- the first pixel electrode PE1 of the pixel P (4, 2) is connected to the second data signal line S2y via the first transistor, and the second pixel electrode PE2 is connected to the second data signal line via the second transistor.
- the first and second transistors are connected to the scanning signal line G4, and the first pixel electrode PE1 of the pixel P (4, 2) forms a storage capacitor line Cs5 and a storage capacitor, and is connected to the second pixel.
- the electrode PE2 forms a storage capacitor with the storage capacitor line Cs4.
- FIG. 18 is a timing chart showing a method for driving each data signal line, each scanning signal line, and each storage capacitor line of the display unit 10g.
- the driving method of each data signal line and each scanning signal line is the same as in FIG. 14, and in synchronization with turning off the scanning signal line connected to one pixel or after turning off,
- the potentials of the first and second pixel electrodes PE1 and PE2 of the pixel and the two storage capacitor lines forming the storage capacitor are level-shifted in the opposite directions (the push-up and push-down directions).
- the level of the storage capacitor line Cs1 is shifted in the direction of pushing up and the potential of the holding capacitor line Cs2 is pushed down to shift the level of the scanning signal line G3.
- the level is shifted in the direction of pushing up the potential of the storage capacitor line Cs3, and the level is shifted in the direction of pushing down the potential of the storage capacitor line Cs4.
- the operation in the first horizontal scanning period shown in FIG. 17B is the same as that in FIG. 5B, and the next horizontal scanning period is as shown in FIG. That is, the scanning signal lines G3 and G4 are simultaneously turned ON (selected), and the same positive potential is written from the second data signal line S1y to the first and second pixel electrodes PE1 and PE2 of the pixel P (3, 1).
- the same negative potential is written from the first data signal line S1x to the first and second pixel electrodes PE1 and PE2 of the pixel P (4,1) and the first data signal line S2x
- the first and second pixels P (4,2) are connected to the first and second pixel electrodes PE1 and PE2 of P (3,2) in synchronization with the same negative potential being written.
- the same positive potential is written to the second pixel electrodes PE1 and PE2.
- the storage capacitor line Cs3 is pushed up and the storage capacitor line Cs4 is pushed down.
- the portion including the second pixel electrode PE2 of the pixel P (2,1) is a dark subpixel
- the portion including the first pixel electrode PE1 of the pixel P (3,1) is a bright subpixel
- the portion including the second pixel electrode PE2 of the pixel P (3,1) is a dark subpixel
- the portion including the first pixel electrode PE1 of the pixel P (4,1) is a bright subpixel.
- the pixel P The portion including the first pixel electrode PE1 of (2, 2) is the bright subpixel, the portion including the second pixel electrode PE2 of the pixel P (3, 2) is the dark subpixel, and the first of the pixel P (3, 2).
- a portion including the pixel electrode PE1 is a bright subpixel, and a portion including the second pixel electrode PE2 of the pixel P (4, 2) is a dark subpixel.
- the next horizontal scanning period is as shown in FIG. Accordingly, in the pixel column PS1, the sub-pixels are arranged in the order of light, dark, bright, dark, bright,..., While in the pixel column PS2, the sub-pixels are dark, bright, dark, bright, dark,. The bright subpixels and the dark subpixels are arranged in a checkered pattern.
- the pixel charging time is increased while suppressing flicker, and the potential reached (charging rate) in the current horizontal scanning period due to the difference in the potential level supplied before one horizontal scanning period. It is possible to substantially eliminate the problem of variation and to improve the viewing angle characteristics.
- the signal potential supplied to two adjacent (adjacent) data signal lines for example, S1y and S2y
- the signal potential supplied to two adjacent (adjacent) data signal lines always has the same polarity.
- the power consumption due to the parasitic capacitance can be suppressed, and the load on the source driver can be reduced.
- the bright subpixels and the dark subpixels can be arranged in a checkered pattern so that the bright subpixels or the dark subpixels are not adjacent to each other. This makes it possible to improve the viewing angle characteristics while suppressing the feeling of roughness (jaggy).
- the present liquid crystal display device is suitable for a liquid crystal display device that performs double speed driving, and a liquid crystal display device that conforms to the digital cinema standard or the super high vision standard.
- the display unit of the present liquid crystal display device can also be configured as shown in FIG.
- the display unit 10h in FIG. 19A differs from the display unit 10g in FIG. 17A in that it corresponds to the second data signal line corresponding to one of the two adjacent pixel columns and the other of the two pixel columns.
- a first data signal line corresponding to one of the two pixel columns and a second data signal line corresponding to the other of the two pixel columns. are adjacent to each other without interposing a pixel column.
- the first and second data signal lines S1x and S1y are arranged on both sides of the pixel column PS1, and the first and second data signal lines S2x and S2y are arranged on both sides of the pixel column PS2, and correspond to the pixel column PS1.
- the second data signal line S1y is adjacent to the first data signal line S2x corresponding to the pixel column PS2.
- the driving method of the display unit 10h is shown in FIG. 20, and the writing state to each pixel is shown in FIGS. 19 (b) to 19 (d).
- the display unit 10h also increases the pixel charging time while suppressing flicker, and reaches the potential reached in the current horizontal scanning period due to the difference in the potential level supplied before one horizontal scanning period.
- the bright subpixels and the dark subpixels can be arranged in a checkered pattern so that the bright subpixels or the dark subpixels are not adjacent to each other. This makes it possible to improve the viewing angle characteristics while suppressing the feeling of roughness (jaggy).
- a refresh period R is provided at the beginning of each horizontal scanning period, and a refresh potential (for example, Vcom) is supplied to each data signal line during the refresh period R.
- the refresh period R is synchronized with, for example, a period when the latch strobe signal LS is “High” (described later).
- FIG. 43 shows the case of double speed driving as described above, where 1H (one horizontal scanning period) is 14.82 [ ⁇ s] and the refresh period is 1.5 [ ⁇ s]. Also in FIG. 21, the specific times of 1H and refresh period R are as described above during double speed driving.
- the display unit 10g of FIG. 17A which is a pixel division method
- the current level caused by the difference in potential level supplied to the same data signal line before one horizontal scanning period. It is possible to greatly suppress variations in the reached potential (charging rate) during the horizontal scanning period.
- the drive shown in FIG. 22 is more advantageous than the drive shown in FIGS. 18 and 20 in terms of suppressing power consumption and suppressing heat generation of the source driver itself.
- a refresh period R is provided at the beginning of each horizontal scanning period, a refresh potential (for example, Vcom) is supplied to each data signal line in the refresh period R, and each scanning signal line is set to 2/3 from the previous scanning.
- the selection is performed a plurality of times (for example, three times) so as to be synchronized with the refresh period R, and the refresh potential (for example, Vcom) is applied to the pixels connected to each scanning signal line in this midway selection period.
- the halfway selection period is shorter than one horizontal scanning period, black is written to each pixel (black insertion is performed by providing the halfway selection period a plurality of times at intervals of one horizontal scanning period and performing impulse driving. )be able to.
- each pixel displays the input video data during the 2/3 frame period of one frame period, while performing the black display during the remaining 1/3 frame period. Etc. can be reduced, and the moving image display quality can be improved.
- FIG. 25A is a schematic diagram showing an example of the configuration of the display unit of the present liquid crystal display device
- FIGS. 25B to 25D are schematic diagrams showing a driving method of the display unit. These are timing charts showing the driving method.
- the display unit 10i is provided with first and second data signal lines (for example, S1x / S1y) corresponding to one pixel column (for example, PS1), and the pixels One pixel (for example, P (1,1)) included in the column is connected to one scanning signal line (for example, G1) and the first and second data signal lines (for example, S1x / S1y) Connected to either.
- first and second data signal lines for example, S1x / S1y
- each pixel in the first row of each pixel column two adjacent pixels in the column direction are paired in order, and two adjacent pairs are sequentially grouped together, and the order is given in that order.
- two pixels in each pair are connected to different data signal lines, and each odd-numbered pixel is connected to the same data signal line, and the above sequence is continued.
- the data signal line connected to the odd-numbered pixels included in one group is different from the data signal line connected to the odd-numbered pixels included in the other group.
- the pixel in the first row is the first pixel to be counted, and the pixels other than the 2 ⁇ 2 ⁇ i + 1th pixel (i is a natural number) counted in the scanning direction are connected to a data signal line different from the preceding pixel.
- the 2 ⁇ 2 ⁇ i + 1-th pixel is connected to the same data signal line as the previous pixel.
- the pixel electrode PE is connected to one data signal line through a transistor (TFT), and the gate terminal of the transistor is connected to one scanning signal line.
- signal potentials having opposite polarities are supplied to the first and second data signal lines, and the polarity of the signal potential supplied to each data signal line is inverted every two horizontal scanning periods (2H).
- each pixel included in one pixel row is connected to the same scanning signal line, and a first data signal line corresponding to one of two adjacent pixel columns and a second data line corresponding to the other of the two pixel columns.
- a signal potential having the same polarity is supplied to one data signal line, and the connection relationship with the first and second data signal lines is reversed between pixels adjacent in the row direction.
- the first and second data signal lines corresponding to the pixel column are arranged on both sides of the pixel column, and the first data signal line and the two pixels corresponding to one of the two adjacent pixel columns.
- the first data signal line corresponding to the other of the columns is adjacent without interposing the pixel column, or the second data signal line corresponding to one of the two pixel columns and the other of the two pixel columns The second data signal line to be adjacent to each other without sandwiching the pixel column.
- a group is selected according to the scanning direction (the above order), and the scanning signal lines connected to each of the two pixels forming a pair are sequentially selected for each pair in the selected group. That is, two adjacent scanning signal lines are simultaneously selected in order from the scanning signal line connected to the pixels in the first row.
- a positive polarity potential is applied to the first data signal line S1x in a predetermined horizontal scanning period (the state shown in FIG. 25B).
- a negative polarity potential is supplied to the second data signal line S1y, and a positive polarity potential is supplied to the first data signal line S1x even in the next horizontal scanning period (the state shown in FIG. 25C).
- a negative polarity potential is supplied to the second data signal line S1y, and a negative polarity potential is supplied to the first data signal line S1x in the next horizontal scanning period (the state shown in FIG. 25D).
- a positive polarity potential is supplied to the second data signal line S1y. Further, for the first and second data signal lines S2x and S2y in FIG. 25A, a positive polarity potential is applied to the first data signal line S2x in a predetermined horizontal scanning period (the state shown in FIG. 25B). On the other hand, a negative polarity potential is supplied to the second data signal line S2y, and a positive polarity potential is supplied to the first data signal line S2x even in the next horizontal scanning period (the state shown in FIG. 25C).
- a negative polarity potential is supplied to the second data signal line S2y, and a negative polarity potential is supplied to the first data signal line S2x in the next horizontal scanning period (the state shown in FIG. 25D).
- a positive polarity potential is supplied to the second data signal line S2y.
- the second data signal line S1y corresponding to the pixel column PS1 and the second data signal line S2y corresponding to the pixel column PS2 are adjacent to each other without sandwiching the pixel column.
- the scanning signal line G2 connected to (2, 2) is first selected simultaneously, and then the scanning signal line G3 connected to the pixels P (3, 1) and P (3, 2) and the pixel P (4, 1).
- the scanning signal line G4 connected to P (4,2) is simultaneously selected, and then the scanning signal line G5 connected to the pixel P (5,1) P (5,2) and the pixel P (6,1) ).
- the scanning signal line G6 connected to P (6, 2) is simultaneously selected.
- the second data signal is synchronized with the writing of the positive polarity potential from the first data signal line S1x to the pixel electrode of the pixel P (1, 1) in the first horizontal scanning period.
- a negative polarity potential is written from the line S1y to the pixel electrode of the pixel P (2,1), and a negative polarity potential is written from the second data signal line S2y to the pixel electrode of the pixel P (1,2).
- a positive polarity potential is written from the first data signal line S2x to the pixel electrode of the pixel P (2, 2) (see FIG. 25B).
- the second data signal line S1y to the pixel P are synchronized with the writing of the positive polarity potential from the first data signal line S1x to the pixel electrode of the pixel P (3, 1).
- the negative polarity potential is written to the pixel electrode of (4, 1) and the negative polarity potential is written to the pixel electrode of the pixel P (3, 2) from the second data signal line S2y.
- a positive polarity potential is written from one data signal line S2x to the pixel electrode of the pixel P (4, 2) (see FIG. 25C).
- the positive polarity potential is written from the second data signal line S1y to the pixel electrode of the pixel P (5, 1), and then the first data signal line S1x to the pixel P ( The negative polarity potential is written to the pixel electrode 6, 1) and the negative polarity potential is written from the first data signal line S 2 x to the pixel electrode of the pixel P (5, 2).
- a positive polarity potential is written from the data signal line S2y to the pixel electrode of the pixel P (6, 2) (see FIG. 25D).
- the display unit 10i it is possible to invert each pixel while extending one horizontal scanning period by simultaneously selecting two scanning signal lines. That is, it is possible to increase the pixel charging time while suppressing flicker.
- the signal potential supplied to two adjacent (adjacent) data signal lines (for example, S1y and S2y) without interposing the pixel column always has the same polarity. The power consumption due to the parasitic capacitance can be suppressed, and the load on the source driver can be reduced.
- the present liquid crystal display device is suitable for a liquid crystal display device that performs double speed driving, and a liquid crystal display device that conforms to the digital cinema standard or the super high vision standard.
- the power consumption of the source driver is reduced as compared with the case where the polarity of the signal potential is inverted every one horizontal scanning period. be able to.
- the display unit 10i in FIG. 25A may be a pixel division method (multi-pixel structure) as shown in FIG. 27A, for example.
- one scanning signal line corresponding to one pixel is provided so as to cross one pixel, and a plurality of storage capacitor lines are provided in parallel with the scanning signal line.
- Each pixel includes a first transistor and a first pixel electrode PE1 on one side of the scanning signal line, and a second transistor and a second pixel electrode PE2 on the other side of the scanning signal line.
- the second pixel electrodes PE1 and PE2 are connected to the same data signal line through first and second transistors, respectively, and the first and second transistors are connected to the same scanning signal line, and the first and second transistors
- the two pixel electrodes PE1 and PE2 form different storage capacitor lines and storage capacitors, respectively.
- one storage capacitor wiring is provided corresponding to two pixels (two pixel columns) adjacent in the column direction, and the first or second pixel electrode provided on one of the two pixels and the above-mentioned
- the first or second pixel electrode provided in the other of the two pixel regions forms the storage capacitor line and the storage capacitor.
- FIG. 28 is a timing chart showing a method for driving each data signal line, each scanning signal line, and each storage capacitor line of the display unit 10j.
- the driving method of each data signal line and each scanning signal line is the same as that in FIG. 26, and in synchronization with turning off the scanning signal line connected to one pixel or after turning off,
- the potentials of the first and second pixel electrodes PE1 and PE2 of the pixel and the two storage capacitor lines forming the storage capacitor are level-shifted in the opposite directions (the push-up and push-down directions).
- the level of the storage capacitor line Cs1 is shifted in the direction of pushing up and the potential of the holding capacitor line Cs2 is pushed down to shift the level of the scanning signal line G3.
- the level is shifted in the direction of pushing up the potential of the storage capacitor line Cs3, and the level is shifted in the direction of pushing down the potential of the storage capacitor line Cs4.
- the operation in the first horizontal scanning period shown in FIG. 27 (b) is the same as that in FIG. 5 (b), and the next horizontal scanning period is as shown in FIG. 27 (c).
- the scanning period is as shown in FIG. Accordingly, in the pixel column PS1, the sub-pixels are arranged in the order of light, dark, bright, dark, bright,..., And in the pixel column PS2, the sub-pixels are dark, bright, dark, bright, dark,. They will be arranged in order.
- the display unit 10j it is possible to increase the pixel charging time while suppressing flicker and to improve the viewing angle characteristics.
- the signal potential supplied to two adjacent (adjacent) data signal lines (for example, S1y and S2y) without interposing the pixel column always has the same polarity.
- the power consumption due to the parasitic capacitance can be suppressed, and the load on the source driver can be reduced.
- the bright subpixels and the dark subpixels can be arranged in a checkered pattern so that the bright subpixels or the dark subpixels are not adjacent to each other. This makes it possible to improve the viewing angle characteristics while suppressing the feeling of roughness (jaggy).
- the present liquid crystal display device is suitable for a liquid crystal display device that performs double speed driving, and a liquid crystal display device that conforms to the digital cinema standard or the super high vision standard.
- a refresh period R is provided at the beginning of each horizontal scanning period, and a refresh potential (for example, Vcom) is supplied to each data signal line during the refresh period R.
- the refresh period R is synchronized with, for example, a period when the latch strobe signal LS is “High” (described later).
- a refresh period R is provided at the beginning of each horizontal scanning period, a refresh potential (for example, Vcom) is supplied to each data signal line in the refresh period R, and each scanning signal line is set to 2/3 from the previous scanning.
- the selection is performed a plurality of times (for example, three times) so as to be synchronized with the refresh period R, and the refresh potential (for example, Vcom) is applied to the pixels connected to each scanning signal line in this midway selection period.
- the halfway selection period is shorter than one horizontal scanning period, black is written to each pixel (black insertion is performed by providing the halfway selection period a plurality of times at intervals of one horizontal scanning period and performing impulse driving. )be able to.
- each pixel displays the input video data during the 2/3 frame period of one frame period, while performing the black display during the remaining 1/3 frame period. Etc. can be reduced, and the moving image display quality can be improved.
- FIG. 33 (a) is a schematic diagram showing a configuration example of the display unit of the present liquid crystal display device
- FIGS. 33 (b) to 33 (e) are schematic diagrams showing a driving method of the display unit. These are timing charts showing the driving method.
- FIG. 33A in the display unit 10k, corresponding to one pixel column (for example, PS1), first and second data signal lines (for example, S1a) on both sides (for example, PS1) are provided.
- S1b) is provided, and one pixel (for example, P (1,1)) included in the pixel column is connected to one scanning signal line (for example, G1) and the first and second data It is connected to one of signal lines (for example, S1a and S1b).
- the first pixel in the first row of each pixel column is used as the first pixel, two consecutive odd pixels counted in the scanning direction are sequentially paired, and two consecutive even pixels are counted.
- the two pixels of each pair are connected to different data signal lines.
- the pixel electrode PE is connected to one data signal line through a transistor (TFT), and the gate terminal of the transistor is connected to one scanning signal line.
- the first and second data signal lines are supplied with signal potentials having the same polarity, and the polarity of the signal potential supplied to each data signal line is set every horizontal scanning period (1H). Invert to. Further, each pixel included in one pixel row is connected to the same scanning signal line, and the first and second data signal lines corresponding to one of the two adjacent pixel columns (for example, PS1), the two A signal potential having a reverse polarity is supplied to the first and second data signal lines corresponding to the other (for example, PS2) of the pixel column.
- each scanning signal line has a scanning signal line connected to the pixels in the first row as the first scanning signal line, and sequentially, two odd-numbered scanning signal lines and two consecutive even-numbered scanning signal lines.
- the scanning signal lines are alternately selected simultaneously.
- the first and second data signal lines S1x and S1y are arranged on both sides of the pixel column PS1, and the first pixel P (1,1) and the third pixel P (3,3) are arranged. 1) and the pixel P (1,1) are connected to the scanning signal line G1 and the first data signal line S1a, and the pixel P (3,1) is connected to the scanning signal line G3. And connected to the second data signal line S1b.
- the second pixel P (2,1) and the fourth pixel P (4,1) are paired, and the pixel P (2,1) is Connected to the scanning signal line G2 and connected to the first data signal line S1a, the pixel P (4, 1) is connected to the scanning signal line G4 and connected to the second data signal line S1b.
- the pixel P (5,1) in the seventh row and the pixel P (7,1) in the seventh row are paired, and the image P (5, 1) is connected to the scanning signal line G5 and to the first data signal line S1a, and the pixel P (7, 1) is connected to the scanning signal line G7 and to the second data signal line S1b. It is connected.
- the first and second data signal lines S2a and S2b are arranged on both sides of the pixel column PS2, and the first pixel P (1,2) and the third pixel P (3 , 2) are paired, the pixel P (1,2) is connected to the scanning signal line G1 and is connected to the first data signal line S2a, and the pixel P (3,2) is connected to the scanning signal line G3. And connected to the second data signal line S2b.
- the second pixel P (2,2) and the fourth pixel P (4,2) are paired, and the pixel P (2,2) Is connected to the scanning signal line G2 and connected to the first data signal line S2a, and the pixel P (4, 2) is connected to the scanning signal line G4 and connected to the second data signal line S2b.
- the fifth pixel P (5,2) and the pixel P (7,2) in the seventh row are paired, and the image P (5, 2) is connected to the scanning signal line G5 and connected to the first data signal line S2a, and the pixel P (7, 2) is connected to the scanning signal line G7 and connected to the second data signal line S2b. It is connected.
- a positive polarity potential is supplied to the first data signal line S1a in the predetermined horizontal scanning period (the state shown in FIG. 33B), and the second A positive polarity potential is also supplied to the data signal line S1b.
- a negative polarity potential is supplied to the first data signal line S1a, and the second A negative polarity potential is also supplied to the data signal line S1b.
- a positive polarity potential is supplied to the first data signal line S1a, and the second A positive polarity potential is also supplied to the data signal line S1b.
- the scanning signal line G1 connected to the pixels P (1,1) ⁇ P (1,2) and the pixels P (3,1) ⁇ P The scanning signal line G3 connected to (3, 2) is first selected simultaneously, and then the scanning signal line G2 and pixel P (4, 1) connected to the pixels P (2, 1) and P (2, 2) are selected.
- the scanning signal line G4 connected to P (4,2) is simultaneously selected, and then the scanning signal line G5 connected to the pixel P (5,1) P (5,2) and the pixel P (7,1) ).
- the scanning signal line G7 connected to P (7, 2) is simultaneously selected.
- the second data signal is synchronized with the writing of the positive polarity potential from the first data signal line S1a to the pixel electrode of the pixel P (1, 1) in the first horizontal scanning period.
- a positive polarity potential is written from the line S1y to the pixel electrode of the pixel P (3,1), and a negative polarity potential is written from the first data signal line S2a to the pixel electrode of the pixel P (1,2).
- a negative polarity potential is written from the second data signal line S2b to the pixel electrode of the pixel P (3, 2) (see FIG. 33B).
- the second data signal line S1b to the pixel P are synchronized with the writing of the negative polarity potential from the first data signal line S1a to the pixel electrode of the pixel P (2,1).
- the negative polarity potential is written to the pixel electrode of (4, 1) and the positive polarity potential is written to the pixel electrode of the pixel P (2, 2) from the first data signal line S2a.
- a positive polarity potential is written from the two data signal lines S2b to the pixel electrode of the pixel P (4, 2) (see FIG. 33C).
- each pixel can be dot-inverted while extending one horizontal scanning period by simultaneously selecting two scanning signal lines. That is, it is possible to increase the pixel charging time while suppressing flicker.
- the present liquid crystal display device is suitable for a liquid crystal display device that performs double speed driving, and a liquid crystal display device that conforms to the digital cinema standard or the super high vision standard.
- the polarity of the signal potential supplied to the data signal line is inverted every horizontal scanning period to perform double speed driving.
- the display unit 10k in FIG. 33 (a) may have a pixel division system (multi-pixel structure) as shown in FIG. 35 (a), for example.
- a pixel division system multi-pixel structure
- FIG. 35A one scanning signal line corresponding to one pixel is provided so as to cross one pixel, and a plurality of storage capacitor lines are provided in parallel with the scanning signal line.
- Each pixel includes a first transistor and a first pixel electrode PE1 on one side of the scanning signal line, and a second transistor and a second pixel electrode PE2 on the other side of the scanning signal line.
- the second pixel electrodes PE1 and PE2 are connected to the same data signal line through first and second transistors, respectively, and the first and second transistors are connected to the same scanning signal line, and the first and second transistors
- the two pixel electrodes PE1 and PE2 form different storage capacitor lines and storage capacitors, respectively.
- one storage capacitor wiring is provided corresponding to two pixels (two pixel columns) adjacent in the column direction, and the first or second pixel electrode provided on one of the two pixels and the above-mentioned
- the first or second pixel electrode provided in the other of the two pixel regions forms the storage capacitor line and the storage capacitor. Note that the connection relationship between each pixel (the first and second pixel electrodes PE1 and PE2 and the first and second transistors included therein), the data signal line, and the scanning signal line is shown in FIG. The same as 10k.
- FIG. 36 is a timing chart showing a method of driving each data signal line, each scanning signal line, and each storage capacitor line of the display unit 10p.
- the driving method of each data signal line and each scanning signal line is the same as that in FIG. 34, and in synchronization with or after turning off the scanning signal line connected to one pixel,
- the potentials of the first and second pixel electrodes PE1 and PE2 of the pixel and the two storage capacitor lines forming the storage capacitor are level-shifted in the opposite directions (the push-up and push-down directions).
- the potentials of the storage capacitor lines Cs1 and Cs2 do not change (level shift), and the potential of the storage capacitor line Cs1 is synchronized with the scanning signal lines G2 and G4 being turned off.
- Level shift in the direction to push up level shift in the direction to push down the potential of the storage capacitor line Cs2
- each storage capacitor wiring of the display unit 10p is formed as follows, and the potential is controlled. That is, the storage capacitor lines that form the storage capacitors with the pixel electrodes PE1 and PE2 of the pixels in the first row (for example, P (1,1)) are the first and second storage capacitor lines Cs1 and Cs2.
- the second storage capacitor line Cs2 also forms a storage capacitor with the pixel electrode PE2 of the pixel in the second row (for example, P (2,1)), or when the simultaneous writing of the pixels in the first row and the second row ends or Thereafter, the potentials of the first and second storage capacitor lines Cs1 and Cs2 are synchronously level-shifted in the opposite directions, and the first storage capacitor line Cs1 is counted in the scanning direction, and the odd-numbered storage capacitor lines are counted.
- the bundles for example, a bundle of Cs1 and Cs3
- the latter is synchronized with the potential level shift of the storage capacitor wiring (for example, Cs1) which is the first.
- Retention capacitance wiring (for example , Cs3) is level-shifted in the same direction as this, and each holding capacity of the bundle positioned downstream in the scanning direction between two adjacent bundles (for example, a bundle of Cs1 and Cs3 and a bundle of Cs5 and Cs7).
- the potential of the wirings (Cs5 and Cs7) is level-shifted after two horizontal scanning periods (2H) in which the potentials of the storage capacitor wirings (Cs1 and Cs3) of the bundle located upstream in the scanning direction are level-shifted, and the even-numbered holding
- each bundle for example, a bundle of Cs2 and Cs4
- the level shift of the potential of the storage capacitor wiring for example, Cs2 which is the first number.
- the potential of the holding capacitor wiring (for example, Cs4) is level-shifted in the same direction as this, and between two adjacent bundles (for example, the bundle of Cs2 and Cs4 and the bundle of Cs6 and Cs8) Two horizontal scanning periods (2H) in which the potentials of the storage capacitor wires (Cs6 and Cs8) of the bundle located on the side shift the level of the potentials of the storage capacitor wires (Cs2 and Cs4) of the bundle located on the upstream side in the scanning direction Level shift later. Note that the period of potential level shift of each storage capacitor wiring is one vertical scanning period (one frame period).
- the scanning signal lines G1 and G3 are simultaneously turned ON (selected) in the first horizontal scanning period, and the pixel P (1,1) from the first data signal line S1a.
- the first and second pixel electrodes PE1 and PE2 of the pixel P (3,1) from the second data signal line S1b are synchronized with the writing of the same positive polarity potential to the first and second pixel electrodes PE1 and PE2. Is written in synchronism with the same potential having the negative polarity written to the first and second pixel electrodes PE1 and PE2 of the pixel P (1,2) from the first data signal line S2a.
- the same negative potential is written from the second data signal line S2b to the first and second pixel electrodes PE1 and PE2 of the pixel P (3, 2).
- the scanning signal lines G2 and G4 are simultaneously turned ON (selected) in the next horizontal scanning period, and the first and second pixels P (2,1) from the first data signal line S1a.
- the negative polarity is applied from the second data signal line S1b to the first and second pixel electrodes PE1 and PE2 of the pixel P (4, 1).
- the same positive polarity potential is written from the data signal line S2b to the first and second pixel electrodes PE1 and PE2 of the pixel P (4, 2).
- the storage capacitor line Cs1 is pushed up, the storage capacitor line Cs2 is pushed down, the storage capacitor line Cs3 is pushed up, and the storage capacitor line Cs4 is pushed down.
- a portion including the first pixel electrode PE1 of the pixel P (1,1) is a bright subpixel
- a portion including the second pixel electrode PE2 of the pixel P (1,1) is a dark subpixel
- the portion including the first pixel electrode PE1 of the pixel P (2,1) is the bright subpixel
- the portion including the second pixel electrode PE2 of the pixel P (2,1) is the dark subpixel
- the pixel P (3,1) is a bright subpixel
- the portion including the second pixel electrode PE2 of the pixel P (3,1) is a dark subpixel, and the like of the pixel P (1,2) in the pixel column PS2.
- the portion including the two pixel electrode PE2 is a dark subpixel
- the portion including the first pixel electrode PE1 of the pixel P (1,2) is the bright subpixel
- the portion including the second pixel electrode PE2 of the pixel P (2,1) is
- the portion including the first pixel electrode PE1 of the dark subpixel, pixel P (2,1) is the second pixel electrode of the bright subpixel, pixel P (3,1).
- Portion including the PE2 is part including the first pixel electrode PE1 of dark subpixel, pixel P (3, 1) becomes a bright sub-pixel ....
- the sub-pixels are arranged in the order of light, dark, bright, dark, bright,..., And in the pixel column PS2, the sub-pixels are dark, bright, dark, bright, dark,. They will be arranged in order.
- the pixel charging time of the pixel is increased while flicker is suppressed, and the potential reached (charged) in the current horizontal scanning period due to the difference in the potential level supplied before one horizontal scanning period. It is possible to substantially eliminate the problem of variation in the rate) and to improve the viewing angle characteristics. Further, the bright subpixels and the dark subpixels can be arranged in a checkered pattern so that the bright subpixels or the dark subpixels are not adjacent to each other. This makes it possible to improve the viewing angle characteristics while suppressing the feeling of roughness (jaggy).
- the present liquid crystal display device is suitable for a liquid crystal display device that performs double speed driving, and a liquid crystal display device that conforms to the digital cinema standard or the super high vision standard.
- the storage capacitor lines Cs1 and Cs3 are synchronized with each other.
- a signal to be applied (Cs signal) can be shared, and a signal (Cs signal) to be supplied to the storage capacitor lines Cs2 and Cs4 can be shared. That is, as described above, if the odd-numbered storage capacitor lines are bundled in pairs from the first storage capacitor line, and the even-numbered storage capacitor lines are bundled in order from the second storage capacitor line.
- the Cs signals to be given to the two storage capacitor wires that are bundled can be shared.
- the number (type) of Cs signals applied to all the storage capacitor wirings can be reduced by almost half, and the circuit scale of the Cs control circuit (see FIG. 46) that generates the Cs signals can be reduced.
- the two holding capacitors (for example, Cs1 and Cs3) that are bundled may be connected within the panel (for example, connected to the same Cs trunk wiring) or the same in the Cs control circuit. It may be connected to the output terminal.
- a refresh period R is provided at the beginning of each horizontal scanning period, and a refresh potential (for example, Vcom) is supplied to each data signal line during the refresh period R.
- the refresh period R is synchronized with, for example, a period when the latch strobe signal LS is “High” (described later).
- the polarity of the signal potential supplied to the data signal line is a positive polarity in one frame and the gray level in the current horizontal scanning period is halftone, one horizontal scanning period before as described above.
- the arrival potential varies depending on the difference in the potential level supplied to (see FIG. 41).
- the polarity of the signal potential supplied to each data signal line is inverted every 1H and each horizontal scanning period.
- V255 -7.5V
- a refresh period R is provided at the beginning of each horizontal scanning period, a refresh potential (for example, Vcom) is supplied to each data signal line in the refresh period R, and each scanning signal line is set to 2/3 from the previous scanning.
- the selection is performed a plurality of times (for example, three times) so as to be synchronized with the refresh period R, and the refresh potential (for example, Vcom) is applied to the pixels connected to each scanning signal line in this midway selection period.
- the halfway selection period is shorter than one horizontal scanning period, black is written to each pixel (black insertion is performed by providing the halfway selection period a plurality of times at intervals of one horizontal scanning period and performing impulse driving. )be able to.
- each pixel displays the input video data during the 2/3 frame period of one frame period, while performing the black display during the remaining 1/3 frame period. Etc. can be reduced, and the moving image display quality can be improved.
- the polarity of the signal potential supplied to the data signal line is inverted every horizontal scanning period (1H), but the present invention is not limited to this.
- the polarity of the signal potential supplied to the data signal line can be inverted for each of a plurality of horizontal scanning periods by changing the order of simultaneous selection while maintaining the connection relationship between the pixels. In this case, the power consumption of the source driver can be reduced as compared with the case where the polarity of the signal potential is inverted every horizontal scanning period.
- the first and second data signal lines are provided on both sides corresponding to one pixel column.
- a first data signal line for example, S1x or S1a
- the second data signal line overlaps the pixel column.
- a data signal line (for example, S1y or S1b) may be provided. In this way, the data signal lines can be separated from each other, and the parasitic capacitance generated between them can be reduced.
- the distance between the data signal lines can be kept wider than the configuration in which the data signal lines corresponding to the pixel columns are arranged on both sides of the pixel column. Thereby, the short circuit rate between the data signal lines can be reduced, and the manufacturing yield can be increased.
- the interlayer insulating film on the data signal line be thick (for example, an organic insulating film is used for the interlayer insulating film).
- FIG. 57 shows variations in the potential reached in the current horizontal scanning period due to the potential level supplied before one horizontal scanning period when the above-described active refresh is performed with the refresh period being 90% of the time constant of the data signal line.
- FIG. 57 From FIG. 57, the arrival of pixels in the case of 0 gradation (1H before) ⁇ 100 gradation (current horizontal scanning period), 100 gradation ⁇ 100 gradation, and 255 gradation (1H before) ⁇ 100 gradation. It can be seen that the potentials are well aligned and the ultimate potential is substantially equal to the set gradation potential.
- FIG. 58 shows variations in the potential reached in the current horizontal scanning period due to the potential level supplied before one horizontal scanning period when the above-described active refresh is performed with the refresh period being 100% of the time constant of the data signal line.
- FIG. 58 From FIG. 58, the arrival of pixels in the case of 0 gradation (1H before) ⁇ 100 gradation (current horizontal scanning period), 100 gradation ⁇ 100 gradation, and 255 gradation (1H before) ⁇ 100 gradation. It can be seen that the potentials are evenly aligned and the ultimate potential is substantially equal to the set gradation potential.
- FIG. 45 is a block diagram showing a configuration of the present liquid crystal display device including the display units 10a, 10e, 10i, 10k, etc. (non-pixel division method).
- the present liquid crystal display device includes a display unit (liquid crystal panel), a source driver, a gate driver, a backlight, a backlight drive circuit, a display control circuit, and a data rearrangement circuit 44.
- the source driver drives the data signal line
- the gate driver drives the scanning signal line
- the data rearrangement circuit 44 rearranges the input data (described later)
- the display control circuit includes the source driver, the gate driver, and the backlight. Control the drive circuit.
- the display control circuit controls a display operation from a digital video signal Dv representing an image to be displayed, a horizontal synchronization signal HSY and a vertical synchronization signal VSY corresponding to the digital video signal Dv from an external signal source (for example, a tuner). For receiving the control signal Dc. Further, the display control circuit, based on the received signals Dv, HSY, VSY, and Dc, uses a data start pulse signal SSP and a data clock as signals for displaying an image represented by the digital video signal Dv on the display unit.
- the video signal Dv is output as a digital image signal DA from the display control circuit, and a pulse corresponding to each pixel of the image represented by the digital image signal DA.
- a data clock signal SCK is generated as a signal consisting of the above, a data start pulse signal SSP is generated as a signal that becomes high level (H level) for a predetermined period every horizontal scanning period based on the horizontal synchronization signal HSY, and the vertical synchronization signal VSY
- the gate start pulse signal GSP is generated as a signal that becomes H level only for a predetermined period every one frame period (one vertical scanning period), and the gate clock signal GCK is generated based on the horizontal synchronization signal HSY, and the horizontal synchronization signal HSY and Based on the control signal Dc, the latch strobe signal LS and the gate driver Generating a bus output control signal GOE.
- the digital image signal DA the latch strobe signal LS, the signal POL for controlling the polarity of the signal potential (data signal potential), the data start pulse signal SSP, and the data clock
- the signal SCK is input to the source driver, and the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE are input to the gate driver.
- the source driver corresponds to the pixel value in each scanning signal line of the image represented by the digital image signal DA based on the digital image signal DA, the data clock signal SCK, the latch strobe signal LS, the data start pulse signal SSP, and the polarity inversion signal POL.
- Data signals as analog potentials are sequentially generated every horizontal scanning period, and these data signals are output to data signal lines (for example, S1x and S1y).
- the gate driver generates a scanning signal based on the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE, and outputs them to the scanning signal line, thereby selectively selecting the scanning signal line. To drive.
- the data signal line and the scanning signal line of the display unit are driven by the source driver and the gate driver, so that the data signal line is connected via the TFT connected to the selected scanning signal line.
- a signal potential is written to the pixel electrode.
- a voltage corresponding to the digital image signal DA is applied to the liquid crystal layer of each pixel, and the amount of light transmitted from the backlight is controlled by applying the voltage, and an image indicated by the digital video signal Dv is displayed on the pixel.
- FIG. 46 is a block diagram showing a configuration of the present liquid crystal display device including the display units 10c, 10g, 10j, 10p, etc. (pixel division method).
- a CS control circuit is added to the configuration of FIG.
- the CS control circuit is a circuit for controlling the phase and cycle of the CS signal for controlling the potential of the storage capacitor wiring (CS wiring), and the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit. Is entered.
- an upper region and a lower region are provided in a display unit (non-pixel division method), and a data signal line, a scanning signal line, and a pixel are provided in each region.
- a configuration in which each region is individually driven may be employed.
- DA1 and DA2 are input from the display control circuit to the first and second source drivers, respectively.
- the first CS control circuit CSC1 corresponding to the upper region and the second CS control circuit CSC2 corresponding to the lower region are added to the configuration of FIG. 47, and the storage capacitor wiring in the upper region is controlled by the first CS control circuit CSC1.
- the storage capacitor wiring in the lower region is controlled by the second CS control circuit CSC2.
- the gate driver includes gate driver IC (Integrated Circuit) chips 411a, 411p,... 411q as a plurality of partial circuits including the shift register 40 (see FIG. 49B).
- each gate driver IC chip includes a shift register 40, first and second AND gates 42 and 43 provided corresponding to each stage of the shift register 40, .. Based on the output signal g (1)... Of the second AND gate 43.
- the output unit 45 outputs a scanning signal G (1). , And the output control signal OE.
- the start pulse signal SPi is applied to the input terminal of the shift register 40, and the start pulse signal SPo to be input to the subsequent gate driver IC chip is output from the output terminal of the shift register 40.
- a logic inversion signal of the clock signal CK is input to each first AND gate 41, while a logic inversion signal of the output control signal OE is input to each second AND gate 43.
- the output signal Qk (k 1%) Of each stage of the shift register 40 is input to the first AND gate 41 corresponding to the stage, and the output signal of the first AND gate 41 is the stage. Are input to the second AND gate 43 corresponding to.
- the gate driver is configured by cascading a plurality of gate driver IC chips 411a to 411q having the above configuration. That is, the output terminals of the shift registers in each gate driver IC chip (the output terminal of the start pulse signal SPo) are next so that the shift registers 40 in the gate driver IC chips 411a to 411q form one shift register.
- the input terminal of the shift register in the gate driver IC chip (the input terminal of the start pulse signal SPi) is connected.
- the gate start pulse signal GSP is input from the display control circuit to the shift register in the first gate driver IC chip 411a, and the shift register in the last gate driver IC chip 411q is not connected to the outside. ing.
- the gate clock signal GCK from the display control circuit is commonly input as a clock signal CK to each gate driver IC chip.
- the gate driver output control signal GOE generated in the display control circuit includes first to q-th gate driver output control signals GOE1 to GOEq. These gate driver output control signals GOE1 to GOEq are gate driver IC chips. (411a... 411q) are individually input as output control signals OE.
- FIG. 50 shows the configuration of the data rearrangement circuit 44 (see FIGS. 45 to 48) used in the present liquid crystal display device.
- the data rearrangement circuit 44 includes a rearrangement control circuit 61, a first line memory 51A, and a second line memory 51B.
- the rearrangement control circuit 61 serializes data for two lines (two pixel rows) input in parallel using the input signals Dv, HSY, VSY and Dc, and outputs for one horizontal scanning period (1H). Data.
- the rearrangement control circuit 61 temporarily writes each data of odd-numbered pixel rows to the first line memory 51A and once writes each data of the next row (even-numbered pixel rows) to the second line memory 51B.
- the data from which data is alternately read from the first line memory 51A and the second line memory 51B corresponds to the signal potential supplied to the first and second data signal lines.
- the source driver in this case is provided with a buffer 31, a data output switch SWa, and a refresh switch SWb corresponding to each data signal line.
- the corresponding data d is input to the buffer 31, and the output of the buffer 31 is connected to the output terminal to the data signal line via the data output switch SWa.
- the output terminals corresponding to the two adjacent data signal lines are connected to each other via the refresh switch SWb. That is, each refresh switch SWb is connected in series, and one end thereof is connected to the refresh potential supply source 35 (Vcom).
- LS latch strobe signal
- the LS signal is input to the gate terminal of the refresh switch SWb.
- the above configuration is suitable when the charge sharing of the refresh potential is relatively easy (the adjacent data signal lines do not have the same polarity, such as the display units 10b and 10f).
- FIG. 51A can be modified as shown in FIG. That is, the refresh switch SWc is connected only to the corresponding data signal line and the refresh potential supply source 35 (Vcom), and the refresh switches SWc are not connected in series. In this way, it is possible to quickly supply a refresh potential to each data signal line.
- This configuration is suitable for cases where it is relatively difficult to perform charge sharing of the refresh potential (display units 10a, 10e, 10k, etc. in which adjacent data signal lines have the same polarity).
- the refresh potential is Vcom, but the present invention is not limited to this.
- an appropriate refresh potential is calculated based on the potential level supplied to the same data signal line before one horizontal scanning period and the signal potential to be supplied during the current horizontal scanning period, and this refresh potential is used as the data signal. It may be supplied to the wire.
- FIG. 52 shows the configuration of the source driver in this case. In this configuration, a data output buffer 131, a refresh buffer 132, a data output switch SWa, and a refresh switch SWe are provided corresponding to each data signal line. The corresponding data d is input to the data output buffer 131, and the output of the data output buffer 131 is connected to the output terminal to the data signal line via the data output switch SWa.
- the refresh buffer 132 stores the corresponding non-image data N (data corresponding to the optimum refresh potential determined based on the potential level supplied before one horizontal scanning period and the signal potential to be supplied during the current horizontal scanning period. ) And the output of the refresh buffer 132 is connected to the output terminal to the data signal line via the refresh switch SWe.
- FIG. 54 is a block diagram showing a configuration of a liquid crystal display device 800 for a television receiver.
- the liquid crystal display device 800 includes a liquid crystal display unit 84, a Y / C separation circuit 80, a video chroma circuit 81, an A / D converter 82, a liquid crystal controller 83, a backlight drive circuit 85, a backlight 86, A microcomputer 87 and a gradation circuit 88 are provided.
- the liquid crystal display unit 84 includes a liquid crystal panel and a source driver and a gate driver for driving the liquid crystal panel.
- a composite color video signal Scv as a television signal is input from the outside to the Y / C separation circuit 80, where it is separated into a luminance signal and a color signal.
- These luminance signals and color signals are converted into analog RGB signals corresponding to the three primary colors of light by the video chroma circuit 81, and the analog RGB signals are further converted into digital RGB signals by the A / D converter 82. .
- This digital RGB signal is input to the liquid crystal controller 83.
- the Y / C separation circuit 80 also extracts horizontal and vertical synchronization signals from the composite color video signal Scv input from the outside, and these synchronization signals are also input to the liquid crystal controller 83 via the microcomputer 87.
- the liquid crystal display unit 84 receives a digital RGB signal from the liquid crystal controller 83 at a predetermined timing together with a timing signal based on the synchronization signal.
- the gradation circuit 88 generates gradation potentials for the three primary colors R, G, and B for color display, and these gradation potentials are also supplied to the liquid crystal display unit 84.
- the backlight drive is performed under the control of the microcomputer 87.
- the circuit 85 drives the backlight 86, so that light is irradiated to the back surface of the liquid crystal panel.
- the microcomputer 87 controls the entire system including the above processing.
- the video signal (composite color video signal) input from the outside includes not only a video signal based on television broadcasting but also a video signal captured by a camera, a video signal supplied via an Internet line, and the like.
- the liquid crystal display device 800 can display images based on various video signals.
- a tuner unit 90 is connected to the liquid crystal display device 800, thereby configuring the television receiver 601.
- the tuner unit 90 extracts a signal of a channel to be received from a received wave (high frequency signal) received by an antenna (not shown), converts the signal to an intermediate frequency signal, and detects the intermediate frequency signal, thereby detecting the television.
- a composite color video signal Scv as a signal is taken out.
- the composite color video signal Scv is input to the liquid crystal display device 800 as described above, and an image based on the composite color video signal Scv is displayed by the liquid crystal display device 800.
- FIG. 56 is an exploded perspective view showing a configuration example of the present television receiver.
- the present television receiver 601 includes a first casing 801 and a second casing 806 in addition to the liquid crystal display device 800 as its constituent elements. It is configured to be sandwiched between one housing 801 and a second housing 806.
- the first housing 801 is formed with an opening 801a through which an image displayed on the liquid crystal display device 800 is transmitted.
- the second housing 806 covers the back side of the liquid crystal display device 800, is provided with an operation circuit 805 for operating the display device 800, and a support member 808 is attached below. Yes.
- the potential of the storage capacitor line is controlled by a storage capacitor line signal supplied to the storage capacitor line.
- the potential (level) of the storage capacitor line can be read as the potential (level) of the storage capacitor line signal supplied to the storage capacitor line.
- the “potential polarity” indicates a potential equal to or lower than a reference potential
- the positive polarity indicates a potential higher than the reference potential
- the negative polarity indicates a potential lower than the reference potential.
- the reference potential may be Vcom (common potential) which is the potential of the common electrode (counter electrode) or any other potential.
- “potential polarity reversal” means that a level shift from a level lower than the reference potential to a reference potential or higher, or a level shift from a level higher than the reference potential to a reference potential or lower. It is shown.
- the reference potential may be Vcom (common potential) which is the potential of the common electrode (counter electrode) or any other potential. Therefore, “potential inversion (potential polarity) Can be rephrased as “potential level shift”.
- the liquid crystal panel and the liquid crystal display device of the present invention are suitable for a liquid crystal television, for example.
Abstract
Description
P(i,j) 画素
S1x 第1データ信号線
S2x 第1データ信号線
S1y 第2データ信号線
S2y 第2データ信号線
G1~G7 走査信号線
Cs1~Cs7 保持容量配線
PS1 PS2 画素列
PE 画素電極
PE1 第1画素電極
PE2 第2の画素電極
84 液晶表示ユニット
601 テレビジョン受像機
800 液晶表示装置
図1(a)は、本液晶表示装置の表示部の一構成例を示す模式図であり、図1(b)~(d)は該表示部の駆動方法を示す模式図であり、図2は、該駆動方法を示すタイミングチャートである。図1(a)に示すように、表示部10aには、1つの画素列(例えば、PS1)に対応して第1および第2データ信号線(例えば、S1x・S1y)が設けられ、該画素列に含まれる1つの画素(例えば、P(1,1))は1本の走査信号線(例えば、G1)に接続されるとともに第1および第2のデータ信号線(例えば、S1x・S1y)のいずれかに接続される。具体的には、各画素列の1行目の画素から、列方向に隣り合う2つの画素を順に対としていき、その順に順序を付して考えた場合に、各対の2つの画素が異なるデータ信号線に接続されるとともに、順序が連続する2つの対については、一方の対に含まれる奇数番目の画素が接続するデータ信号線と、他方の対に含まれる奇数番目の画素が接続するデータ信号線とが同一となっている。すなわち、1つの画素列において、2行目以降の各画素は、前段の画素と異なるデータ信号線に接続される。なお、各画素においては、画素電極PEがトランジスタ(TFT)を介して1本のデータ信号線に接続され、該トランジスタのゲート端子は1本の走査信号線に接続されている。
図13(a)は、本液晶表示装置の表示部の一構成例を示す模式図であり、図13(b)~(d)は該表示部の駆動方法を示す模式図であり、図14は、該駆動方法を示すタイミングチャートである。図13(a)に示すように、表示部10eには、1つの画素列(例えば、PS1)に対応して第1および第2データ信号線(例えば、S1x・S1y)が設けられ、該画素列に含まれる1つの画素(例えば、P(1,1))は1本の走査信号線(例えば、G1)に接続されるとともに第1および第2のデータ信号線(例えば、S1x・S1y)のいずれかに接続される。具体的には、各画素列の1行目の画素から、列方向に隣り合う2つの画素を順に対としていき、その順に順序を付して考えた場合に、各対の2つの画素が異なるデータ信号線に接続されるとともに、順序が連続する2つの対については、一方の対に含まれる奇数番目の画素が接続するデータ信号線と、他方の対に含まれる奇数番目の画素が接続するデータ信号線とが異なっている。すなわち、1行目の画素を数え始めの1番目の画素とし、走査方向に数えて2×1×i+1番目(iは自然数)の画素以外は前段の画素と異なるデータ信号線に接続される一方、2×1×i+1番目の画素は前段の画素と同じデータ信号線に接続される。なお、各画素においては、画素電極PEがトランジスタ(TFT)を介して1本のデータ信号線に接続され、該トランジスタのゲート端子は1本の走査信号線に接続されている。
図25(a)は、本液晶表示装置の表示部の一構成例を示す模式図であり、図25(b)~(d)は該表示部の駆動方法を示す模式図であり、図26は、該駆動方法を示すタイミングチャートである。図25(a)に示すように、表示部10iには、1つの画素列(例えば、PS1)に対応して第1および第2データ信号線(例えば、S1x・S1y)が設けられ、該画素列に含まれる1つの画素(例えば、P(1,1))は1本の走査信号線(例えば、G1)に接続されるとともに第1および第2のデータ信号線(例えば、S1x・S1y)のいずれかに接続される。具体的には、各画素列の1行目の画素から、列方向に隣り合う2つの画素を順に対とするとともに、隣り合う2個の対を順に1グループとしていき、その順に順序を付して考えた場合に、同一のグループでは、各対の2つの画素が異なるデータ信号線に接続されるとともに、奇数番目の各画素が同一のデータ信号線に接続されており、上記順序が連続する2つのグループ間では、一方のグループに含まれる奇数番目の画素が接続するデータ信号線と、他方のグループに含まれる奇数番目の画素が接続するデータ信号線とが異なっている。すなわち、1行目の画素を数え始めの1番目の画素とし、走査方向に数えて2×2×i+1番目(iは自然数)の画素以外は前段の画素と異なるデータ信号線に接続される一方、2×2×i+1番目の画素は前段の画素と同じデータ信号線に接続される。なお、各画素においては、画素電極PEがトランジスタ(TFT)を介して1本のデータ信号線に接続され、該トランジスタのゲート端子は1本の走査信号線に接続されている。
図33(a)は、本液晶表示装置の表示部の一構成例を示す模式図であり、図33(b)~(e)は該表示部の駆動方法を示す模式図であり、図34は、該駆動方法を示すタイミングチャートである。図33(a)に示すように、表示部10kでは、1つの画素列(例えば、PS1)に対応して、その(例えば、PS1の)両側に第1および第2データ信号線(例えば、S1a・S1b)が設けられ、該画素列に含まれる1つの画素(例えば、P(1,1))は1本の走査信号線(例えば、G1)に接続されるとともに第1および第2のデータ信号線(例えば、S1a・S1b)のいずれかに接続される。具体的には、各画素列の1行目の画素を数え始めの1番目の画素とし、走査方向に数えて連続する奇数番目にあたる2画素を順に対としていくとともに連続する偶数番目にあたる2画素を対としていき、奇数番目にあたる2つの画素からなる対と、偶数番目にあたる2つの画素からなる対とを交互に順序付けて考えた場合に、各対の2つの画素が異なるデータ信号線に接続される。なお、各画素においては、画素電極PEがトランジスタ(TFT)を介して1本のデータ信号線に接続され、該トランジスタのゲート端子は1本の走査信号線に接続されている。
上記各実施の形態では、1つの画素列に対応して、その両側に第1および第2データ信号線が設けられているが、これに限定されない。例えば、図53のように、1つの画素列に対応して、該画素列の一方の側に第1データ信号線(例えば、S1xやS1a)が設けられ、該画素列と重なるように第2データ信号線(例えば、S1yやS1b)が設けられていてもよい。こうすれば、データ信号線同士を離すことができ、これらの間に生じる寄生容量を低減することができる。また、こうすれば、画素列の両側に該画素列に対応するデータ信号線を配置する構成に比べてデータ信号線同士の距離を広く保つことができる。これにより、データ信号線同士の短絡率を減少させることができ、製造歩留まりを高めることができる。なお、この構成では、データ信号線と各画素の画素電極とが重なるため、データ信号線上の層間絶縁膜を厚くしておく(例えば、該層間絶縁膜に有機絶縁膜を用いる)ことが望ましい。
Claims (35)
- 走査信号線の延伸方向を行方向とすれば、行および列方向に並ぶ画素を備えた液晶表示装置であって、
1つの画素列に対応して第1および第2のデータ信号線が設けられ、該画素列に含まれる1つの画素は1本の走査信号線に接続されるとともに第1および第2のデータ信号線のいずれかに接続され、第1および第2のデータ信号線には互いに逆極性の信号電位が供給され、
上記画素列の所定画素を数え始めの1番目の画素とし、走査方向に数えて奇数番目の1画素と偶数番目の1画素とを対とするとともにn個(nは自然数)の対を1グループとし、各グループに順序を付して考えた場合に、
同一のグループでは、対をなす2つの画素が異なるデータ信号線に接続されるとともに奇数番目の画素全てが1本のデータ信号線に接続されており、
上記順序が連続する2つのグループ間では、一方のグループに含まれる奇数番目の画素が接続するデータ信号線と、他方のグループに含まれる奇数番目の画素が接続するデータ信号線とが異なっていることを特徴とする液晶表示装置。 - 各データ信号線に供給される信号電位の極性がn水平走査期間ごとに反転することを特徴とする請求項1記載の液晶表示装置。
- 上記順序に従ってグループが選ばれ、選ばれたグループ内で、対をなす2つの画素それぞれに接続する走査信号線の同時選択が行われ、nが2以上の場合にはこの同時選択が各対につき順次行われることを特徴とする請求項1記載の液晶表示装置。
- 走査信号線の延伸方向を行方向とすれば、行および列方向に並ぶ画素を備えた液晶表示装置であって、
1つの画素列に対応して第1および第2のデータ信号線が設けられ、該画素列に含まれる1つの画素は1本の走査信号線に接続されるとともに第1および第2のデータ信号線のいずれかに接続され、第1および第2のデータ信号線には互いに逆極性の信号電位が供給され、
上記画素列の所定画素を数え始めの1番目の画素とし、走査方向に数えて奇数番目の1画素と偶数番目の1画素とを対として各対に順序を付して考えた場合に、
対をなす2つの画素が異なるデータ信号線に接続されており、
順序が連続する2つの対については、一方の対に含まれる奇数番目の画素が接続するデータ信号線と、他方の対に含まれる奇数番目の画素が接続するデータ信号線とが同一であることを特徴とする液晶表示装置。 - 各データ信号線に供給される信号電位の極性が1垂直走査期間ごとに反転することを特徴とする請求項4記載の液晶表示装置。
- 対をなす2つの画素それぞれに接続する走査信号線の同時選択が、上記順序に従って各対につき行われることを特徴とする請求項4記載の液晶表示装置。
- 1つの画素行に含まれる各画素は同一の走査信号線に接続され、隣接する2つの画素列の一方に対応する第1のデータ信号線と、該2つの画素列の他方に対応する第1のデータ信号線とには同極性の信号電位が供給され、行方向に隣り合う画素間では、第1および第2のデータ信号線との接続関係が逆になっていることを特徴とする請求項1~6のいずれか1項に記載の液晶表示装置。
- 1つの画素列の両側に該画素列に対応する第1および第2のデータ信号線が配され、隣接する2つの画素列の一方に対応する第1のデータ信号線と該2つの画素列の他方に対応する第2のデータ信号線とが画素列を挟むことなく隣接するか、あるいは該2つの画素列の一方に対応する第2のデータ信号線と該2つの画素列の他方に対応する第1のデータ信号線とが画素列を挟むことなく隣接していることを特徴とする請求項7記載の液晶表示装置。
- 1つの画素列の両側に該画素列に対応する第1および第2のデータ信号線が配され、隣接する2つの画素列の一方に対応する第1のデータ信号線と該2つの画素列の他方に対応する第1のデータ信号線とが画素列を挟むことなく隣接するか、あるいは該2つの画素列の一方に対応する第2のデータ信号線と該2つの画素列の他方に対応する第2のデータ信号線とが画素列を挟むことなく隣接していることを特徴とする請求項7記載の液晶表示装置。
- 対をなす2つの画素が隣接していることを特徴とする請求項1記載の液晶表示装置。
- 2×n×i+1番目(iは自然数)の画素以外は前段の画素と異なるデータ信号線に接続される一方、2×n×i+1番目の画素は前段の画素と同じデータ信号線に接続され、
走査信号線が、所定画素に接続する走査信号線から順に、隣り合う2本ずつ同時選択されていくことを特徴とする請求項10記載の液晶表示装置。 - n=1であることを特徴とする請求項1に記載の液晶表示装置。
- 対をなす2つの画素が隣接していることを特徴とする請求項4記載の液晶表示装置。
- 上記所定画素よりも走査方向側に位置する各画素は、前段の画素と異なるデータ信号線に接続され、
走査信号線は、所定画素に接続する走査信号線から順に、隣り合う2本ずつ同時選択されていくことを特徴とする請求項13記載の液晶表示装置。 - 走査信号線の延伸方向を行方向とすれば、行および列方向に並ぶ画素を備えた液晶表示装置であって、
1つの画素列に対応して第1および第2のデータ信号線が設けられ、該画素列に含まれる1つの画素は1本の走査信号線に接続されるとともに第1および第2のデータ信号線のいずれかに接続され、第1および第2のデータ信号線には互いに同極性の信号電位が供給され、
上記画素列の所定画素を数え始めの1番目の画素とし、走査方向に数えて奇数番目にあたる2画素を対とするとともに偶数番目にあたる2画素を対とし、奇数番目にあたる2画素からなる対をn個(nは自然数)含むグループと、偶数番目にあたる2画素からなる対をn個含むグループとを交互に順序付けて考えた場合に、
対をなす2つの画素が異なるデータ信号線に接続され、各データ信号線に供給される信号電位の極性がn水平走査期間ごとに反転することを特徴とする液晶表示装置。 - 上記順序に従ってグループが選ばれ、選ばれたグループ内で、対をなす2つの画素それぞれに接続する走査信号線の同時選択が行われ、nが2以上の場合にはこの同時選択が各対につき順次行われることを特徴とする請求項15記載の液晶表示装置。
- 隣り合う2つの画素列の一方に対応する第1および第2のデータ信号線に供給される信号電位の極性と、該2つの画素列の他方に対応する第1および第2のデータ信号線に供給される信号電位の極性とが異なっていることを特徴とする請求項15記載の液晶表示装置。
- 対をなす2つの画素は、連続する2つの奇数番目にあたるか、あるいは連続する2つの偶数番目にあたることを特徴とする請求項15記載の液晶表示装置。
- 電位制御可能な保持容量配線を複数備え、上記1つの画素には、第1および第2のトランジスタと、第1および第2の画素電極とが含まれ、該第1および第2の画素電極はそれぞれ、第1および第2のトランジスタを介して同一のデータ信号線に接続され、上記第1および第2のトランジスタは上記1本の走査信号線に接続され、上記第1および第2の画素電極は、それぞれ異なる保持容量配線と保持容量を形成し、
該第1および第2の画素電極と保持容量を形成する2本の保持容量配線それぞれの電位は、第1および第2のトランジスタに接続する走査信号線の走査終了に同期してあるいはその後に、互いに逆向きにレベルシフトすることを特徴とする請求項1~18のいずれか1項に記載の液晶表示装置。 - 列方向に隣り合う2つの画素に対応して1本の保持容量配線が設けられ、上記2つの画素の一方に設けられた第1あるいは第2の画素電極と上記2つの画素領域の他方に設けられた第1あるいは第2の画素電極とが、この保持容量配線と保持容量を形成していることを特徴とする請求項19記載の液晶表示装置。
- 上記第1および第2のデータ信号線には、各水平走査期間において、予備電位が供給された後に上記信号電位が供給されることを特徴とする請求項1~20のいずれか1項に記載の液晶表示装置。
- 上記予備電位が一定値となっていることを特徴とする請求項21記載の液晶表示装置。
- 上記一定値が信号電位のレンジの中央値であることを特徴とする請求項22に記載の液晶表示装置。
- 上記予備電位が、一水平走査期間前に同一データ信号線に供給された信号電位と現水平走査期間の信号電位とに基づいて決定された値となっていることを特徴とする請求項20記載の液晶表示装置。
- 走査信号線の走査期間と走査期間との間に、上記予備電位の供給タイミングに合わせた中途選択期間が設けられ、この中途選択期間に、該走査信号線に接続する画素へ上記予備電位が書き込まれることを特徴とする請求項21記載の液晶表示装置。
- 上記第1および第2のデータ信号線の一方が上記画素列の一方の側に配されるとともに、他方が上記画素列と重なるように配されていることを特徴とする請求項1、4、15のいずれか1項に記載の液晶表示装置。
- 同時選択される各走査信号線は、液晶パネル内で接続されるか、あるいは走査信号線を駆動するゲートドライバの同一出力端子に接続されていることを特徴とする請求項3、6、16のいずれか1項に記載の液晶表示装置。
- 表示部に複数の領域が設けられるとともに、各領域に上記データ信号線および走査信号線並びに画素が設けられ、これらが領域ごとに個別駆動されることを特徴とする請求項1~27のいずれか1項に記載の液晶表示装置。
- 1秒間に表示するコマ数が60よりも多いことを特徴とする請求項1~28のいずれか1項に記載の液晶表示装置。
- 電位制御可能な複数の保持容量配線を備え、各画素には、第1および第2トランジスタと、第1および第2画素電極とが含まれ、該第1および第2画素電極は、それぞれ第1および第2トランジスタを介して同一のデータ信号線に接続され、上記第1および第2トランジスタは同一の走査信号線に接続され、上記第1および第2画素電極は異なる保持容量配線と保持容量を形成し、
上記画素列の隣り合う2つの画素に対応して1本の保持容量配線が設けられ、上記2つの画素の一方に設けられたいずれかの画素電極と他方に設けられたいずれかの画素電極とが、この2つの画素に対応する1本の保持容量配線と保持容量を形成しており、
1番目の画素の各画素電極と保持容量を形成する保持容量配線が1番目および2番目の保持容量配線であり、2番目の保持容量配線は、2番目の画素のいずかの画素電極とも保持容量を形成しており、1番目および2番目の画素の書き込み終了時あるいはその後に、1番目および2番目の保持容量配線の電位が同期して逆向きにレベルシフトし、
1番目の保持容量配線を数え始めとして走査方向に数え、連続する2つの奇数番目にあたる保持容量配線間では、前番となる保持容量配線の電位のレベルシフトから1水平走査期間後に、後番となる保持容量配線の電位がこれと同じ向きにレベルシフトし、連続する2つの偶数番目にあたる保持容量配線間では、前番となる保持容量配線の電位のレベルシフトから1水平走査期間後に、後番となる保持容量配線の電位がこれと同じ向きにレベルシフトすることを特徴とする請求項11または14に記載の液晶表示装置。 - 電位制御可能な複数の保持容量配線を備え、各画素には、第1および第2トランジスタと、第1および第2画素電極とが含まれ、該第1および第2画素電極は、それぞれ第1および第2トランジスタを介して同一のデータ信号線に接続され、上記第1および第2トランジスタは同一の走査信号線に接続され、上記第1および第2画素電極は異なる保持容量配線と保持容量を形成し、
上記画素列の隣り合う2つの画素に対応して1本の保持容量配線が設けられ、上記2つの画素の一方に設けられたいずれかの画素電極と他方に設けられたいずれかの画素電極とが、この2つの画素に対応する1本の保持容量配線と保持容量を形成しており、
1番目の画素の各画素電極と保持容量を形成する保持容量配線が1番目および2番目の保持容量配線であり、2番目の保持容量配線は、2番目の画素のいずれかの画素電極とも保持容量を形成しており、
1番目の画素の各画素電極と保持容量を形成する保持容量配線が1番目および2番目の保持容量配線であり、2番目の保持容量配線は2番目の画素のいずれかの画素電極とも保持容量を形成しており、1番目および2番目の画素の書き込み終了時あるいはその後に、1番目および2番目の保持容量配線の電位が同期して逆向きにレベルシフトし、
1番目の保持容量配線を数え始めとして走査方向に数え、奇数番目の保持容量配線を2本ずつ束にして考えた場合に、各束では、2本の保持容量配線の電位が同期して同じ向きにレベルシフトし、隣り合う2つの束間では、走査方向上流側に位置する束の各保持容量配線の電位がレベルシフトした2水平走査期間後に、走査方向下流側に位置する束の各保持容量配線の電位がレベルシフトし、
偶数番目の保持容量配線を2本ずつ束にして考えた場合に、各束では、2本の保持容量配線の電位が同期して同じ向きにレベルシフトし、隣り合う2つの束間では、走査方向上流側に位置する束の各保持容量配線の電位がレベルシフトした2水平走査期間後に、走査方向下流側に位置する束の各保持容量配線の電位がレベルシフトすることを特徴とする請求項18に記載の液晶表示装置。 - 走査信号線の延伸方向を行方向とすれば、行および列方向に並ぶ画素を備え、1つの画素列に対応して第1および第2のデータ信号線が設けられ、該画素列に含まれる1つの画素は1本の走査信号線に接続されるとともに第1および第2のデータ信号線のいずれかに接続され、上記画素列の所定画素を数え始めの1番目の画素とし、走査方向に数えて奇数番目の1画素と偶数番目の1画素とを対とするとともにn個(nは自然数)の対を1グループとし、各グループに順序を付して考えた場合に、同一のグループでは、対をなす2つの画素が異なるデータ信号線に接続されるとともに奇数番目の画素全てが1本のデータ信号線に接続されており、順序が連続する2つのグループ間では、一方のグループに含まれる奇数番目の画素が接続するデータ信号線と、他方のグループに含まれる奇数番目の画素が接続するデータ信号線とが異なっている液晶表示装置に対して、
第1および第2のデータ信号線に互いに逆極性の信号電位を供給するとともに、各データ信号線に供給される信号電位の極性をn水平走査期間ごとに反転させ、かつ上記順序に従ってグループを選ぶとともに、選んだグループ内で、対をなす2つの画素それぞれに接続する走査信号線の同時選択を行い、nが2以上の場合にはこの同時選択を各対につき順次行うことを特徴とする液晶表示装置の駆動方法。 - 走査信号線の延伸方向を行方向とすれば、行および列方向に並ぶ画素を備え、1つの画素列に対応して第1および第2のデータ信号線が設けられ、該画素列に含まれる1つの画素は1本の走査信号線に接続されるとともに第1および第2のデータ信号線のいずれかに接続され、上記画素列の所定画素を数え始めの1番目の画素とし、走査方向に数えて奇数番目の1画素と偶数番目の1画素とを対として各対に順序を付して考えた場合に、対をなす2つの画素が異なるデータ信号線に接続されるとともに、上記順序が連続する2つの対については、一方の対に含まれる奇数番目の画素が接続するデータ信号線と、他方の対に含まれる奇数番目の画素が接続するデータ信号線とが同一である液晶表示装置に対し、
第1および第2のデータ信号線に、互いに逆極性の信号電位を供給するとともに、各データ信号線に供給される信号電位の極性を1垂直走査期間ごとに反転させ、かつ対をなす2つの画素それぞれに接続する走査信号線の同時選択を、上記順序に従って各対につき行うことを特徴とする液晶表示装置の駆動方法。 - 走査信号線の延伸方向を行方向とすれば、行および列方向に並ぶ画素を備え、1つの画素列に対応して第1および第2のデータ信号線が設けられ、該画素列に含まれる1つの画素は1本の走査信号線に接続されるとともに第1および第2のデータ信号線のいずれかに接続され、上記画素列の所定画素を数え始めの1番目の画素とし、走査方向に数えて奇数番目にあたる2画素を対とするとともに偶数番目にあたる2画素を対とし、奇数番目にあたる2画素からなる対をn個含むグループと、偶数番目にあたる2画素からなる対をn個含むグループとを交互に順序付けて考えた場合に、対をなす2つの画素が異なるデータ信号線に接続された液晶表示装置に対し、
第1および第2のデータ信号線に、互いに同極性の信号電位を供給するとともに、各データ信号線に供給される信号電位の極性をn水平走査期間(nは自然数)ごとに反転させ、かつ上記順序に従ってグループを選ぶとともに、選んだグループ内で、対をなす2つの画素それぞれに接続する走査信号線の同時選択を行い、nが2以上の場合にはこの同時選択を各対につき順次行うことを特徴とする液晶表示装置の駆動方法。 - 請求項1~31のいずれか1項に記載の液晶表示装置と、テレビジョン放送を受信するチューナー部とを備えることを特徴とするテレビジョン受像機。
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Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011099217A1 (ja) * | 2010-02-15 | 2011-08-18 | シャープ株式会社 | アクティブマトリクス基板、液晶パネル、液晶表示装置、テレビジョン受像機 |
JP2011186362A (ja) * | 2010-03-11 | 2011-09-22 | Seiko Epson Corp | 電気光学装置及び電子機器 |
CN102201205A (zh) * | 2010-03-23 | 2011-09-28 | 深圳华映显示科技有限公司 | 一种液晶显示装置的驱动方法 |
WO2011125459A1 (ja) * | 2010-04-02 | 2011-10-13 | シャープ株式会社 | 表示装置およびその駆動方法 |
WO2011162288A1 (ja) * | 2010-06-25 | 2011-12-29 | シャープ株式会社 | 液晶装置及び液晶制御方法 |
US20120033057A1 (en) * | 2008-05-29 | 2012-02-09 | Seiko Epson Corporation | Electro-optic device and stereoscopic vision display apparatus |
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WO2012157651A1 (ja) * | 2011-05-18 | 2012-11-22 | シャープ株式会社 | 液晶表示装置、液晶表示装置の駆動方法、及びテレビジョン受像機 |
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US8816350B2 (en) | 2009-03-13 | 2014-08-26 | Sharp Kabushiki Kaisha | Array substrate, liquid crystal panel, liquid crystal display device, and television receiver |
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US10657909B2 (en) | 2015-10-22 | 2020-05-19 | Sharp Kabushiki Kaisha | Liquid crystal display panel and method for driving same |
WO2020171130A1 (ja) * | 2019-02-22 | 2020-08-27 | ソニーセミコンダクタソリューションズ株式会社 | 制御回路、表示装置、電子機器、投射型表示装置および制御方法 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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KR101192583B1 (ko) * | 2010-10-28 | 2012-10-18 | 삼성디스플레이 주식회사 | 액정 표시 패널, 액정 표시 장치 및 액정 표시 장치의 구동 방법 |
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WO2012157725A1 (ja) * | 2011-05-18 | 2012-11-22 | シャープ株式会社 | 液晶表示装置 |
JP5780054B2 (ja) | 2011-08-24 | 2015-09-16 | セイコーエプソン株式会社 | 電気光学装置および電子機器 |
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US20140247259A1 (en) * | 2011-09-06 | 2014-09-04 | Sharp Kabushiki Kaisha | Liquid crystal display device, and drive method for liquid crystal panel |
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US8665264B2 (en) | 2011-11-23 | 2014-03-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | LCD panel and LCD device |
JP2013114143A (ja) * | 2011-11-30 | 2013-06-10 | Seiko Epson Corp | 電気光学装置および電子機器 |
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US9311871B2 (en) * | 2012-09-26 | 2016-04-12 | Apple Inc. | Devices and methods for reducing power to drive pixels of a display |
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WO2016024307A1 (ja) * | 2014-08-11 | 2016-02-18 | 日立マクセル株式会社 | 映像出力装置、表示装置、および映像表示システム |
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CN109658897B (zh) * | 2019-02-27 | 2020-12-22 | 惠科股份有限公司 | 显示驱动方法及显示装置 |
US11495172B2 (en) * | 2020-10-19 | 2022-11-08 | X Display Company Technology Limited | Pixel group and column token display architectures |
US11488518B2 (en) * | 2020-10-19 | 2022-11-01 | X Display Company Technology Limited | Pixel group and column token display architectures |
CN112433413B (zh) * | 2020-11-26 | 2022-07-12 | 深圳市华星光电半导体显示技术有限公司 | 液晶显示器及其串扰消除方法 |
US11430375B1 (en) | 2021-03-19 | 2022-08-30 | X Display Company Technology Limited | Pulse-density-modulation pixel control circuits and devices including them |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10253987A (ja) | 1997-03-11 | 1998-09-25 | Matsushita Electric Ind Co Ltd | 液晶表示装置 |
JP2004233949A (ja) * | 2002-12-03 | 2004-08-19 | Sharp Corp | 液晶表示装置 |
JP2005031202A (ja) * | 2003-07-08 | 2005-02-03 | Sharp Corp | 容量性負荷の駆動回路および駆動方法 |
JP2006106062A (ja) * | 2004-09-30 | 2006-04-20 | Sharp Corp | アクティブマトリクス型液晶表示装置およびそれに用いる液晶表示パネル |
JP2007256540A (ja) * | 2006-03-22 | 2007-10-04 | Sharp Corp | 液晶表示装置の検査方法、及び液晶表示装置 |
JP2007298769A (ja) * | 2006-04-28 | 2007-11-15 | Sharp Corp | 表示装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0622772B1 (en) * | 1993-04-30 | 1998-06-24 | International Business Machines Corporation | Method and apparatus for eliminating crosstalk in active matrix liquid crystal displays |
JP4242963B2 (ja) * | 1999-02-10 | 2009-03-25 | 三洋電機株式会社 | カラー液晶表示装置 |
JP3365357B2 (ja) * | 1999-07-21 | 2003-01-08 | 日本電気株式会社 | アクティブマトリクス型液晶表示装置 |
KR100442304B1 (ko) * | 2000-07-07 | 2004-08-04 | 가부시끼가이샤 도시바 | 액정 표시 방법 |
KR100367015B1 (ko) * | 2000-12-29 | 2003-01-09 | 엘지.필립스 엘시디 주식회사 | 액정 표시장치의 구동방법 |
JP4218249B2 (ja) * | 2002-03-07 | 2009-02-04 | 株式会社日立製作所 | 表示装置 |
KR100890022B1 (ko) * | 2002-07-19 | 2009-03-25 | 삼성전자주식회사 | 액정 표시 장치 및 그 구동 방법 |
JP4265788B2 (ja) * | 2003-12-05 | 2009-05-20 | シャープ株式会社 | 液晶表示装置 |
JP4197322B2 (ja) * | 2004-01-21 | 2008-12-17 | シャープ株式会社 | 表示装置,液晶モニター,液晶テレビジョン受像機および表示方法 |
KR100698983B1 (ko) * | 2004-03-30 | 2007-03-26 | 샤프 가부시키가이샤 | 표시 장치 및 구동 장치 |
US20060044241A1 (en) * | 2004-08-31 | 2006-03-02 | Vast View Technology Inc. | Driving device for quickly changing the gray level of the liquid crystal display and its driving method |
TWI303407B (en) * | 2004-12-24 | 2008-11-21 | Innolux Display Corp | Driving circuit of display and method of driving the circuit |
KR101187207B1 (ko) * | 2005-08-04 | 2012-10-02 | 삼성디스플레이 주식회사 | 디스플레이장치 |
KR101189277B1 (ko) * | 2005-12-06 | 2012-10-09 | 삼성디스플레이 주식회사 | 액정 표시 장치 |
WO2007099673A1 (ja) * | 2006-02-28 | 2007-09-07 | Sharp Kabushiki Kaisha | 表示装置およびその駆動方法 |
US7852446B2 (en) * | 2006-09-18 | 2010-12-14 | Samsung Electronics Co., Ltd. | Liquid crystal display and method of driving the same |
-
2008
- 2008-11-11 US US12/735,033 patent/US20100253668A1/en not_active Abandoned
- 2008-11-11 JP JP2009547954A patent/JP5512284B2/ja active Active
- 2008-11-11 CN CN200880122156XA patent/CN101903938B/zh not_active Expired - Fee Related
- 2008-11-11 WO PCT/JP2008/070491 patent/WO2009084331A1/ja active Application Filing
- 2008-11-11 EP EP08867439A patent/EP2237257A4/en not_active Withdrawn
- 2008-11-11 EP EP12162005A patent/EP2472503A3/en not_active Withdrawn
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10253987A (ja) | 1997-03-11 | 1998-09-25 | Matsushita Electric Ind Co Ltd | 液晶表示装置 |
JP2004233949A (ja) * | 2002-12-03 | 2004-08-19 | Sharp Corp | 液晶表示装置 |
JP2005031202A (ja) * | 2003-07-08 | 2005-02-03 | Sharp Corp | 容量性負荷の駆動回路および駆動方法 |
JP2006106062A (ja) * | 2004-09-30 | 2006-04-20 | Sharp Corp | アクティブマトリクス型液晶表示装置およびそれに用いる液晶表示パネル |
JP2007256540A (ja) * | 2006-03-22 | 2007-10-04 | Sharp Corp | 液晶表示装置の検査方法、及び液晶表示装置 |
JP2007298769A (ja) * | 2006-04-28 | 2007-11-15 | Sharp Corp | 表示装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2237257A4 |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120033057A1 (en) * | 2008-05-29 | 2012-02-09 | Seiko Epson Corporation | Electro-optic device and stereoscopic vision display apparatus |
US9843791B2 (en) | 2008-05-29 | 2017-12-12 | Seiko Epson Corporation | Electro-optic device and stereoscopic vision display apparatus |
US9577794B2 (en) * | 2008-05-29 | 2017-02-21 | Seiko Epson Corporation | Electro-optic device and stereoscopic vision display apparatus |
CN102378027A (zh) * | 2008-05-29 | 2012-03-14 | 精工爱普生株式会社 | 电光装置以及立体观看显示装置 |
US8816350B2 (en) | 2009-03-13 | 2014-08-26 | Sharp Kabushiki Kaisha | Array substrate, liquid crystal panel, liquid crystal display device, and television receiver |
CN102725676A (zh) * | 2010-01-29 | 2012-10-10 | 夏普株式会社 | 液晶显示装置 |
US9818348B2 (en) | 2010-01-29 | 2017-11-14 | Sharp Kabushiki Kaisha | Liquid crystal display device |
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JP5540020B2 (ja) * | 2010-01-29 | 2014-07-02 | シャープ株式会社 | 液晶表示装置 |
JP5619787B2 (ja) * | 2010-02-15 | 2014-11-05 | シャープ株式会社 | アクティブマトリクス基板、液晶パネル、液晶表示装置、テレビジョン受像機 |
WO2011099217A1 (ja) * | 2010-02-15 | 2011-08-18 | シャープ株式会社 | アクティブマトリクス基板、液晶パネル、液晶表示装置、テレビジョン受像機 |
US9076394B2 (en) | 2010-02-15 | 2015-07-07 | Sharp Kabushiki Kaisha | Active matrix substrate, liquid crystal panel, liquid crystal display device, television receiver |
JP2011186362A (ja) * | 2010-03-11 | 2011-09-22 | Seiko Epson Corp | 電気光学装置及び電子機器 |
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Also Published As
Publication number | Publication date |
---|---|
CN101903938A (zh) | 2010-12-01 |
JP5512284B2 (ja) | 2014-06-04 |
US20100253668A1 (en) | 2010-10-07 |
JPWO2009084331A1 (ja) | 2011-05-12 |
EP2237257A1 (en) | 2010-10-06 |
EP2472503A2 (en) | 2012-07-04 |
CN101903938B (zh) | 2013-09-04 |
EP2237257A4 (en) | 2011-09-21 |
EP2472503A3 (en) | 2012-08-01 |
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