WO2022007059A1 - Goa电路、显示面板和显示装置 - Google Patents

Goa电路、显示面板和显示装置 Download PDF

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Publication number
WO2022007059A1
WO2022007059A1 PCT/CN2020/105769 CN2020105769W WO2022007059A1 WO 2022007059 A1 WO2022007059 A1 WO 2022007059A1 CN 2020105769 W CN2020105769 W CN 2020105769W WO 2022007059 A1 WO2022007059 A1 WO 2022007059A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
gate
circuit
signal input
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Application number
PCT/CN2020/105769
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English (en)
French (fr)
Inventor
陶健
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/979,234 priority Critical patent/US11238823B1/en
Publication of WO2022007059A1 publication Critical patent/WO2022007059A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the field of display technology, and in particular, to a GOA circuit, a display panel and a display device.
  • GOA Gate Driver On Array, array substrate row drive
  • the gate line scanning driving signal circuit is fabricated on the array substrate to realize the driving method of line-by-line scanning of the gate.
  • the number of lines scanned is also increasing, and the probability of grading errors is also increasing.
  • users may experience abnormal interruptions during the operation of the liquid crystal display device. In the case of electricity, if the display area is not scanned and reset after the power is turned off, it will cause abnormal display due to residual charge.
  • the existing GOA circuit with a black sweeping module has high requirements on the thin film transistors in the black sweeping module, and the effect of setting the gate high is not good.
  • the effect of sweeping black has potential risks to the taste of the picture.
  • the present application provides a GOA circuit, a display panel and a display device to alleviate the technical problem that the existing GOA circuit cannot guarantee the black sweeping effect.
  • the application provides a drive circuit
  • the drive circuit includes a plurality of cascaded drive units, each of the drive units specifically includes a pull-up control circuit, a pull-down circuit, a pull-down hold circuit, a bootstrap circuit, a discharge circuit and a reset circuit
  • the pull-up control circuit is connected to the pull-down circuit
  • the pull-down hold circuit is also connected to the pull-down circuit
  • the pull-down hold circuit the bootstrap circuit
  • the circuit, the discharge circuit and the reset circuit are all connected to the gate drive signal output end of the current stage
  • the pull-up control circuit is also connected to the gate drive signal input end of the previous stage:
  • the discharge circuit includes a twelfth thin film transistor and a fourteenth thin film transistor, the gate of the fourteenth thin film transistor is connected to the constant voltage high-level signal input terminal, and the source and drain are respectively connected to the first global
  • the control signal input terminal is connected to the gate of the twelfth thin film transistor, and the source and drain of the twelfth thin film transistor are respectively connected to the first global control signal input terminal and the gate driving signal of the current stage
  • the output terminal is connected, wherein, when the signal input from the first global control signal input terminal is high level, the voltage of the gate of the twelfth thin film transistor is greater than the voltage of the constant voltage high level signal input terminal, so that The discharge circuit is fully discharged.
  • the pull-up control circuit includes a third thin film transistor and a first capacitor, the gate of the third thin film transistor is connected to the input terminal of the gate driving signal of the previous stage, and the source and the The drain is respectively connected with the forward scanning DC control signal input end and the bootstrap circuit, and the two ends of the first capacitor are respectively connected with the constant voltage low level signal input end and the bootstrap circuit.
  • the gate of the third thin film transistor is connected to the input terminal of the scan start signal.
  • the bootstrap circuit includes a sixth thin film transistor and an eighth thin film transistor, the gate of the sixth thin film transistor is connected to the constant voltage high-level signal input terminal, the source and drain The poles are respectively connected to the pull-up control circuit and the gate of the eighth thin film transistor, and the source and drain of the eighth thin film transistor are respectively connected to the clock signal input terminal of this stage and the gate driving signal of this stage
  • the output terminal is connected, wherein the bootstrap circuit is used to control the gate drive signal output terminal of the current stage to output the gate of the current stage when the clock signal of the current stage inputted by the clock signal input terminal of the current stage is a constant voltage high level pole drive signal.
  • the pull-down circuit includes a first thin film transistor, a second thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a ninth thin film transistor, and the gate of the first thin film transistor is connected to the
  • the forward scanning DC control signal input terminal is connected to the source and the drain are respectively connected to the next stage clock signal input terminal and the gate of the fifth thin film transistor;
  • the gate of the second thin film transistor is connected to the reverse scanning DC
  • the control signal input end is connected, the source electrode and the drain electrode are respectively connected with the clock signal input end of the previous stage and the gate of the fifth thin film transistor;
  • the gate of the fourth thin film transistor is input with the gate driving signal of the next stage
  • the source and drain are respectively connected to the reverse scanning DC control signal input terminal and the gate of the ninth thin film transistor;
  • the source and drain of the fifth thin film transistor are respectively connected to the constant voltage high voltage
  • the level signal input terminal is connected to the pull-down holding circuit, the source and drain of the ninth thin film transistor are respectively connected to the constant
  • the gate of the fourth thin film transistor is connected to the input terminal of the scan driving signal.
  • the pull-down hold circuit includes a seventh thin film transistor, a tenth thin film transistor, an eleventh thin film transistor and a second capacitor, and the gate of the seventh thin film transistor is connected to the pull-down circuit,
  • the source electrode and the drain electrode are respectively connected with the constant voltage low level signal input end and the pull-up control circuit;
  • the gate electrode of the tenth thin film transistor is connected with the first global control signal input end, the source electrode and the pull-up control circuit are respectively connected.
  • the drain is respectively connected with the constant voltage low level signal input terminal and the gate of the seventh thin film transistor; the gate of the eleventh thin film transistor is connected with the gate of the seventh thin film transistor, and the source and the drain are respectively connected to the constant voltage low level signal input terminal and the gate driving signal output terminal of the current stage, wherein the pull-down hold circuit is used for outputting the gate driving signal output terminal of the current stage.
  • the gate driving signal of the current stage is a constant voltage low level
  • the gate driving signal of the current stage is controlled to maintain the constant voltage low level.
  • the reset circuit includes a thirteenth thin film transistor, the gate of the thirteenth thin film transistor is connected to the second global control signal input terminal, and the source and drain are respectively connected to the constant
  • the low-level signal input terminal is connected to the gate drive signal output terminal of the current stage, wherein the reset circuit is used for when the second global control signal input to the second global control signal input terminal is at a high level , the current-stage gate driving signal output from the current-stage gate driving signal output terminal is pulled down to a constant voltage low level.
  • the driving circuit is an NMOS type driving circuit.
  • the present application also provides a display panel including the driving circuit described in any one of the above.
  • the pull-up control circuit includes a third thin film transistor and a first capacitor, the gate of the third thin film transistor is connected to the input terminal of the gate driving signal of the previous stage, the source and the The drain is respectively connected with the forward scanning DC control signal input end and the bootstrap circuit, and the two ends of the first capacitor are respectively connected with the constant voltage low level signal input end and the bootstrap circuit.
  • the gate of the third thin film transistor is connected to the input end of the scan start signal.
  • the bootstrap circuit includes a sixth thin film transistor and an eighth thin film transistor, the gate of the sixth thin film transistor is connected to the constant voltage high-level signal input terminal, the source and drain The poles are respectively connected to the pull-up control circuit and the gate of the eighth thin film transistor, and the source and drain of the eighth thin film transistor are respectively connected to the clock signal input terminal of this stage and the gate driving signal of this stage
  • the output terminal is connected, wherein the bootstrap circuit is used to control the gate drive signal output terminal of the current stage to output the gate of the current stage when the clock signal of the current stage inputted by the clock signal input terminal of the current stage is a constant voltage high level pole drive signal.
  • the pull-down circuit includes a first thin film transistor, a second thin film transistor, a fourth thin film transistor, a fifth thin film transistor and a ninth thin film transistor, and the gate of the first thin film transistor is connected to the
  • the forward scanning DC control signal input terminal is connected to the source and the drain are respectively connected to the next stage clock signal input terminal and the gate of the fifth thin film transistor; the gate of the second thin film transistor is connected to the reverse scanning DC
  • the control signal input end is connected, the source electrode and the drain electrode are respectively connected with the clock signal input end of the previous stage and the gate of the fifth thin film transistor;
  • the gate of the fourth thin film transistor is input with the gate driving signal of the next stage
  • the source and drain are respectively connected to the reverse scanning DC control signal input terminal and the gate of the ninth thin film transistor; the source and drain of the fifth thin film transistor are respectively connected to the constant voltage high voltage
  • the level signal input terminal is connected to the pull-down holding circuit, the source and drain of the ninth thin film transistor are respectively connected to the constant-voltage low-
  • the driving unit when the driving unit is a final-stage driving unit, the gate of the fourth thin film transistor is connected to the input terminal of the scan driving signal.
  • the pull-down hold circuit includes a seventh thin film transistor, a tenth thin film transistor, an eleventh thin film transistor and a second capacitor, and the gate of the seventh thin film transistor is connected to the pull-down circuit,
  • the source electrode and the drain electrode are respectively connected with the constant voltage low level signal input end and the pull-up control circuit;
  • the gate electrode of the tenth thin film transistor is connected with the first global control signal input end, the source electrode and the pull-up control circuit are respectively connected.
  • the drain is respectively connected with the constant voltage low level signal input terminal and the gate of the seventh thin film transistor; the gate of the eleventh thin film transistor is connected with the gate of the seventh thin film transistor, and the source and the drain are respectively connected to the constant voltage low level signal input terminal and the gate driving signal output terminal of the current stage, wherein the pull-down hold circuit is used for outputting the gate driving signal output terminal of the current stage.
  • the gate driving signal of the current stage is a constant voltage low level
  • the gate driving signal of the current stage is controlled to maintain the constant voltage low level.
  • the reset circuit includes a thirteenth thin film transistor, the gate of the thirteenth thin film transistor is connected to the second global control signal input terminal, and the source and drain are respectively connected to the constant
  • the low-level signal input terminal is connected to the gate drive signal output terminal of the current stage, wherein the reset circuit is used for when the second global control signal input to the second global control signal input terminal is at a high level , the current-stage gate driving signal output from the current-stage gate driving signal output terminal is pulled down to a constant voltage low level.
  • the driving circuit is an NMOS type driving circuit.
  • the present application also provides a display device including the above-mentioned display panel.
  • the signal input to the first global control signal input terminal is at a low level.
  • the present application provides a drive circuit, a display panel and a display device.
  • the drive circuit includes a plurality of cascaded drive units, and each drive unit specifically includes a pull-up control circuit, a pull-down circuit, a pull-down hold circuit, a bootstrap circuit, and a discharge circuit. and the reset circuit, wherein the discharge circuit includes a fourteenth thin film transistor and a twelfth thin film transistor, and by arranging the fourteenth thin film transistor, it can be prevented that the bootstrap voltage of the gate of the twelfth thin film transistor is reversed during the black sweeping stage.
  • the gate voltage is reduced due to the charging, so that the twelfth thin film transistor is fully turned on, the output voltage is increased, the discharge circuit is fully discharged, and the abnormal display caused by the residual charge in the black sweeping stage is avoided.
  • the blackening effect is guaranteed, which greatly improves the reliability of the product.
  • FIG. 1 is a schematic structural diagram of an Nth-stage driving unit in a driving circuit in the prior art.
  • FIG. 2 is a schematic structural diagram of an Nth-level driving unit in a driving circuit provided by an embodiment of the present application.
  • FIG. 3 is a timing diagram of a discharge process and a reset process of the driving circuit provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a simulation solution of a discharge circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the voltage change of GAS1 in the simulation solution provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of an output voltage of a simulation solution provided by an embodiment of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • FIG. 1 is a schematic structural diagram of an Nth-level driving unit in a conventional driving circuit
  • FIG. 2 is a schematic structural diagram of an N-level driving unit in a driving circuit provided by an embodiment of the present application.
  • the existing driving circuit The pull-up control circuit 11 , the bootstrap circuit 12 , the pull-down circuit 13 , the pull-down hold circuit 14 , and the reset circuit 16 in the N-th stage driving unit 10 and the N-th stage driving unit 20 in the driving circuit provided by the embodiment of the present application
  • the pull-up control circuit 21 , the bootstrap circuit 22 , the pull-down circuit 23 , the pull-down hold circuit 24 , and the reset circuit 26 are all the same, and the only difference is the discharge circuit (15 in FIG. 1 , 25 in FIG. 2 ).
  • the discharge circuit 15 in the N-th stage driving unit 10 in the existing driving circuit includes a twelfth thin film transistor (T12), wherein the gate of T12 is connected to the first global control signal input terminal (GAS1), And the gate and source are connected, and the drain is connected to the gate drive signal output terminal of this stage (Gate N), this way of connecting the gate and the source to set the voltage of the gate high is not good.
  • T12 thin film transistor
  • the discharge circuit 25 includes a fourteenth thin film transistor T14 and a twelfth thin film transistor T12 , wherein , the gate of T14 is connected to the constant voltage high-level signal input terminal, the source and drain are respectively connected to the first global control signal input terminal (GAS1) and the gate of T12, and the source and drain of T12 are respectively connected to GAS1 It is connected to the gate drive signal output terminal (Gate N) of this stage.
  • GAS1 global control signal input terminal
  • GAS1 gate drive signal output terminal
  • T14 is equivalent to a unidirectional diode, which can prevent the backflow of the bootstrap voltage at the gate (Q point) of T12.
  • the signal input by GAS1 is at high level, due to The currents of T14 and T12 both flow to the Q point, and the voltage of the Q point is about twice the VGH, so that T12 is fully opened, and the output voltage is correspondingly increased.
  • FIG. 4 is a schematic structural diagram of a simulation scheme of a discharge circuit provided by an embodiment of the application
  • FIG. 5 is a schematic diagram of a voltage change of GAS1 in the simulation scheme provided by an embodiment of the application
  • FIG. 6 is A schematic diagram of the output voltage of the simulation scheme of the discharge circuit provided by the embodiment of the present application, as shown in FIG. 4 , the present application proposes three simulation schemes (Case1, Case2, Case3), among which, Case1 is the discharge circuit provided by the embodiment of the present application.
  • the simulation scheme of the circuit that is, the discharge circuit includes T12 and T14, and the width-to-length ratio of T12 is 6um/7um
  • Case2 and Case3 are simulation schemes of the discharge circuit in the existing drive circuit, that is, the discharge circuit only includes T12, both The difference is that the width-length ratio of T12 in Case2 is 35um/7um, and the width-length ratio of T12 in Case3 is 4um/7um. It is worth noting that in addition to the difference in the number of thin film transistors and the width-length ratio among the three simulation schemes, Other components are the same, such as the value of resistors and capacitors, to exclude the influence of other factors on the output voltage (Gate).
  • Figure 5 and Figure 6 respectively show a coordinate axis
  • the horizontal axis of the two coordinate axes is time T
  • the vertical axis is voltage U
  • CAS1 changes from low level (-7V) to high level (7V).
  • the output voltage (Gate) of the discharge circuit in the three simulation schemes increases.
  • Case1 is 8.5V
  • Case2 is 6.2V
  • Case3 is 3.8V.
  • the pull-up control circuit 21 includes a third thin film transistor T3 and a first capacitor C1.
  • the gate of the third thin film transistor T3 is connected to the gate driving signal input terminal (Gate N-1) connection, the source and drain are respectively connected to the forward scanning DC control signal input terminal (U2D) and the bootstrap circuit 22, and the two ends of the first capacitor C1 are respectively connected to the constant voltage low level signal input terminal ( VGL) and the bootstrap circuit 22 are connected.
  • the pull-up control circuit 21 is mainly used to allow the gate drive signal of the previous stage and the forward scanning DC control signal to be N-1), and the input of the forward scanning DC control signal input terminal (U2D), wherein, when the signal input by U2D is at a high level, the driving circuit will scan line by line from top to bottom.
  • the gate of T3 is connected to the input terminal of the scan start signal.
  • the bootstrap circuit 22 includes a sixth thin film transistor T6 and an eighth thin film transistor T8, the gate of the sixth thin film transistor T6 is connected to the constant voltage high-level signal input terminal (VGH), and the source and drain It is respectively connected with the pull-up control circuit 21 and the gate of the eighth thin film transistor T8, and the source and drain of the eighth thin film transistor T8 are respectively connected with the clock signal input terminal (CKN) of this stage and the gate drive signal output terminal of this stage ( Gate n) Connect.
  • VGH constant voltage high-level signal input terminal
  • the bootstrap circuit 22 is configured to control the gate driving signal output terminal (Gate N) of the current stage to output the gate of the current stage when the clock signal of the current stage input by the clock signal input terminal (CKN) of the current stage is a constant voltage high level. drive signal.
  • the pull-down circuit 23 includes a first thin film transistor T1, a second thin film transistor T2, a fourth thin film transistor T4, a fifth thin film transistor, and a T5 ninth thin film transistor T9.
  • the gate of the first thin film transistor T1 is connected to the positive Connect to the scanning DC control signal input terminal (U2D), the source and drain are respectively connected to the next-stage clock signal input terminal (CKN+1) and the gate of the fifth thin film transistor T5;
  • the gate of the second thin film transistor T2 It is connected to the input terminal of the reverse scanning DC control signal (D2U), and the source and drain are respectively connected to the upper-stage clock signal input terminal (CKN-1) and the gate of the fifth thin film transistor T5;
  • the gate and the next stage gate drive signal input terminal (Gate N+1) connection, the source and drain are respectively connected to the reverse scanning DC control signal input terminal (D2U) and the gate of the ninth thin film transistor T9;
  • the source and drain of the fifth thin film transistor T5 are respectively connected to the constant voltage
  • the pull-down circuit 23 is used to pull down the gate of the current stage when the signals input to the next-stage clock signal input terminal (CKN+1) and the next-stage gate driving signal input terminal (Gate N+1) are both high-level. Pole drive signal output terminal (Gate N) The output gate drive signal of the current stage goes to a constant voltage low level.
  • the driving circuit will scan line by line from bottom to top.
  • the driving circuit in this application has four levels of clock signals CK1, CK2, CK3, and CK4. It is worth noting that when the Nth level clock signal CKN is CK1, the previous level clock signal CKN-1 is CK4, The clock signal CKN+1 of the next stage is CK2; when the clock signal CKN of the Nth stage is CK4, the clock signal CKN-1 of the previous stage is CK3, and the clock signal CKN+1 of the next stage is CK1.
  • the gate of the fourth thin film transistor T4 is connected to the input terminal of the scan start signal.
  • the pull-down holding circuit 24 includes a seventh thin film transistor T7, a tenth thin film transistor T10, an eleventh thin film transistor T11 and a second capacitor C2.
  • the gate of the seventh thin film transistor T7 is connected to the pull-down circuit 23, and the source is connected to the pull-down circuit 23.
  • the pole and drain are respectively connected with the constant voltage low level signal input terminal (VGL) and the pull-up control circuit 21; the gate of the tenth thin film transistor T10 is connected with the first global control signal input terminal (GAS1), the source and drain
  • the electrodes are respectively connected with the constant voltage low level signal input terminal (VGL) and the gate of the seventh thin film transistor T7; the gate of the eleventh thin film transistor T11 is connected with the gate of the seventh thin film transistor T7, the source and drain They are respectively connected with the constant voltage low level signal input terminal (VGL) and the gate drive signal output terminal (Gate N) of this stage.
  • the pull-down hold circuit 24 is used to control the gate drive signal of the current stage to maintain the constant voltage low level when the gate drive signal of the current stage output from the gate drive signal output terminal (Gate N) of the current stage is a constant voltage low level.
  • the reset circuit 26 includes a thirteenth thin film transistor T13, the gate of the thirteenth thin film transistor T13 is connected to the second global control signal input terminal (GAS2), and the source and drain are respectively connected to the constant voltage low voltage The level signal input terminal (VGL) and the gate drive signal output terminal of this stage (Gate n) Connect.
  • the reset circuit 26 is used for, when the second global control signal input from the second global control signal input terminal (GAS2) is at a high level, to output the gate driving signal output terminal (Gate N) of the current stage gate The drive signal is pulled down to a constant voltage low level.
  • FIG. 3 is a timing diagram of a discharge process and a reset process of the driving circuit provided by the embodiment of the present application, wherein t1 is the discharge process, and t3 is the reset process.
  • the input signal of GAS1 is high level, and T12 is turned on. Since the Q point is subjected to the bootstrap effect, the Q point potential will be pulled to an amplitude of about 2 times VGH. However, since the Q point is not precharged to VGH , so the waveform is somewhat distorted, but it does not hinder the black screen, and the output waveform of Gate N is also better.
  • the signal input by GAS1 is low level and T12 is off. Since the signal input by GAS2 is still low level and T13 has not been turned on, the output level of Gate N is still high.
  • the driving circuit of the present application is a NOMS type driving circuit.
  • CMOS type driving circuits include CMOS type driving circuits and NMOS type driving circuits.
  • CMOS type driving circuits include NTFT (N-channel thin film transistor) devices and PTFT (P-channel thin film transistor) devices, while NMOS type driving circuits Including only NTFT devices, in this embodiment, the discharge circuit 25 is suitable for all non-CMOS type GOA circuits.
  • the present application further provides a display panel including the driving circuit described in any of the above embodiments.
  • the present application also provides a display device, including the display panel described in the above embodiments.
  • the signal input to the first global control signal input terminal (GAS1) is at a low level.
  • the signal input to the second global control signal input terminal (GAS2) is also low level.
  • the display device usually needs to be used in conjunction with the touch panel function, so the driving circuit needs to realize signal pause to cooperate with the touch panel function, such as in conjunction with the touch panel scanning.
  • the drive circuit needs to wake up the display device from black screen after the signal is stopped.
  • the drive circuit needs to set all the gate lines to the conducting state within a period of time, and apply a black voltage to the data lines by applying a black voltage.
  • this period of time is called the gate line fully open (All Gate On) stage.
  • the GAS1 input at the first global control signal input terminal is at a high level
  • the GAS2 input at the second global control signal input terminal is at a low level.
  • the drive circuit needs to be reset.
  • the GAS1 input at the first global control signal input terminal is at a low level
  • the GAS2 input at the second global control signal input terminal is at a high level.
  • the present application provides a drive circuit, a display panel and a display device, the drive circuit includes a plurality of cascaded drive units, and each drive unit 20 specifically includes a pull-up control circuit 21, a pull-down circuit 23, a pull-down circuit
  • the occurrence of abnormal display caused by the residual charge in the stage ensures the blackening effect without limiting the size of the thin film transistor in the discharge circuit, which greatly improves the reliability of the product.

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Abstract

一种驱动电路、显示面板和显示装置，该驱动电路包括多个级联的驱动单元，每个驱动单元具体包括上拉控制电路、下拉电路、下拉保持电路、自举电路、放电电路和重置电路，其中，放电电路包括第十四薄膜晶体管和第十二薄膜晶体管。

Description

GOA电路、显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种GOA电路、显示面板和显示装置。
 背景技术
目前，液晶显示装置已经广泛地应用于各种电子产品中，其中，GOA(Gate Driver On Array，阵列基板行驱动)电路是液晶显示装置中的一个重要组成部分，GOA是指利用现有薄膜晶体管液晶显示器阵列(Array)制程将栅极(Gate)行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式的一项技术。随着产品的像素密度越来越高，扫描的行数也越来越多，其发生级传错误的概率也在增大，同时，用户在对液晶显示装置的操作过程中有可能出现异常断电的情况，如果在断电后没有对显示区进行扫黑和重置，会造成由于电荷残留而引起的异常显示的情况发生。
现有的具有扫黑模块的GOA电路对扫黑模块中薄膜晶体管的要求很高，而且将栅极置高的效果并不好，如果薄膜晶体管的大小稍有不合适，就会影响断电后扫黑的效果，对画面的品味有潜在风险。
 技术问题
本申请提供一种GOA电路、显示面板和显示装置，以缓解现有GOA电路无法保证扫黑效果的技术问题。
 技术解决方案
本申请提供一种驱动电路，所述驱动电路包括多个级联的驱动单元，每个所述驱动单元具体包括上拉控制电路、下拉电路、下拉保持电路、自举电路、放电电路和重置电路，所述上拉控制电路与所述下拉电路、所述下拉保持电路以及所述自举电路连接，所述下拉保持电路还与所述下拉电路连接，所述下拉保持电路、所述自举电路、所述放电电路和所述重置电路均与本级栅极驱动信号输出端连接，所述上拉控制电路还与上一级栅极驱动信号输入端连接：
其中，所述放电电路包括第十二薄膜晶体管和第十四薄膜晶体管，所述第十四薄膜晶体管的栅极与恒压高电平信号输入端连接，源极和漏极分别与第一全局控制信号输入端和所述第十二薄膜晶体管的栅极连接，所述第十二薄膜晶体管的源极和漏极分别与所述第一全局控制信号输入端和所述本级栅极驱动信号输出端连接，其中，当所述第一全局控制信号输入端输入的信号为高电平时，所述第十二薄膜晶体管的栅极的电压大于所述恒压高电平信号输入端的电压，使所述放电电路充分放电。
在本申请的驱动电路中，所述上拉控制电路包括第三薄膜晶体管和第一电容，所述第三薄膜晶体管的栅极与所述上一级栅极驱动信号输入端连接，源极和漏极分别与正向扫描直流控制信号输入端、以及所述自举电路连接，所述第一电容的两端分别与恒压低电平信号输入端和所述自举电路连接。
在本申请的驱动电路中，当所述驱动单元为首级驱动单元时，所述第三薄膜晶体管的栅极与扫描启动信号输入端连接。
在本申请的驱动电路中，所述自举电路包括第六薄膜晶体管和第八薄膜晶体管，所述第六薄膜晶体管的栅极与所述恒压高电平信号输入端连接，源极和漏极分别与所述上拉控制电路和所述第八薄膜晶体管的栅极连接，所述第八薄膜晶体管的源极和漏极分别与本级时钟信号输入端和所述本级栅极驱动信号输出端连接，其中，所述自举电路用于在所述本级时钟信号输入端输入的本级时钟信号为恒压高电平时，控制所述本级栅极驱动信号输出端输出本级栅极驱动信号。
在本申请的驱动电路中，所述下拉电路包括第一薄膜晶体管、第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第九薄膜晶体管，所述第一薄膜晶体管的栅极与所述正向扫描直流控制信号输入端连接，源极和漏极分别与下一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第二薄膜晶体管的栅极与反向扫描直流控制信号输入端连接，源极和漏极分别与上一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第四薄膜晶体管的栅极与下一级栅极驱动信号输入端连接，源极和漏极分别与所述反向扫描直流控制信号输入端和第九薄膜晶体管的栅极连接；所述第五薄膜晶体管的源极和漏极分别与所述恒压高电平信号输入端和所述下拉保持电路连接，所述第九薄膜晶体管的源极和漏极分别与所述恒压低电平信号输入端和所述下拉保持电路连接，其中，所述下拉电路用于在所述下一级时钟信号输入端和所述下一级栅极驱动信号输入端输入的信号均为高电平时，拉低所述本级栅极驱动信号输出端输出的本级栅极驱动信号至恒压低电平。
在本申请的驱动电路中，当所述驱动单元为末级驱动单元时，所述第四薄膜晶体管的栅极与扫描驱动信号输入端连接。
在本申请的驱动电路中，所述下拉保持电路包括第七薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第二电容，所述第七薄膜晶体管的栅极与所述下拉电路连接，源极和漏极分别与所述恒压低电平信号输入端和所述上拉控制电路连接；所述第十薄膜晶体管的栅极与所述第一全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述第七薄膜晶体管的栅极连接；所述第十一薄膜晶体管的栅极与所述第七薄膜晶体管的栅极连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述下拉保持电路用于在所述本级栅极驱动信号输出端输出的本级栅极驱动信号为恒压低电平时，控制所述本级栅极驱动信号保持所述恒压低电平。
在本申请的驱动电路中，所述重置电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的栅极与第二全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述重置电路用于在所述第二全局控制信号输入端输入的第二全局控制信号为高电平时，将所述本级栅极驱动信号输出端输出的本级栅极驱动信号拉低至恒压低电平。
在本申请的驱动电路中，所述驱动电路为NMOS型驱动电路。
本申请还提供一种显示面板，包括上述任一项所述的驱动电路。
在本申请的显示面板中，所述上拉控制电路包括第三薄膜晶体管和第一电容，所述第三薄膜晶体管的栅极与所述上一级栅极驱动信号输入端连接，源极和漏极分别与正向扫描直流控制信号输入端、以及所述自举电路连接，所述第一电容的两端分别与恒压低电平信号输入端和所述自举电路连接。
在本申请的显示面板中，当所述驱动单元为首级驱动单元时，所述第三薄膜晶体管的栅极与扫描启动信号输入端连接。
在本申请的显示面板中，所述自举电路包括第六薄膜晶体管和第八薄膜晶体管，所述第六薄膜晶体管的栅极与所述恒压高电平信号输入端连接，源极和漏极分别与所述上拉控制电路和所述第八薄膜晶体管的栅极连接，所述第八薄膜晶体管的源极和漏极分别与本级时钟信号输入端和所述本级栅极驱动信号输出端连接，其中，所述自举电路用于在所述本级时钟信号输入端输入的本级时钟信号为恒压高电平时，控制所述本级栅极驱动信号输出端输出本级栅极驱动信号。
在本申请的显示面板中，所述下拉电路包括第一薄膜晶体管、第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第九薄膜晶体管，所述第一薄膜晶体管的栅极与所述正向扫描直流控制信号输入端连接，源极和漏极分别与下一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第二薄膜晶体管的栅极与反向扫描直流控制信号输入端连接，源极和漏极分别与上一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第四薄膜晶体管的栅极与下一级栅极驱动信号输入端连接，源极和漏极分别与所述反向扫描直流控制信号输入端和第九薄膜晶体管的栅极连接；所述第五薄膜晶体管的源极和漏极分别与所述恒压高电平信号输入端和所述下拉保持电路连接，所述第九薄膜晶体管的源极和漏极分别与所述恒压低电平信号输入端和所述下拉保持电路连接，其中，所述下拉电路用于在所述下一级时钟信号输入端和所述下一级栅极驱动信号输入端输入的信号均为高电平时，拉低所述本级栅极驱动信号输出端输出的本级栅极驱动信号至恒压低电平。
在本申请的显示面板中，当所述驱动单元为末级驱动单元时，所述第四薄膜晶体管的栅极与扫描驱动信号输入端连接。
在本申请的显示面板中，所述下拉保持电路包括第七薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第二电容，所述第七薄膜晶体管的栅极与所述下拉电路连接，源极和漏极分别与所述恒压低电平信号输入端和所述上拉控制电路连接；所述第十薄膜晶体管的栅极与所述第一全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述第七薄膜晶体管的栅极连接；所述第十一薄膜晶体管的栅极与所述第七薄膜晶体管的栅极连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述下拉保持电路用于在所述本级栅极驱动信号输出端输出的本级栅极驱动信号为恒压低电平时，控制所述本级栅极驱动信号保持所述恒压低电平。
在本申请的显示面板中，所述重置电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的栅极与第二全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述重置电路用于在所述第二全局控制信号输入端输入的第二全局控制信号为高电平时，将所述本级栅极驱动信号输出端输出的本级栅极驱动信号拉低至恒压低电平。
在本申请的显示面板中，所述驱动电路为NMOS型驱动电路。
本申请还提供一种显示装置，包括上述显示面板。
在本申请提供的显示装置中，在所述显示装置的正常显示阶段，所述第一全局控制信号输入端输入的信号为低电平。
 有益效果
本申请提供一种驱动电路、显示面板和显示装置，该驱动电路包括多个级联的驱动单元，每个驱动单元具体包括上拉控制电路、下拉电路、下拉保持电路、自举电路、放电电路和重置电路，其中，放电电路包括第十四薄膜晶体管和第十二薄膜晶体管，通过设置第十四薄膜晶体管，可以防止在扫黑阶段由于第十二薄膜晶体管的栅极的自举电压反灌而导致的栅极电压降低，从而使第十二薄膜晶体管充分打开，提高输出电压，使放电电路充分放电，避免了由于扫黑阶段电荷残留而引起的异常显示的情况的发生，在无须限制放电电路中薄膜晶体管的大小的情况下保证了扫黑效果，大大提高产品的信赖度。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术中的驱动电路中第N级驱动单元的结构示意图。
图2为本申请实施例提供的驱动电路中第N级驱动单元的结构示意图。
图3为本申请实施例提供的驱动电路的放电过程和重置过程的时序图。
图4为本申请实施例提供的放电电路的仿真方案的结构示意图。
图5为本申请实施例提供的仿真方案中GAS1的电压变化示意图。
图6为本申请实施例提供的仿真方案的输出电压示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
请参阅图1和图2，图1为现有驱动电路中第N级驱动单元的结构示意图，图2为本申请实施例提供的驱动电路中第N级驱动单元的结构示意图，现有驱动电路中第N级驱动单元10中的上拉控制电路11、自举电路12、下拉电路13、下拉保持电路14、以及重置电路16与本申请实施例提供的驱动电路中第N级驱动单元20中的上拉控制电路21、自举电路22、下拉电路23、下拉保持电路24、以及重置电路26均相同，区别仅在于放电电路（如图1中的15、图2中的25）。
由图1可知，现有驱动电路中第N级驱动单元10中的放电电路15包括第十二薄膜晶体管（T12），其中，T12的栅极连接至第一全局控制信号输入端（GAS1），且栅极和源极连接，漏极连接至本级栅极驱动信号输出端（Gate N），这种栅极和源极连接的方式将栅极的电压置高的效果并不好，若想要提高本级栅极驱动信号输出端的输出电压，则对T12的大小具有很高的要求，如果T12的大小稍有不适，就会影响放电的效果，对画面的品味具有潜在风险。
因此，如图2所示，为了保证放电效果，在本申请实施例提供的驱动电路中第N级驱动单元20中，放电电路25包括第十四薄膜晶体管T14和第十二薄膜晶体管T12，其中，T14的栅极与恒压高电平信号输入端连接，源极和漏极分别与第一全局控制信号输入端（GAS1）和T12的栅极连接，T12的源极和漏极分别与GAS1和本级栅极驱动信号输出端（Gate N）连接。
具体地，当GAS1输入的信号为高电平时，T14相当于一个单向的二极管，可以防止T12的栅极（Q点）的自举电压反灌，当GAS1输入的信号为高电平时， 由于T14和T12的电流均流至Q点，Q点的电压约为两倍的VGH，使T12充分打开，输出电压相应提高。
值得注意的是，当GAS1输入的信号为高电平时，在驱动电路的各级驱动单元中放电电路的T12均打开，使得各级栅极驱动信号输出端的输出电压升高，实现栅极全开（All Gate On），以清空电路中残留的电荷。
请参阅图4、图5和图6，图4为本申请实施例提供的放电电路的仿真方案的结构示意图，图5为本申请实施例提供的仿真方案中GAS1的电压变化示意图，图6为本申请过实施例提供的放电电路的仿真方案的输出电压示意图，如图4所示，本申请提出了三种仿真方案（Case1、Case2、Case3）,其中，Case1为本申请实施例提供的放电电路的仿真方案，即该放电电路包括T12和T14，T12的宽长比均为6um/7um；Case2和Case3均为现有驱动电路中放电电路的仿真方案，即放电电路只包括T12，二者的区别在于，Case2中T12的宽长比为35um/7um，Case3中T12的宽长比为4um/7um，值得注意的是，三种仿真方案中除了薄膜晶体管数量和宽长比的差异外，其他元件均相同，例如电阻、电容的值，以排除其他因素对输出电压（Gate）的影响。
如图5和图6所示，图5和图6分别出示了一个坐标轴，两个坐标轴的横轴均为时间T，纵轴均为电压U，具体地，请参阅图5，在20us时，CAS1由低电平（-7V）变为了高电平（7V），同时，请参见图6，在20us时，三种仿真方案中放电电路的输出电压（Gate）均增大，其中，Case1为8.5V、Case2为6.2V、Case3为3.8V。这三种仿真方案进一步证实了T14将T12栅极电压置高的效果，以及现有放电电路对T12宽长比的要求。
请继续参阅图2，在本实施例中，上拉控制电路21包括第三薄膜晶体管T3和第一电容C1，第三薄膜晶体管T3的栅极与上一级栅极驱动信号输入端（Gate N-1）连接，源极和漏极分别与正向扫描直流控制信号输入端（U2D）、以及自举电路22连接，第一电容C1的两端分别与恒压低电平信号输入端（VGL）和自举电路22连接。
具体地，上拉控制电路21主要用于让上一级栅极驱动信号和正向扫描直流控制信号分别由上一级栅极驱动信号输入端（Gate N-1）、以及正向扫描直流控制信号输入端（U2D）输入，其中，当U2D输入的信号为高电平时，该驱动电路将由上到下逐行扫描。
在一些实施例中，当N为1时，即当该第N级驱动单元20为第一级驱动单元时，T3的栅极与扫描启动信号输入端连接。
在本实施例中，自举电路22包括第六薄膜晶体管T6和第八薄膜晶体管T8，第六薄膜晶体管T6的栅极与恒压高电平信号输入端（VGH）连接，源极和漏极分别与上拉控制电路21和第八薄膜晶体管T8的栅极连接，第八薄膜晶体管T8的源极和漏极分别与本级时钟信号输入端（CKN）和本级栅极驱动信号输出端（Gate N）连接。
具体地，自举电路22用于在本级时钟信号输入端（CKN）输入的本级时钟信号为恒压高电平时，控制本级栅极驱动信号输出端（Gate N）输出本级栅极驱动信号。
在本实施例中，下拉电路23包括第一薄膜晶体管T1、第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管和T5第九薄膜晶体管T9，第一薄膜晶体管T1的栅极与正向扫描直流控制信号输入端（U2D）连接，源极和漏极分别与下一级时钟信号输入端（CKN+1）和第五薄膜晶体管T5的栅极连接；第二薄膜晶体管T2的栅极与反向扫描直流控制信号（D2U）输入端连接，源极和漏极分别与上一级时钟信号输入端（CKN-1）和第五薄膜晶体管T5的栅极连接；第四薄膜晶体管T4的栅极与下一级栅极驱动信号输入端（Gate N+1）连接，源极和漏极分别与反向扫描直流控制信号输入端（D2U）和第九薄膜晶体管T9的栅极连接；第五薄膜晶体管T5的源极和漏极分别与恒压高电平信号（VGH）输入端和下拉保持电路24连接，第九薄膜晶体管T9的源极和漏极分别与恒压低电平信号输入端（VGH）和下拉保持电路24连接。
具体地，下拉电路23用于在下一级时钟信号输入端（CKN+1）和下一级栅极驱动信号输入端（Gate N+1）输入的信号均为高电平时，拉低本级栅极驱动信号输出端（Gate N）输出的本级栅极驱动信号至恒压低电平。其中，当反向扫描直流控制信号（D2U）为高电平时，该驱动电路将由下向上逐行扫描。
优选地，本申请中的驱动电路有四级时钟信号CK1、CK2、CK3、以及CK4，值得注意的是，当第N级时钟信号CKN为CK1时，上一级时钟信号CKN-1为CK4，下一级时钟信号CKN+1为CK2；当第N级时钟信号CKN为CK4时，上一级时钟信号CKN-1为CK3，下一级时钟信号CKN+1为CK1。
值得注意的是，当该第N级驱动单元20为最后一级驱动单元时，第四薄膜晶体管T4的栅极与扫描启动信号输入端连接。
在本实施例中，下拉保持电路24包括第七薄膜晶体管T7、第十薄膜晶体管T10、第十一薄膜晶体管T11和第二电容C2，第七薄膜晶体管T7的栅极与下拉电路23连接，源极和漏极分别与恒压低电平信号输入端（VGL）和上拉控制电路21连接；第十薄膜晶体管T10的栅极与第一全局控制信号输入端（GAS1）连接，源极和漏极分别与恒压低电平信号输入端（VGL）和第七薄膜晶体管T7的栅极连接；第十一薄膜晶体管T11的栅极与第七薄膜晶体管T7的栅极连接，源极和漏极分别与恒压低电平信号输入端（VGL）和本级栅极驱动信号输出端（Gate N）连接。
其中，下拉保持电路24用于在本级栅极驱动信号输出端（Gate N）输出的本级栅极驱动信号为恒压低电平时，控制本级栅极驱动信号保持恒压低电平。
在实施例中，重置电路26包括第十三薄膜晶体管T13，第十三薄膜晶体管T13的栅极与第二全局控制信号输入端（GAS2）连接，源极和漏极分别与恒压低电平信号输入端（VGL）和本级栅极驱动信号输出端（Gate N）连接。
其中，重置电路26用于在第二全局控制信号输入端（GAS2）输入的第二全局控制信号为高电平时，将本级栅极驱动信号输出端（Gate N）输出的本级栅极驱动信号拉低至恒压低电平。
具体地，请参阅图3，图3为本申请实施例提供的驱动电路的放电过程和重置过程的时序图，其中，t1为放电过程，t3为重置过程。
t1时刻，GAS1输入的信号为高电平，T12打开，由于Q点受到自举效应，所以Q点电位会被拉到大约2倍VGH的幅值，然而，由于Q点没有被预充到VGH，所以波形有些失真，但是对扫黑画面无碍，Gate N的输出波形也较好。
t2时刻，GAS1输入的信号为低电平，T12关闭，由于GAS2输入的信号还为低电平，T13还未打开，因此，Gate N的输出电平仍为高。
t3时刻，GAS2输入的信号为高电平，T13被打开，VGL将GateN的输出拉低，起到重置作用。
在本实施例中，本申请这种的驱动电路为NOMS型驱动电路。
具体地，常用的驱动电路包括CMOS型驱动电路和NMOS型驱动电路，CMOS型驱动电路中包括NTFT(N沟道薄膜晶体管)器件和PTFT(P沟道薄膜晶体管)器件，而NMOS型驱动电路中只包括NTFT器件，在本实施例中，放电电路25适用于所有非CMOS型GOA电路。
本申请还提供一种显示面板，包括上述任一实施例所述的驱动电路。
本申请还提供一种显示装置，包括上述实施例所述的显示面板。
在一些实施例中，在显示装置的正常显示阶段，第一全局控制信号输入端（GAS1）输入的信号为低电平。
同时，在显示装置的正常显示阶段，第二全局控制信号输入端（GAS2）输入的信号也为低电平。
具体地，显示装置通常需要搭配触摸屏(Touch Panel)功能进行使用， 因此驱动电路需要实现信号中停以配合触摸屏的功能，如配合触摸屏的扫描。通常情况下， 驱动电路在实现信号中停后，需将显示装置进行黑屏唤醒，此时，驱动电路需要在一段时间内将所有的栅线均设置为导通状态，通过向数据线施加黑电压以清空像素电容中残留的电位，以使得显示装置的显示效果良好，此段时间称为栅线全开(All Gate On)阶段。在All Gate On阶段，第一全局控制信号输入端输入的GAS1为高电平，第二全局控制信号输入端输入的GAS2为低电平。
此外，在All Gate On阶段后，为了避免All Gate On后各级栅极漏电而导致的栅极电压不正常，以及避免驱动电路出现失效的情况，在All Gate On阶段后，需要对驱动电路进行重置，在重置阶段，第一全局控制信号输入端输入的GAS1为低电平，第二全局控制信号输入端输入的GAS2为高电平。
根据上述实施例可知：本申请提供一种驱动电路、显示面板和显示装置，该驱动电路包括多个级联的驱动单元，每个驱动单元20具体包括上拉控制电路21、下拉电路23、下拉保持电路24、自举电路22、放电电路25和重置电路26，其中，放电电路25包括第十四薄膜晶体管T14和第十二薄膜晶体管T12，通过设置第十四薄膜晶体管，可以防止在扫黑阶段由于第十二薄膜晶体管的栅极的自举电压反灌而导致的栅极电压降低，从而使第十二薄膜晶体管充分打开，提高输出电压，使放电电路充分放电，避免了由于扫黑阶段电荷残留而引起的异常显示的情况的发生，在无须限制放电电路中薄膜晶体管的大小的情况下保证了扫黑效果，大大提高产品的信赖度。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种驱动电路，其包括多个级联的驱动单元，每个所述驱动单元具体包括上拉控制电路、下拉电路、下拉保持电路、自举电路、放电电路和重置电路，所述上拉控制电路与所述下拉电路、所述下拉保持电路以及所述自举电路连接，所述下拉保持电路还与所述下拉电路连接，所述下拉保持电路、所述自举电路、所述放电电路和所述重置电路均与本级栅极驱动信号输出端连接，所述上拉控制电路还与上一级栅极驱动信号输入端连接：
    其中，所述放电电路包括第十二薄膜晶体管和第十四薄膜晶体管，所述第十四薄膜晶体管的栅极与恒压高电平信号输入端连接，源极和漏极分别与第一全局控制信号输入端和所述第十二薄膜晶体管的栅极连接，所述第十二薄膜晶体管的源极和漏极分别与所述第一全局控制信号输入端和所述本级栅极驱动信号输出端连接，其中，当所述第一全局控制信号输入端输入的信号为高电平时，所述第十二薄膜晶体管的栅极的电压大于所述恒压高电平信号输入端的电压，使所述放电电路充分放电。
  2. 如权利要求1所述的驱动电路，其中，所述上拉控制电路包括第三薄膜晶体管和第一电容，所述第三薄膜晶体管的栅极与所述上一级栅极驱动信号输入端连接，源极和漏极分别与正向扫描直流控制信号输入端、以及所述自举电路连接，所述第一电容的两端分别与恒压低电平信号输入端和所述自举电路连接。
  3. 如权利要求2所述的驱动电路，其中，当所述驱动单元为首级驱动单元时，所述第三薄膜晶体管的栅极与扫描启动信号输入端连接。
  4. 如权利要求1所述的驱动电路，其特征在于，所述自举电路包括第六薄膜晶体管和第八薄膜晶体管，所述第六薄膜晶体管的栅极与所述恒压高电平信号输入端连接，源极和漏极分别与所述上拉控制电路和所述第八薄膜晶体管的栅极连接，所述第八薄膜晶体管的源极和漏极分别与本级时钟信号输入端和所述本级栅极驱动信号输出端连接，其中，所述自举电路用于在所述本级时钟信号输入端输入的本级时钟信号为恒压高电平时，控制所述本级栅极驱动信号输出端输出本级栅极驱动信号。
  5. 如权利要求1所述的驱动电路，其中，所述下拉电路包括第一薄膜晶体管、第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第九薄膜晶体管，所述第一薄膜晶体管的栅极与所述正向扫描直流控制信号输入端连接，源极和漏极分别与下一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第二薄膜晶体管的栅极与反向扫描直流控制信号输入端连接，源极和漏极分别与上一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第四薄膜晶体管的栅极与下一级栅极驱动信号输入端连接，源极和漏极分别与所述反向扫描直流控制信号输入端和第九薄膜晶体管的栅极连接；所述第五薄膜晶体管的源极和漏极分别与所述恒压高电平信号输入端和所述下拉保持电路连接，所述第九薄膜晶体管的源极和漏极分别与所述恒压低电平信号输入端和所述下拉保持电路连接，其中，所述下拉电路用于在所述下一级时钟信号输入端和所述下一级栅极驱动信号输入端输入的信号均为高电平时，拉低所述本级栅极驱动信号输出端输出的本级栅极驱动信号至恒压低电平。
  6. 如权利要求5所述的驱动电路，其中，当所述驱动单元为末级驱动单元时，所述第四薄膜晶体管的栅极与扫描驱动信号输入端连接。
  7. 如权利要求1所述的驱动电路，其中，所述下拉保持电路包括第七薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第二电容，所述第七薄膜晶体管的栅极与所述下拉电路连接，源极和漏极分别与所述恒压低电平信号输入端和所述上拉控制电路连接；所述第十薄膜晶体管的栅极与所述第一全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述第七薄膜晶体管的栅极连接；所述第十一薄膜晶体管的栅极与所述第七薄膜晶体管的栅极连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述下拉保持电路用于在所述本级栅极驱动信号输出端输出的本级栅极驱动信号为恒压低电平时，控制所述本级栅极驱动信号保持所述恒压低电平。
  8. 如权利要求1所述的驱动电路，其中，所述重置电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的栅极与第二全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述重置电路用于在所述第二全局控制信号输入端输入的第二全局控制信号为高电平时，将所述本级栅极驱动信号输出端输出的本级栅极驱动信号拉低至恒压低电平。
  9. 如权利要求1所述的驱动电路，其中，所述驱动电路为NMOS型驱动电路。
  10. 一种显示面板，其包括如权利要求1所述的驱动电路。
  11. 如权利要求10所述的显示面板，其中，所述上拉控制电路包括第三薄膜晶体管和第一电容，所述第三薄膜晶体管的栅极与所述上一级栅极驱动信号输入端连接，源极和漏极分别与正向扫描直流控制信号输入端、以及所述自举电路连接，所述第一电容的两端分别与恒压低电平信号输入端和所述自举电路连接。
  12. 如权利要求11所述的显示面板，其中，当所述驱动单元为首级驱动单元时，所述第三薄膜晶体管的栅极与扫描启动信号输入端连接。
  13. 如权利要求10所述的显示面板，其中，所述自举电路包括第六薄膜晶体管和第八薄膜晶体管，所述第六薄膜晶体管的栅极与所述恒压高电平信号输入端连接，源极和漏极分别与所述上拉控制电路和所述第八薄膜晶体管的栅极连接，所述第八薄膜晶体管的源极和漏极分别与本级时钟信号输入端和所述本级栅极驱动信号输出端连接，其中，所述自举电路用于在所述本级时钟信号输入端输入的本级时钟信号为恒压高电平时，控制所述本级栅极驱动信号输出端输出本级栅极驱动信号。
  14. 如权利要求10所述的显示面板，其中，所述下拉电路包括第一薄膜晶体管、第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第九薄膜晶体管，所述第一薄膜晶体管的栅极与所述正向扫描直流控制信号输入端连接，源极和漏极分别与下一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第二薄膜晶体管的栅极与反向扫描直流控制信号输入端连接，源极和漏极分别与上一级时钟信号输入端和所述第五薄膜晶体管的栅极连接；所述第四薄膜晶体管的栅极与下一级栅极驱动信号输入端连接，源极和漏极分别与所述反向扫描直流控制信号输入端和第九薄膜晶体管的栅极连接；所述第五薄膜晶体管的源极和漏极分别与所述恒压高电平信号输入端和所述下拉保持电路连接，所述第九薄膜晶体管的源极和漏极分别与所述恒压低电平信号输入端和所述下拉保持电路连接，其中，所述下拉电路用于在所述下一级时钟信号输入端和所述下一级栅极驱动信号输入端输入的信号均为高电平时，拉低所述本级栅极驱动信号输出端输出的本级栅极驱动信号至恒压低电平。
  15. 如权利要求14所述的显示面板，其中，当所述驱动单元为末级驱动单元时，所述第四薄膜晶体管的栅极与扫描驱动信号输入端连接。
  16. 如权利要求10所述的显示面板，其中，所述下拉保持电路包括第七薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管和第二电容，所述第七薄膜晶体管的栅极与所述下拉电路连接，源极和漏极分别与所述恒压低电平信号输入端和所述上拉控制电路连接；所述第十薄膜晶体管的栅极与所述第一全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述第七薄膜晶体管的栅极连接；所述第十一薄膜晶体管的栅极与所述第七薄膜晶体管的栅极连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述下拉保持电路用于在所述本级栅极驱动信号输出端输出的本级栅极驱动信号为恒压低电平时，控制所述本级栅极驱动信号保持所述恒压低电平。
  17. 如权利要求10所述的显示面板，其中，所述重置电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的栅极与第二全局控制信号输入端连接，源极和漏极分别与所述恒压低电平信号输入端和所述本级栅极驱动信号输出端连接，其中，所述重置电路用于在所述第二全局控制信号输入端输入的第二全局控制信号为高电平时，将所述本级栅极驱动信号输出端输出的本级栅极驱动信号拉低至恒压低电平。
  18. 如权利要求10所述的显示面板，其中，所述驱动电路为NMOS型驱动电路。
  19. 一种显示装置，其包括如权利要求10所述的显示面板。
  20. 如权利要求19所述的显示装置，其中，在所述显示装置的正常显示阶段，所述第一全局控制信号输入端输入的信号为低电平。
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