WO2020224077A1 - 用于显示屏的驱动电路 - Google Patents

用于显示屏的驱动电路 Download PDF

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Publication number
WO2020224077A1
WO2020224077A1 PCT/CN2019/099700 CN2019099700W WO2020224077A1 WO 2020224077 A1 WO2020224077 A1 WO 2020224077A1 CN 2019099700 W CN2019099700 W CN 2019099700W WO 2020224077 A1 WO2020224077 A1 WO 2020224077A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
pull
signal
conversion
Prior art date
Application number
PCT/CN2019/099700
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English (en)
French (fr)
Inventor
薛炎
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/603,286 priority Critical patent/US10891902B2/en
Publication of WO2020224077A1 publication Critical patent/WO2020224077A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of electronic display, and in particular to a driving circuit for a display screen.
  • the horizontal scan lines of the OLED display panel are driven by an external integrated circuit.
  • An external integrated circuit can control the charging and discharging of scan lines at all levels.
  • GOA Gate Driver on Array
  • GOA Gate Driver on Array
  • the use of the GOA circuit can reduce the production cost and power consumption of the display panel, and reduce the frame width of the display device.
  • Indium gallium zinc oxide (IGZO) thin film transistors have high mobility and good stability, but their threshold voltage is prone to negative drift. In order to suppress the negative drift of the threshold voltage, multiple thin film transistors are required, which leads to a complicated design of the driving circuit of the display screen using IGZO, which is not conducive to reducing the frame width of the display panel.
  • IGZO Indium gallium zinc oxide
  • the present application provides a driving circuit for a display screen to reduce the space occupied by the layout of the driving circuit and reduce the frame width of the display panel.
  • a driving circuit for a display screen which includes:
  • An output module includes a signal bus and a signal output sub-module, the output module is used to provide a plurality of scan signals for display, the plurality of scan signals are cascaded scan signals;
  • a signal amplifying module where the signal amplifying module is used to amplify the multiple scan signals
  • a plurality of signal conversion modules are in one-to-one correspondence with the plurality of amplified scan signals, and are configured to convert each amplified scan signal into at least two row scan signals;
  • a plurality of row scan lines correspond to the plurality of row scan signals one-to-one, and are used to transmit the plurality of row scan signals to the display control circuit of the display screen.
  • the signal conversion module includes at least two secondary clock signals, and the multiple secondary clock signals have the same period and duty cycle; wherein,
  • the sum of the pulse widths of the multiple secondary clock signals is equal to the pulse width of the amplified scan signal.
  • the number of the plurality of secondary clock signals is equal to the number of the row scan signals.
  • each of the signal conversion modules includes at least a first signal conversion unit and a second signal conversion unit;
  • the first signal conversion unit includes a first conversion thin film transistor and a second conversion thin film transistor; wherein,
  • the source of the first conversion thin film transistor is connected to the first secondary clock signal, the gate is connected to the output terminal of the signal amplifying module, and the drain is connected to the source of the second conversion thin film transistor, and outputs the first line scan signal;
  • the gate of the second conversion thin film transistor is connected to the second secondary clock signal, and the drain is connected to the third DC voltage;
  • the second signal conversion unit includes a third conversion thin film transistor and a fourth conversion thin film transistor; wherein,
  • the source of the third conversion thin film transistor is connected to the second secondary clock signal, the gate is connected to the output terminal of the signal amplifying module, and the drain is connected to the source of the fourth conversion thin film transistor, and outputs a second row scan signal ;
  • the gate of the fourth conversion thin film transistor is connected to the third secondary clock signal, and the drain is connected to the third DC voltage.
  • each of the signal conversion modules further includes a third signal conversion unit, and the third signal conversion unit includes a fifth conversion thin film transistor and a sixth conversion thin film transistor;
  • the source of the fifth conversion thin film transistor is connected to the third secondary clock signal, the gate is connected to the output terminal of the signal amplifying module, and the drain is connected to the source terminal of the sixth conversion thin film transistor, and the third line scan is output signal;
  • the gate of the sixth conversion thin film transistor is connected to the first secondary clock signal, and the drain is connected to the third DC voltage.
  • the signal amplifying module includes:
  • a pull-up unit the pull-up unit is used to convert a clock signal into a stage transmission signal, and convert a DC voltage signal into an output signal;
  • a pull-up control unit the pull-up control unit is used to control the opening time of the pull-up unit
  • Bootstrap capacitor the bootstrap capacitor is used to boost the stage transmission signal and output signal voltage
  • a pull-down unit which is used to pull the output voltage of the bootstrap capacitor to a low level
  • a pull-down sustaining unit configured to pull and maintain the output voltage of the bootstrap capacitor to a low potential
  • An inverter which is used to make the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down sustaining unit opposite;
  • the feedback unit is used to increase the output voltage of the pull-down unit.
  • the pull-up unit includes a first pull-up unit and a second pull-up unit
  • the first pull-up unit includes a first pull-up thin film transistor and a second pull-up thin film transistor; wherein,
  • the source of the first pull-up thin film transistor is connected to a first direct current voltage, the drain is connected to a plate of the bootstrap capacitor, and the gate is connected to the gate of the second pull-up thin film transistor;
  • the source electrode of the second pull-up thin film transistor is connected to the first direct current voltage, the drain electrode is connected to the other plate of the bootstrap capacitor, and the gate electrode is connected to the previous stage transmission signal;
  • the second pull-up unit includes a third pull-up thin film transistor, the source of the third pull-up thin film transistor is connected to the second clock signal, the gate is connected to a plate of the bootstrap capacitor, and the drain is connected to the The other plate of the bootstrap capacitor.
  • the pull-up control unit includes a first control thin film transistor and a second control thin film transistor; wherein,
  • the source of the first control thin film transistor is connected to the previous stage transmission signal, the gate is connected to the first clock signal, and the drain is connected to the source of the second control thin film transistor;
  • the gate of the second control thin film transistor is connected to the first clock signal, and the drain is connected to the pull-down sustain unit.
  • the pull-down unit includes a first pull-down unit and a second pull-down unit; wherein,
  • the first pull-down unit includes a first pull-down thin film transistor, the source of the first pull-down thin film transistor is connected to the first pull-up unit, the gate is connected to the next stage signal, and the drain is connected to the The third DC voltage;
  • the second pull-down unit includes a second pull-down thin film transistor and a third pull-down thin film transistor;
  • the source of the second pull-down thin film transistor is connected to the second pull-up unit, the gate is connected to the next-stage stage signal, and the drain is connected to the source of the third pull-down thin film transistor;
  • the gate of the third pull-down thin film transistor is connected to the next stage signal, and the drain is connected to the third DC voltage.
  • the inverter includes a first inverter and a second inverter; wherein,
  • the first inverter includes a first reverse thin film transistor, a second reverse thin film transistor, a third reverse thin film transistor, and a fourth reverse thin film transistor;
  • the source and gate of the first reverse thin film transistor are connected to the second pull-down unit, and the drain is connected to the source of the second reverse thin film transistor;
  • the gate of the second reverse thin film transistor is connected to the second pull-down unit, and the drain is connected to the third DC voltage;
  • the source of the third reverse thin film transistor is connected to the second pull-down unit, the gate is connected to the drain of the first reverse thin film transistor, and the drain is connected to the source of the fourth reverse thin film transistor;
  • the gate of the fourth reverse thin film transistor is connected to the gate of the second reverse thin film transistor, and the drain is connected to the third direct current voltage;
  • the second inverter includes a fifth reverse thin film transistor, a sixth reverse thin film transistor, a seventh reverse thin film transistor, and an eighth reverse thin film transistor;
  • the gate and source of the fifth reverse thin film transistor are connected to the feedback unit, and the drain is connected to the source of the sixth reverse thin film transistor;
  • the gate of the sixth reverse thin film transistor is connected to the second pull-up unit, and the drain is connected to the third DC voltage;
  • the source of the seventh reverse thin film transistor is connected to the feedback unit, the gate is connected to the drain of the fifth reverse thin film transistor, and the drain is connected to the source of the eighth reverse thin film transistor;
  • the gate of the eighth reverse thin film transistor is connected to the gate of the sixth reverse thin film transistor, and the drain is connected to the third DC voltage.
  • the feedback unit includes a feedback thin film transistor, the source of the feedback thin film transistor is connected to the first pull-up unit, the drain is connected to the pull-up control unit, and the gate is connected to the current stage.
  • Level transmission signal the source of the feedback thin film transistor is connected to the first pull-up unit, the drain is connected to the pull-up control unit, and the gate is connected to the current stage.
  • the bootstrap capacitor includes a first storage capacitor and a second storage capacitor; wherein,
  • One plate of the first storage capacitor is connected to the first pull-up unit, and the other plate is connected to the pull-down maintenance unit;
  • One plate of the first storage capacitor is connected to the second pull-up unit, and the other plate is connected to the second pull-down unit.
  • each of the signal conversion modules includes at least a first signal conversion unit and a second signal conversion unit;
  • the first signal conversion unit includes a first conversion thin film transistor and a second conversion thin film transistor; wherein,
  • the source of the first conversion thin film transistor is connected to the first secondary clock signal, the gate is connected to the output terminal of the signal amplifying module, and the drain is connected to the source of the second conversion thin film transistor, and outputs the first line scan signal;
  • the gate of the second conversion thin film transistor is connected to the second secondary clock signal, and the drain is connected to the third DC voltage;
  • the second signal conversion unit includes a third conversion thin film transistor and a fourth conversion thin film transistor; wherein,
  • the source of the third conversion thin film transistor is connected to the second secondary clock signal, the gate is connected to the output terminal of the signal amplifying module, and the drain is connected to the source of the fourth conversion thin film transistor, and outputs a second row scan signal ;
  • the gate of the fourth conversion thin film transistor is connected to the third secondary clock signal, and the drain is connected to the third DC voltage.
  • each of the signal conversion modules further includes a third signal conversion unit, and the third signal conversion unit includes a fifth conversion thin film transistor and a sixth conversion thin film transistor;
  • the source of the fifth conversion thin film transistor is connected to the third secondary clock signal, the gate is connected to the output terminal of the signal amplifying module, and the drain is connected to the source terminal of the sixth conversion thin film transistor, and the third line scan is output signal;
  • the gate of the sixth conversion thin film transistor is connected to the first secondary clock signal, and the drain is connected to the third DC voltage.
  • the driving circuit of the present application and the driving circuit can drive three row scan lines, the space occupied by the layout of the driving circuit is greatly reduced, and the frame width of the display panel can be further reduced.
  • FIG. 1 is a schematic structural diagram of a driving circuit for driving a display screen in the prior art
  • FIG. 2 is a schematic structural diagram of a driving circuit for driving a display screen in a specific embodiment of the application
  • FIG. 3 is a circuit diagram of a signal amplifying module in a driving circuit in a specific embodiment of the application;
  • FIG. 4 is a circuit diagram of a signal conversion module in a driving circuit in a specific embodiment of the application.
  • FIG. 5 is a schematic diagram of simulation results of the driving circuit in a specific embodiment of the application.
  • FIG. 6 is a timing diagram of the correlation between the secondary clock signal and the output line scan signal in a specific embodiment of the application.
  • FIG. 1 is a schematic structural diagram of a driving circuit for driving a display screen in the prior art.
  • the driving circuit in the prior art is a structure in which a first-level driving circuit drives a first-level row scan line. This design structure occupies too much area, which is not conducive to reducing the frame width of the display panel.
  • FIG. 2 is a schematic structural diagram of a driving circuit for driving a display screen in a specific embodiment of the application.
  • the first-level driving circuit can drive the third-level row scan lines, which greatly reduces the layout area occupied by the driving circuit.
  • the driving circuit shown includes: an output module, the output module includes a signal bus and a signal output sub-module, the output module is used to provide a plurality of scanning signals for display, the plurality of scanning
  • the signal is a cascaded scan signal.
  • a signal amplifying module which is used to amplify the multiple scanning signals.
  • a plurality of signal conversion modules, the plurality of signal conversion modules correspond to the plurality of amplified scanning signals one-to-one, and are used for converting each amplified scanning signal into at least two horizontal scanning signals.
  • a plurality of row scan lines, the plurality of row scan lines correspond to the plurality of row scan signals one-to-one, and are used to transmit the plurality of row scan signals to the display control circuit of the display screen.
  • the signal conversion module includes at least two secondary clock signals, the multiple secondary clock signals have the same period and duty ratio, and the number of the multiple secondary clock signals is equal to the number of the row scan signals . Wherein, the sum of the pulse widths of the multiple secondary clock signals is equal to the pulse width of the amplified scanning signal.
  • FIG. 6 is a timing diagram of the correlation between the secondary clock signal and the output line scan signal in a specific embodiment of the application.
  • the number of the secondary clock signals is three, and the sum of the pulse widths of the three secondary clock signals is equal to the pulse width of the amplified scan signal.
  • each of the signal conversion modules includes at least a first signal conversion unit and a second signal conversion unit.
  • the first signal conversion unit includes a first conversion thin film transistor Ta1 and a second conversion thin film transistor Ta2.
  • the source of the first conversion thin film transistor Ta1 is connected to the first secondary clock signal
  • the gate is connected to the output terminal of the signal amplifying module
  • the drain is connected to the source terminal of the second conversion thin film transistor Ta2 and outputs The first line scan signal.
  • the gate of the second conversion thin film transistor Ta2 is connected to the second secondary clock signal, and the drain is connected to the third DC voltage.
  • the second signal conversion unit includes a third conversion thin film transistor Ta3 and a fourth conversion thin film transistor Ta4.
  • the source of the third conversion thin film transistor Ta3 is connected to the second secondary clock signal
  • the gate is connected to the output terminal of the signal amplifying module
  • the drain is connected to the source of the fourth conversion thin film transistor Ta4, and outputs the first Two-line scanning signal.
  • the gate of the fourth conversion thin film transistor Ta4 is connected to the third secondary clock signal, and the drain is connected to the third DC voltage.
  • each of the signal conversion modules further includes a third signal conversion unit
  • the third signal conversion unit includes a fifth conversion thin film transistor Ta5 and a sixth conversion thin film transistor Ta6.
  • the source of the fifth conversion thin film transistor Ta5 is connected to the third secondary clock signal
  • the gate is connected to the output end of the signal amplifying module
  • the drain is connected to the source end of the sixth conversion thin film transistor Ta6 and outputs The third line scan signal.
  • the gate of the sixth conversion thin film transistor Ta6 is connected to the first secondary clock signal, and the drain is connected to the third DC voltage.
  • the signal amplifying module includes: a pull-up unit M2, the pull-up unit M2 is used to convert a clock signal into a stage transmission signal, and a DC voltage signal into an output signal; a pull-up control unit M1, the pull-up The control unit M1 is used to control the open time of the pull-up unit M2; a bootstrap capacitor, the bootstrap capacitor is used to raise the stage transmission signal and output signal voltage; the pull-down unit M3, the pull-down unit M3 is used to The output voltage of the bootstrap capacitor is pulled down to a low level; the pull-down sustain unit M4 is used to pull and maintain the output voltage of the bootstrap capacitor to a low level; the inverter M5 is used for In order to make the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down sustaining unit M4 opposite; and a feedback unit M6, the feedback
  • the pull-up unit M2 includes a first pull-up unit M21 and a second pull-up unit M22.
  • the first pull-up unit M21 includes a first pull-up thin film transistor T21 and a second pull-up thin film transistor T22.
  • the source of the first pull-up thin film transistor T21 is connected to the first DC voltage
  • the drain is connected to a plate of the bootstrap capacitor
  • the gate is connected to the gate of the second pull-up thin film transistor T22.
  • the source of the second pull-up thin film transistor T22 is connected to the first direct current voltage
  • the drain is connected to the other plate of the bootstrap capacitor
  • the gate is connected to the previous stage signal.
  • the second pull-up unit M22 includes a third pull-up thin film transistor, the source of the third pull-up thin film transistor is connected to the second clock signal, the gate is connected to a plate of the bootstrap capacitor, and the drain is connected to the The other plate of the bootstrap capacitor is described.
  • the pull-up control unit M1 includes a first control thin film transistor T11 and a second control thin film transistor T12. Wherein, the source of the first control thin film transistor T11 is connected to the previous stage transmission signal, the gate is connected to the first clock signal, and the drain is connected to the source of the second control thin film transistor T12; the second control The gate of the thin film transistor T12 is connected to the first clock signal, and the drain is connected to the pull-down sustain unit M4.
  • the first control thin film transistor T11 and the second control thin film transistor T12 are N-type thin film transistors.
  • the pull-down unit M3 includes a first pull-down unit M31 and a second pull-down unit M32.
  • the first pull-down unit M31 includes a first pull-down thin film transistor T31
  • the source of the first pull-down thin film transistor T31 is connected to the first pull-up unit M21
  • the gate is connected to the next stage pass Signal
  • the drain is connected to the third DC voltage VGL.
  • the second pull-down unit M32 includes a second pull-down thin film transistor T32 and a third pull-down thin film transistor T33.
  • the source of the second pull-down thin film transistor T32 is connected to the bootstrap capacitor, the gate is connected to the next stage signal, and the drain is connected to the source of the third pull-down thin film transistor T33.
  • the gate of the third pull-down thin film transistor T33 is connected to the next-stage stage signal, and the drain is connected to the third DC voltage VGL.
  • the first pull-down thin film transistor T31 and the third pull-down thin film transistor T33 are N-type thin film transistors, and the second pull-down thin film transistor T32 is a P-type thin film transistor.
  • the pull-down maintenance unit M4 includes a first pull-down maintenance unit M41 and a second pull-down maintenance unit M42.
  • the first pull-down sustain unit M41 includes a first sustain thin film transistor T41 and a second sustain thin film transistor T42.
  • the source of the first sustaining thin film transistor T41 is connected to the first pull-up unit M21, the gate is connected to the inverter, and the drain is connected to the third DC voltage VGL.
  • the source of the second sustain thin film transistor T42 is connected to the second pull-up unit M22, and the drain is connected to the third DC voltage VGL.
  • the second pull-down sustain unit M42 includes a fourth sustain thin film transistor T44 and a fifth sustain thin film transistor T45.
  • the source of the fourth sustain thin film transistor T44 is connected to the pull-up control unit M1, the gate is connected to the inverter M5, and the drain is connected to the source of the fifth sustain thin film transistor T45.
  • the gate of the fifth sustain thin film transistor T45 is connected to the inverter M5, and the drain is connected to the third DC voltage VGL.
  • the inverter M5 includes a first inverter M51 and a second inverter M52.
  • the first inverter M51 includes a first reverse thin film transistor T51, a second reverse thin film transistor T52, a third reverse thin film transistor T53, and a fourth reverse thin film transistor T54.
  • the source and gate of the first reverse thin film transistor T51 are connected to the second pull-down unit M32, and the drain is connected to the source of the second reverse thin film transistor T52.
  • the gate of the second reverse thin film transistor T52 is connected to the second pull-down unit M32, and the drain is connected to the third DC voltage VGL.
  • the source of the third reverse thin film transistor T53 is connected to the second pull-down unit M32, the gate is connected to the drain of the first reverse thin film transistor T51, and the drain is connected to the fourth reverse thin film transistor T54. Source.
  • the gate of the fourth reverse thin film transistor T54 is connected to the gate of the second reverse thin film transistor T52, and the drain is connected to the third DC voltage VGL.
  • the second inverter M52 includes a fifth reverse thin film transistor T55, a sixth reverse thin film transistor T56, a seventh reverse thin film transistor T57, and an eighth reverse thin film transistor T58.
  • the gate and source of the fifth reverse thin film transistor T55 are connected to the feedback unit M6, and the drain is connected to the source of the sixth reverse thin film transistor T56.
  • the gate of the sixth reverse thin film transistor T56 is connected to the second pull-up unit M22, and the drain is connected to the third DC voltage VGL.
  • the source of the seventh reverse thin film transistor T57 is connected to the feedback unit M6, the gate is connected to the drain of the fifth reverse thin film transistor T55, and the drain is connected to the source of the eighth reverse thin film transistor T58. .
  • the gate of the eighth reverse thin film transistor T58 is connected to the gate of the sixth reverse thin film transistor T56, and the drain is connected to the third DC voltage VGL.
  • the feedback unit M6 includes a feedback thin film transistor T6.
  • the source of the feedback thin film transistor T6 is connected to the first pull-up unit M21, the drain is connected to the pull-up control unit M1, and the gate is connected to the stage transmission signal of the current stage.
  • the feedback thin film transistor T6 is an N-type thin film transistor.
  • the bootstrap capacitor includes a first storage capacitor Cbt1 and a second storage capacitor Cbt2. Wherein, one plate of the first storage capacitor Cbt1 is connected to the first pull-up unit M21, and the other plate is connected to the pull-down maintenance unit M4. One plate of the second storage capacitor Cbt2 is connected to the second pull-up unit M22, and the other plate is connected to the second pull-down unit M32.
  • Each of the signal conversion modules includes at least a first signal conversion unit, a second signal conversion unit, and a third signal conversion unit.
  • the first signal conversion unit includes a first conversion thin film transistor Ta1 and a second conversion thin film transistor Ta2.
  • the source of the first conversion thin film transistor Ta1 is connected to the first secondary clock signal
  • the gate is connected to the output terminal of the signal amplifying module
  • the drain is connected to the source terminal of the second conversion thin film transistor Ta2 and outputs The first line scan signal.
  • the gate of the second conversion thin film transistor Ta2 is connected to the second secondary clock signal, and the drain is connected to the third DC voltage.
  • the second signal conversion unit includes a third conversion thin film transistor Ta3 and a fourth conversion thin film transistor Ta4.
  • the source of the third conversion thin film transistor Ta3 is connected to the second secondary clock signal
  • the gate is connected to the output terminal of the signal amplifying module
  • the drain is connected to the source of the fourth conversion thin film transistor Ta4, and outputs the first Two-line scanning signal.
  • the gate of the fourth conversion thin film transistor Ta4 is connected to the third secondary clock signal, and the drain is connected to the third DC voltage.
  • the third signal conversion unit includes a fifth conversion thin film transistor Ta5 and a sixth conversion thin film transistor Ta6.
  • the source of the fifth conversion thin film transistor Ta5 is connected to the third secondary clock signal
  • the gate is connected to the output end of the signal amplifying module
  • the drain is connected to the source end of the sixth conversion thin film transistor Ta6 and outputs The third line scan signal.
  • the gate of the sixth conversion thin film transistor Ta6 is connected to the first secondary clock signal, and the drain is connected to the third DC voltage.
  • FIG. 5 is a schematic diagram of the simulation results of the driving circuit in a specific embodiment of the application
  • FIG. 6 is the relationship between the secondary clock signal and the output line scan signal in a specific embodiment of the application. The associated timing diagram.
  • CK1 is the first clock signal
  • CK2 is the second clock signal
  • the waveforms of the first clock signal CK1 and the second clock signal CK2 are opposite.
  • XCK1 is the first secondary clock signal
  • XCK2 is the second secondary clock signal
  • XCK3 is the third secondary clock signal.
  • OUTm(n) is the output signal of this level.
  • OUT(n) is the level transmission signal of this level;
  • OUT(n-1) is the level transmission signal of the upper level;
  • OUT(n+1) is the level transmission signal of the next level.
  • the working cycle of the driving circuit in this embodiment includes a first phase T1, a second phase T2, and a third phase T3.
  • the first control thin film transistor T11 and the second control thin film transistor T12 are turned on, OUT(n-1) is a high potential, and the potential of point Q is raised to a high potential.
  • the fourth pull-up thin film transistor T24, the second reverse thin film transistor T52, and the fourth reverse thin film transistor T54 are turned on, and QB is pulled down to a low potential.
  • the transistor T45 and the sixth sustain thin film transistor T46 are turned off. Since the second clock signal CK2 is at a low level, the stage transfer signal OUT(n) of this stage is at a low level.
  • the sixth reverse thin film transistor T56 and the eighth reverse thin film transistor T58 Turn off, point P is pulled up to a high potential, the first sustaining thin film transistor T41 and the second sustaining thin film transistor T42 are turned on, and the previous stage transfer signal OUT (n-1) is a high potential, the third pull-up thin film transistor T23 is turned on, the potential at point M is pulled to a high potential, the first pull-up thin film transistor T21 and the second pull-up thin film transistor T22 are turned on, because the second sustain thin film transistor T42 When the first sustaining thin film transistor T41 is turned on, point N and the amplified signal Outm(n) still maintain a low potential.
  • the second stage when the first clock signal CK1 is at a low level, the first control thin film transistor T11 and the second control thin film transistor T12 are turned off, the fourth pull-up thin film transistor T24 is turned on, CK2 becomes high, and the level signal OUT (n) becomes a high potential. Therefore, the potential of point Q is pulled up to a higher potential, which is beneficial to turning on the fourth pull-up thin film transistor T24.
  • the feedback thin film transistor T6, the sixth reverse thin film transistor T56, and the eighth reverse thin film transistor T58 are turned on, and the point F rises to a high potential, which is beneficial to reduce the second control thin film transistor T12.
  • the fifth sustaining thin film transistors T45 and T32 leak current and maintain the potential at point Q.
  • Point P drops to a low potential.
  • the first sustain thin film transistor T41 and the second sustain thin film transistor T42 are turned off, and the point N is raised to a high potential. Due to the existence of the second storage capacitor Cbt2, the potential at point M is pulled up to a higher potential.
  • the first pull-up thin film transistor T21 and the second pull-up thin film transistor T22 are turned on, and the potential at point N and the output signal gradually rise to a high potential.
  • the amplified signal Outm(n) rises to a high level.
  • the first clock signal CK1 rises to a high potential
  • the first control thin film transistor T11 and the second control thin film transistor T12 are turned on, because the previous stage transfer signal OUT(n-1) is at a low potential, point Q The potential is pulled down to a low potential.
  • the fourth pull-up thin film transistor T24, the second reverse thin film transistor T52, and the fourth reverse thin film transistor T54 are turned off, and the QB point rises to a high potential.
  • the third sustain thin film transistor T43, the fourth sustain thin film transistor T44, the fifth sustain thin film transistor T45, and the sixth sustain thin film transistor T46 are turned on, and the stage transfer signal OUT(n) drops to a low level.
  • the sixth reverse thin film transistor T56, the eighth reverse thin film transistor T58 and the feedback thin film transistor T6 are turned off, and point P rises to a high potential.
  • the first sustaining thin film transistor T41 and the second sustaining thin film transistor T42 are turned on, and the level transfer signal OUT(n+1) of the next stage rises to a high level.
  • T31 is turned on, and the level transmission signal Out(n) and the amplified signal Outm(n) drop to low level.
  • the driving circuit of the present application and the driving circuit can drive three row scan lines, the space occupied by the layout of the driving circuit is greatly reduced, and the frame width of the display panel can be further reduced.

Abstract

本申请提供一种用于显示屏的驱动电路，其包括：输出模块、信号放大模块、多个信号转换模块、以及多个行扫描线。所述输出模块用于提供用于显示的多个扫描信号。所述信号放大模块用于对所述多个扫描信号进行放大。所述多个信号转换模用于将每一个放大后的扫描信号转换为至少两个行扫描信号。所述多个行扫描线用于将所述多个行扫描信号传递给显示屏的显示控制电路。

Description

用于显示屏的驱动电路 技术领域
本申请涉及电子显示领域，尤其涉及一种用于显示屏的驱动电路。
 背景技术
目前，OLED显示面板的水平扫描线由外接集成电路驱动。外接集成电路可以控制各级扫描线的充电与放电。GOA(Gate Driver on Array)可以将行扫描驱动电路集成在显示面板的阵列基板上，显著的减少了外接集成电路的使用量。采用GOA电路能够降低显示面板的生产成本以及功耗，并且减小显示装置的边框宽度。
 技术问题
铟镓锌氧化物(indium gallium zinc oxide, IGZO)薄膜晶体管具有高迁移率和良好的稳定性，但其阈值电压容易负向漂移。为了抑制阈值电压的负向漂移，需要采用多个薄膜晶体管，导致应用IGZO的显示屏的驱动电路设计复杂，不利于减小显示面板的边框宽度。
因此，有必要对应用IGZO的显示屏的驱动电路进行优化，以减少GOA电路版图所占空间。
 技术解决方案
本申请提供一种用于显示屏的驱动电路，以减少驱动电路的版图占用的空间，减小显示面板的边框宽度。
为解决上述问题，本申请提供了一种用于显示屏的驱动电路，其包括：
输出模块，所述输出模块包括信号总线和信号输出子模块，所述输出模块用于提供用于显示的多个扫描信号，所述多个扫描信号为级联的扫描信号；
信号放大模块，所述信号放大模块用于对所述多个扫描信号进行放大；
多个信号转换模块，所述多个信号转换模块与所述多个放大后的扫描信号一一对应，用于将每一个放大后的扫描信号转换为至少两个行扫描信号；以及
多个行扫描线，所述多个行扫描线与所述多个行扫描信号一一对应，用于将所述多个行扫描信号传递给显示屏的显示控制电路。
根据本申请的其中一个方面，所述信号转换模块包括至少两个次级时钟信号，所述多个次级时钟信号具有相同的周期和占空比；其中，
所述多个次级时钟信号的脉冲宽度之和等于所述放大后的扫描信号的脉冲宽度。
根据本申请的其中一个方面，所述多个次级时钟信号的数目等于所述行扫描信号的数目。
根据本申请的其中一个方面，所述每一个所述信号转换模块包括至少包括第一信号转换单元和第二信号转换单元；
所述第一信号转换单元包括第一转换薄膜晶体管和第二转换薄膜晶体管；其中，
所述第一转换薄膜晶体管的源极连接第一次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第二转换薄膜晶体管的源端，并输出第一行扫描信号；
所述第二转换薄膜晶体管的栅极连接第二次级时钟信号，漏极连接第三直流电压；
所述第二信号转换单元包括第三转换薄膜晶体管和第四转换薄膜晶体管；其中，
所述第三转换薄膜晶体管源极连接第二次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第四转换薄膜晶体管的源端，并输出第二行扫描信号；
所述第四转换薄膜晶体管的栅极连接第三次级时钟信号，漏极连接第三直流电压。
根据本申请的其中一个方面，每一个所述信号转换模块还包括第三信号转换单元，所述第三信号转换单元包括第五转换薄膜晶体管和第六转换薄膜晶体管；其中，
所述第五转换薄膜晶体管的源极连接第三次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第六转换薄膜晶体管的源端，并输出第三行扫描信号；
所述第六转换薄膜晶体管的栅极连接第一次级时钟信号，漏极连接第三直流电压。
根据本申请的其中一个方面，所述信号放大模块包括：
上拉单元，所述上拉单元用于将时钟信号转换为级传信号，将直流电压信号转换为输出信号；
上拉控制单元，所述上拉控制单元用于控制所述上拉单元的打开时间；
自举电容，所述自举电容用于抬升所述级传信号和输出信号电压；
下拉单元，所述下拉单元用于将自举电容的输出电压拉低为低电位；
下拉维持单元，所述下拉维持单元用于将自举电容的输出电压拉保持为低电位；
反相器，所述反相器用于使所述自举电容的输出电压和下拉维持单元的输出电压电位相反；以及
反馈单元，所述反馈单元用于提高下拉单元的输出电压。
根据本申请的其中一个方面，所述上拉单元包括第一上拉单元和第二上拉单元；
所述第一上拉单元包括第一上拉薄膜晶体管和第二上拉薄膜晶体管；其中，
所述第一上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述自举电容的一个极板，栅极连接第二上拉薄膜晶体管的栅极；
所述第二上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述自举电容的另一个极板，栅极连接上一级的级传信号；
所述第二上拉单元包括第三上拉薄膜晶体管，所述第三上拉薄膜晶体管的源极连接第二时钟信号，栅极连接所述自举电容的一个极板，漏极连接所述自举电容的另一个极板。
根据本申请的其中一个方面，所述上拉控制单元包括第一控制薄膜晶体管和第二控制薄膜晶体管；其中，
所述第一控制薄膜晶体管的源极连接上一级的级传信号，栅极连接第一时钟信号，漏极连接所述第二控制薄膜晶体管的源极；
所述第二控制薄膜晶体管的栅极连接所述第一时钟信号，漏极连接所述下拉维持单元。
根据本申请的其中一个方面，所述下拉单元包括第一下拉单元和第二下拉单元；其中，
所述第一下拉单元包括第一下拉薄膜晶体管，所述第一下拉薄膜晶体管的源极连接所述第一上拉单元，栅极连接下一级的级传信号，漏极连接所述第三直流电压；
所述第二下拉单元包括第二下拉薄膜晶体管和第三下拉薄膜晶体管；
所述第二下拉薄膜晶体管的源极连接所述第二上拉单元，栅极连接下一级的级传信号，漏极连接所述第三下拉薄膜晶体管的源极；
所述第三下拉薄膜晶体管的栅极连接下一级的级传信号，漏极连接所述第三直流电压。
根据本申请的其中一个方面，所述反相器包括第一反相器和第二反相器；其中，
所述第一反相器包括第一反向薄膜晶体管、第二反向薄膜晶体管、第三反向薄膜晶体管和第四反向薄膜晶体管；
所述第一反向薄膜晶体管的源极和栅极连接所述第二下拉单元，漏极连接所述第二反向薄膜晶体管的源极；
所述第二反向薄膜晶体管的栅极连接所述第二下拉单元，漏极连接所述第三直流电压；
所述第三反向薄膜晶体管的源极连接所述第二下拉单元，栅极连接所述第一反向薄膜晶体管的漏极，漏极连接所述第四反向薄膜晶体管的源极；
所述第四反向薄膜晶体管的栅极连接所述第二反向薄膜晶体管的栅极，漏极连接所述第三直流电压；
所述第二反相器包括第五反向薄膜晶体管、第六反向薄膜晶体管、第七反向薄膜晶体管和第八反向薄膜晶体管；
所述第五反向薄膜晶体管的栅极和源极连接所述反馈单元，漏极连接所述第六反向薄膜晶体管的源极；
所述第六反向薄膜晶体管的栅极连接所述第二上拉单元，漏极连接所述第三直流电压；
所述第七反向薄膜晶体管的源极连接所述反馈单元，栅极连接所述第五反向薄膜晶体管的漏极，漏极连接所述第八反向薄膜晶体管的源极；
所述第八反向薄膜晶体管的栅极连接所述第六反向薄膜晶体管的栅极，漏极连接所述第三直流电压。
根据本申请的其中一个方面，所述反馈单元包括反馈薄膜晶体管，所述反馈薄膜晶体管的源极连接所述第一上拉单元，漏极连接所述上拉控制单元，栅极连接本级的级传信号。
根据本申请的其中一个方面，所述自举电容包括第一存储电容和第二存储电容；其中，
所述第一存储电容的一个极板连接所述第一上拉单元，另一个极板连接所述下拉维持单元；
所述第一存储电容的一个极板连接所述第二上拉单元，另一个极板连接所述第二下拉单元。
根据本申请的其中一个方面，每一个所述信号转换模块包括至少包括第一信号转换单元和第二信号转换单元；
所述第一信号转换单元包括第一转换薄膜晶体管和第二转换薄膜晶体管；其中，
所述第一转换薄膜晶体管的源极连接第一次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第二转换薄膜晶体管的源端，并输出第一行扫描信号；
所述第二转换薄膜晶体管的栅极连接第二次级时钟信号，漏极连接第三直流电压；
所述第二信号转换单元包括第三转换薄膜晶体管和第四转换薄膜晶体管；其中，
所述第三转换薄膜晶体管源极连接第二次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第四转换薄膜晶体管的源端，并输出第二行扫描信号；
所述第四转换薄膜晶体管的栅极连接第三次级时钟信号，漏极连接第三直流电压。
根据本申请的其中一个方面，每一个所述信号转换模块还包括第三信号转换单元，所述第三信号转换单元包括第五转换薄膜晶体管和第六转换薄膜晶体管；其中，
所述第五转换薄膜晶体管的源极连接第三次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第六转换薄膜晶体管的源端，并输出第三行扫描信号；
所述第六转换薄膜晶体管的栅极连接第一次级时钟信号，漏极连接第三直流电压。
 有益效果
本申请的驱动电路中，以及驱动电路能够驱动三条行扫描线，大大减少了驱动电路的版图占用的空间，能够进一步减小显示面板的边框宽度。
 附图说明
图1为现有技术中的用于驱动显示屏的驱动电路的结构示意图；
图2为本申请的一个具体实施例中的用于驱动显示屏的驱动电路的结构示意图；
图3为本申请的一个具体实施例中的驱动电路中的信号放大模块的电路图；
图4为本申请的一个具体实施例中的驱动电路中的信号转换模块的电路图；
图5为本申请的一个具体实施例中的驱动电路的仿真结果示意图；
图6为本申请的一个具体实施例中的次级时钟信号和输出的行扫描信号之间的关联时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
参见图1，图1为现有技术中的用于驱动显示屏的驱动电路的结构示意图。现有技术的驱动电路为一级驱动电路驱动一级行扫描线的架构，这种设计架构占用的面积太大，不利于减小显示面板的边框宽度。
参见图2，图2为本申请的一个具体实施例中的用于驱动显示屏的驱动电路的结构示意图。如图2所示，本申请的驱动电路中，一级驱动电路能够驱动三级行扫描线，极大的减小了驱动电路占用的版图面积。
具体的，参见图2，所示驱动电路包括：输出模块，所述输出模块包括信号总线和信号输出子模块，所述输出模块用于提供用于显示的多个扫描信号，所述多个扫描信号为级联的扫描信号。信号放大模块，所述信号放大模块用于对所述多个扫描信号进行放大。多个信号转换模块，所述多个信号转换模块与所述多个放大后的扫描信号一一对应，用于将每一个放大后的扫描信号转换为至少两个行扫描信号。以及多个行扫描线，所述多个行扫描线与所述多个行扫描信号一一对应，用于将所述多个行扫描信号传递给显示屏的显示控制电路。
所述信号转换模块包括至少两个次级时钟信号，所述多个次级时钟信号具有相同的周期和占空比，且所述多个次级时钟信号的数目等于所述行扫描信号的数目。其中，所述多个次级时钟信号的脉冲宽度之和等于所述放大后的扫描信号的脉冲宽度。
参见图 6，图6为本申请的一个具体实施例中的次级时钟信号和输出的行扫描信号之间的关联时序图。如图6所示，在本实施例中，所述次级时钟信号的数目为三个，所述三个次级时钟信号的脉冲宽度之和等于所述放大后的扫描信号的脉冲宽度。
参见图4，图4为本申请的一个具体实施例中的驱动电路中的信号转换模块的电路图。其中，所述每一个所述信号转换模块包括至少包括第一信号转换单元和第二信号转换单元。
所述第一信号转换单元包括第一转换薄膜晶体管Ta1和第二转换薄膜晶体管Ta2。其中，所述第一转换薄膜晶体管Ta1的源极连接第一次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第二转换薄膜晶体管Ta2的源端，并输出第一行扫描信号。所述第二转换薄膜晶体管Ta2的栅极连接第二次级时钟信号，漏极连接第三直流电压。
所述第二信号转换单元包括第三转换薄膜晶体管Ta3和第四转换薄膜晶体管Ta4。其中，所述第三转换薄膜晶体管Ta3源极连接第二次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第四转换薄膜晶体管Ta4的源端，并输出第二行扫描信号。所述第四转换薄膜晶体管Ta4的栅极连接第三次级时钟信号，漏极连接第三直流电压。
优选的，每一个所述信号转换模块还包括第三信号转换单元，所述第三信号转换单元包括第五转换薄膜晶体管Ta5和第六转换薄膜晶体管Ta6。其中，所述第五转换薄膜晶体管Ta5的源极连接第三次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第六转换薄膜晶体管Ta6的源端，并输出第三行扫描信号。所述第六转换薄膜晶体管Ta6的栅极连接第一次级时钟信号，漏极连接第三直流电压。
在本实施例中，参见图3，图3为本申请的一个具体实施例中的驱动电路中的信号放大模块的电路图。其中，所述信号放大模块包括：上拉单元M2，所述上拉单元M2用于将时钟信号转换为级传信号，将直流电压信号转换为输出信号；上拉控制单元M1，所述上拉控制单元M1用于控制所述上拉单元M2的打开时间；自举电容，所述自举电容用于抬升所述级传信号和输出信号电压；下拉单元M3，所述下拉单元M3用于将自举电容的输出电压拉低为低电位；下拉维持单元M4，所述下拉维持单元M4用于将自举电容的输出电压拉保持为低电位；反相器M5，所述反相器M5用于使所述自举电容的输出电压和下拉维持单元M4的输出电压电位相反；以及反馈单元M6，所述反馈单元M6用于提高下拉单元M3的输出电压。
本实施例中，所述上拉单元M2包括第一上拉单元M21和第二上拉单元M22.
所述第一上拉单元M21包括第一上拉薄膜晶体管T21和第二上拉薄膜晶体管T22。其中，所述第一上拉薄膜晶体管T21的源极连接第一直流电压，漏极连接所述自举电容的一个极板，栅极连接第二上拉薄膜晶体管T22的栅极。所述第二上拉薄膜晶体管T22的源极连接第一直流电压，漏极连接所述自举电容的另一个极板，栅极连接上一级的级传信号。
所述第二上拉单元M22包括第三上拉薄膜晶体管，所述第三上拉薄膜晶体管的源极连接第二时钟信号，栅极连接所述自举电容的一个极板，漏极连接所述自举电容的另一个极板。
所述上拉控制单元M1包括第一控制薄膜晶体管T11和第二控制薄膜晶体管T12。其中，所述第一控制薄膜晶体管T11的源极连接上一级的级传信号，栅极连接第一时钟信号，漏极连接所述第二控制薄膜晶体管T12的源极；所述第二控制薄膜晶体管T12的栅极连接所述第一时钟信号，漏极连接所述下拉维持单元M4。
所述第一控制薄膜晶体管T11和第二控制薄膜晶体管T12为N型薄膜晶体管。
所述下拉单元M3包括第一下拉单元M31和第二下拉单元M32。其中，所述第一下拉单元M31包括第一下拉薄膜晶体管T31，所述第一下拉薄膜晶体管T31的源极连接所述第一上拉单元M21，栅极连接下一级的级传信号，漏极连接所述第三直流电压VGL。所述第二下拉单元M32包括第二下拉薄膜晶体管T32和第三下拉薄膜晶体管T33。所述第二下拉薄膜晶体管T32的源极连接所述自举电容，栅极连接下一级的级传信号，漏极连接所述第三下拉薄膜晶体管T33的源极。所述第三下拉薄膜晶体管T33的栅极连接下一级的级传信号，漏极连接所述第三直流电压VGL。
优选的，所述第一下拉薄膜晶体管T31和第三下拉薄膜晶体管T33为N型薄膜晶体管，所述第二下拉薄膜晶体管T32为P型薄膜晶体管。
所述下拉维持单元M4包括第一下拉维持单元M41和第二下拉维持单元M42。其中，所述第一下拉维持单元M41包括第一维持薄膜晶体管T41和第二维持薄膜晶体管T42。所述第一维持薄膜晶体管T41的源极连接所述第一上拉单元M21，栅极连接所述反相器，漏极连接所述第三直流电压VGL。所述第二维持薄膜晶体管T42的源极连接所述第二上拉单元M22，漏极连接所述第三直流电压VGL。所述第二下拉维持单元M42包括第四维持薄膜晶体管T44和第五维持薄膜晶体管T45。所述第四维持薄膜晶体管T44的源极连接所述上拉控制单元M1，栅极连接所述反相器M5，漏极连接所述第五维持薄膜晶体管T45的源极。所述第五维持薄膜晶体管T45的栅极连接所述反相器M5，漏极连接所述第三直流电压VGL。
所述反相器M5包括第一反相器M51和第二反相器M52。
其中，所述第一反相器M51包括第一反向薄膜晶体管T51、第二反向薄膜晶体管T52、第三反向薄膜晶体管T53和第四反向薄膜晶体管T54。所述第一反向薄膜晶体管T51的源极和栅极连接所述第二下拉单元M32，漏极连接所述第二反向薄膜晶体管T52的源极。所述第二反向薄膜晶体管T52的栅极连接所述第二下拉单元M32，漏极连接所述第三直流电压VGL。所述第三反向薄膜晶体管T53的源极连接所述第二下拉单元M32，栅极连接所述第一反向薄膜晶体管T51的漏极，漏极连接所述第四反向薄膜晶体管T54的源极。所述第四反向薄膜晶体管T54的栅极连接所述第二反向薄膜晶体管T52的栅极，漏极连接所述第三直流电压VGL。
所述第二反相器M52包括第五反向薄膜晶体管T55、第六反向薄膜晶体管T56、第七反向薄膜晶体管T57和第八反向薄膜晶体管T58。所述第五反向薄膜晶体管T55的栅极和源极连接所述反馈单元M6，漏极连接所述第六反向薄膜晶体管T56的源极。所述第六反向薄膜晶体管T56的栅极连接所述第二上拉单元M22，漏极连接所述第三直流电压VGL。所述第七反向薄膜晶体管T57的源极连接所述反馈单元M6，栅极连接所述第五反向薄膜晶体管T55的漏极，漏极连接所述第八反向薄膜晶体管T58的源极。所述第八反向薄膜晶体管T58的栅极连接所述第六反向薄膜晶体管T56的栅极，漏极连接所述第三直流电压VGL。
所述反馈单元M6包括反馈薄膜晶体管T6，所述反馈薄膜晶体管T6的源极连接所述第一上拉单元M21，漏极连接所述上拉控制单元M1，栅极连接本级的级传信号。优选的，所述反馈薄膜晶体管T6为N型薄膜晶体管。
所述自举电容包括第一存储电容Cbt1和第二存储电容Cbt2。其中，所述第一存储电容Cbt1的一个极板连接所述第一上拉单元M21，另一个极板连接所述下拉维持单元M4。所述第二存储电容Cbt2的一个极板连接所述第二上拉单元M22，另一个极板连接所述第二下拉单元M32。
每一个所述信号转换模块包括至少包括第一信号转换单元、第二信号转换单元和第三信号转换单元。
所述第一信号转换单元包括第一转换薄膜晶体管Ta1和第二转换薄膜晶体管Ta2。其中，所述第一转换薄膜晶体管Ta1的源极连接第一次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第二转换薄膜晶体管Ta2的源端，并输出第一行扫描信号。所述第二转换薄膜晶体管Ta2的栅极连接第二次级时钟信号，漏极连接第三直流电压。
所述第二信号转换单元包括第三转换薄膜晶体管Ta3和第四转换薄膜晶体管Ta4。其中，所述第三转换薄膜晶体管Ta3源极连接第二次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第四转换薄膜晶体管Ta4的源端，并输出第二行扫描信号。所述第四转换薄膜晶体管Ta4的栅极连接第三次级时钟信号，漏极连接第三直流电压。
所述第三信号转换单元包括第五转换薄膜晶体管Ta5和第六转换薄膜晶体管Ta6。其中，所述第五转换薄膜晶体管Ta5的源极连接第三次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第六转换薄膜晶体管Ta6的源端，并输出第三行扫描信号。所述第六转换薄膜晶体管Ta6的栅极连接第一次级时钟信号，漏极连接第三直流电压。
下面将结合具体的实施例对本申请中的驱动电路的工作原理进行详细说明。参见图5和图6，图5为本申请的一个具体实施例中的驱动电路的仿真结果示意图，图6为本申请的一个具体实施例中的次级时钟信号和输出的行扫描信号之间的关联时序图。
其中，CK1为第一时钟信号，CK2为第二时钟信号，第一时钟信号CK1和第二时钟信号CK2的波形相反。XCK1为第一次级时钟信号，XCK2为第二次级时钟信号，XCK3为第三次级时钟信号。OUTm(n)为本级输出信号。OUT(n)为本级的级传信号；OUT(n-1)为上一级的级传信号；OUT(n+1)为下一级的级传信号。
参见图3，本实施例中的驱动电路的工作周期包括第一阶段T1，第二阶段T2和第三阶段T3。
第一阶段时：当第一时钟信号CK1处于高电位时，第一控制薄膜晶体管T11与第二控制薄膜晶体管T12打开，OUT(n-1)为高电位，Q点电位被抬升为高电位，第四上拉薄膜晶体管T24、第二反向薄膜晶体管T52及第四反向薄膜晶体管T54打开，QB被拉低至低电位第三维持薄膜晶体管T43、第四维持薄膜晶体管T44、第五维持薄膜晶体管T45和第六维持薄膜晶体管T46关闭，由于第二时钟信号CK2为低电位，本级的级传信号OUT(n)为低电位，第六反向薄膜晶体管T56与第八反向薄膜晶体管T58关闭，P点被拉升至高电位，第一维持薄膜晶体管T41与第二维持薄膜晶体管T42打开，上一级的级传信号OUT (n-1)为高电位，第三上拉薄膜晶体管T23打开，M点电位被拉至高电位，第一上拉薄膜晶体管T21与第二上拉薄膜晶体管T22打开，由于第二维持薄膜晶体管T42与第一维持薄膜晶体管T41打开，N点与放大讯号Outm(n)仍然维持低电位。
第二阶段时：当第一时钟信号CK1处于低电位时，第一控制薄膜晶体管T11与第二控制薄膜晶体管T12关闭，第四上拉薄膜晶体管T24打开，CK2变为高电位，级传讯号OUT (n)变为高电位，因此，Q点电位被上拉至更高电位，有利于第四上拉薄膜晶体管T24打开。同时反馈薄膜晶体管T6、第六反向薄膜晶体管T56与第八反向薄膜晶体管T58管打开，点F升至高电位，有利于减少第二控制薄膜晶体管T12。第五维持薄膜晶体管T45及T32管漏电，维持Q 点电位。P点降为低电位。第一维持薄膜晶体管T41与第二维持薄膜晶体管T42关闭，N点被抬升至高电位。由于第二存储电容Cbt2的存在，M点电位被上拉至更高电位。第一上拉薄膜晶体管T21与第二上拉薄膜晶体管T22打开，N点电位与输出信号也逐渐升至高电位。放大讯号Outm(n)升为高电位。
第三阶段时：第一时钟信号CK1升为高电位，第一控制薄膜晶体管T11与第二控制薄膜晶体管T12打开，由于上一级的级传信号OUT(n-1)为低电位，Q点电位被拉低至低电位。第四上拉薄膜晶体管T24、第二反向薄膜晶体管T52和第四反向薄膜晶体管T54关闭，QB点升至高电位。第三维持薄膜晶体管T43、第四维持薄膜晶体管T44、第五维持薄膜晶体管T45和第六维持薄膜晶体管T46打开，级传信号OUT(n)降至低电位。第六反向薄膜晶体管T56与第八反向薄膜晶体管T58及反馈薄膜晶体管T6关闭，P点升为高电位。第一维持薄膜晶体管T41与第二维持薄膜晶体管T42打开，下一级的级传信号OUT(n+1)升为高电位。T31打开，级传信号Out(n)与放大讯号Outm(n)降为低电位。
本申请的驱动电路中，以及驱动电路能够驱动三条行扫描线，大大减少了驱动电路的版图占用的空间，能够进一步减小显示面板的边框宽度。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种用于显示屏的驱动电路，其中，包括：
    输出模块，所述输出模块包括信号总线和信号输出子模块，所述输出模块用于提供用于显示的多个扫描信号，所述多个扫描信号为级联的扫描信号；
    信号放大模块，所述信号放大模块用于对所述多个扫描信号进行放大；
    多个信号转换模块，所述多个信号转换模块与所述多个放大后的扫描信号一一对应，用于将每一个放大后的扫描信号转换为至少两个行扫描信号；以及
    多个行扫描线，所述多个行扫描线与所述多个行扫描信号一一对应，用于将所述多个行扫描信号传递给显示屏的显示控制电路。
  2. 根据权利要求1所述的驱动电路，其中，所述信号转换模块包括至少两个次级时钟信号，所述多个次级时钟信号具有相同的周期和占空比；其中，
    所述多个次级时钟信号的脉冲宽度之和等于所述放大后的扫描信号的脉冲宽度。
  3. 根据权利要求2所述的驱动电路，其中，所述多个次级时钟信号的数目等于所述行扫描信号的数目。
  4. 根据权利要求1所述的驱动电路，其中，所述每一个所述信号转换模块包括至少包括第一信号转换单元和第二信号转换单元；
    所述第一信号转换单元包括第一转换薄膜晶体管和第二转换薄膜晶体管；其中，
    所述第一转换薄膜晶体管的源极连接第一次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第二转换薄膜晶体管的源端，并输出第一行扫描信号；
    所述第二转换薄膜晶体管的栅极连接第二次级时钟信号，漏极连接第三直流电压；
    所述第二信号转换单元包括第三转换薄膜晶体管和第四转换薄膜晶体管；其中，
    所述第三转换薄膜晶体管源极连接第二次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第四转换薄膜晶体管的源端，并输出第二行扫描信号；
    所述第四转换薄膜晶体管的栅极连接第三次级时钟信号，漏极连接第三直流电压。
  5. 根据权利要求4所述的驱动电路，其中，每一个所述信号转换模块还包括第三信号转换单元，所述第三信号转换单元包括第五转换薄膜晶体管和第六转换薄膜晶体管；其中，
    所述第五转换薄膜晶体管的源极连接第三次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第六转换薄膜晶体管的源端，并输出第三行扫描信号；
    所述第六转换薄膜晶体管的栅极连接第一次级时钟信号，漏极连接第三直流电压。
  6. 根据权利要求1所述的驱动电路，其中，所述信号放大模块包括：
    上拉单元，所述上拉单元用于将时钟信号转换为级传信号，将直流电压信号转换为输出信号；
    上拉控制单元，所述上拉控制单元用于控制所述上拉单元的打开时间；
    自举电容，所述自举电容用于抬升所述级传信号和输出信号电压；
    下拉单元，所述下拉单元用于将自举电容的输出电压拉低为低电位；
    下拉维持单元，所述下拉维持单元用于将自举电容的输出电压拉保持为低电位；
    反相器，所述反相器用于使所述自举电容的输出电压和下拉维持单元的输出电压电位相反；以及
    反馈单元，所述反馈单元用于提高下拉单元的输出电压。
  7. 根据权利要求6所述的驱动电路，其中，所述上拉单元包括第一上拉单元和第二上拉单元；
    所述第一上拉单元包括第一上拉薄膜晶体管和第二上拉薄膜晶体管；其中，
    所述第一上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述自举电容的一个极板，栅极连接第二上拉薄膜晶体管的栅极；
    所述第二上拉薄膜晶体管的源极连接第一直流电压，漏极连接所述自举电容的另一个极板，栅极连接上一级的级传信号；
    所述第二上拉单元包括第三上拉薄膜晶体管，所述第三上拉薄膜晶体管的源极连接第二时钟信号，栅极连接所述自举电容的一个极板，漏极连接所述自举电容的另一个极板。
  8. 根据权利要求7所述的驱动电路，其中，所述上拉控制单元包括第一控制薄膜晶体管和第二控制薄膜晶体管；其中，
    所述第一控制薄膜晶体管的源极连接上一级的级传信号，栅极连接第一时钟信号，漏极连接所述第二控制薄膜晶体管的源极；
    所述第二控制薄膜晶体管的栅极连接所述第一时钟信号，漏极连接所述下拉维持单元。
  9. 根据权利要求8所述的驱动电路，其中，所述下拉单元包括第一下拉单元和第二下拉单元；其中，
    所述第一下拉单元包括第一下拉薄膜晶体管，所述第一下拉薄膜晶体管的源极连接所述第一上拉单元，栅极连接下一级的级传信号，漏极连接所述第三直流电压；
    所述第二下拉单元包括第二下拉薄膜晶体管和第三下拉薄膜晶体管；
    所述第二下拉薄膜晶体管的源极连接所述第二上拉单元，栅极连接下一级的级传信号，漏极连接所述第三下拉薄膜晶体管的源极；
    所述第三下拉薄膜晶体管的栅极连接下一级的级传信号，漏极连接所述第三直流电压。
  10. 根据权利要求9所述的驱动电路，其中，所述反相器包括第一反相器和第二反相器；其中，
    所述第一反相器包括第一反向薄膜晶体管、第二反向薄膜晶体管、第三反向薄膜晶体管和第四反向薄膜晶体管；
    所述第一反向薄膜晶体管的源极和栅极连接所述第二下拉单元，漏极连接所述第二反向薄膜晶体管的源极；
    所述第二反向薄膜晶体管的栅极连接所述第二下拉单元，漏极连接所述第三直流电压；
    所述第三反向薄膜晶体管的源极连接所述第二下拉单元，栅极连接所述第一反向薄膜晶体管的漏极，漏极连接所述第四反向薄膜晶体管的源极；
    所述第四反向薄膜晶体管的栅极连接所述第二反向薄膜晶体管的栅极，漏极连接所述第三直流电压；
    所述第二反相器包括第五反向薄膜晶体管、第六反向薄膜晶体管、第七反向薄膜晶体管和第八反向薄膜晶体管；
    所述第五反向薄膜晶体管的栅极和源极连接所述反馈单元，漏极连接所述第六反向薄膜晶体管的源极；
    所述第六反向薄膜晶体管的栅极连接所述第二上拉单元，漏极连接所述第三直流电压；
    所述第七反向薄膜晶体管的源极连接所述反馈单元，栅极连接所述第五反向薄膜晶体管的漏极，漏极连接所述第八反向薄膜晶体管的源极；
    所述第八反向薄膜晶体管的栅极连接所述第六反向薄膜晶体管的栅极，漏极连接所述第三直流电压。
  11. 根据权利要求10所述的驱动电路，其中，所述反馈单元包括反馈薄膜晶体管，所述反馈薄膜晶体管的源极连接所述第一上拉单元，漏极连接所述上拉控制单元，栅极连接本级的级传信号。
  12. 根据权利要求11所述的驱动电路，其中，所述自举电容包括第一存储电容和第二存储电容；其中，
    所述第一存储电容的一个极板连接所述第一上拉单元，另一个极板连接所述下拉维持单元；
    所述第一存储电容的一个极板连接所述第二上拉单元，另一个极板连接所述第二下拉单元。
  13. 根据权利要求12所述的驱动电路，其中，每一个所述信号转换模块包括至少包括第一信号转换单元和第二信号转换单元；
    所述第一信号转换单元包括第一转换薄膜晶体管和第二转换薄膜晶体管；其中，
    所述第一转换薄膜晶体管的源极连接第一次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第二转换薄膜晶体管的源端，并输出第一行扫描信号；
    所述第二转换薄膜晶体管的栅极连接第二次级时钟信号，漏极连接第三直流电压；
    所述第二信号转换单元包括第三转换薄膜晶体管和第四转换薄膜晶体管；其中，
    所述第三转换薄膜晶体管源极连接第二次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第四转换薄膜晶体管的源端，并输出第二行扫描信号；
    所述第四转换薄膜晶体管的栅极连接第三次级时钟信号，漏极连接第三直流电压。
  14. 根据权利要求13所述的驱动电路，其中，每一个所述信号转换模块还包括第三信号转换单元，所述第三信号转换单元包括第五转换薄膜晶体管和第六转换薄膜晶体管；其中，
    所述第五转换薄膜晶体管的源极连接第三次级时钟信号，栅极连接所述信号放大模块的输出端，漏极连接所述第六转换薄膜晶体管的源端，并输出第三行扫描信号；
    所述第六转换薄膜晶体管的栅极连接第一次级时钟信号，漏极连接第三直流电压。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109961746B (zh) * 2019-05-06 2020-09-08 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路
CN110379349B (zh) * 2019-07-22 2020-10-16 深圳市华星光电半导体显示技术有限公司 栅极驱动电路
CN111223452B (zh) * 2020-03-18 2021-07-23 深圳市华星光电半导体显示技术有限公司 Goa电路
CN111986605B (zh) * 2020-08-13 2022-05-31 深圳市华星光电半导体显示技术有限公司 栅极驱动电路
CN111986622B (zh) * 2020-08-27 2022-04-26 武汉华星光电技术有限公司 驱动电路及其驱动方法、显示装置
CN112382249B (zh) * 2020-11-13 2022-04-26 昆山龙腾光电股份有限公司 栅极驱动单元、栅极驱动电路及显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140079106A (ko) * 2012-12-18 2014-06-26 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치
CN104167195A (zh) * 2014-08-26 2014-11-26 昆山龙腾光电有限公司 栅极驱动电路单元及其显示面板
CN105304044A (zh) * 2015-11-16 2016-02-03 深圳市华星光电技术有限公司 液晶显示设备及goa电路
CN107393473A (zh) * 2017-08-25 2017-11-24 深圳市华星光电半导体显示技术有限公司 Goa电路
CN108154835A (zh) * 2018-01-02 2018-06-12 京东方科技集团股份有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
CN109003588A (zh) * 2018-08-06 2018-12-14 深圳市华星光电半导体显示技术有限公司 液晶显示装置
CN109243351A (zh) * 2017-07-10 2019-01-18 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN109712552A (zh) * 2019-02-12 2019-05-03 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN109961746A (zh) * 2019-05-06 2019-07-02 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101404542B1 (ko) * 2006-05-25 2014-06-09 삼성디스플레이 주식회사 액정 표시 장치
KR101965724B1 (ko) * 2012-10-18 2019-04-04 삼성디스플레이 주식회사 표시장치를 위한 발광 구동 장치, 표시장치 및 그 구동 방법
CN104078021B (zh) * 2014-07-17 2016-05-04 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104282279B (zh) * 2014-09-28 2016-09-28 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器、栅极驱动电路和显示装置
CN107331361B (zh) * 2017-08-15 2020-05-05 深圳市华星光电半导体显示技术有限公司 一种基于igzo制程的栅极驱动电路及液晶显示屏
CN109559698B (zh) * 2018-12-26 2020-09-01 深圳市华星光电半导体显示技术有限公司 一种goa电路

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140079106A (ko) * 2012-12-18 2014-06-26 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치
CN104167195A (zh) * 2014-08-26 2014-11-26 昆山龙腾光电有限公司 栅极驱动电路单元及其显示面板
CN105304044A (zh) * 2015-11-16 2016-02-03 深圳市华星光电技术有限公司 液晶显示设备及goa电路
CN109243351A (zh) * 2017-07-10 2019-01-18 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN107393473A (zh) * 2017-08-25 2017-11-24 深圳市华星光电半导体显示技术有限公司 Goa电路
CN108154835A (zh) * 2018-01-02 2018-06-12 京东方科技集团股份有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
CN109003588A (zh) * 2018-08-06 2018-12-14 深圳市华星光电半导体显示技术有限公司 液晶显示装置
CN109712552A (zh) * 2019-02-12 2019-05-03 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN109961746A (zh) * 2019-05-06 2019-07-02 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路

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