WO2021203471A1 - 显示面板和电子设备 - Google Patents

显示面板和电子设备 Download PDF

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Publication number
WO2021203471A1
WO2021203471A1 PCT/CN2020/085803 CN2020085803W WO2021203471A1 WO 2021203471 A1 WO2021203471 A1 WO 2021203471A1 CN 2020085803 W CN2020085803 W CN 2020085803W WO 2021203471 A1 WO2021203471 A1 WO 2021203471A1
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WO
WIPO (PCT)
Prior art keywords
goa
transistor
unit
module
electrode
Prior art date
Application number
PCT/CN2020/085803
Other languages
English (en)
French (fr)
Inventor
何孝金
董成才
金一坤
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/765,477 priority Critical patent/US11450253B2/en
Publication of WO2021203471A1 publication Critical patent/WO2021203471A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • This application relates to the field of display technology, and in particular to a display panel and electronic equipment.
  • the existing 8K display panel includes multiple clock signal lines and GOA circuits.
  • the GOA circuit includes multiple cascaded GOA units. Each GOA unit is connected to a clock signal line.
  • the clock signal line provides the GOA unit with a clock signal. To control the GOA unit to output the drive signal.
  • the number of GOA units connected to each clock signal line in the current display panel is not uniform, so the load of each clock signal line is also different, causing the display panel to produce periodic dark lines at low gray levels, which affects the display effect.
  • the existing display panel has a technical problem of generating periodic dark lines at low gray levels, which needs to be improved.
  • the embodiments of the present application provide a display panel and an electronic device, which are used to alleviate the technical problem that the existing display panel generates periodic dark lines at low gray levels.
  • An embodiment of the present application provides a display panel, including:
  • a plurality of scan lines, the scan lines are located in the display area;
  • the GOA circuit is located between the display area and the signal line setting area.
  • the GOA circuit includes a plurality of cascaded GOA units, and the GOA unit includes a plurality of effective GOA units and 2m redundant GOAs arranged in sequence Unit, the drive signal output terminals of the effective GOA unit are sequentially connected to the scan line and correspond to each other, and the multiple effective GOA units form multiple effective GOA modules arranged in sequence, and each effective GOA module includes 2m effective GOA modules.
  • the clock signal input ends of the 2m effective GOA units are sequentially connected to the 2m clock signal lines and correspond to each other one-to-one, and the clock signals of the 2m redundant GOA units are input
  • the terminals are sequentially connected with the 2m clock signal lines and correspond one-to-one.
  • the 2m redundant GOA units have the same structure.
  • the redundant GOA unit and the effective GOA unit have the same structure.
  • every m GOA units from the first position form a GOA module, and between adjacent GOA modules, the rear GOA module is used to provide a reset signal to the previous GOA module.
  • the drive signal output terminal of the n-th level GOA unit in the subsequent GOA module is connected to the reset signal terminal of the n-th level GOA unit in the previous GOA module.
  • the drive signal output terminal of the n-th level GOA unit in the preceding GOA module is connected to the drive signal input terminal of the n-th level GOA unit in the subsequent GOA module.
  • the drive signal input end of each GOA unit is connected to the frame start signal line.
  • the GOA unit of the Nth level includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node according to the previous stage transmission signal
  • a pull-up module connected to the first node, and configured to pull up the potential of the gate drive signal of the current level according to the clock signal of the current level;
  • the signal download module is connected to the first node, and is used to control the output of the transmission signal of the current level according to the clock signal of the current level;
  • the first pull-down module is used to pull down the potential of the gate drive signal of the current stage according to the first subsequent stage gate drive signal
  • a second pull-down module connected to the first node, and configured to pull down the potential of the first node according to a second rear-stage gate drive signal
  • a first pull-down maintenance module connected to the first node, and configured to maintain the low potential of the first node and the gate drive signal of the current stage according to the first low-frequency clock signal;
  • the second pull-down maintenance module connected to the first node, is used to maintain the low potentials of the first node and the gate drive signal of the current stage according to the second low-frequency clock signal, the first low-frequency clock signal and The second low-frequency clock signal has an opposite potential at the same time;
  • the first pull-down maintenance module and the second pull-down maintenance module each include an inversion unit and a maintenance unit, the output terminal of the inversion unit is connected to the input terminal of the maintenance unit, and at least one of the inverters
  • the reverse unit is a first reverse unit;
  • the first reverse unit includes a first reverse transistor, a second reverse transistor, and a third reverse transistor, and the gate of the first reverse transistor is connected to the first electrode Low-frequency clock signal input terminal, the second electrode of the first reverse transistor and the first electrode of the second reverse transistor are connected to a second node, and the gate of the second reverse transistor is connected to the first node ,
  • the second electrode of the second reverse transistor is connected to the first power supply low potential signal, the gate and the first electrode of the third reverse transistor are connected to the second node, and the second electrode of the third reverse transistor is connected to the second node.
  • the two electrodes are connected to the input end of the sustain unit.
  • the sustain unit includes a first sustain transistor and a second sustain transistor, and the gate of the first sustain transistor and the gate of the second sustain transistor are connected to the input terminal of the sustain unit ,
  • the first electrode of the first sustain transistor is connected to the first power supply low potential signal
  • the second electrode of the first sustain transistor is connected to the first node
  • the first electrode of the second sustain transistor is connected to the first node.
  • Two power supply low-potential signals, and the second electrode of the second sustain transistor is connected to the gate drive signal of the current stage.
  • the inversion units in the first pull-down maintenance module and the second pull-down maintenance module are both first inversion units.
  • one of the inverting unit of the first pull-down maintaining module and the second pull-down maintaining module is a first inverting unit
  • the other inverting unit is a second inverting unit
  • the second inversion unit includes a fourth inversion transistor, a fifth inversion transistor, a sixth inversion transistor, and a seventh inversion transistor, and the gate and the first electrode of the fourth inversion transistor are connected to a low-frequency clock signal
  • the second electrode of the fourth reverse transistor and the first electrode of the fifth reverse transistor are connected to the third node
  • the gate of the fifth reverse transistor is connected to the first node
  • the The second electrode of the fifth reverse transistor is connected to the first power supply low potential signal
  • the gate of the sixth reverse transistor is connected to the third node
  • the first electrode of the sixth reverse transistor is connected to the fourth
  • the first electrode of the reverse transistor, the second electrode of the sixth reverse transistor and the first electrode of the seventh reverse transistor are connected to the input terminal of the sustain unit, and the gate of the seventh reverse transistor
  • the pull-up control module includes a first transistor, the gate and the first electrode of the first transistor are connected to the previous stage signal transmission, and the second electrode is connected to the first node.
  • the pull-up module includes a second transistor, the gate of the second transistor is connected to the first node, the first electrode is connected to the clock signal of the current stage, and the second electrode is connected to the This level of gate drive signal.
  • the signal download module includes a third transistor, the gate of the third transistor is connected to the first node, the first electrode is connected to the clock signal of the current stage, and the second electrode is connected to the Describe the transmission signal at this level.
  • the first pull-down module includes a fourth transistor, the gate of the fourth transistor is connected to the first rear-stage gate driving signal, and the first electrode is connected to the second power source. Potential signal, the second electrode is connected to the gate drive signal of the current stage.
  • the second pull-down module includes a fifth transistor, the gate of the fifth transistor is connected to the second rear-stage gate driving signal, and the first electrode is connected to the first power supply low potential Signal, the second electrode is connected to the first node.
  • the present application also provides an electronic device, including a display panel and a driving chip, the display panel including:
  • a plurality of scan lines, the scan lines are located in the display area;
  • the GOA circuit is located between the display area and the signal line setting area.
  • the GOA circuit includes a plurality of cascaded GOA units, and the GOA unit includes a plurality of effective GOA units and 2m redundant GOAs arranged in sequence Unit, the drive signal output terminals of the effective GOA unit are sequentially connected to the scan line and correspond to each other, and the multiple effective GOA units form multiple effective GOA modules arranged in sequence, and each effective GOA module includes 2m effective GOA modules.
  • the clock signal input ends of the 2m effective GOA units are sequentially connected to the 2m clock signal lines and correspond to each other one-to-one, and the clock signals of the 2m redundant GOA units are input
  • the terminals are sequentially connected with the 2m clock signal lines and correspond one-to-one.
  • the 2m redundant GOA units have the same structure.
  • the redundant GOA unit and the effective GOA unit have the same structure.
  • every m GOA units from the first position form a GOA module, and between adjacent GOA modules, the rear GOA module is used to provide a reset signal to the previous GOA module.
  • the embodiments of the present application provide a display panel and an electronic device.
  • the display panel includes a plurality of scan lines, 2m clock signal lines, and a GOA circuit.
  • the scan lines are located in the display area; the clock signal lines are located in the display area.
  • the signal line setting area in the non-display area; the GOA circuit is located between the display area and the signal line setting area, the GOA circuit includes a plurality of cascaded GOA units, and the GOA unit includes a plurality of GOA units arranged in sequence.
  • Effective GOA units and 2m redundant GOA units the drive signal output terminals of the effective GOA units are sequentially connected to the scan lines and correspond one to one, and the multiple effective GOA units form multiple effective GOA modules arranged in sequence,
  • Each valid GOA module includes 2m valid GOA units.
  • the clock signal input terminals of the 2m valid GOA units are sequentially connected to the 2m clock signal lines and correspond to each other one-to-one.
  • the clock signal input ends of the redundant GOA units are sequentially connected to the 2m clock signal lines and correspond one-to-one.
  • the number of GOA units connected to each clock signal line is equal, so the load of each clock signal line is the same, and no periodic dark lines are generated under low gray levels.
  • FIG. 1 is a schematic diagram of the first structure of a display panel provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a second structure of a display panel provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a third structure of a display panel provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a fourth structure of a display panel provided by an embodiment of the application.
  • FIG. 5 is a timing diagram of CK1 and CK7 in the display panel provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of the first structure of the N-th level GOA unit in the GOA circuit of the embodiment of the application.
  • FIG. 7 is a schematic structural diagram of the first pull-down sustaining module in the Nth-level GOA unit of the GOA circuit according to the embodiment of the application.
  • FIG. 8 is a schematic diagram of the first structure of an N-th level GOA unit in a GOA circuit in the prior art.
  • FIG. 9 is a schematic diagram of the film layer stacking structure of the first pull-down sustaining module and the second pull-down sustaining module in the Nth-level GOA unit of the prior art GOA circuit.
  • FIG. 10 is a schematic diagram of the film layer stacking structure of the first pull-down sustaining module and the second pull-down sustaining module in the Nth-level GOA unit of the GOA circuit according to the embodiment of the application.
  • FIG. 11 is a schematic diagram of the second structure of the Nth level GOA unit in the GOA circuit of the embodiment of the present application.
  • the embodiments of the present application provide a display panel and an electronic device, which are used to alleviate the technical problem that the existing display panel generates periodic dark lines at low gray levels.
  • the display panel of the present application includes multiple scan lines, 2m clock signal lines, and GOA circuits.
  • the scan lines are located in the display area
  • the clock signal lines are located in the signal line setting area of the non-display area
  • the GOA circuit is located in the display area and the signal line setting area.
  • the GOA circuit includes multiple cascaded GOA units.
  • the GOA unit includes multiple effective GOA units and 2m redundant GOA units arranged in sequence.
  • the drive signal output terminals of the effective GOA units are sequentially connected to the scan lines and correspond to each other.
  • each effective GOA module includes 2m effective GOA units, in the effective GOA module, 2m effective GOA unit clock signal input terminals and 2m clock signal lines
  • the clock signal input terminals of the 2m redundant GOA units are connected in sequence with the 2m clock signal lines and correspond to each other in sequence.
  • FIG. 1 a schematic diagram of the first structure of a display panel provided by an embodiment of this application.
  • the display panel includes a display area 10 and a non-display area located around the display area 10.
  • the non-display area includes a signal line setting area 21.
  • GOA Gate Driver on Array, GOA
  • a plurality of sub-pixels arranged in an array are arranged in the display area 10, and each sub-pixel is driven by a pixel drive circuit in the display area 10.
  • the scan signal and data signal of the drive transistor in the pixel drive circuit are respectively driven by the scan line 11 and the data line.
  • the gate of the driving transistor is connected to the same gate line 11, and in the pixel driving circuit of the sub-pixel in the same column, the source or drain of the driving transistor is connected to The same data line 12 is connected.
  • the signal line setting area 21 is provided with multiple clock signal lines
  • the GOA circuit setting area 22 is provided with a GOA circuit
  • the clock signal line provides a clock signal to the GOA circuit
  • the GOA circuit outputs a gate drive signal and drives the gate The signal is provided to the scan line 11.
  • FIG. 2 a schematic diagram of the second structure of the display panel provided by this embodiment of the application.
  • This embodiment takes an 8K product as an example for description.
  • the resolution of the display panel in the 8K product is 7680x4320, so it includes 7680 data lines. , 4320 scan lines.
  • the display panel includes 2m clock signal lines and 4320 scan lines.
  • the GOA circuit includes multiple cascaded GOA units.
  • the GOA unit includes multiple effective GOA units and 2m redundant GOA units from top to bottom, of which effective GOA The unit is represented by "GOA Unit", and the redundant GOA unit is represented by "Dummy GOA Unit".
  • the value of m can be any positive integer. In this embodiment, m is selected as 6, so it includes 12 clock signal lines CK1 to CK12 and 12 redundant GOA units Dummy GOA Unit 1 to Dummy GOA Unit 12, 4320 scan lines are represented by G1 to G4320, respectively.
  • the drive signal output terminals of the effective GOA unit are connected to the scan lines in sequence and correspond one-to-one, that is, the number of effective units is the same as the number of scan lines. Since there are 4320 scan lines, the number of effective GOA units is also 4320. Use GOA Unit 1 To GOA Unit 4320 said. The drive signal output terminal of the redundant GOA unit is not connected to the scan line.
  • Each effective GOA unit in the GOA circuit includes a clock signal input terminal, the clock signal line is connected to the clock signal input terminal, the clock signal is input to drive the effective GOA unit to work, and the gate drive signal is output to the corresponding scan line.
  • the redundant GOA unit although it is not connected to the scan line, it also needs to output a signal to reset the previous valid GOA unit, so it also needs to be connected to the clock signal line.
  • each valid GOA module includes 12 valid GOA units, in the valid GOA module, the clock signal input terminals of 12 valid GOA units and 12 clock signal lines are in sequence Connection and one-to-one correspondence.
  • GOA Unit 1 to GOA Unit 12 is a valid GOA module
  • GOA Unit 13 to GOA Unit 24 are valid GOA modules
  • each valid GOA module the clock signal input terminals of 12 valid GOA units are connected in sequence with 12 clock signal lines and correspond to each other, namely GOA Unit 1 is connected to CK1, GOA Unit 2 is connected to CK2, and so on, GOA Unit 12 is connected to CK12.
  • each valid GOA module has a clock signal input terminal of a valid GOA unit connected to it. Therefore, each clock signal line in CK1 to CK12 is connected to 360 valid GOA units.
  • the clock signal input terminals of the 12 redundant GOA units arranged after the valid GOA unit are connected to the 12 clock signal lines in sequence and one-to-one correspondence, that is, Dummy GOA Unit 1 is connected to CK1, and Dummy GOA Unit 2 is connected to CK2 , And so on, Dummy GOA Unit 12 is connected to CK12, therefore, each clock signal line in CK1 to CK12 is connected to a redundant GOA unit.
  • the number of GOA units connected to each clock signal line in CK1 to CK12 is 361, so the load is uniform.
  • the output gate of the valid GOA unit The polar drive signal is also stable, which in turn makes the brightness of the display panel consistent under the same gray scale, and no periodic dark lines appear under low gray scales, which improves the display effect.
  • the 12 redundant GOA units have the same structure.
  • the same structure means that each redundant GOA unit has the same number of transistors and the same connection mode.
  • the clock signal line is input to each redundant GOA unit after the clock signal is driven in the same way. Therefore, each clock signal line is redundant
  • the load of the GOA unit is also equal.
  • the redundant GOA unit and the effective GOA unit have the same structure, that is, the number and connection mode of the transistors in the redundant GOA unit and the effective GOA unit are the same, and the redundant GOA unit and the effective GOA unit are arranged in structure
  • the manufacturing process can be simplified, and the load difference between the effective GOA unit and the redundant GOA unit connected to the same clock signal line can be reduced.
  • Figure 3 and Figure 4 show the connection relationship of each GOA unit in the display panel.
  • the previous 12-level effective GOA units in Figure 3 are taken as an example to illustrate the signal transmission mode between each GOA unit.
  • Figure 4 uses the last 6 levels
  • the effective GOA unit and the 12-level redundant GOA unit are taken as examples to describe the signal transmission mode between each GOA unit.
  • every m GOA units from the first position form a GOA module, and between adjacent GOA modules, the subsequent GOA module is used to provide a reset signal to the previous GOA module.
  • GOA Unit 1 to GOA Unit 6 is the first GOA module
  • GOA Unit 7 to GOA Unit 12 are the second GOA module
  • Dummy GOA Unit 7 to Dummy GOA Unit 12 are the last GOA module.
  • the second GOA module provides the reset signal for the first GOA module
  • the third GOA module provides the reset signal for the second GOA module
  • the last GOA module provides the reset signal for the penultimate GOA module.
  • Each effective GOA unit includes a drive signal input terminal Input, a drive signal output terminal Output, and a reset signal terminal Reset.
  • the drive signal output terminal of the nth level GOA unit in the rear GOA module is connected to the reset signal terminal of the nth level GOA unit in the previous GOA module.
  • 1 ⁇ n ⁇ m As shown in Figure 3, GOA Unit 7 in the second GOA module is the first-level GOA unit, and GOA Unit 1 in the first GOA module is the first-level GOA unit.
  • the drive signal output terminal of GOA Unit 7 is in addition to scanning In addition to the connection of line G7, it is also connected to the reset signal terminal Reset of GOA Unit 1 to provide a reset signal to GOA Unit 1.
  • GOA Unit 8 to GOA The drive signal output terminal Output in Unit 12 is connected to the scan lines G8 to G12, and is also connected to the reset signal terminal Reset of GOA Unit 2 to GOA Unit 6, respectively, for GOA Unit 2 to GOA Unit 6 provides reset signal.
  • the purpose of reset is to clear the gate drive signal of the previous frame to prevent crosstalk between the gate drive signal of the previous frame and the gate drive signal of the next frame, which will affect the picture effect.
  • FIG 5 it is the timing diagram of CK1 and CK7. Since t1, the phases of CK1 and CK7 are opposite. At time t1, CK1 starts to input the first high potential, CK7 has not yet started to be low, and CK1 controls GOA Unit 1 outputs the gate drive signal to G1.
  • CK1 is at low level
  • GOA Unit 1 stops outputting the gate drive signal
  • CK7 starts to input the first high level
  • the drive signal is transmitted to the reset signal terminal Reset of GOA Unit 1
  • the gate drive signal potential of GOA Unit 1 output at t1 is pulled down, that is, cleared, then at t3 time period, the second one of CK1
  • the gate drive signal in the t3 period will not affect the current gate drive signal, and crosstalk will not occur, thus ensuring the display effect.
  • the drive signal output terminal of the nth level GOA unit in the front GOA module is connected to the drive signal input terminal of the nth level GOA unit in the rear GOA module.
  • GOA Unit 7 in the second GOA module is the first-level GOA unit
  • GOA Unit 1 in the first GOA module is the first-level GOA unit.
  • the drive signal output terminal of GOA Unit 1 is in addition to scanning In addition to the connection of line G1, it is also connected to the drive signal input terminal Input of GOA Unit 7 to provide drive signals to GOA Unit 7.
  • GOA Unit 2 to GOA The drive signal output terminal Output in Unit 6 is connected to the scan lines G2 to G6, and is also connected to the drive signal input terminal Input in GOA Unit 8 to GOA Unit 12 to provide GOA Unit 8 to GOA Unit 12 provides drive signals.
  • the drive signal input end of each GOA unit is connected to the frame start signal line.
  • the first m GOA units are GOA Unit 1 to GOA Unit 6, forming the first GOA module, GOA Unit 1 to GOA
  • the drive signal input terminals Input of Unit 6 are all provided by the frame start signal line STV, and the frame start signal line STV is located in the signal line setting area.
  • the GOA unit further includes a power signal input terminal (not shown in the figure), and the power signal input terminal is connected to a power signal line.
  • the GOA unit is usually provided with a pull-up unit or a pull-down unit.
  • the power signal line is located in the signal line setting area, including the power high-potential signal line VGH and the power low-potential signal line VSS.
  • the pull-up unit is connected to the power high-potential signal line VGH , The potential of a specific node is pulled up, and the pull-down unit is connected to the power supply low-potential signal line VSS to pull down the potential of the specific node to meet the requirements of the GOA unit in different working stages.
  • the GOA circuit is located on the left or right side of the display area, that is, the driving mode of the GOA circuit in this application is single-side driving.
  • GOA Unit 4315 to GOA Unit 4320 are the 720th GOA module from the first place
  • Dummy GOA Unit 1 to Dummy GOA Unit 6 are the 721th GOA module
  • Dummy GOA Unit 7 to Dummy GOA Unit 12 are the No. 722 GOA modules, of which each redundant GOA unit in the 721th GOA module provides a reset signal for each valid GOA unit in the 720th GOA module, and each redundant GOA unit in the 722th GOA module is in the 721th GOA module
  • Each redundant GOA unit provides a reset signal, and each redundant GOA unit in the 722th GOA module does not reset itself.
  • the added Dummy GOA Unit 7 to Dummy GOA Unit 12 pair Dummy GOA Unit 7 to Dummy GOA Unit 12.
  • GOA Unit 1 to Dummy GOA Unit 6 are reset, so Dummy GOA Unit 1 to Dummy
  • the drive signal output by the drive signal output terminal Output of GOA Unit 6 will not be affected by the drive signal of the previous frame, and crosstalk will not occur.
  • Unit 4315 to GOA Unit 4320 are reset, the reset effect is also better, so compared with the prior art, the display effect is improved.
  • the GOA unit structure of the Nth stage in the GOA circuit is shown in Figure 6, including a pull-up control module 601, a pull-up module 602, and a signal
  • the pull-up control module 601 is connected to the first node Q(N), and is used to pull up the potential of the first node Q(N) according to the transmission signal of the previous stage; the pull-up module 602 is connected to the first node Q(N), It is used to pull up the potential of the gate drive signal G(N) of the current level according to the clock signal CK of the current level; the signal download module 603 is connected to the first node Q(N), and is used to control the current level according to the clock signal CK of the current level.
  • the output of the step-by-step transmission signal ST(N); the first pull-down module 604 is used to pull down the potential of the current-level gate drive signal G(N) according to the first subsequent-stage gate drive signal; the second pull-down module 605 and the second A node Q(N) is connected to pull down the potential of the first node Q(N) according to the second subsequent gate drive signal; the first pull-down maintaining module 606 is connected to the first node Q(N) for According to the first low-frequency clock signal LC1, the first node Q(N) and the gate drive signal G(N) of the current stage are maintained at a low level; the second pull-down maintaining module 607 is connected to the first node Q(N) for The second low-frequency clock signal LC2 maintains the low potentials of the first node Q(N) and the gate drive signal G(N) of the current stage.
  • the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 have opposite potentials at the same time; where ,
  • the first pull-down maintaining module 606 and the second pull-down maintaining module 607 both include a reverse unit and a sustain unit, the output terminal of the reverse unit is connected to the input terminal of the sustain unit, and at least one reverse unit is the first reverse unit;
  • the first inverting unit includes a first inverting transistor, a second inverting transistor, and a third inverting transistor. The gate and first electrode of the first inverting transistor are connected to the low-frequency clock signal input terminal.
  • the two electrodes and the first electrode of the second reverse transistor are connected to the second node A(N), the gate of the second reverse transistor is connected to the first node Q(N), and the second electrode of the second reverse transistor is connected to the first node.
  • the power supply low potential signal VSSQ, the gate and the first electrode of the third reverse transistor are connected to the second node A(N), and the second electrode of the third reverse transistor is connected to the input terminal of the sustain unit.
  • the drive signal input terminal Input of a certain GOA unit is connected to the drive signal output terminal Output of the GOA unit six stages away from the GOA unit, and the Nth-stage GOA
  • the stage transmission signal output by the unit is the Nth stage transmission signal ST(N)
  • the output gate drive signal is the nth stage gate drive signal G(N), 6 ⁇ N ⁇ M, where N is an integer and M is The total number of stages of GOA units in the GOA circuit.
  • the previous stage transmission signal is the stage transmission signal of other GOA units before the Nth stage GOA unit, which can be the first stage, the first two stages or the previous multiple stages, the first and the second back-level gate drive signal and the second back-level gate
  • the driving signals are all the gate driving signals of the other GOA units after the Nth-level GOA unit, and can be the last one level, the last two levels, or the last multiple levels.
  • the GOA circuit of the 8K product in this application is taken as an example.
  • the transmission signal of the previous stage is ST(N-6)
  • the gate drive signal of the first and subsequent stage is G(N+6)
  • the gate drive signal of the second and subsequent stage is G(N+6).
  • Is G(N+8) where ST(N-6) is the stage transmission signal before and six stages away from the Nth stage gate drive signal G(N), and the first subsequent stage gate drive signal G(N+ 6) is the gate drive signal after the Nth stage gate drive signal G(N) and is separated from it by six stages, and the second subsequent stage gate drive signal G(N+8) is the Nth stage gate drive signal G( N) The gate drive signal after and eight levels away from it.
  • the pull-up control module 601 includes a first transistor T11, the gate and the first electrode of the first transistor T11 are connected to the previous stage transmission signal ST(N-6), and the second electrode is connected to the first node Q (N).
  • the pull-up module 602 includes a second transistor T21, the gate of the second transistor T21 is connected to the first node Q(N), the first electrode is connected to the clock signal CK of the current stage, and the second electrode is connected to the gate of the current stage. Pole drive signal G(N).
  • the signal download module 603 includes a third transistor T22, the gate of the third transistor T22 is connected to the first node Q(N), the first electrode is connected to the clock signal CK of the current stage, and the second electrode is connected to the current stage Stage transmission signal ST(N).
  • the first pull-down module 604 includes a fourth transistor T31, the gate of the fourth transistor T31 is connected to the first back-end gate drive signal G(N+6), and the first electrode is connected to the second power source.
  • the potential signal VSSG, and the second electrode is connected to the gate drive signal G(N) of the current stage.
  • the second pull-down module 605 includes a fifth transistor T41, the gate of the fifth transistor T41 is connected to the second back-stage gate drive signal G(N+8), and the first electrode is connected to the low potential of the first power supply.
  • the signal VSSQ, the second electrode is connected to the first node Q(N).
  • the first pull-down sustaining module 606 and the second pull-down sustaining module 607 are both used to maintain the low potentials of the first node Q(N) and the gate drive signal G(N) of the current stage, so the functions of both same.
  • the low-frequency clock signal input terminal of the first pull-down maintenance module 606 inputs the first low-frequency clock signal LC1
  • the low-frequency clock signal input terminal of the second pull-down maintenance module 607 inputs the second low-frequency clock signal LC2.
  • a low-frequency clock signal LC1 and a second low-frequency clock signal LC2 are both low-frequency clock signals with 200 times the frame period and a duty ratio of 1/2, and the phase difference between the two is 1/2 period.
  • the first low-frequency clock signal LC1 The phase of the second low-frequency clock signal LC2 is opposite, so the first pull-down maintenance module 606 and the second pull-down maintenance module 607 can be driven to work alternately, that is, the working time of the two is staggered, and only one pull-down maintenance module is working at the same time. Due to the input characteristics of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2, for a certain pull-down maintenance module that is currently working, its low-frequency clock signal input terminal is equivalent to receiving a DC signal, which is high Potential, the value is 28V.
  • Both the first pull-down maintenance module 606 and the second pull-down maintenance module 607 include an inversion unit and a maintenance unit, the output terminal of the inversion unit is connected to the input terminal of the maintenance unit, and at least one inversion unit is the first inversion unit.
  • the reverse units in the first pull-down maintaining module 606 and the second pull-down maintaining module 607 are both the first reverse unit, that is, the structure of the first pull-down maintaining module 606 and the second pull-down maintaining module 607.
  • FIG. 7 takes the first pull-down sustaining module 606 as an example to illustrate the structure of the first inversion unit and the sustaining unit, and the specific working principle is also applicable to the second pull-down sustaining module 607.
  • the first pull-down sustaining module 606 includes a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, a ninth transistor T42, and a tenth transistor T32
  • the second pull-down sustaining module 607 includes an eleventh transistor.
  • the first pull-down sustaining module 606 includes a first inverting unit 200 and a sustaining unit 300.
  • the sixth transistor T51 is the first inverting transistor
  • the seventh transistor T52 is the first inverting transistor.
  • the eighth transistor T53 is a third reverse transistor
  • the ninth transistor T42 is a first sustain transistor
  • the tenth transistor T32 is a second sustain transistor.
  • the eleventh transistor T61 is the first inverting transistor
  • the twelfth transistor T62 is the second inverting transistor
  • the thirteenth transistor T63 is the third.
  • Inversion transistor in the sustain unit 300 of the second pull-down sustain module 607, the fourteenth transistor T43 is the first sustain transistor, and the fifteenth transistor T33 is the second sustain transistor.
  • one of the first electrode and the second electrode of each transistor is the source and the other is the drain.
  • the first reverse transistor, the second reverse transistor, the third reverse transistor, the first sustain transistor, the second sustain transistor, and the other transistors are all N-type or P-type transistors.
  • the gate and first electrode of the sixth transistor T51 are connected to the low-frequency clock signal input terminal, the second electrode of the sixth transistor T51 and the first electrode of the seventh transistor T52 are connected to the second node A(N),
  • the gate of the seventh transistor T52 is connected to the first node Q(N), the second electrode of the seventh transistor T52 is connected to the first power supply low potential signal VSSQ, and the gate and the first electrode of the eighth transistor T53 are connected to the second node A(N).
  • the second electrode of the eighth transistor T53 is connected to the input terminal of the sustain unit 300.
  • the gate of the ninth transistor T42 and the gate of the tenth transistor T32 are connected to the input terminal of the sustain unit 300, the first electrode of the ninth transistor T42 is connected to the first power supply low potential signal VSSQ, and the second electrode of the ninth transistor T42 is connected to the A node Q(N), the first electrode of the tenth transistor T32 is connected to the second power low potential signal VSSG, and the second electrode of the tenth transistor T32 is connected to the gate drive signal G(N) of the current stage.
  • the low-frequency clock signal input terminal inputs the first low-frequency clock signal LC1
  • the input terminal of the sustain unit 300 is connected to the fourth node P(N).
  • the signal input from the low-frequency clock signal input terminal of the first inversion unit 200 is equivalent to a DC signal with a value of 28v, that is, the first low-frequency clock signal LC1 is always at a high level during operation, so
  • the sixth transistor T51 is always in the on state, pulling the potential of the second node A(N) high.
  • the seventh transistor T52 is turned on, and the first power supply low potential signal VSSQ pulls the potential of the second node A(N) low, so the second node A(N) simultaneously receives the sixth node A(N).
  • the high potential input from the transistor T51 and the low potential input from the seventh transistor T52 make the second node A(N) low in potential, which is not enough to turn on the eighth transistor T53, so the fourth node P(N) is low in potential, that is The input terminal potential of the sustain unit is low, and the ninth transistor T42 and the tenth transistor T32 are turned off.
  • the seventh transistor T52 is turned off, and the second node A(N) only receives the high potential input by the sixth transistor T51.
  • the potential of the second node A(N) is high, so that The eighth transistor T53 is turned on, the potential of the fourth node P(N) is high, that is, the potential of the input terminal of the sustaining unit 300 is high, the ninth transistor T42 and the tenth transistor T32 are turned on, and the first power supply low potential signal VSSQ and The second power supply low potential signal VSSG is input to the first node Q(N) and the gate drive signal G(N) of the current stage, and the potentials of both are maintained at a low potential.
  • the structure of the Nth-level GOA unit in the existing 8K product is shown in Figure 8, including a pull-up control module 801, a pull-up module 802, a signal download module 803, a first pull-down module 804, a second pull-down module 805, The first pull-down maintenance module 806 and the second pull-down maintenance module 807.
  • the pull-up control module 801 includes a transistor T11
  • the pull-up module 802 includes a transistor T21
  • the signal download module 803 includes a transistor T22
  • the first pull-down module 804 includes a transistor T31
  • the second pull-down module 805 includes a transistor T41.
  • the pull-down sustaining module 806 includes transistors T51, T52, T53, T54, T32, and T42.
  • the second pull-down sustaining module 807 includes transistors T61, T62, T63, T64, T33, and T43.
  • the connection mode of each transistor is shown in the figure.
  • the first pull-down maintenance module 806 includes an inverter 100 and transistors T32 and T42.
  • the inverter 100 is composed of 4 transistors. Its working principle is: when the potential of the Q(N) point is low, T52 and T54 Turn off, T51 turns on, so that the potential of point A is high, and then turns on T53, and point P(N) is high; when the potential of point Q(N) is high, T52 and T54 are turned on, and VSSQ is input to point A At low potential, T51 is turned on, and high potential is input to point A.
  • the inverting units are both the first inverting unit 200, and each first inverting unit 200 can be realized by only three transistors.
  • the first node and the voltage of the signal at the input terminal of the sustaining unit are opposite, so the Nth-stage GOA unit in the GOA circuit only needs 16 transistors.
  • two transistors are reduced, so that the structure of the GOA circuit is simplified and saved.
  • the space occupied by the GOA circuit is reduced.
  • the same settings as the Nth level of GOA unit can be used.
  • FIGS 9 and 10 respectively show the layer stacking structure of the first pull-down sustaining module and the reverse unit in the second pull-down sustaining module of the Nth-level GOA unit in the GOA circuit provided by the prior art and the embodiments of the present application.
  • Each film layer includes a first metal layer 110, a source and drain layer 120, and a connecting member 130.
  • the overlapping portion of the first metal layer 110 and the active layer forms the gate of each transistor, and also forms the second A node Q(N)
  • the source-drain layer 120 forms the source and drain of each transistor, the first power low-potential signal line VSSQ, and the low-frequency clock signal line LC.
  • One end of the connecting member 130 covers the source-drain layer 120 , The other end is connected to the via hole in the first metal layer 110 to realize the connection between the gate of one transistor and the source or drain of another transistor.
  • the material of the connecting member 130 is indium tin oxide.
  • each inverter needs to be provided with four transistors, and the connection requires three connecting members.
  • the structure is relatively complex and takes up a lot of space.
  • each inverter unit in the present application Only three transistors need to be provided, and only two connecting members are needed for connection, the structure is relatively simple, the space is less, the manufacturing process is simplified, and the cost is saved.
  • the reverse units in the first pull-down maintaining module 606 and the second pull-down maintaining module 607 are both the first reverse unit 200, but the present application is not limited to this.
  • the first pull-down maintaining module 606 and the second pull-down maintaining module 607 One of the pull-down sustaining module 606 and the second pull-down sustaining module 607 is a first inverting unit, the other is a second inverting unit, and the second inverting unit includes a fourth inverting transistor and a second inverting unit.
  • the gate and first electrode of the fourth reverse transistor are connected to the low-frequency clock signal input terminal, and the second electrode of the fourth reverse transistor and the fifth reverse transistor
  • the first electrode of the transistor is connected to the third node
  • the gate of the fifth reverse transistor is connected to the first node
  • the second electrode of the fifth reverse transistor is connected to the first power supply low potential signal
  • the gate of the sixth reverse transistor is connected to the first node.
  • the first electrode of the sixth reverse transistor is connected to the first electrode of the fourth reverse transistor, the second electrode of the sixth reverse transistor and the first electrode of the seventh reverse transistor are connected to the input end of the sustain unit,
  • the gate of the seventh reverse transistor is connected to the first node, and the second electrode of the seventh reverse transistor is connected to the first power low potential signal.
  • FIG. 11 it is a schematic diagram of the second structure of the N-th level GOA unit in the GOA circuit provided by the embodiment of this application.
  • the inversion unit in the first pull-down maintenance module 606 is the first inversion unit 200, and the structure is the same as that in FIG. 3, and the inversion unit in the second pull-down maintenance module 607 is the second inversion unit 400.
  • the second inverting unit 400 includes an eleventh transistor T61, a twelfth transistor T62, a thirteenth transistor T63, and a sixteenth transistor T64, wherein the eleventh transistor T61 is a fourth inverting transistor, and the twelfth transistor T62 is the fifth reverse transistor, the thirteenth transistor T63 is the sixth reverse transistor, and the sixteenth transistor T64 is the seventh reverse transistor.
  • the gate and the first electrode of the eleventh transistor T61 are connected to the low-frequency clock signal input terminal, the second electrode of the eleventh transistor T61 and the first electrode of the twelfth transistor T62 are connected to the third node B(N), and the twelfth transistor T61 is connected to the third node B(N).
  • the gate of the transistor T62 is connected to the first node Q(N), the second electrode of the twelfth transistor T62 is connected to the first power supply low potential signal VSSQ, the gate of the thirteenth transistor T63 is connected to the third node B(N), The first electrode of the thirteenth transistor T63 is connected to the first electrode of the eleventh transistor T61, the second electrode of the thirteenth transistor T63 and the first electrode of the sixteenth transistor T64 are connected to the input end of the sustain unit 300, and the sixteenth transistor The gate of T64 is connected to the first node Q(N), and the second electrode of the sixteenth transistor T64 is connected to the first power low potential signal VSSQ.
  • the low-frequency clock signal input terminal inputs the second low-frequency clock signal LC2, and the input terminal of the sustain unit 300 is connected to the fifth node R(N).
  • the structure of the second inversion unit 400 is the same as that in the prior art, so it can also play the role of making the first node Q(N) and the input terminal potential of the sustaining unit 300 opposite.
  • the reverse unit in the first pull-down maintaining module 606 is designed as the first reverse unit 200
  • the reverse unit in the second pull-down maintaining module 607 is designed as the second reverse unit 400
  • the first pull-down maintaining module 607 is designed as the second reverse unit 400.
  • the inverting unit in the sustaining module 606 is designed as the second inverting unit 400
  • the inverting unit in the second pull-down sustaining module 607 is designed as the first inverting unit 200, both of which can make the total number of transistors in the Nth-level GOA unit be 16. Compared with the prior art, one transistor is reduced, so the GOA circuit structure is simplified and the occupied space is saved.
  • An embodiment of the present application also provides an electronic device, including a display panel and a driving chip.
  • the display panel includes multiple scan lines, 2m clock signal lines, and GOA circuits; the scan lines are located in the display area; the clock signal lines are located in the non-display area.
  • the signal line setting area; the GOA circuit is located between the display area and the signal line setting area.
  • the GOA circuit includes multiple cascaded GOA units.
  • the GOA unit includes multiple effective GOA units and 2m redundant GOA units arranged in sequence. Effective GOA The drive signal output terminal of the unit is connected to the scan line sequentially and corresponds to each other. Multiple effective GOA units form multiple effective GOA modules arranged in sequence. Each effective GOA module includes 2m effective GOA units.
  • each valid GOA unit is sequentially connected with 2m clock signal lines and correspond one-to-one
  • the clock signal input terminals of 2m redundant GOA units are sequentially connected with 2m clock signal lines and correspond one-to-one.
  • the 2m redundant GOA units have the same structure.
  • the redundant GOA unit has the same structure as the effective GOA unit.
  • every m GOA units from the first position form a GOA module, and between adjacent GOA modules, the rear GOA module is used to provide a reset signal to the previous GOA module.
  • the drive signal output terminal of the n-th level GOA unit in the subsequent GOA module is connected to the reset signal terminal of the n-th level GOA unit in the previous GOA module.
  • the drive signal output terminal of the nth level GOA unit in the preceding GOA module is connected to the drive signal input terminal of the nth level GOA unit in the subsequent GOA module.
  • the drive signal input end of each GOA unit is connected to the frame start signal line.
  • the GOA unit further includes a power signal input terminal, and the power signal input terminal is connected to a power signal line.
  • the GOA circuit is located on the left or right side of the display area.
  • the GOA unit of the Nth stage includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node according to the previous stage transmission signal
  • a pull-up module connected to the first node, and configured to pull up the potential of the gate drive signal of the current level according to the clock signal of the current level;
  • the signal download module is connected to the first node, and is used to control the output of the transmission signal of the current level according to the clock signal of the current level;
  • the first pull-down module is used to pull down the potential of the gate drive signal of the current stage according to the first subsequent stage gate drive signal
  • a second pull-down module connected to the first node, and configured to pull down the potential of the first node according to a second rear-stage gate drive signal
  • a first pull-down maintenance module connected to the first node, and configured to maintain the low potential of the first node and the gate drive signal of the current stage according to the first low-frequency clock signal;
  • the second pull-down maintenance module connected to the first node, is used to maintain the low potentials of the first node and the gate drive signal of the current stage according to the second low-frequency clock signal, the first low-frequency clock signal and The second low-frequency clock signal has an opposite potential at the same time;
  • the first pull-down maintaining module and the second pull-down maintaining module both include an inverting unit and a maintaining unit, the output terminal of the inverting unit is connected to the input terminal of the maintaining unit, and at least one of the inverters is
  • the reverse unit is a first reverse unit;
  • the first reverse unit includes a first reverse transistor, a second reverse transistor, and a third reverse transistor, and the gate of the first reverse transistor is connected to the first electrode Low-frequency clock signal input terminal, the second electrode of the first reverse transistor and the first electrode of the second reverse transistor are connected to a second node, and the gate of the second reverse transistor is connected to the first node ,
  • the second electrode of the second reverse transistor is connected to the first power supply low potential signal, the gate and the first electrode of the third reverse transistor are connected to the second node, and the second electrode of the third reverse transistor is connected to the second node.
  • the two electrodes are connected to the input end of the sustain unit.
  • the sustain unit includes a first sustain transistor and a second sustain transistor, and the gate of the first sustain transistor and the gate of the second sustain transistor are connected to the input terminal of the sustain unit,
  • the first electrode of the first sustain transistor is connected to the first power supply low potential signal
  • the second electrode of the first sustain transistor is connected to the first node
  • the first electrode of the second sustain transistor is connected to the second The power supply low-level signal
  • the second electrode of the second sustain transistor is connected to the gate drive signal of the current stage.
  • the electronic device of this application can be an 8K product with a resolution of 7680*4320, where the display panel can be a liquid crystal display panel or an OLED display panel, a timing controller is provided in the driving chip, and the clock in each clock signal line in the display panel The signals are provided by the timing controller.
  • the number of GOA units connected to each clock signal line in the display panel is the same, so the load of each clock signal line is the same, and periodic dark lines will not be generated at low gray levels, and the display effect is better.
  • the embodiments of the present application provide a display panel and an electronic device.
  • the display panel includes a plurality of scan lines, 2m clock signal lines and GOA circuits; the scan lines are located in the display area; the clock signal lines are located in the signal line setting area of the non-display area;
  • the GOA circuit is located between the display area and the signal line setting area.
  • the GOA circuit includes multiple cascaded GOA units.
  • the GOA unit includes multiple effective GOA units and 2m redundant GOA units arranged in sequence.
  • the drive signal of the effective GOA unit is output.
  • the terminals are connected in sequence with the scan lines and correspond to each other. Multiple effective GOA units form multiple effective GOA modules arranged in sequence.
  • Each effective GOA module includes 2m effective GOA units.
  • 2m effective GOA units The clock signal input terminals are sequentially connected to the 2m clock signal lines and correspond one to one, and the clock signal input terminals of the 2m redundant GOA units are sequentially connected to the 2m clock signal lines and correspond to each other.
  • the number of GOA units connected to each clock signal line is equal, so the load of each clock signal line is the same, and no periodic dark lines are generated under low gray levels.

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Abstract

提供了一种显示面板和电子设备，显示面板中GOA电路包括多个级联的GOA单元，GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块内2m个有效GOA单元与2m条时钟信号线顺序连接，2m个冗余GOA单元与2m条时钟信号线顺序连接。该显示面板低灰阶下无周期性暗纹。

Description

显示面板和电子设备 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和电子设备。
 背景技术
现有8K显示面板中，包括多条时钟信号线和GOA电路，GOA电路包括多个级联的GOA单元，其中每个GOA单元与一条时钟信号线连接，时钟信号线给GOA单元提供时钟信号，以控制GOA单元输出驱动信号。然而，目前的显示面板中各时钟信号线上连接的GOA单元数量不是均匀的，因此各时钟信号线的负载也不同，造成显示面板在低灰阶下产生周期性暗纹，影响显示效果。
因此，现有的显示面板存在低灰阶下产生周期性暗纹的技术问题，需要改进。
 技术问题
本申请实施例提供一种显示面板和电子设备，用以缓解现有显示面板在低灰阶下产生周期性暗纹的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，包括：
多条扫描线，所述扫描线位于显示区；
2m条时钟信号线，所述时钟信号线位于非显示区内的信号线设置区；
GOA电路，位于所述显示区和所述信号线设置区之间，所述GOA电路包括多个级联的GOA单元，所述GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，所述有效GOA单元的驱动信号输出端与所述扫描线顺序连接且一一对应，所述多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在所述有效GOA模块内，所述2m个有效GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应，所述2m个冗余GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应。
在本申请的显示面板中，所述2m个冗余GOA单元的结构相同。
在本申请的显示面板中，所述冗余GOA单元与所述有效GOA单元的结构相同。
在本申请的显示面板中，所述GOA电路中，自首位起每m个GOA单元形成一个GOA模块，相邻所述GOA模块间，在后GOA模块用于向在前GOA模块提供复位信号。
在本申请的显示面板中，所述在后GOA模块中第n级GOA单元的驱动信号输出端，与所述在前GOA模块中第n级GOA单元的复位信号端连接。
在本申请的显示面板中，所述在前GOA模块中第n级GOA单元的驱动信号输出端，与所述在后GOA模块中第n级GOA单元的驱动信号输入端连接。
在本申请的显示面板中，自首位起m个GOA单元形成的GOA模块中，各GOA单元的驱动信号输入端均连接帧起始信号线。
在本申请的显示面板中，所述GOA电路中，第N级的GOA单元包括：
上拉控制模块，与第一节点连接，用于根据前级级传信号，上拉所述第一节点的电位；
上拉模块，与所述第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；
信号下传模块，与所述第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；
第一下拉模块，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；
第二下拉模块，与所述第一节点连接，用于根据第二后级栅极驱动信号，下拉所述第一节点的电位；
第一下拉维持模块，与所述第一节点连接，用于根据第一低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位；
第二下拉维持模块，与所述第一节点连接，用于根据第二低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位，所述第一低频时钟信号和所述第二低频时钟信号在相同时刻电位相反；
其中，所述第一下拉维持模块和所述第二下拉维持模块中均包括反向单元和维持单元，所述反向单元的输出端连接所述维持单元的输入端，至少一个所述反向单元为第一反向单元；所述第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，所述第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第一反向晶体管的第二电极和所述第二反向晶体管的第一电极连接第二节点，所述第二反向晶体管的栅极连接所述第一节点，所述第二反向晶体管的第二电极连接第一电源低电位信号，所述第三反向晶体管的栅极和第一电极连接所述第二节点，所述第三反向晶体管的第二电极连接所述维持单元的输入端。
在本申请的显示面板中，所述维持单元包括第一维持晶体管和第二维持晶体管，所述第一维持晶体管的栅极和所述第二维持晶体管的栅极连接所述维持单元的输入端，所述第一维持晶体管的第一电极连接所述第一电源低电位信号，所述第一维持晶体管的第二电极连接所述第一节点，所述第二维持晶体管的第一电极连接第二电源低电位信号，所述第二维持晶体管的第二电极连接所述本级栅极驱动信号。
在本申请的显示面板中，所述第一下拉维持模块和所述第二下拉维持模块中的反向单元均为第一反向单元。
在本申请的显示面板中，所述第一下拉维持模块和所述第二下拉维持模块中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，所述第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，所述第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第四反向晶体管的第二电极和所述第五反向晶体管的第一电极连接第三节点，所述第五反向晶体管的栅极连接所述第一节点，所述第五反向晶体管的第二电极连接第一电源低电位信号，所述第六反向晶体管的栅极连接所述第三节点，所述第六反向晶体管的第一电极连接所述第四反向晶体管的第一电极，所述第六反向晶体管的第二电极与所述第七反向晶体管的第一电极连接所述维持单元的输入端，所述第七反向晶体管的栅极连接所述第一节点，所述第七反向晶体管的第二电极连接所述第一电源低电位信号。
在本申请的显示面板中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极和第一电极连接所述前级级传信号，第二电极连接所述第一节点。
在本申请的显示面板中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级栅极驱动信号。
在本申请的显示面板中，所述信号下传模块包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级级传信号。
在本申请的显示面板中，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极连接所述第一后级栅极驱动信号，第一电极连接所述第二电源低电位信号，第二电极连接所述本级栅极驱动信号。
在本申请的显示面板中，所述第二下拉模块包括第五晶体管，所述第五晶体管的栅极连接所述第二后级栅极驱动信号，第一电极连接所述第一电源低电位信号，第二电极连接所述第一节点。
本申请还提供一种电子设备，包括显示面板和驱动芯片，所述显示面板包括：
多条扫描线，所述扫描线位于显示区；
2m条时钟信号线，所述时钟信号线位于非显示区内的信号线设置区；
GOA电路，位于所述显示区和所述信号线设置区之间，所述GOA电路包括多个级联的GOA单元，所述GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，所述有效GOA单元的驱动信号输出端与所述扫描线顺序连接且一一对应，所述多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在所述有效GOA模块内，所述2m个有效GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应，所述2m个冗余GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应。
在本申请的电子设备中，所述2m个冗余GOA单元的结构相同。
在本申请的电子设备中，所述冗余GOA单元与所述有效GOA单元的结构相同。
在本申请的电子设备中，所述GOA电路中，自首位起每m个GOA单元形成一个GOA模块，相邻所述GOA模块间，在后GOA模块用于向在前GOA模块提供复位信号。
 有益效果
本申请的有益效果：本申请实施例提供一种显示面板和电子设备，显示面板包括多条扫描线、2m条时钟信号线和GOA电路，所述扫描线位于显示区；所述时钟信号线位于非显示区内的信号线设置区；GOA电路位于所述显示区和所述信号线设置区之间，所述GOA电路包括多个级联的GOA单元，所述GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，所述有效GOA单元的驱动信号输出端与所述扫描线顺序连接且一一对应，所述多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在所述有效GOA模块内，所述2m个有效GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应，所述2m个冗余GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应。本申请中每条时钟信号线连接的GOA单元数量相等，因此每条时钟信号线的负载相同，在低灰阶下不会产生周期性暗纹。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的第一种结构示意图。
图2为本申请实施例提供的显示面板的第二种结构示意图。
图3为本申请实施例提供的显示面板的第三种结构示意图。
图4为本申请实施例提供的显示面板的第四种结构示意图。
图5为本申请实施例提供的显示面板中CK1和CK7的时序图。
图6为本申请实施例的GOA电路中第N级GOA单元的第一种结构示意图。
图7为本申请实施例的GOA电路的第N级GOA单元中第一下拉维持模块的结构示意图。
图8为现有技术的的GOA电路中第N级GOA单元的第一种结构示意图。
图9为现有技术的GOA电路的第N级GOA单元中，第一下拉维持模块和第二下拉维持模块中反向单元的膜层叠加结构示意图。
图10为本申请实施例的GOA电路的第N级GOA单元中，第一下拉维持模块和第二下拉维持模块中反向单元的膜层叠加结构示意图。
图11本申请实施例的GOA电路中第N级GOA单元的第二种结构示意图。
本申请的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相近的单元是用以相同标号表示。
本申请实施例提供一种显示面板和电子设备，用以缓解现有显示面板在低灰阶下产生周期性暗纹的技术问题。
本申请的显示面板包括多条扫描线、2m条时钟信号线和GOA电路，扫描线位于显示区，时钟信号线位于非显示区内的信号线设置区，GOA电路位于显示区和信号线设置区之间，GOA电路包括多个级联的GOA单元，GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，有效GOA单元的驱动信号输出端与扫描线顺序连接且一一对应，多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在有效GOA模块内，2m个有效GOA单元的时钟信号输入端与2m条时钟信号线顺序连接且一一对应，2m个冗余GOA单元的时钟信号输入端与2m条时钟信号线顺序连接且一一对应。
如图1所示，为本申请实施例提供的显示面板的第一种结构示意图，显示面板包括显示区10和位于显示区10四周的非显示区，其中，非显示区包括信号线设置区21、GOA(Gate Driver on Array，GOA)电路设置区22和数据驱动电路设置区23。显示区10内设置有阵列排布的多个子像素，每个子像素通过显示区10中的一个像素驱动电路进行驱动，像素驱动电路中驱动晶体管的扫描信号和数据信号分别由扫描线11和数据线12提供，在显示区10中，同行子像素的像素驱动电路中，驱动晶体管的栅极与同一条栅极线11连接，同列子像素的像素驱动电路中，驱动晶体管的源极或漏极与同一条数据线12连接。
信号线设置区21中设置有多条时钟信号线，GOA电路设置区22中设置有GOA电路，时钟信号线提供时钟信号给GOA电路，GOA电路中再输出栅极驱动信号，并将栅极驱动信号提供给扫描线11。
如图2所示，为本申请实施例提供的显示面板的第二种结构示意图，本实施例以8K产品为例进行说明，8K产品中显示面板的分辨率为7680x4320，因此包括7680条数据线，4320条扫描线。
显示面板包括2m条时钟信号线和4320条扫描线，GOA电路中包括多个级联的GOA单元，GOA单元从上往下依次包括多个有效GOA单元和2m个冗余GOA单元，其中有效GOA单元用“GOA Unit”表示，冗余GOA单元用“Dummy GOA Unit”表示。m的取值可以是任意正整数，本实施例取m为6，因此包括12条时钟信号线CK1至CK12和12个冗余GOA单元Dummy GOA Unit 1至Dummy GOA Unit 12，4320条扫描线分别用G1至G4320表示。
有效GOA单元的驱动信号输出端与扫描线顺序连接且一一对应，即有效单元的数量与扫描线的数量一致，由于扫描线有4320条，有效GOA单元数量也为4320个，用GOA Unit 1至GOA Unit 4320表示。冗余GOA单元的驱动信号输出端不与扫描线连接。
GOA电路中的每个有效GOA单元，均包括时钟信号输入端，时钟信号线与时钟信号输入端连接，输入时钟信号，以驱动有效GOA单元工作，输出栅极驱动信号给对应的扫描线。而对于冗余GOA单元，虽不与扫描线连接，但也需输出信号给在前的有效GOA单元进行复位，因此也需要与时钟信号线连接。
4320个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括12个有效GOA单元，在有效GOA模块内，12个有效GOA单元的时钟信号输入端与12条时钟信号线顺序连接且一一对应。如图2所示，GOA Unit 1至GOA Unit 12为一个有效GOA模块，GOA Unit 13至GOA Unit 24为一个有效GOA模块，依次类推，GOA Unit 4309至GOA Unit 4320为一个有效GOA模块。因此，4320个有效GOA单元形成了4320/12=360个有效GOA模块，每个有效GOA模块中，12个有效GOA单元的时钟信号输入端与12条时钟信号线顺序连接且一一对应，即GOA Unit 1与CK1连接，GOA Unit 2与CK2连接，依次类推，GOA Unit 12与CK12连接。对于同一条时钟信号线，每个有效GOA模块中均有一个有效GOA单元的时钟信号输入端与其相连，因此CK1至CK12中每条时钟信号线均连接360个有效GOA单元。
此外，排列在有效GOA单元后的12个冗余GOA单元的时钟信号输入端与12条时钟信号线也顺序连接且一一对应，即Dummy GOA Unit 1与CK1连接，Dummy GOA Unit 2与CK2连接，依次类推，Dummy GOA Unit 12与CK12连接，因此，CK1至CK12中每条时钟信号线均连接1个冗余GOA单元。
由上述连接方式可知，CK1至CK12中每条时钟信号线连接的GOA单元数均为361个，因此负载是均匀的，每条时钟信号线在输入给有效GOA单元后，有效GOA单元输出的栅极驱动信号也是稳定的，进而使得显示面板在同一灰阶下的亮度一致，低灰阶下不会出现周期性暗纹，提高了显示效果。
在一种实施例中，12个冗余GOA单元的结构相同。结构相同指每个冗余GOA单元内部各晶体管的设置数量和连接方式相同，时钟信号线输入给每个冗余GOA单元的时钟信号后驱动方式也是相同的，因此每条时钟信号线对于冗余GOA单元的负载也相等。
在一种实施例中，冗余GOA单元与有效GOA单元的结构相同，即冗余GOA单元与有效GOA单元内部各晶体管的设置数量和连接方式相同，将冗余GOA单元与有效GOA单元结构设置成相同，可以简化制作工艺，且减小了同一时钟信号线连接的有效GOA单元与冗余GOA单元之间的负载差异。
如图3和图4示出了显示面板中各GOA单元的连接关系，其中图3以前12级有效GOA单元为例，对各GOA单元之间信号的传输方式进行说明，图4以最后6级有效GOA单元和12级冗余GOA单元为例，对各GOA单元之间信号的传输方式进行说明。
在一种实施例中，GOA电路中，自首位起每m个GOA单元形成一个GOA模块，相邻GOA模块间，在后GOA模块用于向在前GOA模块提供复位信号。
本申请实施例中m取6，因此如图3所示，自首位起每6个GOA单元形成一个GOA模块，即GOA Unit 1至GOA Unit 6为第一个GOA模块，GOA Unit 7至GOA Unit 12为第二个GOA模块，依次类推，Dummy GOA Unit 7至Dummy GOA Unit 12为最后一个GOA模块。第二个GOA模块为第一个GOA模块提供复位信号，第三个GOA模块为第二个GOA模块提供复位信号，依次类推，最后一个GOA模块为倒数第二个GOA模块提供复位信号。
每个有效GOA单元中，均包括驱动信号输入端Input、驱动信号输出端Output、以及复位信号端Reset。
在一种实施例中，在后GOA模块中第n级GOA单元的驱动信号输出端，与在前GOA模块中第n级GOA单元的复位信号端连接。其中，1≤n≤m。如图3所示，第二个GOA模块中GOA Unit 7为第1级GOA单元，第一个GOA模块中GOA Unit 1为第1级GOA单元，GOA Unit 7的驱动信号输出端Output除了与扫描线G7连接外，还与GOA Unit 1的复位信号端Reset连接，给GOA Unit 1提供复位信号，同样地，GOA Unit 8至GOA Unit 12中的驱动信号输出端Output除了与扫描线G8至G12连接外，也分别与GOA Unit 2至GOA Unit 6的复位信号端Reset连接，给GOA Unit 2至GOA Unit 6提供复位信号。
复位的目的是将上一帧时的栅极驱动信号清零，防止上一帧的栅极驱动信号与下一帧的栅极驱动信号发生串扰，影响画面效果。如图5所示，为CK1和CK7的时序图，自t1时刻起CK1与CK7的相位相反，在t1时间段，CK1开始输入第一个高电位，CK7还未开始为低电位，CK1控制GOA Unit 1输出栅极驱动信号给G1，在t2时间段，CK1为低电位，GOA Unit 1停止输出栅极驱动信号，CK7开始输入第一个高电位，控制GOA Unit 7输出栅极驱动信号给G7，同时，将该驱动信号传输给GOA Unit 1的复位信号端Reset，将t1时刻GOA Unit 1输出的栅极驱动信号电位拉低，也即清零，则在t3时间段，CK1的第二个高电位到来时，t3时间段的栅极驱动信号不会对本次的栅极驱动信号产生影响，不会发生串扰，因此保证了显示效果。
在一种实施例中，在前GOA模块中第n级GOA单元的驱动信号输出端，与在后GOA模块中第n级GOA单元的驱动信号输入端连接。其中，1≤n≤m。如图3所示，第二个GOA模块中GOA Unit 7为第1级GOA单元，第一个GOA模块中GOA Unit 1为第1级GOA单元，GOA Unit 1的驱动信号输出端Output除了与扫描线G1连接外，还与GOA Unit 7的驱动信号输入端Input连接，给GOA Unit 7提供驱动信号，同样地，GOA Unit 2至GOA Unit 6中的驱动信号输出端Output除了与扫描线G2至G6连接外，也分别与GOA Unit 8至GOA Unit 12中的驱动信号输入端Input连接，给GOA Unit 8至GOA Unit 12提供驱动信号。
在一种实施例中，自首位起m个GOA单元形成的GOA模块中，各GOA单元的驱动信号输入端均连接帧起始信号线。如图3所示，m为6时，前m个GOA单元为GOA Unit 1至GOA Unit 6，形成第一个GOA模块，GOA Unit 1至GOA Unit 6的驱动信号输入端Input均由帧起始信号线STV提供，帧起始信号线STV位于信号线设置区内。
在一种实施例中，GOA单元还包括电源信号输入端（图未示出），电源信号输入端连接电源信号线。GOA单元中通常设置有上拉单元或下拉单元等，电源信号线位于信号线设置区，包括电源高电位信号线VGH和电源低电位信号线VSS，上拉单元通过与电源高电位信号线VGH连接，上拉特定节点的电位，下拉单元通过与电源电源低电位信号线VSS连接，下拉特定节点的电位，以满足GOA单元在不同工作阶段的需求。
在一种实施例中，GOA电路位于显示区的左侧或右侧，即本申请中GOA电路的驱动方式为单侧驱动。
如图4所示，GOA Unit 4315至GOA Unit 4320为自首位起第720个GOA模块，Dummy GOA Unit 1至Dummy GOA Unit 6为第721个GOA模块，Dummy GOA Unit 7至Dummy GOA Unit 12为第722个GOA模块，其中第721个GOA模块中各冗余GOA单元为第720个GOA模块中各有效GOA单元提供复位信号，第722个GOA模块中各冗余GOA单元为第721个GOA模块中各冗余GOA单元提供复位信号，第722个GOA模块中各冗余GOA单元自身不进行复位。
在现有技术中，仅设置有6个冗余GOA单元，以满足对GOA Unit 4315至GOA Unit 4320这6个有效GOA单元的复位需求，然而Dummy GOA Unit 1至Dummy GOA Unit 6本身不进行复位，因此Dummy GOA Unit 1至Dummy GOA Unit 6的驱动信号输出端Output输出的驱动信号会受到前一帧驱动信号的影响，产生串扰，而Dummy GOA Unit 1至Dummy GOA Unit 6的驱动信号输出端Output又分别与GOA Unit 4315至GOA Unit 4320中的复位信号端Reset连接，因此对GOA Unit 4315至GOA Unit 4320的复位效果也有一定的影响，使得G4315至G4315中接受到的栅极驱动信号也会有一定偏差，影响显示效果。而本申请实施例中，增加的Dummy GOA Unit 7至Dummy GOA Unit 12对Dummy GOA Unit 1至Dummy GOA Unit 6进行了复位，因此Dummy GOA Unit 1至Dummy GOA Unit 6的驱动信号输出端Output输出的驱动信号不会受到前一帧驱动信号的影响，不会产生串扰，在对GOA Unit 4315至GOA Unit 4320复位时，复位效果也较好，因此相对于现有技术，提升了显示效果。
当冗余GOA单元与有效GOA单元的结构相同，即所有GOA单元结构相同时，GOA电路中第N级的GOA单元结构如图6所示，包括上拉控制模块601、上拉模块602、信号下传模块603、第一下拉模块604、第二下拉模块605、第一下拉维持模块606和第二下拉维持模块607。上拉控制模块601与第一节点Q(N)连接，用于根据前级级传信号，上拉第一节点Q(N)的电位；上拉模块602与第一节点Q(N)连接，用于根据本级时钟信号CK，上拉本级栅极驱动信号G(N)的电位；信号下传模块603与第一节点Q(N)连接，用于根据本级时钟信号CK，控制本级级传信号ST(N)的输出；第一下拉模块604用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号G(N)的电位；第二下拉模块605与第一节点Q(N)连接，用于根据第二后级栅极驱动信号，下拉第一节点Q(N)的电位；第一下拉维持模块606与第一节点Q(N)连接，用于根据第一低频时钟信号LC1，维持第一节点Q(N)和本级栅极驱动信号G(N)的低电位；第二下拉维持模块607与第一节点Q(N)连接，用于根据第二低频时钟信号LC2，维持第一节点Q(N)和本级栅极驱动信号G(N)的低电位，第一低频时钟信号LC1和第二低频时钟信号LC2在相同时刻电位相反；其中，第一下拉维持模块606和第二下拉维持模块607中均包括反向单元和维持单元，反向单元的输出端连接维持单元的输入端，至少一个反向单元为第一反向单元；第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，第一反向晶体管的第二电极和第二反向晶体管的第一电极连接第二节点A(N)，第二反向晶体管的栅极连接第一节点Q(N)，第二反向晶体管的第二电极连接第一电源低电位信号VSSQ，第三反向晶体管的栅极和第一电极连接第二节点A(N)，第三反向晶体管的第二电极连接维持单元的输入端。
在上述实施例中可知，本申请的GOA电路中，某一GOA单元的驱动信号输入端Input与该GOA单元之间且与其相隔六级的GOA单元的驱动信号输出端Output连接，第N级GOA单元输出的级传信号为第N级级传信号ST(N)，输出的栅极驱动信号为第n级栅极驱动信号G(N)，6≤N≤M，其中N为整数，M为GOA电路中GOA单元的总级数。前级级传信号为第N级GOA单元之前的其他GOA单元的级传信号，可以是前1级、前2级或前多级，第一后级栅极驱动信号和第二后级栅极驱动信号均为第N级GOA单元之后的其他GOA单元的栅极驱动信号，可以是后1级、后2级或后多级。本申请的以8K产品的GOA电路为例，取前级级传信号为ST(N-6)，第一后级栅极驱动信号为G(N+6)，第二后级栅极驱动信号为G(N+8)，其中ST(N-6)为第N级栅极驱动信号G(N)之前且与其相隔六级的级传信号，第一后级栅极驱动信号G(N+6)为第N级栅极驱动信号G(N)之后且与其相隔六级的栅极驱动信号，第二后级栅极驱动信号G(N+8)为第N级栅极驱动信号G(N)之后且与其相隔八级的栅极驱动信号。
在一种实施例中，上拉控制模块601包括第一晶体管T11，第一晶体管T11的栅极和第一电极连接前级级传信号ST(N-6)，第二电极连接第一节点Q(N)。
在一种实施例中，上拉模块602包括第二晶体管T21，第二晶体管T21的栅极连接第一节点Q(N)，第一电极连接本级时钟信号CK，第二电极连接本级栅极驱动信号G(N)。
在一种实施例中，信号下传模块603包括第三晶体管T22，第三晶体管T22的栅极连接第一节点Q(N)，第一电极连接本级时钟信号CK，第二电极连接本级级传信号ST(N)。
在一种实施例中，第一下拉模块604包括第四晶体管T31，第四晶体管T31的栅极连接第一后级栅极驱动信号G(N+6)，第一电极连接第二电源低电位信号VSSG，第二电极连接本级栅极驱动信号G(N)。
在一种实施例中，第二下拉模块605包括第五晶体管T41，第五晶体管T41的栅极连接第二后级栅极驱动信号G(N+8)，第一电极连接第一电源低电位信号VSSQ，第二电极连接第一节点Q(N)。
在本申请中，第一下拉维持模块606和第二下拉维持模块607均用于维持第一节点Q(N)和本级栅极驱动信号G(N)的低电位，因此两者的作用相同。在GOA电路进行驱动时，第一下拉维持模块606的低频时钟信号输入端输入第一低频时钟信号LC1，第二下拉维持模块607的低频时钟信号输入端输入第二低频时钟信号LC2，其中第一低频时钟信号LC1和第二低频时钟信号LC2均为200倍帧周期，占空比1/2的低频时钟信号，且两者相位差1/2周期，在相同时刻，第一低频时钟信号LC1和第二低频时钟信号LC2的相位相反，因此可以驱动第一下拉维持模块606和第二下拉维持模块607交替进行工作，即两者工作时间错开，同一时刻只有一个下拉维持模块在工作。由于第一低频时钟信号LC1和第二低频时钟信号LC2的输入特性，对于此刻正在工作的某个下拉维持模块，其低频时钟信号输入端相当于接收到的是一个直流信号，该直流信号为高电位，数值为28V。
第一下拉维持模块606和第二下拉维持模块607中均包括反向单元和维持单元，反向单元的输出端连接维持单元的输入端，至少一个反向单元为第一反向单元。在本实施例中，第一下拉维持模块606和第二下拉维持模块607中的反向单元均为第一反向单元，即第一下拉维持模块606和第二下拉维持模块607的结构相同，因此图7以第一下拉维持模块606为例，对第一反向单元和维持单元结构进行说明，具体工作原理对第二下拉维持模块607也适用。
如图6所示，第一下拉维持模块606包括第六晶体管T51、第七晶体管T52、第八晶体管T53、第九晶体管T42和第十晶体管T32，第二下拉维持模块607包括第十一晶体管T61、第十二晶体管T62、第十三晶体管T63、第十四晶体管T43和第十五晶体管T33。如图7所示，第一下拉维持模块606包括第一反向单元200和维持单元300，第一反向单元200中，第六晶体管T51为第一反向晶体管，第七晶体管T52为第二反向晶体管，第八晶体管T53为第三反向晶体管，维持单元300中，第九晶体管T42为第一维持晶体管，第十晶体管T32为第二维持晶体管。同样地，第二下拉维持模块607的第一反向单元200中，第十一晶体管T61为第一反向晶体管，第十二晶体管T62为第二反向晶体管，第十三晶体管T63为第三反向晶体管，第二下拉维持模块607的维持单元300中，第十四晶体管T43为第一维持晶体管，第十五晶体管T33为第二维持晶体管。
在本申请中，各晶体管的第一电极和第二电极，其中一个为源极，另一个为漏极。第一反向晶体管、第二反向晶体管、第三反向晶体管、第一维持晶体管、第二维持晶体管以及其他各晶体管均为N型或P型晶体管。
在图7中，第六晶体管T51的栅极和第一电极连接低频时钟信号输入端，第六晶体管T51的第二电极和第七晶体管T52的第一电极连接第二节点A(N)，第七晶体管T52的栅极连接第一节点Q(N)，第七晶体管T52的第二电极连接第一电源低电位信号VSSQ，第八晶体管T53的栅极和第一电极连接第二节点A(N)，第八晶体管T53的第二电极连接维持单元300的输入端。第九晶体管T42的栅极和第十晶体管T32的栅极连接维持单元300的输入端，第九晶体管T42的第一电极连接第一电源低电位信号VSSQ，第九晶体管T42的第二电极连接第一节点Q(N)，第十晶体管T32的第一电极连接第二电源低电位信号VSSG，第十晶体管T32的第二电极连接本级栅极驱动信号G(N)。其中，低频时钟信号输入端输入第一低频时钟信号LC1，维持单元300的输入端与第四节点P(N)连接。
在第一下拉维持模块606工作时，第一反向单元200的低频时钟信号输入端输入的信号等同于直流信号，数值为28v，即工作期间第一低频时钟信号LC1一直为高电位，因此第六晶体管T51始终处于打开状态，将第二节点A(N)电位拉高。在第一节点Q(N)为高电位时，第七晶体管T52打开，第一电源低电位信号VSSQ将第二节点A(N)电位拉低，因此第二节点A(N)同时接收第六晶体管T51输入的高电位和第七晶体管T52输入的低电位，使得第二节点A(N)电位偏低，不足以打开第八晶体管T53，因此第四节点P(N)电位为低，也即维持单元的输入端电位为低，第九晶体管T42和第十晶体管T32关闭。在第一节点Q(N)为低电位时，第七晶体管T52关闭，第二节点A(N)仅接收第六晶体管T51输入的高电位，因此第二节点A(N)电位为高，使得第八晶体管T53打开，第四节点P(N)电位为高，也即维持单元300的输入端电位为高，第九晶体管T42和第十晶体管T32打开，分别将第一电源低电位信号VSSQ和第二电源低电位信号VSSG输入给第一节点Q(N)和本级栅极驱动信号G(N)，将两者的电位维持在低电位。
现有8K产品中的第N级GOA单元的结构如图8所示，包括上拉控制模块801、上拉模块802、信号下传模块803、第一下拉模块804、第二下拉模块805、第一下拉维持模块806和第二下拉维持模块807。其中，上拉控制模块801包括晶体管T11，上拉模块802包括晶体管T21，信号下传模块803包括晶体管T22，第一下拉模块804包括晶体管T31，第二下拉模块805包括晶体管T41，第一下拉维持模块806包括晶体管T51、T52、T53、T54、T32、T42，第二下拉维持模块807包括晶体管T61、T62、T63、T64、T33、T43，各晶体管的连接方式如图。第一下拉维持模块806包括反相器100和晶体管T32、T42，反相器100由4颗晶体管组成，它的工作原理为：当Q(N)点的电位为低电位时，T52和T54关闭，T51打开，使得A点的电位为高，进而使T53打开，P(N)点为高电位；当Q(N)点的电位为高电位时，T52和T54打开，VSSQ向A点输入低电位，T51打开，向A点输入高电位，两者共同作用使得A点电位偏低，T53不能正常打开，因此P(N)点为低电位。即，反相器100总是使Q(N)点和P(N)点的电位相反。然而，8K产品由于窄边框限制，且负载较大，对于GOA电路的空间较为紧张，现有的第一下拉维持模块806和第二下拉维持模块807中，反相器100均需要4颗晶体管才能实现Q(N)点和P(N)点的电位相反，使得整个第N级GOA单元需要18个晶体管，造成GOA电路空间占用过大，不能满足8K产品的需求。
本实施例中的第一下拉维持模块606和第二下拉维持模块607中，反向单元均为第一反向单元200，每个第一反向单元200仅需通过三个晶体管就能实现第一节点和维持单元输入端信号的电位相反，因此GOA电路中第N级GOA单元仅需16个晶体管，相对于现有技术，减少了两个晶体管，从而使得GOA电路的结构得到精简，节省了GOA电路的占用空间。对于GOA电路中每级GOA单元，均可采用与第N级GOA单元相同的设置。
图9和图10分别示出了现有技术和本申请实施例提供的GOA电路中，第N级GOA单元的第一下拉维持模块和第二下拉维持模块中反向单元的膜层叠加结构，各膜层包括第一金属层110、源漏极层120和连接构件130，第一金属层110与有源层（图未示出）重叠的部分形成各晶体管的栅极，此外还形成第一节点Q(N)，源漏极层120形成各晶体管的源极和漏极、第一电源低电位信号线VSSQ、以及低频时钟信号线LC，连接构件130一端覆盖在源漏极层120上，另一端与第一金属层110中的过孔连接，实现一个晶体管的栅极和另一个晶体管的源极或漏极连接，连接构件130的材料为氧化铟锡。
由图9和图10对比可知，现有技术中每个反向器需要设置四个晶体管，且连接需要三个连接构件，结构较为复杂，占用空间较多，而本申请中每个反向单元仅需要设置三个晶体管，连接仅需要两个连接构件，结构较为简单，占用空间较少，且简化了制作工艺，节省了成本。
在上述实施例中，第一下拉维持模块606和第二下拉维持模块607中反向单元均为第一反向单元200，但本申请不限于此，在一种实施例中，第一下拉维持模块606和第二下拉维持模块607中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，第四反向晶体管的第二电极和第五反向晶体管的第一电极连接第三节点，第五反向晶体管的栅极连接第一节点，第五反向晶体管的第二电极连接第一电源低电位信号，第六反向晶体管的栅极连接第三节点，第六反向晶体管的第一电极连接第四反向晶体管的第一电极，第六反向晶体管的第二电极与第七反向晶体管的第一电极连接维持单元的输入端，第七反向晶体管的栅极连接第一节点，第七反向晶体管的第二电极连接第一电源低电位信号。
如图11所示，为本申请实施例提供的GOA电路中第N级GOA单元的第二种结构示意图。在本实施例中，第一下拉维持模块606中反向单元为第一反向单元200，结构与图3中相同，第二下拉维持模块607中反向单元为第二反向单元400，第二反向单元400中包括第十一晶体管T61、第十二晶体管T62、第十三晶体管T63、第十六晶体管T64，其中，第十一晶体管T61为第四反向晶体管，第十二晶体管T62为第五反向晶体管，第十三晶体管T63为第六反向晶体管，第十六晶体管T64为第七反向晶体管。
第十一晶体管T61的栅极和第一电极连接低频时钟信号输入端，第十一晶体管T61的第二电极和第十二晶体管T62的第一电极连接第三节点B(N)，第十二晶体管T62的栅极连接第一节点Q(N)，第十二晶体管T62的第二电极连接第一电源低电位信号VSSQ，第十三晶体管T63的栅极连接第三节点B(N)，第十三晶体管T63的第一电极连接第十一晶体管T61的第一电极，第十三晶体管T63的第二电极与第十六晶体管T64的第一电极连接维持单元300的输入端，第十六晶体管T64的栅极连接第一节点Q(N)，第十六晶体管T64的第二电极连接第一电源低电位信号VSSQ。其中，低频时钟信号输入端输入第二低频时钟信号LC2，维持单元300的输入端与第五节点R(N)连接。
第二反向单元400中结构与现有技术中结构相同，因此也能起到使第一节点Q(N)与维持单元300的输入端电位相反的作用。本实施例中将第一下拉维持模块606中反向单元设计为第一反向单元200，第二下拉维持模块607中反向单元设计为第二反向单元400，或将第一下拉维持模块606中反向单元设计为第二反向单元400，第二下拉维持模块607中反向单元设计为第一反向单元200，均可以使得第N级GOA单元中晶体管总数为16个，相对于现有技术，减少了一个晶体管，因此精简了GOA电路结构，节省了占用空间。
本申请实施例还提供一种电子设备，包括显示面板和驱动芯片，显示面板包括多条扫描线、2m条时钟信号线和GOA电路；扫描线位于显示区；时钟信号线位于非显示区内的信号线设置区；GOA电路位于显示区和信号线设置区之间，GOA电路包括多个级联的GOA单元，GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，有效GOA单元的驱动信号输出端与扫描线顺序连接且一一对应，多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在有效GOA模块内，2m个有效GOA单元的时钟信号输入端与2m条时钟信号线顺序连接且一一对应，2m个冗余GOA单元的时钟信号输入端与2m条时钟信号线顺序连接且一一对应。
在一种实施例中，所述2m个冗余GOA单元的结构相同。
在一种实施例中，所述冗余GOA单元与所述有效GOA单元的结构相同。
在一种实施例中，所述GOA电路中，自首位起每m个GOA单元形成一个GOA模块，相邻所述GOA模块间，在后GOA模块用于向在前GOA模块提供复位信号。
在一种实施例中，所述在后GOA模块中第n级GOA单元的驱动信号输出端，与所述在前GOA模块中第n级GOA单元的复位信号端连接。
在一种实施例中，所述在前GOA模块中第n级GOA单元的驱动信号输出端，与所述在后GOA模块中第n级GOA单元的驱动信号输入端连接。
在一种实施例中，自首位起m个GOA单元形成的GOA模块中，各GOA单元的驱动信号输入端均连接帧起始信号线。
在一种实施例中，所述GOA单元还包括电源信号输入端，所述电源信号输入端连接电源信号线。
在一种实施例中，所述GOA电路位于所述显示区的左侧或右侧。
在一种实施例中，所述GOA电路中，第N级的GOA单元包括：
上拉控制模块，与第一节点连接，用于根据前级级传信号，上拉所述第一节点的电位；
上拉模块，与所述第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；
信号下传模块，与所述第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；
第一下拉模块，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；
第二下拉模块，与所述第一节点连接，用于根据第二后级栅极驱动信号，下拉所述第一节点的电位；
第一下拉维持模块，与所述第一节点连接，用于根据第一低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位；
第二下拉维持模块，与所述第一节点连接，用于根据第二低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位，所述第一低频时钟信号和所述第二低频时钟信号在相同时刻电位相反；
其中，所述第一下拉维持模块和所述第二下拉维持模块中均包括反向单元和维持单元，所述反向单元的输出端连接所述维持单元的输入端，至少一个所述反向单元为第一反向单元；所述第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，所述第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第一反向晶体管的第二电极和所述第二反向晶体管的第一电极连接第二节点，所述第二反向晶体管的栅极连接所述第一节点，所述第二反向晶体管的第二电极连接第一电源低电位信号，所述第三反向晶体管的栅极和第一电极连接所述第二节点，所述第三反向晶体管的第二电极连接所述维持单元的输入端。
在一种实施例中，所述维持单元包括第一维持晶体管和第二维持晶体管，所述第一维持晶体管的栅极和所述第二维持晶体管的栅极连接所述维持单元的输入端，所述第一维持晶体管的第一电极连接所述第一电源低电位信号，所述第一维持晶体管的第二电极连接所述第一节点，所述第二维持晶体管的第一电极连接第二电源低电位信号，所述第二维持晶体管的第二电极连接所述本级栅极驱动信号。
本申请的电子设备可以是分辨率为7680*4320的8K产品，其中显示面板可以是液晶显示面板或OLED显示面板，驱动芯片中设置有时序控制器，显示面板中的各时钟信号线中的时钟信号均由该时序控制器提供。显示面板中每条时钟信号线连接的GOA单元数量相等，因此每条时钟信号线的负载相同，在低灰阶下不会产生周期性暗纹，显示效果较好。
根据以上实施例可知：
本申请实施例提供一种显示面板和电子设备，显示面板包括多条扫描线、2m条时钟信号线和GOA电路；扫描线位于显示区；时钟信号线位于非显示区内的信号线设置区；GOA电路位于显示区和信号线设置区之间，GOA电路包括多个级联的GOA单元，GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，有效GOA单元的驱动信号输出端与扫描线顺序连接且一一对应，多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在有效GOA模块内，2m个有效GOA单元的时钟信号输入端与2m条时钟信号线顺序连接且一一对应，2m个冗余GOA单元的时钟信号输入端与2m条时钟信号线顺序连接且一一对应。本申请中每条时钟信号线连接的GOA单元数量相等，因此每条时钟信号线的负载相同，在低灰阶下不会产生周期性暗纹。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和电子设备进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括：
    多条扫描线，所述扫描线位于显示区；
    2m条时钟信号线，所述时钟信号线位于非显示区内的信号线设置区；
    GOA电路，位于所述显示区和所述信号线设置区之间，所述GOA电路包括多个级联的GOA单元，所述GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，所述有效GOA单元的驱动信号输出端与所述扫描线顺序连接且一一对应，所述多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在所述有效GOA模块内，所述2m个有效GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应，所述2m个冗余GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应。
  2. 如权利要求1所述的显示面板，其中，所述2m个冗余GOA单元的结构相同。
  3. 如权利要求2所述的显示面板，其中，所述冗余GOA单元与所述有效GOA单元的结构相同。
  4. 如权利要求1所述的显示面板，其中，所述GOA电路中，自首位起每m个GOA单元形成一个GOA模块，相邻所述GOA模块间，在后GOA模块用于向在前GOA模块提供复位信号。
  5. 如权利要求4所述的显示面板，其中，所述在后GOA模块中第n级GOA单元的驱动信号输出端，与所述在前GOA模块中第n级GOA单元的复位信号端连接。
  6. 如权利要求4所述的显示面板，其中，所述在前GOA模块中第n级GOA单元的驱动信号输出端，与所述在后GOA模块中第n级GOA单元的驱动信号输入端连接。
  7. 如权利要求4所述的显示面板，其中，自首位起m个GOA单元形成的GOA模块中，各GOA单元的驱动信号输入端均连接帧起始信号线。
  8. 如权利要求1所述的显示面板，其中，所述GOA电路中，第N级的GOA单元包括：
    上拉控制模块，与第一节点连接，用于根据前级级传信号，上拉所述第一节点的电位；
    上拉模块，与所述第一节点连接，用于根据本级时钟信号，上拉本级栅极驱动信号的电位；
    信号下传模块，与所述第一节点连接，用于根据本级时钟信号，控制本级级传信号的输出；
    第一下拉模块，用于根据第一后级栅极驱动信号，下拉本级栅极驱动信号的电位；
    第二下拉模块，与所述第一节点连接，用于根据第二后级栅极驱动信号，下拉所述第一节点的电位；
    第一下拉维持模块，与所述第一节点连接，用于根据第一低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位；
    第二下拉维持模块，与所述第一节点连接，用于根据第二低频时钟信号，维持所述第一节点和所述本级栅极驱动信号的低电位，所述第一低频时钟信号和所述第二低频时钟信号在相同时刻电位相反；
    其中，所述第一下拉维持模块和所述第二下拉维持模块中均包括反向单元和维持单元，所述反向单元的输出端连接所述维持单元的输入端，至少一个所述反向单元为第一反向单元；所述第一反向单元包括第一反向晶体管、第二反向晶体管和第三反向晶体管，所述第一反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第一反向晶体管的第二电极和所述第二反向晶体管的第一电极连接第二节点，所述第二反向晶体管的栅极连接所述第一节点，所述第二反向晶体管的第二电极连接第一电源低电位信号，所述第三反向晶体管的栅极和第一电极连接所述第二节点，所述第三反向晶体管的第二电极连接所述维持单元的输入端。
  9. 如权利要求8所述的显示面板，其中，所述维持单元包括第一维持晶体管和第二维持晶体管，所述第一维持晶体管的栅极和所述第二维持晶体管的栅极连接所述维持单元的输入端，所述第一维持晶体管的第一电极连接所述第一电源低电位信号，所述第一维持晶体管的第二电极连接所述第一节点，所述第二维持晶体管的第一电极连接第二电源低电位信号，所述第二维持晶体管的第二电极连接所述本级栅极驱动信号。
  10. 如权利要求8所述的显示面板，其中，所述第一下拉维持模块和所述第二下拉维持模块中的反向单元均为第一反向单元。
  11. 如权利要求8所述的显示面板，其中，所述第一下拉维持模块和所述第二下拉维持模块中的其中一个反向单元为第一反向单元，另一个反向单元为第二反向单元，所述第二反向单元包括第四反向晶体管、第五反向晶体管、第六反向晶体管和第七反向晶体管，所述第四反向晶体管的栅极和第一电极连接低频时钟信号输入端，所述第四反向晶体管的第二电极和所述第五反向晶体管的第一电极连接第三节点，所述第五反向晶体管的栅极连接所述第一节点，所述第五反向晶体管的第二电极连接第一电源低电位信号，所述第六反向晶体管的栅极连接所述第三节点，所述第六反向晶体管的第一电极连接所述第四反向晶体管的第一电极，所述第六反向晶体管的第二电极与所述第七反向晶体管的第一电极连接所述维持单元的输入端，所述第七反向晶体管的栅极连接所述第一节点，所述第七反向晶体管的第二电极连接所述第一电源低电位信号。
  12. 如权利要求8所述的显示面板，其中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极和第一电极连接所述前级级传信号，第二电极连接所述第一节点。
  13. 如权利要求12所述的显示面板，其中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级栅极驱动信号。
  14. 如权利要求13所述的显示面板，其中，所述信号下传模块包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，第一电极连接所述本级时钟信号，第二电极连接所述本级级传信号。
  15. 如权利要求14所述的显示面板，其中，所述第一下拉模块包括第四晶体管，所述第四晶体管的栅极连接所述第一后级栅极驱动信号，第一电极连接所述第二电源低电位信号，第二电极连接所述本级栅极驱动信号。
  16. 如权利要求15所述的显示面板，其中，所述第二下拉模块包括第五晶体管，所述第五晶体管的栅极连接所述第二后级栅极驱动信号，第一电极连接所述第一电源低电位信号，第二电极连接所述第一节点。
  17. 一种电子设备，其包括显示面板和驱动芯片，所述显示面板包括：
    多条扫描线，所述扫描线位于显示区；
    2m条时钟信号线，所述时钟信号线位于非显示区内的信号线设置区；
    GOA电路，位于所述显示区和所述信号线设置区之间，所述GOA电路包括多个级联的GOA单元，所述GOA单元包括依次排列的多个有效GOA单元和2m个冗余GOA单元，所述有效GOA单元的驱动信号输出端与所述扫描线顺序连接且一一对应，所述多个有效GOA单元形成顺序排列的多个有效GOA模块，每个有效GOA模块包括2m个有效GOA单元，在所述有效GOA模块内，所述2m个有效GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应，所述2m个冗余GOA单元的时钟信号输入端与所述2m条时钟信号线顺序连接且一一对应。
  18. 如权利要求17所述的电子设备，其中，所述2m个冗余GOA单元的结构相同。
  19. 如权利要求18所述的电子设备，其中，所述冗余GOA单元与所述有效GOA单元的结构相同。
  20. 如权利要求17所述的电子设备，其中，所述GOA电路中，自首位起每m个GOA单元形成一个GOA模块，相邻所述GOA模块间，在后GOA模块用于向在前GOA模块提供复位信号。
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